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6956e238 MG |
1 | #include <linux/io.h> |
2 | #include <linux/of.h> | |
3 | #include <linux/clk.h> | |
4 | #include <linux/iopoll.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/mtd/nand.h> | |
7 | #include <linux/dmaengine.h> | |
8 | #include <linux/dma-mapping.h> | |
9 | #include <linux/platform_device.h> | |
10 | ||
11 | /* Offsets relative to chip->base */ | |
12 | #define PBUS_CMD 0 | |
13 | #define PBUS_ADDR 4 | |
14 | #define PBUS_DATA 8 | |
15 | ||
16 | /* Offsets relative to reg_base */ | |
17 | #define NFC_STATUS 0x00 | |
18 | #define NFC_FLASH_CMD 0x04 | |
19 | #define NFC_DEVICE_CFG 0x08 | |
20 | #define NFC_TIMING1 0x0c | |
21 | #define NFC_TIMING2 0x10 | |
22 | #define NFC_XFER_CFG 0x14 | |
23 | #define NFC_PKT_0_CFG 0x18 | |
24 | #define NFC_PKT_N_CFG 0x1c | |
25 | #define NFC_BB_CFG 0x20 | |
26 | #define NFC_ADDR_PAGE 0x24 | |
27 | #define NFC_ADDR_OFFSET 0x28 | |
28 | #define NFC_XFER_STATUS 0x2c | |
29 | ||
30 | /* NFC_STATUS values */ | |
31 | #define CMD_READY BIT(31) | |
32 | ||
33 | /* NFC_FLASH_CMD values */ | |
34 | #define NFC_READ 1 | |
35 | #define NFC_WRITE 2 | |
36 | ||
37 | /* NFC_XFER_STATUS values */ | |
38 | #define PAGE_IS_EMPTY BIT(16) | |
39 | ||
40 | /* Offsets relative to mem_base */ | |
41 | #define METADATA 0x000 | |
42 | #define ERROR_REPORT 0x1c0 | |
43 | ||
44 | /* | |
45 | * Error reports are split in two bytes: | |
46 | * byte 0 for the first packet in the page (PKT_0) | |
47 | * byte 1 for other packets in the page (PKT_N, for N > 0) | |
48 | * ERR_COUNT_PKT_N is the max error count over all but the first packet. | |
49 | */ | |
50 | #define DECODE_OK_PKT_0(v) ((v) & BIT(7)) | |
51 | #define DECODE_OK_PKT_N(v) ((v) & BIT(15)) | |
52 | #define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) | |
53 | #define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) | |
54 | ||
55 | /* Offsets relative to pbus_base */ | |
56 | #define PBUS_CS_CTRL 0x83c | |
57 | #define PBUS_PAD_MODE 0x8f0 | |
58 | ||
59 | /* PBUS_CS_CTRL values */ | |
60 | #define PBUS_IORDY BIT(31) | |
61 | ||
62 | /* | |
63 | * PBUS_PAD_MODE values | |
64 | * In raw mode, the driver communicates directly with the NAND chips. | |
65 | * In NFC mode, the NAND Flash controller manages the communication. | |
66 | * We use NFC mode for read and write; raw mode for everything else. | |
67 | */ | |
68 | #define MODE_RAW 0 | |
69 | #define MODE_NFC BIT(31) | |
70 | ||
71 | #define METADATA_SIZE 4 | |
72 | #define BBM_SIZE 6 | |
73 | #define FIELD_ORDER 15 | |
74 | ||
75 | #define MAX_CS 4 | |
76 | ||
77 | struct tango_nfc { | |
78 | struct nand_hw_control hw; | |
79 | void __iomem *reg_base; | |
80 | void __iomem *mem_base; | |
81 | void __iomem *pbus_base; | |
82 | struct tango_chip *chips[MAX_CS]; | |
83 | struct dma_chan *chan; | |
84 | int freq_kHz; | |
85 | }; | |
86 | ||
87 | #define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) | |
88 | ||
89 | struct tango_chip { | |
90 | struct nand_chip nand_chip; | |
91 | void __iomem *base; | |
92 | u32 timing1; | |
93 | u32 timing2; | |
94 | u32 xfer_cfg; | |
95 | u32 pkt_0_cfg; | |
96 | u32 pkt_n_cfg; | |
97 | u32 bb_cfg; | |
98 | }; | |
99 | ||
100 | #define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) | |
101 | ||
102 | #define XFER_CFG(cs, page_count, steps, metadata_size) \ | |
103 | ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) | |
104 | ||
105 | #define PKT_CFG(size, strength) ((size) << 16 | (strength)) | |
106 | ||
107 | #define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) | |
108 | ||
109 | #define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) | |
110 | ||
111 | static void tango_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) | |
112 | { | |
113 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
114 | ||
115 | if (ctrl & NAND_CLE) | |
116 | writeb_relaxed(dat, tchip->base + PBUS_CMD); | |
117 | ||
118 | if (ctrl & NAND_ALE) | |
119 | writeb_relaxed(dat, tchip->base + PBUS_ADDR); | |
120 | } | |
121 | ||
122 | static int tango_dev_ready(struct mtd_info *mtd) | |
123 | { | |
124 | struct nand_chip *chip = mtd_to_nand(mtd); | |
125 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
126 | ||
127 | return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY; | |
128 | } | |
129 | ||
130 | static u8 tango_read_byte(struct mtd_info *mtd) | |
131 | { | |
132 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
133 | ||
134 | return readb_relaxed(tchip->base + PBUS_DATA); | |
135 | } | |
136 | ||
137 | static void tango_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
138 | { | |
139 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
140 | ||
141 | ioread8_rep(tchip->base + PBUS_DATA, buf, len); | |
142 | } | |
143 | ||
144 | static void tango_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
145 | { | |
146 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
147 | ||
148 | iowrite8_rep(tchip->base + PBUS_DATA, buf, len); | |
149 | } | |
150 | ||
151 | static void tango_select_chip(struct mtd_info *mtd, int idx) | |
152 | { | |
153 | struct nand_chip *chip = mtd_to_nand(mtd); | |
154 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
155 | struct tango_chip *tchip = to_tango_chip(chip); | |
156 | ||
157 | if (idx < 0) | |
158 | return; /* No "chip unselect" function */ | |
159 | ||
160 | writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); | |
161 | writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); | |
162 | writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); | |
163 | writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); | |
164 | writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); | |
165 | writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); | |
166 | } | |
167 | ||
168 | /* | |
169 | * The controller does not check for bitflips in erased pages, | |
170 | * therefore software must check instead. | |
171 | */ | |
172 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
173 | { | |
174 | u8 *meta = chip->oob_poi + BBM_SIZE; | |
175 | u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; | |
176 | const int ecc_size = chip->ecc.bytes; | |
177 | const int pkt_size = chip->ecc.size; | |
178 | int i, res, meta_len, bitflips = 0; | |
179 | ||
180 | for (i = 0; i < chip->ecc.steps; ++i) { | |
181 | meta_len = i ? 0 : METADATA_SIZE; | |
182 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
183 | meta, meta_len, | |
184 | chip->ecc.strength); | |
185 | if (res < 0) | |
186 | chip->mtd.ecc_stats.failed++; | |
187 | ||
188 | bitflips = max(res, bitflips); | |
189 | buf += pkt_size; | |
190 | ecc += ecc_size; | |
191 | } | |
192 | ||
193 | return bitflips; | |
194 | } | |
195 | ||
196 | static int decode_error_report(struct tango_nfc *nfc) | |
197 | { | |
198 | u32 status, res; | |
199 | ||
200 | status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); | |
201 | if (status & PAGE_IS_EMPTY) | |
202 | return 0; | |
203 | ||
204 | res = readl_relaxed(nfc->mem_base + ERROR_REPORT); | |
205 | ||
206 | if (DECODE_OK_PKT_0(res) && DECODE_OK_PKT_N(res)) | |
207 | return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); | |
208 | ||
209 | return -EBADMSG; | |
210 | } | |
211 | ||
212 | static void tango_dma_callback(void *arg) | |
213 | { | |
214 | complete(arg); | |
215 | } | |
216 | ||
217 | static int do_dma(struct tango_nfc *nfc, int dir, int cmd, const void *buf, | |
218 | int len, int page) | |
219 | { | |
220 | void __iomem *addr = nfc->reg_base + NFC_STATUS; | |
221 | struct dma_chan *chan = nfc->chan; | |
222 | struct dma_async_tx_descriptor *desc; | |
223 | struct scatterlist sg; | |
224 | struct completion tx_done; | |
225 | int err = -EIO; | |
226 | u32 res, val; | |
227 | ||
228 | sg_init_one(&sg, buf, len); | |
229 | if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) | |
230 | return -EIO; | |
231 | ||
232 | desc = dmaengine_prep_slave_sg(chan, &sg, 1, dir, DMA_PREP_INTERRUPT); | |
233 | if (!desc) | |
234 | goto dma_unmap; | |
235 | ||
236 | desc->callback = tango_dma_callback; | |
237 | desc->callback_param = &tx_done; | |
238 | init_completion(&tx_done); | |
239 | ||
240 | writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); | |
241 | ||
242 | writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); | |
243 | writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); | |
244 | writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); | |
245 | ||
246 | dmaengine_submit(desc); | |
247 | dma_async_issue_pending(chan); | |
248 | ||
249 | res = wait_for_completion_timeout(&tx_done, HZ); | |
250 | if (res > 0) | |
251 | err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); | |
252 | ||
253 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); | |
254 | ||
255 | dma_unmap: | |
256 | dma_unmap_sg(chan->device->dev, &sg, 1, dir); | |
257 | ||
258 | return err; | |
259 | } | |
260 | ||
261 | static int tango_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
262 | u8 *buf, int oob_required, int page) | |
263 | { | |
264 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
265 | int err, res, len = mtd->writesize; | |
266 | ||
267 | if (oob_required) | |
268 | chip->ecc.read_oob(mtd, chip, page); | |
269 | ||
270 | err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); | |
271 | if (err) | |
272 | return err; | |
273 | ||
274 | res = decode_error_report(nfc); | |
275 | if (res < 0) { | |
276 | chip->ecc.read_oob_raw(mtd, chip, page); | |
277 | res = check_erased_page(chip, buf); | |
278 | } | |
279 | ||
280 | return res; | |
281 | } | |
282 | ||
283 | static int tango_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
284 | const u8 *buf, int oob_required, int page) | |
285 | { | |
286 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
287 | int err, len = mtd->writesize; | |
288 | ||
289 | /* Calling tango_write_oob() would send PAGEPROG twice */ | |
290 | if (oob_required) | |
291 | return -ENOTSUPP; | |
292 | ||
293 | writel_relaxed(0xffffffff, nfc->mem_base + METADATA); | |
294 | err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); | |
295 | if (err) | |
296 | return err; | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) | |
302 | { | |
303 | *pos += len; | |
304 | ||
305 | if (!*buf) { | |
306 | /* skip over "len" bytes */ | |
307 | chip->cmdfunc(&chip->mtd, NAND_CMD_RNDOUT, *pos, -1); | |
308 | } else { | |
309 | tango_read_buf(&chip->mtd, *buf, len); | |
310 | *buf += len; | |
311 | } | |
312 | } | |
313 | ||
314 | static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) | |
315 | { | |
316 | *pos += len; | |
317 | ||
318 | if (!*buf) { | |
319 | /* skip over "len" bytes */ | |
320 | chip->cmdfunc(&chip->mtd, NAND_CMD_SEQIN, *pos, -1); | |
321 | } else { | |
322 | tango_write_buf(&chip->mtd, *buf, len); | |
323 | *buf += len; | |
324 | } | |
325 | } | |
326 | ||
327 | /* | |
328 | * Physical page layout (not drawn to scale) | |
329 | * | |
330 | * NB: Bad Block Marker area splits PKT_N in two (N1, N2). | |
331 | * | |
332 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
333 | * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | | |
334 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
335 | * | |
336 | * Logical page layout: | |
337 | * | |
338 | * +-----+---+-------+-----+-------+ | |
339 | * oob = | BBM | M | ECC_0 | ... | ECC_N | | |
340 | * +-----+---+-------+-----+-------+ | |
341 | * | |
342 | * +-----------------+-----+-----------------+ | |
343 | * buf = | PKT_0 | ... | PKT_N | | |
344 | * +-----------------+-----+-----------------+ | |
345 | */ | |
346 | static int raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) | |
347 | { | |
348 | u8 *oob_orig = oob; | |
349 | const int page_size = chip->mtd.writesize; | |
350 | const int ecc_size = chip->ecc.bytes; | |
351 | const int pkt_size = chip->ecc.size; | |
352 | int pos = 0; /* position within physical page */ | |
353 | int rem = page_size; /* bytes remaining until BBM area */ | |
354 | ||
355 | if (oob) | |
356 | oob += BBM_SIZE; | |
357 | ||
358 | aux_read(chip, &oob, METADATA_SIZE, &pos); | |
359 | ||
360 | while (rem > pkt_size) { | |
361 | aux_read(chip, &buf, pkt_size, &pos); | |
362 | aux_read(chip, &oob, ecc_size, &pos); | |
363 | rem = page_size - pos; | |
364 | } | |
365 | ||
366 | aux_read(chip, &buf, rem, &pos); | |
367 | aux_read(chip, &oob_orig, BBM_SIZE, &pos); | |
368 | aux_read(chip, &buf, pkt_size - rem, &pos); | |
369 | aux_read(chip, &oob, ecc_size, &pos); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static int raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) | |
375 | { | |
376 | const u8 *oob_orig = oob; | |
377 | const int page_size = chip->mtd.writesize; | |
378 | const int ecc_size = chip->ecc.bytes; | |
379 | const int pkt_size = chip->ecc.size; | |
380 | int pos = 0; /* position within physical page */ | |
381 | int rem = page_size; /* bytes remaining until BBM area */ | |
382 | ||
383 | if (oob) | |
384 | oob += BBM_SIZE; | |
385 | ||
386 | aux_write(chip, &oob, METADATA_SIZE, &pos); | |
387 | ||
388 | while (rem > pkt_size) { | |
389 | aux_write(chip, &buf, pkt_size, &pos); | |
390 | aux_write(chip, &oob, ecc_size, &pos); | |
391 | rem = page_size - pos; | |
392 | } | |
393 | ||
394 | aux_write(chip, &buf, rem, &pos); | |
395 | aux_write(chip, &oob_orig, BBM_SIZE, &pos); | |
396 | aux_write(chip, &buf, pkt_size - rem, &pos); | |
397 | aux_write(chip, &oob, ecc_size, &pos); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static int tango_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
403 | u8 *buf, int oob_required, int page) | |
404 | { | |
405 | return raw_read(chip, buf, chip->oob_poi); | |
406 | } | |
407 | ||
408 | static int tango_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
409 | const u8 *buf, int oob_required, int page) | |
410 | { | |
411 | return raw_write(chip, buf, chip->oob_poi); | |
412 | } | |
413 | ||
414 | static int tango_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
415 | int page) | |
416 | { | |
417 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
418 | return raw_read(chip, NULL, chip->oob_poi); | |
419 | } | |
420 | ||
421 | static int tango_write_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
422 | int page) | |
423 | { | |
424 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page); | |
425 | raw_write(chip, NULL, chip->oob_poi); | |
426 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
427 | chip->waitfunc(mtd, chip); | |
428 | return 0; | |
429 | } | |
430 | ||
431 | static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
432 | { | |
433 | struct nand_chip *chip = mtd_to_nand(mtd); | |
434 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
435 | ||
436 | if (idx >= ecc->steps) | |
437 | return -ERANGE; | |
438 | ||
439 | res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; | |
440 | res->length = ecc->bytes; | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
446 | { | |
447 | return -ERANGE; /* no free space in spare area */ | |
448 | } | |
449 | ||
450 | static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { | |
451 | .ecc = oob_ecc, | |
452 | .free = oob_free, | |
453 | }; | |
454 | ||
455 | static u32 to_ticks(int kHz, int ps) | |
456 | { | |
457 | return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); | |
458 | } | |
459 | ||
460 | static int tango_set_timings(struct mtd_info *mtd, | |
461 | const struct nand_data_interface *conf, | |
462 | bool check_only) | |
463 | { | |
464 | const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); | |
465 | struct nand_chip *chip = mtd_to_nand(mtd); | |
466 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
467 | struct tango_chip *tchip = to_tango_chip(chip); | |
468 | u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; | |
469 | int kHz = nfc->freq_kHz; | |
470 | ||
471 | if (IS_ERR(sdr)) | |
472 | return PTR_ERR(sdr); | |
473 | ||
474 | if (check_only) | |
475 | return 0; | |
476 | ||
477 | Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); | |
478 | Textw = to_ticks(kHz, sdr->tWB_max); | |
479 | Twc = to_ticks(kHz, sdr->tWC_min); | |
480 | Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); | |
481 | ||
482 | Tacc = to_ticks(kHz, sdr->tREA_max); | |
483 | Thold = to_ticks(kHz, sdr->tREH_min); | |
484 | Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); | |
485 | Textr = to_ticks(kHz, sdr->tRHZ_max); | |
486 | ||
487 | tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); | |
488 | tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int chip_init(struct device *dev, struct device_node *np) | |
494 | { | |
495 | u32 cs; | |
496 | int err, res; | |
497 | struct mtd_info *mtd; | |
498 | struct nand_chip *chip; | |
499 | struct tango_chip *tchip; | |
500 | struct nand_ecc_ctrl *ecc; | |
501 | struct tango_nfc *nfc = dev_get_drvdata(dev); | |
502 | ||
503 | tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); | |
504 | if (!tchip) | |
505 | return -ENOMEM; | |
506 | ||
507 | res = of_property_count_u32_elems(np, "reg"); | |
508 | if (res < 0) | |
509 | return res; | |
510 | ||
511 | if (res != 1) | |
512 | return -ENOTSUPP; /* Multi-CS chips are not supported */ | |
513 | ||
514 | err = of_property_read_u32_index(np, "reg", 0, &cs); | |
515 | if (err) | |
516 | return err; | |
517 | ||
518 | if (cs >= MAX_CS) | |
519 | return -EINVAL; | |
520 | ||
521 | chip = &tchip->nand_chip; | |
522 | ecc = &chip->ecc; | |
523 | mtd = &chip->mtd; | |
524 | ||
525 | chip->read_byte = tango_read_byte; | |
526 | chip->write_buf = tango_write_buf; | |
527 | chip->read_buf = tango_read_buf; | |
528 | chip->select_chip = tango_select_chip; | |
529 | chip->cmd_ctrl = tango_cmd_ctrl; | |
530 | chip->dev_ready = tango_dev_ready; | |
531 | chip->setup_data_interface = tango_set_timings; | |
532 | chip->options = NAND_USE_BOUNCE_BUFFER | | |
533 | NAND_NO_SUBPAGE_WRITE | | |
534 | NAND_WAIT_TCCS; | |
535 | chip->controller = &nfc->hw; | |
536 | tchip->base = nfc->pbus_base + (cs * 256); | |
537 | ||
538 | nand_set_flash_node(chip, np); | |
539 | mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); | |
540 | mtd->dev.parent = dev; | |
541 | ||
542 | err = nand_scan_ident(mtd, 1, NULL); | |
543 | if (err) | |
544 | return err; | |
545 | ||
546 | ecc->mode = NAND_ECC_HW; | |
547 | ecc->algo = NAND_ECC_BCH; | |
548 | ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); | |
549 | ||
550 | ecc->read_page_raw = tango_read_page_raw; | |
551 | ecc->write_page_raw = tango_write_page_raw; | |
552 | ecc->read_page = tango_read_page; | |
553 | ecc->write_page = tango_write_page; | |
554 | ecc->read_oob = tango_read_oob; | |
555 | ecc->write_oob = tango_write_oob; | |
556 | ||
557 | err = nand_scan_tail(mtd); | |
558 | if (err) | |
559 | return err; | |
560 | ||
561 | tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); | |
562 | tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); | |
563 | tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); | |
564 | tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); | |
565 | ||
566 | err = mtd_device_register(mtd, NULL, 0); | |
567 | if (err) | |
568 | return err; | |
569 | ||
570 | nfc->chips[cs] = tchip; | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | static int tango_nand_remove(struct platform_device *pdev) | |
576 | { | |
577 | int cs; | |
578 | struct tango_nfc *nfc = platform_get_drvdata(pdev); | |
579 | ||
580 | dma_release_channel(nfc->chan); | |
581 | ||
582 | for (cs = 0; cs < MAX_CS; ++cs) { | |
583 | if (nfc->chips[cs]) | |
584 | nand_release(&nfc->chips[cs]->nand_chip.mtd); | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int tango_nand_probe(struct platform_device *pdev) | |
591 | { | |
592 | int err; | |
593 | struct clk *clk; | |
594 | struct resource *res; | |
595 | struct tango_nfc *nfc; | |
596 | struct device_node *np; | |
597 | ||
598 | nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); | |
599 | if (!nfc) | |
600 | return -ENOMEM; | |
601 | ||
602 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
603 | nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
604 | if (IS_ERR(nfc->reg_base)) | |
605 | return PTR_ERR(nfc->reg_base); | |
606 | ||
607 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
608 | nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); | |
609 | if (IS_ERR(nfc->mem_base)) | |
610 | return PTR_ERR(nfc->mem_base); | |
611 | ||
612 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
613 | nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); | |
614 | if (IS_ERR(nfc->pbus_base)) | |
615 | return PTR_ERR(nfc->pbus_base); | |
616 | ||
617 | clk = clk_get(&pdev->dev, NULL); | |
618 | if (IS_ERR(clk)) | |
619 | return PTR_ERR(clk); | |
620 | ||
621 | nfc->chan = dma_request_chan(&pdev->dev, "nfc_sbox"); | |
622 | if (IS_ERR(nfc->chan)) | |
623 | return PTR_ERR(nfc->chan); | |
624 | ||
625 | platform_set_drvdata(pdev, nfc); | |
626 | nand_hw_control_init(&nfc->hw); | |
627 | nfc->freq_kHz = clk_get_rate(clk) / 1000; | |
628 | ||
629 | for_each_child_of_node(pdev->dev.of_node, np) { | |
630 | err = chip_init(&pdev->dev, np); | |
631 | if (err) { | |
632 | tango_nand_remove(pdev); | |
633 | return err; | |
634 | } | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | static const struct of_device_id tango_nand_ids[] = { | |
641 | { .compatible = "sigma,smp8758-nand" }, | |
642 | { /* sentinel */ } | |
643 | }; | |
644 | ||
645 | static struct platform_driver tango_nand_driver = { | |
646 | .probe = tango_nand_probe, | |
647 | .remove = tango_nand_remove, | |
648 | .driver = { | |
649 | .name = "tango-nand", | |
650 | .of_match_table = tango_nand_ids, | |
651 | }, | |
652 | }; | |
653 | ||
654 | module_platform_driver(tango_nand_driver); | |
655 | ||
656 | MODULE_LICENSE("GPL"); | |
657 | MODULE_AUTHOR("Sigma Designs"); | |
658 | MODULE_DESCRIPTION("Tango4 NAND Flash controller driver"); |