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1fef62c1 BB |
1 | /* |
2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com> | |
3 | * | |
4 | * Derived from: | |
5 | * https://github.com/yuq/sunxi-nfc-mtd | |
6 | * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com> | |
7 | * | |
8 | * https://github.com/hno/Allwinner-Info | |
9 | * Copyright (C) 2013 Henrik Nordström <Henrik Nordström> | |
10 | * | |
11 | * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com> | |
12 | * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | */ | |
24 | ||
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/of.h> | |
31 | #include <linux/of_device.h> | |
32 | #include <linux/of_gpio.h> | |
33 | #include <linux/of_mtd.h> | |
34 | #include <linux/mtd/mtd.h> | |
35 | #include <linux/mtd/nand.h> | |
36 | #include <linux/mtd/partitions.h> | |
37 | #include <linux/clk.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/dmaengine.h> | |
40 | #include <linux/gpio.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/io.h> | |
43 | ||
44 | #define NFC_REG_CTL 0x0000 | |
45 | #define NFC_REG_ST 0x0004 | |
46 | #define NFC_REG_INT 0x0008 | |
47 | #define NFC_REG_TIMING_CTL 0x000C | |
48 | #define NFC_REG_TIMING_CFG 0x0010 | |
49 | #define NFC_REG_ADDR_LOW 0x0014 | |
50 | #define NFC_REG_ADDR_HIGH 0x0018 | |
51 | #define NFC_REG_SECTOR_NUM 0x001C | |
52 | #define NFC_REG_CNT 0x0020 | |
53 | #define NFC_REG_CMD 0x0024 | |
54 | #define NFC_REG_RCMD_SET 0x0028 | |
55 | #define NFC_REG_WCMD_SET 0x002C | |
56 | #define NFC_REG_IO_DATA 0x0030 | |
57 | #define NFC_REG_ECC_CTL 0x0034 | |
58 | #define NFC_REG_ECC_ST 0x0038 | |
59 | #define NFC_REG_DEBUG 0x003C | |
60 | #define NFC_REG_ECC_CNT0 0x0040 | |
61 | #define NFC_REG_ECC_CNT1 0x0044 | |
62 | #define NFC_REG_ECC_CNT2 0x0048 | |
63 | #define NFC_REG_ECC_CNT3 0x004c | |
64 | #define NFC_REG_USER_DATA_BASE 0x0050 | |
65 | #define NFC_REG_SPARE_AREA 0x00A0 | |
66 | #define NFC_RAM0_BASE 0x0400 | |
67 | #define NFC_RAM1_BASE 0x0800 | |
68 | ||
69 | /* define bit use in NFC_CTL */ | |
70 | #define NFC_EN BIT(0) | |
71 | #define NFC_RESET BIT(1) | |
72 | #define NFC_BUS_WIDYH BIT(2) | |
73 | #define NFC_RB_SEL BIT(3) | |
74 | #define NFC_CE_SEL GENMASK(26, 24) | |
75 | #define NFC_CE_CTL BIT(6) | |
76 | #define NFC_CE_CTL1 BIT(7) | |
77 | #define NFC_PAGE_SIZE GENMASK(11, 8) | |
78 | #define NFC_SAM BIT(12) | |
79 | #define NFC_RAM_METHOD BIT(14) | |
80 | #define NFC_DEBUG_CTL BIT(31) | |
81 | ||
82 | /* define bit use in NFC_ST */ | |
83 | #define NFC_RB_B2R BIT(0) | |
84 | #define NFC_CMD_INT_FLAG BIT(1) | |
85 | #define NFC_DMA_INT_FLAG BIT(2) | |
86 | #define NFC_CMD_FIFO_STATUS BIT(3) | |
87 | #define NFC_STA BIT(4) | |
88 | #define NFC_NATCH_INT_FLAG BIT(5) | |
89 | #define NFC_RB_STATE0 BIT(8) | |
90 | #define NFC_RB_STATE1 BIT(9) | |
91 | #define NFC_RB_STATE2 BIT(10) | |
92 | #define NFC_RB_STATE3 BIT(11) | |
93 | ||
94 | /* define bit use in NFC_INT */ | |
95 | #define NFC_B2R_INT_ENABLE BIT(0) | |
96 | #define NFC_CMD_INT_ENABLE BIT(1) | |
97 | #define NFC_DMA_INT_ENABLE BIT(2) | |
98 | #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \ | |
99 | NFC_CMD_INT_ENABLE | \ | |
100 | NFC_DMA_INT_ENABLE) | |
101 | ||
d052e508 RS |
102 | /* define bit use in NFC_TIMING_CTL */ |
103 | #define NFC_TIMING_CTL_EDO BIT(8) | |
104 | ||
9c618292 RS |
105 | /* define NFC_TIMING_CFG register layout */ |
106 | #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ | |
107 | (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \ | |
108 | (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \ | |
109 | (((tCAD) & 0x7) << 8)) | |
110 | ||
1fef62c1 BB |
111 | /* define bit use in NFC_CMD */ |
112 | #define NFC_CMD_LOW_BYTE GENMASK(7, 0) | |
113 | #define NFC_CMD_HIGH_BYTE GENMASK(15, 8) | |
114 | #define NFC_ADR_NUM GENMASK(18, 16) | |
115 | #define NFC_SEND_ADR BIT(19) | |
116 | #define NFC_ACCESS_DIR BIT(20) | |
117 | #define NFC_DATA_TRANS BIT(21) | |
118 | #define NFC_SEND_CMD1 BIT(22) | |
119 | #define NFC_WAIT_FLAG BIT(23) | |
120 | #define NFC_SEND_CMD2 BIT(24) | |
121 | #define NFC_SEQ BIT(25) | |
122 | #define NFC_DATA_SWAP_METHOD BIT(26) | |
123 | #define NFC_ROW_AUTO_INC BIT(27) | |
124 | #define NFC_SEND_CMD3 BIT(28) | |
125 | #define NFC_SEND_CMD4 BIT(29) | |
126 | #define NFC_CMD_TYPE GENMASK(31, 30) | |
127 | ||
128 | /* define bit use in NFC_RCMD_SET */ | |
129 | #define NFC_READ_CMD GENMASK(7, 0) | |
130 | #define NFC_RANDOM_READ_CMD0 GENMASK(15, 8) | |
131 | #define NFC_RANDOM_READ_CMD1 GENMASK(23, 16) | |
132 | ||
133 | /* define bit use in NFC_WCMD_SET */ | |
134 | #define NFC_PROGRAM_CMD GENMASK(7, 0) | |
135 | #define NFC_RANDOM_WRITE_CMD GENMASK(15, 8) | |
136 | #define NFC_READ_CMD0 GENMASK(23, 16) | |
137 | #define NFC_READ_CMD1 GENMASK(31, 24) | |
138 | ||
139 | /* define bit use in NFC_ECC_CTL */ | |
140 | #define NFC_ECC_EN BIT(0) | |
141 | #define NFC_ECC_PIPELINE BIT(3) | |
142 | #define NFC_ECC_EXCEPTION BIT(4) | |
143 | #define NFC_ECC_BLOCK_SIZE BIT(5) | |
144 | #define NFC_RANDOM_EN BIT(9) | |
145 | #define NFC_RANDOM_DIRECTION BIT(10) | |
146 | #define NFC_ECC_MODE_SHIFT 12 | |
147 | #define NFC_ECC_MODE GENMASK(15, 12) | |
148 | #define NFC_RANDOM_SEED GENMASK(30, 16) | |
149 | ||
150 | #define NFC_DEFAULT_TIMEOUT_MS 1000 | |
151 | ||
152 | #define NFC_SRAM_SIZE 1024 | |
153 | ||
154 | #define NFC_MAX_CS 7 | |
155 | ||
156 | /* | |
157 | * Ready/Busy detection type: describes the Ready/Busy detection modes | |
158 | * | |
159 | * @RB_NONE: no external detection available, rely on STATUS command | |
160 | * and software timeouts | |
161 | * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy | |
162 | * pin of the NAND flash chip must be connected to one of the | |
163 | * native NAND R/B pins (those which can be muxed to the NAND | |
164 | * Controller) | |
165 | * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy | |
166 | * pin of the NAND flash chip must be connected to a GPIO capable | |
167 | * pin. | |
168 | */ | |
169 | enum sunxi_nand_rb_type { | |
170 | RB_NONE, | |
171 | RB_NATIVE, | |
172 | RB_GPIO, | |
173 | }; | |
174 | ||
175 | /* | |
176 | * Ready/Busy structure: stores information related to Ready/Busy detection | |
177 | * | |
178 | * @type: the Ready/Busy detection mode | |
179 | * @info: information related to the R/B detection mode. Either a gpio | |
180 | * id or a native R/B id (those supported by the NAND controller). | |
181 | */ | |
182 | struct sunxi_nand_rb { | |
183 | enum sunxi_nand_rb_type type; | |
184 | union { | |
185 | int gpio; | |
186 | int nativeid; | |
187 | } info; | |
188 | }; | |
189 | ||
190 | /* | |
191 | * Chip Select structure: stores information related to NAND Chip Select | |
192 | * | |
193 | * @cs: the NAND CS id used to communicate with a NAND Chip | |
194 | * @rb: the Ready/Busy description | |
195 | */ | |
196 | struct sunxi_nand_chip_sel { | |
197 | u8 cs; | |
198 | struct sunxi_nand_rb rb; | |
199 | }; | |
200 | ||
201 | /* | |
202 | * sunxi HW ECC infos: stores information related to HW ECC support | |
203 | * | |
204 | * @mode: the sunxi ECC mode field deduced from ECC requirements | |
205 | * @layout: the OOB layout depending on the ECC requirements and the | |
206 | * selected ECC mode | |
207 | */ | |
208 | struct sunxi_nand_hw_ecc { | |
209 | int mode; | |
210 | struct nand_ecclayout layout; | |
211 | }; | |
212 | ||
213 | /* | |
214 | * NAND chip structure: stores NAND chip device related information | |
215 | * | |
216 | * @node: used to store NAND chips into a list | |
217 | * @nand: base NAND chip structure | |
218 | * @mtd: base MTD structure | |
219 | * @clk_rate: clk_rate required for this NAND chip | |
9c618292 | 220 | * @timing_cfg TIMING_CFG register value for this NAND chip |
1fef62c1 BB |
221 | * @selected: current active CS |
222 | * @nsels: number of CS lines required by the NAND chip | |
223 | * @sels: array of CS lines descriptions | |
224 | */ | |
225 | struct sunxi_nand_chip { | |
226 | struct list_head node; | |
227 | struct nand_chip nand; | |
228 | struct mtd_info mtd; | |
229 | unsigned long clk_rate; | |
9c618292 | 230 | u32 timing_cfg; |
d052e508 | 231 | u32 timing_ctl; |
1fef62c1 BB |
232 | int selected; |
233 | int nsels; | |
234 | struct sunxi_nand_chip_sel sels[0]; | |
235 | }; | |
236 | ||
237 | static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) | |
238 | { | |
239 | return container_of(nand, struct sunxi_nand_chip, nand); | |
240 | } | |
241 | ||
242 | /* | |
243 | * NAND Controller structure: stores sunxi NAND controller information | |
244 | * | |
245 | * @controller: base controller structure | |
246 | * @dev: parent device (used to print error messages) | |
247 | * @regs: NAND controller registers | |
248 | * @ahb_clk: NAND Controller AHB clock | |
249 | * @mod_clk: NAND Controller mod clock | |
250 | * @assigned_cs: bitmask describing already assigned CS lines | |
251 | * @clk_rate: NAND controller current clock rate | |
252 | * @chips: a list containing all the NAND chips attached to | |
253 | * this NAND controller | |
254 | * @complete: a completion object used to wait for NAND | |
255 | * controller events | |
256 | */ | |
257 | struct sunxi_nfc { | |
258 | struct nand_hw_control controller; | |
259 | struct device *dev; | |
260 | void __iomem *regs; | |
261 | struct clk *ahb_clk; | |
262 | struct clk *mod_clk; | |
263 | unsigned long assigned_cs; | |
264 | unsigned long clk_rate; | |
265 | struct list_head chips; | |
266 | struct completion complete; | |
267 | }; | |
268 | ||
269 | static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl) | |
270 | { | |
271 | return container_of(ctrl, struct sunxi_nfc, controller); | |
272 | } | |
273 | ||
274 | static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id) | |
275 | { | |
276 | struct sunxi_nfc *nfc = dev_id; | |
277 | u32 st = readl(nfc->regs + NFC_REG_ST); | |
278 | u32 ien = readl(nfc->regs + NFC_REG_INT); | |
279 | ||
280 | if (!(ien & st)) | |
281 | return IRQ_NONE; | |
282 | ||
283 | if ((ien & st) == ien) | |
284 | complete(&nfc->complete); | |
285 | ||
286 | writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST); | |
287 | writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT); | |
288 | ||
289 | return IRQ_HANDLED; | |
290 | } | |
291 | ||
292 | static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags, | |
293 | unsigned int timeout_ms) | |
294 | { | |
295 | init_completion(&nfc->complete); | |
296 | ||
297 | writel(flags, nfc->regs + NFC_REG_INT); | |
298 | ||
299 | if (!timeout_ms) | |
300 | timeout_ms = NFC_DEFAULT_TIMEOUT_MS; | |
301 | ||
302 | if (!wait_for_completion_timeout(&nfc->complete, | |
303 | msecs_to_jiffies(timeout_ms))) { | |
304 | dev_err(nfc->dev, "wait interrupt timedout\n"); | |
305 | return -ETIMEDOUT; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc) | |
312 | { | |
313 | unsigned long timeout = jiffies + | |
314 | msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS); | |
315 | ||
316 | do { | |
317 | if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS)) | |
318 | return 0; | |
319 | } while (time_before(jiffies, timeout)); | |
320 | ||
321 | dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n"); | |
322 | return -ETIMEDOUT; | |
323 | } | |
324 | ||
325 | static int sunxi_nfc_rst(struct sunxi_nfc *nfc) | |
326 | { | |
327 | unsigned long timeout = jiffies + | |
328 | msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS); | |
329 | ||
330 | writel(0, nfc->regs + NFC_REG_ECC_CTL); | |
331 | writel(NFC_RESET, nfc->regs + NFC_REG_CTL); | |
332 | ||
333 | do { | |
334 | if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)) | |
335 | return 0; | |
336 | } while (time_before(jiffies, timeout)); | |
337 | ||
338 | dev_err(nfc->dev, "wait for NAND controller reset timedout\n"); | |
339 | return -ETIMEDOUT; | |
340 | } | |
341 | ||
342 | static int sunxi_nfc_dev_ready(struct mtd_info *mtd) | |
343 | { | |
344 | struct nand_chip *nand = mtd->priv; | |
345 | struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); | |
346 | struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); | |
347 | struct sunxi_nand_rb *rb; | |
348 | unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20); | |
349 | int ret; | |
350 | ||
351 | if (sunxi_nand->selected < 0) | |
352 | return 0; | |
353 | ||
354 | rb = &sunxi_nand->sels[sunxi_nand->selected].rb; | |
355 | ||
356 | switch (rb->type) { | |
357 | case RB_NATIVE: | |
358 | ret = !!(readl(nfc->regs + NFC_REG_ST) & | |
359 | (NFC_RB_STATE0 << rb->info.nativeid)); | |
360 | if (ret) | |
361 | break; | |
362 | ||
363 | sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo); | |
364 | ret = !!(readl(nfc->regs + NFC_REG_ST) & | |
365 | (NFC_RB_STATE0 << rb->info.nativeid)); | |
366 | break; | |
367 | case RB_GPIO: | |
368 | ret = gpio_get_value(rb->info.gpio); | |
369 | break; | |
370 | case RB_NONE: | |
371 | default: | |
372 | ret = 0; | |
373 | dev_err(nfc->dev, "cannot check R/B NAND status!\n"); | |
374 | break; | |
375 | } | |
376 | ||
377 | return ret; | |
378 | } | |
379 | ||
380 | static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip) | |
381 | { | |
382 | struct nand_chip *nand = mtd->priv; | |
383 | struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); | |
384 | struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); | |
385 | struct sunxi_nand_chip_sel *sel; | |
386 | u32 ctl; | |
387 | ||
388 | if (chip > 0 && chip >= sunxi_nand->nsels) | |
389 | return; | |
390 | ||
391 | if (chip == sunxi_nand->selected) | |
392 | return; | |
393 | ||
394 | ctl = readl(nfc->regs + NFC_REG_CTL) & | |
395 | ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN); | |
396 | ||
397 | if (chip >= 0) { | |
398 | sel = &sunxi_nand->sels[chip]; | |
399 | ||
400 | ctl |= (sel->cs << 24) | NFC_EN | | |
401 | (((nand->page_shift - 10) & 0xf) << 8); | |
402 | if (sel->rb.type == RB_NONE) { | |
403 | nand->dev_ready = NULL; | |
404 | } else { | |
405 | nand->dev_ready = sunxi_nfc_dev_ready; | |
406 | if (sel->rb.type == RB_NATIVE) | |
407 | ctl |= (sel->rb.info.nativeid << 3); | |
408 | } | |
409 | ||
410 | writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA); | |
411 | ||
412 | if (nfc->clk_rate != sunxi_nand->clk_rate) { | |
413 | clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate); | |
414 | nfc->clk_rate = sunxi_nand->clk_rate; | |
415 | } | |
416 | } | |
417 | ||
d052e508 | 418 | writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL); |
9c618292 | 419 | writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG); |
1fef62c1 BB |
420 | writel(ctl, nfc->regs + NFC_REG_CTL); |
421 | ||
422 | sunxi_nand->selected = chip; | |
423 | } | |
424 | ||
425 | static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
426 | { | |
427 | struct nand_chip *nand = mtd->priv; | |
428 | struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); | |
429 | struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); | |
430 | int ret; | |
431 | int cnt; | |
432 | int offs = 0; | |
433 | u32 tmp; | |
434 | ||
435 | while (len > offs) { | |
436 | cnt = min(len - offs, NFC_SRAM_SIZE); | |
437 | ||
438 | ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); | |
439 | if (ret) | |
440 | break; | |
441 | ||
442 | writel(cnt, nfc->regs + NFC_REG_CNT); | |
443 | tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; | |
444 | writel(tmp, nfc->regs + NFC_REG_CMD); | |
445 | ||
446 | ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
447 | if (ret) | |
448 | break; | |
449 | ||
450 | if (buf) | |
451 | memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE, | |
452 | cnt); | |
453 | offs += cnt; | |
454 | } | |
455 | } | |
456 | ||
457 | static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, | |
458 | int len) | |
459 | { | |
460 | struct nand_chip *nand = mtd->priv; | |
461 | struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); | |
462 | struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); | |
463 | int ret; | |
464 | int cnt; | |
465 | int offs = 0; | |
466 | u32 tmp; | |
467 | ||
468 | while (len > offs) { | |
469 | cnt = min(len - offs, NFC_SRAM_SIZE); | |
470 | ||
471 | ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); | |
472 | if (ret) | |
473 | break; | |
474 | ||
475 | writel(cnt, nfc->regs + NFC_REG_CNT); | |
476 | memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt); | |
477 | tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | | |
478 | NFC_ACCESS_DIR; | |
479 | writel(tmp, nfc->regs + NFC_REG_CMD); | |
480 | ||
481 | ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
482 | if (ret) | |
483 | break; | |
484 | ||
485 | offs += cnt; | |
486 | } | |
487 | } | |
488 | ||
489 | static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd) | |
490 | { | |
491 | uint8_t ret; | |
492 | ||
493 | sunxi_nfc_read_buf(mtd, &ret, 1); | |
494 | ||
495 | return ret; | |
496 | } | |
497 | ||
498 | static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, | |
499 | unsigned int ctrl) | |
500 | { | |
501 | struct nand_chip *nand = mtd->priv; | |
502 | struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); | |
503 | struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); | |
504 | int ret; | |
505 | u32 tmp; | |
506 | ||
507 | ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); | |
508 | if (ret) | |
509 | return; | |
510 | ||
511 | if (ctrl & NAND_CTRL_CHANGE) { | |
512 | tmp = readl(nfc->regs + NFC_REG_CTL); | |
513 | if (ctrl & NAND_NCE) | |
514 | tmp |= NFC_CE_CTL; | |
515 | else | |
516 | tmp &= ~NFC_CE_CTL; | |
517 | writel(tmp, nfc->regs + NFC_REG_CTL); | |
518 | } | |
519 | ||
520 | if (dat == NAND_CMD_NONE) | |
521 | return; | |
522 | ||
523 | if (ctrl & NAND_CLE) { | |
524 | writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD); | |
525 | } else { | |
526 | writel(dat, nfc->regs + NFC_REG_ADDR_LOW); | |
527 | writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD); | |
528 | } | |
529 | ||
530 | sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
531 | } | |
532 | ||
533 | static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd, | |
534 | struct nand_chip *chip, uint8_t *buf, | |
535 | int oob_required, int page) | |
536 | { | |
537 | struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); | |
538 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
539 | struct nand_ecclayout *layout = ecc->layout; | |
540 | struct sunxi_nand_hw_ecc *data = ecc->priv; | |
541 | unsigned int max_bitflips = 0; | |
542 | int offset; | |
543 | int ret; | |
544 | u32 tmp; | |
545 | int i; | |
546 | int cnt; | |
547 | ||
548 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
549 | tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); | |
550 | tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | | |
551 | NFC_ECC_EXCEPTION; | |
552 | ||
553 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
554 | ||
555 | for (i = 0; i < ecc->steps; i++) { | |
556 | if (i) | |
557 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1); | |
558 | ||
559 | offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4; | |
560 | ||
561 | chip->read_buf(mtd, NULL, ecc->size); | |
562 | ||
563 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); | |
564 | ||
565 | ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); | |
566 | if (ret) | |
567 | return ret; | |
568 | ||
569 | tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30); | |
570 | writel(tmp, nfc->regs + NFC_REG_CMD); | |
571 | ||
572 | ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
573 | if (ret) | |
574 | return ret; | |
575 | ||
576 | memcpy_fromio(buf + (i * ecc->size), | |
577 | nfc->regs + NFC_RAM0_BASE, ecc->size); | |
578 | ||
579 | if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) { | |
580 | mtd->ecc_stats.failed++; | |
581 | } else { | |
582 | tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff; | |
583 | mtd->ecc_stats.corrected += tmp; | |
584 | max_bitflips = max_t(unsigned int, max_bitflips, tmp); | |
585 | } | |
586 | ||
587 | if (oob_required) { | |
588 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); | |
589 | ||
590 | ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); | |
591 | if (ret) | |
592 | return ret; | |
593 | ||
594 | offset -= mtd->writesize; | |
595 | chip->read_buf(mtd, chip->oob_poi + offset, | |
596 | ecc->bytes + 4); | |
597 | } | |
598 | } | |
599 | ||
600 | if (oob_required) { | |
601 | cnt = ecc->layout->oobfree[ecc->steps].length; | |
602 | if (cnt > 0) { | |
603 | offset = mtd->writesize + | |
604 | ecc->layout->oobfree[ecc->steps].offset; | |
605 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); | |
606 | offset -= mtd->writesize; | |
607 | chip->read_buf(mtd, chip->oob_poi + offset, cnt); | |
608 | } | |
609 | } | |
610 | ||
611 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
612 | tmp &= ~NFC_ECC_EN; | |
613 | ||
614 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
615 | ||
616 | return max_bitflips; | |
617 | } | |
618 | ||
619 | static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd, | |
620 | struct nand_chip *chip, | |
621 | const uint8_t *buf, int oob_required) | |
622 | { | |
623 | struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); | |
624 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
625 | struct nand_ecclayout *layout = ecc->layout; | |
626 | struct sunxi_nand_hw_ecc *data = ecc->priv; | |
627 | int offset; | |
628 | int ret; | |
629 | u32 tmp; | |
630 | int i; | |
631 | int cnt; | |
632 | ||
633 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
634 | tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); | |
635 | tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | | |
636 | NFC_ECC_EXCEPTION; | |
637 | ||
638 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
639 | ||
640 | for (i = 0; i < ecc->steps; i++) { | |
641 | if (i) | |
642 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1); | |
643 | ||
644 | chip->write_buf(mtd, buf + (i * ecc->size), ecc->size); | |
645 | ||
646 | offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize; | |
647 | ||
648 | /* Fill OOB data in */ | |
649 | if (oob_required) { | |
650 | tmp = 0xffffffff; | |
651 | memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, &tmp, | |
652 | 4); | |
653 | } else { | |
654 | memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, | |
655 | chip->oob_poi + offset - mtd->writesize, | |
656 | 4); | |
657 | } | |
658 | ||
659 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1); | |
660 | ||
661 | ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); | |
662 | if (ret) | |
663 | return ret; | |
664 | ||
665 | tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR | | |
666 | (1 << 30); | |
667 | writel(tmp, nfc->regs + NFC_REG_CMD); | |
668 | ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
669 | if (ret) | |
670 | return ret; | |
671 | } | |
672 | ||
673 | if (oob_required) { | |
674 | cnt = ecc->layout->oobfree[i].length; | |
675 | if (cnt > 0) { | |
676 | offset = mtd->writesize + | |
677 | ecc->layout->oobfree[i].offset; | |
678 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1); | |
679 | offset -= mtd->writesize; | |
680 | chip->write_buf(mtd, chip->oob_poi + offset, cnt); | |
681 | } | |
682 | } | |
683 | ||
684 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
685 | tmp &= ~NFC_ECC_EN; | |
686 | ||
687 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd, | |
693 | struct nand_chip *chip, | |
694 | uint8_t *buf, int oob_required, | |
695 | int page) | |
696 | { | |
697 | struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); | |
698 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
699 | struct sunxi_nand_hw_ecc *data = ecc->priv; | |
700 | unsigned int max_bitflips = 0; | |
701 | uint8_t *oob = chip->oob_poi; | |
702 | int offset = 0; | |
703 | int ret; | |
704 | int cnt; | |
705 | u32 tmp; | |
706 | int i; | |
707 | ||
708 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
709 | tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); | |
710 | tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | | |
711 | NFC_ECC_EXCEPTION; | |
712 | ||
713 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
714 | ||
715 | for (i = 0; i < ecc->steps; i++) { | |
716 | chip->read_buf(mtd, NULL, ecc->size); | |
717 | ||
718 | tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30); | |
719 | writel(tmp, nfc->regs + NFC_REG_CMD); | |
720 | ||
721 | ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
722 | if (ret) | |
723 | return ret; | |
724 | ||
725 | memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size); | |
726 | buf += ecc->size; | |
727 | offset += ecc->size; | |
728 | ||
729 | if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) { | |
730 | mtd->ecc_stats.failed++; | |
731 | } else { | |
732 | tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff; | |
733 | mtd->ecc_stats.corrected += tmp; | |
734 | max_bitflips = max_t(unsigned int, max_bitflips, tmp); | |
735 | } | |
736 | ||
737 | if (oob_required) { | |
738 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); | |
739 | chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad); | |
740 | oob += ecc->bytes + ecc->prepad; | |
741 | } | |
742 | ||
743 | offset += ecc->bytes + ecc->prepad; | |
744 | } | |
745 | ||
746 | if (oob_required) { | |
747 | cnt = mtd->oobsize - (oob - chip->oob_poi); | |
748 | if (cnt > 0) { | |
749 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); | |
750 | chip->read_buf(mtd, oob, cnt); | |
751 | } | |
752 | } | |
753 | ||
754 | writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN, | |
755 | nfc->regs + NFC_REG_ECC_CTL); | |
756 | ||
757 | return max_bitflips; | |
758 | } | |
759 | ||
760 | static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd, | |
761 | struct nand_chip *chip, | |
762 | const uint8_t *buf, | |
763 | int oob_required) | |
764 | { | |
765 | struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); | |
766 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
767 | struct sunxi_nand_hw_ecc *data = ecc->priv; | |
768 | uint8_t *oob = chip->oob_poi; | |
769 | int offset = 0; | |
770 | int ret; | |
771 | int cnt; | |
772 | u32 tmp; | |
773 | int i; | |
774 | ||
775 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
776 | tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); | |
777 | tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | | |
778 | NFC_ECC_EXCEPTION; | |
779 | ||
780 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
781 | ||
782 | for (i = 0; i < ecc->steps; i++) { | |
783 | chip->write_buf(mtd, buf + (i * ecc->size), ecc->size); | |
784 | offset += ecc->size; | |
785 | ||
786 | /* Fill OOB data in */ | |
787 | if (oob_required) { | |
788 | tmp = 0xffffffff; | |
789 | memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, &tmp, | |
790 | 4); | |
791 | } else { | |
792 | memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, oob, | |
793 | 4); | |
794 | } | |
795 | ||
796 | tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR | | |
797 | (1 << 30); | |
798 | writel(tmp, nfc->regs + NFC_REG_CMD); | |
799 | ||
800 | ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); | |
801 | if (ret) | |
802 | return ret; | |
803 | ||
804 | offset += ecc->bytes + ecc->prepad; | |
805 | oob += ecc->bytes + ecc->prepad; | |
806 | } | |
807 | ||
808 | if (oob_required) { | |
809 | cnt = mtd->oobsize - (oob - chip->oob_poi); | |
810 | if (cnt > 0) { | |
811 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1); | |
812 | chip->write_buf(mtd, oob, cnt); | |
813 | } | |
814 | } | |
815 | ||
816 | tmp = readl(nfc->regs + NFC_REG_ECC_CTL); | |
817 | tmp &= ~NFC_ECC_EN; | |
818 | ||
819 | writel(tmp, nfc->regs + NFC_REG_ECC_CTL); | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
9c618292 RS |
824 | static const s32 tWB_lut[] = {6, 12, 16, 20}; |
825 | static const s32 tRHW_lut[] = {4, 8, 12, 20}; | |
826 | ||
827 | static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration, | |
828 | u32 clk_period) | |
829 | { | |
830 | u32 clk_cycles = DIV_ROUND_UP(duration, clk_period); | |
831 | int i; | |
832 | ||
833 | for (i = 0; i < lut_size; i++) { | |
834 | if (clk_cycles <= lut[i]) | |
835 | return i; | |
836 | } | |
837 | ||
838 | /* Doesn't fit */ | |
839 | return -EINVAL; | |
840 | } | |
841 | ||
842 | #define sunxi_nand_lookup_timing(l, p, c) \ | |
843 | _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c) | |
844 | ||
1fef62c1 BB |
845 | static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, |
846 | const struct nand_sdr_timings *timings) | |
847 | { | |
9c618292 | 848 | struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller); |
1fef62c1 | 849 | u32 min_clk_period = 0; |
9c618292 | 850 | s32 tWB, tADL, tWHR, tRHW, tCAD; |
1fef62c1 BB |
851 | |
852 | /* T1 <=> tCLS */ | |
853 | if (timings->tCLS_min > min_clk_period) | |
854 | min_clk_period = timings->tCLS_min; | |
855 | ||
856 | /* T2 <=> tCLH */ | |
857 | if (timings->tCLH_min > min_clk_period) | |
858 | min_clk_period = timings->tCLH_min; | |
859 | ||
860 | /* T3 <=> tCS */ | |
861 | if (timings->tCS_min > min_clk_period) | |
862 | min_clk_period = timings->tCS_min; | |
863 | ||
864 | /* T4 <=> tCH */ | |
865 | if (timings->tCH_min > min_clk_period) | |
866 | min_clk_period = timings->tCH_min; | |
867 | ||
868 | /* T5 <=> tWP */ | |
869 | if (timings->tWP_min > min_clk_period) | |
870 | min_clk_period = timings->tWP_min; | |
871 | ||
872 | /* T6 <=> tWH */ | |
873 | if (timings->tWH_min > min_clk_period) | |
874 | min_clk_period = timings->tWH_min; | |
875 | ||
876 | /* T7 <=> tALS */ | |
877 | if (timings->tALS_min > min_clk_period) | |
878 | min_clk_period = timings->tALS_min; | |
879 | ||
880 | /* T8 <=> tDS */ | |
881 | if (timings->tDS_min > min_clk_period) | |
882 | min_clk_period = timings->tDS_min; | |
883 | ||
884 | /* T9 <=> tDH */ | |
885 | if (timings->tDH_min > min_clk_period) | |
886 | min_clk_period = timings->tDH_min; | |
887 | ||
888 | /* T10 <=> tRR */ | |
889 | if (timings->tRR_min > (min_clk_period * 3)) | |
890 | min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3); | |
891 | ||
892 | /* T11 <=> tALH */ | |
893 | if (timings->tALH_min > min_clk_period) | |
894 | min_clk_period = timings->tALH_min; | |
895 | ||
896 | /* T12 <=> tRP */ | |
897 | if (timings->tRP_min > min_clk_period) | |
898 | min_clk_period = timings->tRP_min; | |
899 | ||
900 | /* T13 <=> tREH */ | |
901 | if (timings->tREH_min > min_clk_period) | |
902 | min_clk_period = timings->tREH_min; | |
903 | ||
904 | /* T14 <=> tRC */ | |
905 | if (timings->tRC_min > (min_clk_period * 2)) | |
906 | min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2); | |
907 | ||
908 | /* T15 <=> tWC */ | |
909 | if (timings->tWC_min > (min_clk_period * 2)) | |
910 | min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); | |
911 | ||
9c618292 RS |
912 | /* T16 - T19 + tCAD */ |
913 | tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, | |
914 | min_clk_period); | |
915 | if (tWB < 0) { | |
916 | dev_err(nfc->dev, "unsupported tWB\n"); | |
917 | return tWB; | |
918 | } | |
919 | ||
920 | tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; | |
921 | if (tADL > 3) { | |
922 | dev_err(nfc->dev, "unsupported tADL\n"); | |
923 | return -EINVAL; | |
924 | } | |
925 | ||
926 | tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; | |
927 | if (tWHR > 3) { | |
928 | dev_err(nfc->dev, "unsupported tWHR\n"); | |
929 | return -EINVAL; | |
930 | } | |
931 | ||
932 | tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, | |
933 | min_clk_period); | |
934 | if (tRHW < 0) { | |
935 | dev_err(nfc->dev, "unsupported tRHW\n"); | |
936 | return tRHW; | |
937 | } | |
938 | ||
939 | /* | |
940 | * TODO: according to ONFI specs this value only applies for DDR NAND, | |
941 | * but Allwinner seems to set this to 0x7. Mimic them for now. | |
942 | */ | |
943 | tCAD = 0x7; | |
944 | ||
945 | /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ | |
946 | chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD); | |
1fef62c1 | 947 | |
d052e508 RS |
948 | /* |
949 | * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data | |
950 | * output cycle timings shall be used if the host drives tRC less than | |
951 | * 30 ns. | |
952 | */ | |
953 | chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0; | |
954 | ||
1fef62c1 BB |
955 | /* Convert min_clk_period from picoseconds to nanoseconds */ |
956 | min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); | |
957 | ||
958 | /* | |
959 | * Convert min_clk_period into a clk frequency, then get the | |
960 | * appropriate rate for the NAND controller IP given this formula | |
961 | * (specified in the datasheet): | |
962 | * nand clk_rate = 2 * min_clk_rate | |
963 | */ | |
964 | chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period; | |
965 | ||
1fef62c1 BB |
966 | return 0; |
967 | } | |
968 | ||
969 | static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip, | |
970 | struct device_node *np) | |
971 | { | |
972 | const struct nand_sdr_timings *timings; | |
973 | int ret; | |
974 | int mode; | |
975 | ||
976 | mode = onfi_get_async_timing_mode(&chip->nand); | |
977 | if (mode == ONFI_TIMING_MODE_UNKNOWN) { | |
978 | mode = chip->nand.onfi_timing_mode_default; | |
979 | } else { | |
980 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {}; | |
981 | ||
982 | mode = fls(mode) - 1; | |
983 | if (mode < 0) | |
984 | mode = 0; | |
985 | ||
986 | feature[0] = mode; | |
987 | ret = chip->nand.onfi_set_features(&chip->mtd, &chip->nand, | |
988 | ONFI_FEATURE_ADDR_TIMING_MODE, | |
989 | feature); | |
990 | if (ret) | |
991 | return ret; | |
992 | } | |
993 | ||
994 | timings = onfi_async_timing_mode_to_sdr_timings(mode); | |
995 | if (IS_ERR(timings)) | |
996 | return PTR_ERR(timings); | |
997 | ||
998 | return sunxi_nand_chip_set_timings(chip, timings); | |
999 | } | |
1000 | ||
1001 | static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, | |
1002 | struct nand_ecc_ctrl *ecc, | |
1003 | struct device_node *np) | |
1004 | { | |
1005 | static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; | |
1006 | struct nand_chip *nand = mtd->priv; | |
1007 | struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); | |
1008 | struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); | |
1009 | struct sunxi_nand_hw_ecc *data; | |
1010 | struct nand_ecclayout *layout; | |
1011 | int nsectors; | |
1012 | int ret; | |
1013 | int i; | |
1014 | ||
1015 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1016 | if (!data) | |
1017 | return -ENOMEM; | |
1018 | ||
1019 | /* Add ECC info retrieval from DT */ | |
1020 | for (i = 0; i < ARRAY_SIZE(strengths); i++) { | |
1021 | if (ecc->strength <= strengths[i]) | |
1022 | break; | |
1023 | } | |
1024 | ||
1025 | if (i >= ARRAY_SIZE(strengths)) { | |
1026 | dev_err(nfc->dev, "unsupported strength\n"); | |
1027 | ret = -ENOTSUPP; | |
1028 | goto err; | |
1029 | } | |
1030 | ||
1031 | data->mode = i; | |
1032 | ||
1033 | /* HW ECC always request ECC bytes for 1024 bytes blocks */ | |
1034 | ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8); | |
1035 | ||
1036 | /* HW ECC always work with even numbers of ECC bytes */ | |
1037 | ecc->bytes = ALIGN(ecc->bytes, 2); | |
1038 | ||
1039 | layout = &data->layout; | |
1040 | nsectors = mtd->writesize / ecc->size; | |
1041 | ||
1042 | if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) { | |
1043 | ret = -EINVAL; | |
1044 | goto err; | |
1045 | } | |
1046 | ||
1047 | layout->eccbytes = (ecc->bytes * nsectors); | |
1048 | ||
1049 | ecc->layout = layout; | |
1050 | ecc->priv = data; | |
1051 | ||
1052 | return 0; | |
1053 | ||
1054 | err: | |
1055 | kfree(data); | |
1056 | ||
1057 | return ret; | |
1058 | } | |
1059 | ||
1060 | static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc) | |
1061 | { | |
1062 | kfree(ecc->priv); | |
1063 | } | |
1064 | ||
1065 | static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, | |
1066 | struct nand_ecc_ctrl *ecc, | |
1067 | struct device_node *np) | |
1068 | { | |
1069 | struct nand_ecclayout *layout; | |
1070 | int nsectors; | |
1071 | int i, j; | |
1072 | int ret; | |
1073 | ||
1074 | ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np); | |
1075 | if (ret) | |
1076 | return ret; | |
1077 | ||
1078 | ecc->read_page = sunxi_nfc_hw_ecc_read_page; | |
1079 | ecc->write_page = sunxi_nfc_hw_ecc_write_page; | |
1080 | layout = ecc->layout; | |
1081 | nsectors = mtd->writesize / ecc->size; | |
1082 | ||
1083 | for (i = 0; i < nsectors; i++) { | |
1084 | if (i) { | |
1085 | layout->oobfree[i].offset = | |
1086 | layout->oobfree[i - 1].offset + | |
1087 | layout->oobfree[i - 1].length + | |
1088 | ecc->bytes; | |
1089 | layout->oobfree[i].length = 4; | |
1090 | } else { | |
1091 | /* | |
1092 | * The first 2 bytes are used for BB markers, hence we | |
1093 | * only have 2 bytes available in the first user data | |
1094 | * section. | |
1095 | */ | |
1096 | layout->oobfree[i].length = 2; | |
1097 | layout->oobfree[i].offset = 2; | |
1098 | } | |
1099 | ||
1100 | for (j = 0; j < ecc->bytes; j++) | |
1101 | layout->eccpos[(ecc->bytes * i) + j] = | |
1102 | layout->oobfree[i].offset + | |
1103 | layout->oobfree[i].length + j; | |
1104 | } | |
1105 | ||
1106 | if (mtd->oobsize > (ecc->bytes + 4) * nsectors) { | |
1107 | layout->oobfree[nsectors].offset = | |
1108 | layout->oobfree[nsectors - 1].offset + | |
1109 | layout->oobfree[nsectors - 1].length + | |
1110 | ecc->bytes; | |
1111 | layout->oobfree[nsectors].length = mtd->oobsize - | |
1112 | ((ecc->bytes + 4) * nsectors); | |
1113 | } | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd, | |
1119 | struct nand_ecc_ctrl *ecc, | |
1120 | struct device_node *np) | |
1121 | { | |
1122 | struct nand_ecclayout *layout; | |
1123 | int nsectors; | |
1124 | int i; | |
1125 | int ret; | |
1126 | ||
1127 | ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np); | |
1128 | if (ret) | |
1129 | return ret; | |
1130 | ||
1131 | ecc->prepad = 4; | |
1132 | ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page; | |
1133 | ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page; | |
1134 | ||
1135 | layout = ecc->layout; | |
1136 | nsectors = mtd->writesize / ecc->size; | |
1137 | ||
1138 | for (i = 0; i < (ecc->bytes * nsectors); i++) | |
1139 | layout->eccpos[i] = i; | |
1140 | ||
1141 | layout->oobfree[0].length = mtd->oobsize - i; | |
1142 | layout->oobfree[0].offset = i; | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc) | |
1148 | { | |
1149 | switch (ecc->mode) { | |
1150 | case NAND_ECC_HW: | |
1151 | case NAND_ECC_HW_SYNDROME: | |
1152 | sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc); | |
1153 | break; | |
1154 | case NAND_ECC_NONE: | |
1155 | kfree(ecc->layout); | |
1156 | default: | |
1157 | break; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc, | |
1162 | struct device_node *np) | |
1163 | { | |
1164 | struct nand_chip *nand = mtd->priv; | |
1165 | int strength; | |
1166 | int blk_size; | |
1167 | int ret; | |
1168 | ||
1169 | blk_size = of_get_nand_ecc_step_size(np); | |
1170 | strength = of_get_nand_ecc_strength(np); | |
1171 | if (blk_size > 0 && strength > 0) { | |
1172 | ecc->size = blk_size; | |
1173 | ecc->strength = strength; | |
1174 | } else { | |
1175 | ecc->size = nand->ecc_step_ds; | |
1176 | ecc->strength = nand->ecc_strength_ds; | |
1177 | } | |
1178 | ||
1179 | if (!ecc->size || !ecc->strength) | |
1180 | return -EINVAL; | |
1181 | ||
1182 | ecc->mode = NAND_ECC_HW; | |
1183 | ||
1184 | ret = of_get_nand_ecc_mode(np); | |
1185 | if (ret >= 0) | |
1186 | ecc->mode = ret; | |
1187 | ||
1188 | switch (ecc->mode) { | |
1189 | case NAND_ECC_SOFT_BCH: | |
1fef62c1 BB |
1190 | break; |
1191 | case NAND_ECC_HW: | |
1192 | ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np); | |
1193 | if (ret) | |
1194 | return ret; | |
1195 | break; | |
1196 | case NAND_ECC_HW_SYNDROME: | |
1197 | ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np); | |
1198 | if (ret) | |
1199 | return ret; | |
1200 | break; | |
1201 | case NAND_ECC_NONE: | |
1202 | ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL); | |
1203 | if (!ecc->layout) | |
1204 | return -ENOMEM; | |
1205 | ecc->layout->oobfree[0].length = mtd->oobsize; | |
1206 | case NAND_ECC_SOFT: | |
1207 | break; | |
1208 | default: | |
1209 | return -EINVAL; | |
1210 | } | |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc, | |
1216 | struct device_node *np) | |
1217 | { | |
1218 | const struct nand_sdr_timings *timings; | |
1219 | struct sunxi_nand_chip *chip; | |
1220 | struct mtd_part_parser_data ppdata; | |
1221 | struct mtd_info *mtd; | |
1222 | struct nand_chip *nand; | |
1223 | int nsels; | |
1224 | int ret; | |
1225 | int i; | |
1226 | u32 tmp; | |
1227 | ||
1228 | if (!of_get_property(np, "reg", &nsels)) | |
1229 | return -EINVAL; | |
1230 | ||
1231 | nsels /= sizeof(u32); | |
1232 | if (!nsels) { | |
1233 | dev_err(dev, "invalid reg property size\n"); | |
1234 | return -EINVAL; | |
1235 | } | |
1236 | ||
1237 | chip = devm_kzalloc(dev, | |
1238 | sizeof(*chip) + | |
1239 | (nsels * sizeof(struct sunxi_nand_chip_sel)), | |
1240 | GFP_KERNEL); | |
1241 | if (!chip) { | |
1242 | dev_err(dev, "could not allocate chip\n"); | |
1243 | return -ENOMEM; | |
1244 | } | |
1245 | ||
1246 | chip->nsels = nsels; | |
1247 | chip->selected = -1; | |
1248 | ||
1249 | for (i = 0; i < nsels; i++) { | |
1250 | ret = of_property_read_u32_index(np, "reg", i, &tmp); | |
1251 | if (ret) { | |
1252 | dev_err(dev, "could not retrieve reg property: %d\n", | |
1253 | ret); | |
1254 | return ret; | |
1255 | } | |
1256 | ||
1257 | if (tmp > NFC_MAX_CS) { | |
1258 | dev_err(dev, | |
1259 | "invalid reg value: %u (max CS = 7)\n", | |
1260 | tmp); | |
1261 | return -EINVAL; | |
1262 | } | |
1263 | ||
1264 | if (test_and_set_bit(tmp, &nfc->assigned_cs)) { | |
1265 | dev_err(dev, "CS %d already assigned\n", tmp); | |
1266 | return -EINVAL; | |
1267 | } | |
1268 | ||
1269 | chip->sels[i].cs = tmp; | |
1270 | ||
1271 | if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) && | |
1272 | tmp < 2) { | |
1273 | chip->sels[i].rb.type = RB_NATIVE; | |
1274 | chip->sels[i].rb.info.nativeid = tmp; | |
1275 | } else { | |
1276 | ret = of_get_named_gpio(np, "rb-gpios", i); | |
1277 | if (ret >= 0) { | |
1278 | tmp = ret; | |
1279 | chip->sels[i].rb.type = RB_GPIO; | |
1280 | chip->sels[i].rb.info.gpio = tmp; | |
1281 | ret = devm_gpio_request(dev, tmp, "nand-rb"); | |
1282 | if (ret) | |
1283 | return ret; | |
1284 | ||
1285 | ret = gpio_direction_input(tmp); | |
1286 | if (ret) | |
1287 | return ret; | |
1288 | } else { | |
1289 | chip->sels[i].rb.type = RB_NONE; | |
1290 | } | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | timings = onfi_async_timing_mode_to_sdr_timings(0); | |
1295 | if (IS_ERR(timings)) { | |
1296 | ret = PTR_ERR(timings); | |
1297 | dev_err(dev, | |
1298 | "could not retrieve timings for ONFI mode 0: %d\n", | |
1299 | ret); | |
1300 | return ret; | |
1301 | } | |
1302 | ||
1303 | ret = sunxi_nand_chip_set_timings(chip, timings); | |
1304 | if (ret) { | |
1305 | dev_err(dev, "could not configure chip timings: %d\n", ret); | |
1306 | return ret; | |
1307 | } | |
1308 | ||
1309 | nand = &chip->nand; | |
1310 | /* Default tR value specified in the ONFI spec (chapter 4.15.1) */ | |
1311 | nand->chip_delay = 200; | |
1312 | nand->controller = &nfc->controller; | |
1313 | nand->select_chip = sunxi_nfc_select_chip; | |
1314 | nand->cmd_ctrl = sunxi_nfc_cmd_ctrl; | |
1315 | nand->read_buf = sunxi_nfc_read_buf; | |
1316 | nand->write_buf = sunxi_nfc_write_buf; | |
1317 | nand->read_byte = sunxi_nfc_read_byte; | |
1318 | ||
1319 | if (of_get_nand_on_flash_bbt(np)) | |
1320 | nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; | |
1321 | ||
1322 | mtd = &chip->mtd; | |
1323 | mtd->dev.parent = dev; | |
1324 | mtd->priv = nand; | |
1325 | mtd->owner = THIS_MODULE; | |
1326 | ||
1327 | ret = nand_scan_ident(mtd, nsels, NULL); | |
1328 | if (ret) | |
1329 | return ret; | |
1330 | ||
1331 | ret = sunxi_nand_chip_init_timings(chip, np); | |
1332 | if (ret) { | |
1333 | dev_err(dev, "could not configure chip timings: %d\n", ret); | |
1334 | return ret; | |
1335 | } | |
1336 | ||
1337 | ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np); | |
1338 | if (ret) { | |
1339 | dev_err(dev, "ECC init failed: %d\n", ret); | |
1340 | return ret; | |
1341 | } | |
1342 | ||
1343 | ret = nand_scan_tail(mtd); | |
1344 | if (ret) { | |
1345 | dev_err(dev, "nand_scan_tail failed: %d\n", ret); | |
1346 | return ret; | |
1347 | } | |
1348 | ||
1349 | ppdata.of_node = np; | |
1350 | ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); | |
1351 | if (ret) { | |
1352 | dev_err(dev, "failed to register mtd device: %d\n", ret); | |
1353 | nand_release(mtd); | |
1354 | return ret; | |
1355 | } | |
1356 | ||
1357 | list_add_tail(&chip->node, &nfc->chips); | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc) | |
1363 | { | |
1364 | struct device_node *np = dev->of_node; | |
1365 | struct device_node *nand_np; | |
1366 | int nchips = of_get_child_count(np); | |
1367 | int ret; | |
1368 | ||
1369 | if (nchips > 8) { | |
1370 | dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips); | |
1371 | return -EINVAL; | |
1372 | } | |
1373 | ||
1374 | for_each_child_of_node(np, nand_np) { | |
1375 | ret = sunxi_nand_chip_init(dev, nfc, nand_np); | |
1376 | if (ret) | |
1377 | return ret; | |
1378 | } | |
1379 | ||
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc) | |
1384 | { | |
1385 | struct sunxi_nand_chip *chip; | |
1386 | ||
1387 | while (!list_empty(&nfc->chips)) { | |
1388 | chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip, | |
1389 | node); | |
1390 | nand_release(&chip->mtd); | |
1391 | sunxi_nand_ecc_cleanup(&chip->nand.ecc); | |
1392 | } | |
1393 | } | |
1394 | ||
1395 | static int sunxi_nfc_probe(struct platform_device *pdev) | |
1396 | { | |
1397 | struct device *dev = &pdev->dev; | |
1398 | struct resource *r; | |
1399 | struct sunxi_nfc *nfc; | |
1400 | int irq; | |
1401 | int ret; | |
1402 | ||
1403 | nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); | |
1404 | if (!nfc) | |
1405 | return -ENOMEM; | |
1406 | ||
1407 | nfc->dev = dev; | |
1408 | spin_lock_init(&nfc->controller.lock); | |
1409 | init_waitqueue_head(&nfc->controller.wq); | |
1410 | INIT_LIST_HEAD(&nfc->chips); | |
1411 | ||
1412 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1413 | nfc->regs = devm_ioremap_resource(dev, r); | |
1414 | if (IS_ERR(nfc->regs)) | |
1415 | return PTR_ERR(nfc->regs); | |
1416 | ||
1417 | irq = platform_get_irq(pdev, 0); | |
1418 | if (irq < 0) { | |
1419 | dev_err(dev, "failed to retrieve irq\n"); | |
1420 | return irq; | |
1421 | } | |
1422 | ||
1423 | nfc->ahb_clk = devm_clk_get(dev, "ahb"); | |
1424 | if (IS_ERR(nfc->ahb_clk)) { | |
1425 | dev_err(dev, "failed to retrieve ahb clk\n"); | |
1426 | return PTR_ERR(nfc->ahb_clk); | |
1427 | } | |
1428 | ||
1429 | ret = clk_prepare_enable(nfc->ahb_clk); | |
1430 | if (ret) | |
1431 | return ret; | |
1432 | ||
1433 | nfc->mod_clk = devm_clk_get(dev, "mod"); | |
1434 | if (IS_ERR(nfc->mod_clk)) { | |
1435 | dev_err(dev, "failed to retrieve mod clk\n"); | |
1436 | ret = PTR_ERR(nfc->mod_clk); | |
1437 | goto out_ahb_clk_unprepare; | |
1438 | } | |
1439 | ||
1440 | ret = clk_prepare_enable(nfc->mod_clk); | |
1441 | if (ret) | |
1442 | goto out_ahb_clk_unprepare; | |
1443 | ||
1444 | ret = sunxi_nfc_rst(nfc); | |
1445 | if (ret) | |
1446 | goto out_mod_clk_unprepare; | |
1447 | ||
1448 | writel(0, nfc->regs + NFC_REG_INT); | |
1449 | ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt, | |
1450 | 0, "sunxi-nand", nfc); | |
1451 | if (ret) | |
1452 | goto out_mod_clk_unprepare; | |
1453 | ||
1454 | platform_set_drvdata(pdev, nfc); | |
1455 | ||
1fef62c1 BB |
1456 | ret = sunxi_nand_chips_init(dev, nfc); |
1457 | if (ret) { | |
1458 | dev_err(dev, "failed to init nand chips\n"); | |
1459 | goto out_mod_clk_unprepare; | |
1460 | } | |
1461 | ||
1462 | return 0; | |
1463 | ||
1464 | out_mod_clk_unprepare: | |
1465 | clk_disable_unprepare(nfc->mod_clk); | |
1466 | out_ahb_clk_unprepare: | |
1467 | clk_disable_unprepare(nfc->ahb_clk); | |
1468 | ||
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | static int sunxi_nfc_remove(struct platform_device *pdev) | |
1473 | { | |
1474 | struct sunxi_nfc *nfc = platform_get_drvdata(pdev); | |
1475 | ||
1476 | sunxi_nand_chips_cleanup(nfc); | |
1477 | ||
1478 | return 0; | |
1479 | } | |
1480 | ||
1481 | static const struct of_device_id sunxi_nfc_ids[] = { | |
1482 | { .compatible = "allwinner,sun4i-a10-nand" }, | |
1483 | { /* sentinel */ } | |
1484 | }; | |
1485 | MODULE_DEVICE_TABLE(of, sunxi_nfc_ids); | |
1486 | ||
1487 | static struct platform_driver sunxi_nfc_driver = { | |
1488 | .driver = { | |
1489 | .name = "sunxi_nand", | |
1490 | .of_match_table = sunxi_nfc_ids, | |
1491 | }, | |
1492 | .probe = sunxi_nfc_probe, | |
1493 | .remove = sunxi_nfc_remove, | |
1494 | }; | |
1495 | module_platform_driver(sunxi_nfc_driver); | |
1496 | ||
1497 | MODULE_LICENSE("GPL v2"); | |
1498 | MODULE_AUTHOR("Boris BREZILLON"); | |
1499 | MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver"); | |
1500 | MODULE_ALIAS("platform:sunxi_nand"); |