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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
7e74a507 BD |
3 | * Copyright © 2004-2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
fdf2fd52 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1da177e4 | 6 | * |
7e74a507 | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
92aeb5d2 SK |
24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
25 | ||
1da177e4 LT |
26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
27 | #define DEBUG | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
1da177e4 LT |
32 | #include <linux/kernel.h> |
33 | #include <linux/string.h> | |
d2a89be8 | 34 | #include <linux/io.h> |
1da177e4 | 35 | #include <linux/ioport.h> |
d052d1be | 36 | #include <linux/platform_device.h> |
1da177e4 LT |
37 | #include <linux/delay.h> |
38 | #include <linux/err.h> | |
4e57b681 | 39 | #include <linux/slab.h> |
f8ce2547 | 40 | #include <linux/clk.h> |
30821fee | 41 | #include <linux/cpufreq.h> |
1da177e4 LT |
42 | |
43 | #include <linux/mtd/mtd.h> | |
44 | #include <linux/mtd/nand.h> | |
45 | #include <linux/mtd/nand_ecc.h> | |
46 | #include <linux/mtd/partitions.h> | |
47 | ||
436d42c6 | 48 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
1da177e4 | 49 | |
02d01862 SK |
50 | #define S3C2410_NFREG(x) (x) |
51 | ||
52 | #define S3C2410_NFCONF S3C2410_NFREG(0x00) | |
53 | #define S3C2410_NFCMD S3C2410_NFREG(0x04) | |
54 | #define S3C2410_NFADDR S3C2410_NFREG(0x08) | |
55 | #define S3C2410_NFDATA S3C2410_NFREG(0x0C) | |
56 | #define S3C2410_NFSTAT S3C2410_NFREG(0x10) | |
57 | #define S3C2410_NFECC S3C2410_NFREG(0x14) | |
58 | #define S3C2440_NFCONT S3C2410_NFREG(0x04) | |
59 | #define S3C2440_NFCMD S3C2410_NFREG(0x08) | |
60 | #define S3C2440_NFADDR S3C2410_NFREG(0x0C) | |
61 | #define S3C2440_NFDATA S3C2410_NFREG(0x10) | |
62 | #define S3C2440_NFSTAT S3C2410_NFREG(0x20) | |
63 | #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) | |
64 | #define S3C2412_NFSTAT S3C2410_NFREG(0x28) | |
65 | #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) | |
66 | #define S3C2410_NFCONF_EN (1<<15) | |
67 | #define S3C2410_NFCONF_INITECC (1<<12) | |
68 | #define S3C2410_NFCONF_nFCE (1<<11) | |
69 | #define S3C2410_NFCONF_TACLS(x) ((x)<<8) | |
70 | #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) | |
71 | #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) | |
72 | #define S3C2410_NFSTAT_BUSY (1<<0) | |
73 | #define S3C2440_NFCONF_TACLS(x) ((x)<<12) | |
74 | #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) | |
75 | #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) | |
76 | #define S3C2440_NFCONT_INITECC (1<<4) | |
77 | #define S3C2440_NFCONT_nFCE (1<<1) | |
78 | #define S3C2440_NFCONT_ENABLE (1<<0) | |
79 | #define S3C2440_NFSTAT_READY (1<<0) | |
80 | #define S3C2412_NFCONF_NANDBOOT (1<<31) | |
81 | #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) | |
82 | #define S3C2412_NFCONT_nFCE0 (1<<1) | |
83 | #define S3C2412_NFSTAT_READY (1<<0) | |
84 | ||
1da177e4 LT |
85 | /* new oob placement block for use with hardware ecc generation |
86 | */ | |
87 | ||
5bd34c09 | 88 | static struct nand_ecclayout nand_hw_eccoob = { |
e0c7d767 DW |
89 | .eccbytes = 3, |
90 | .eccpos = {0, 1, 2}, | |
91 | .oobfree = {{8, 8}} | |
1da177e4 LT |
92 | }; |
93 | ||
94 | /* controller and mtd information */ | |
95 | ||
96 | struct s3c2410_nand_info; | |
97 | ||
3db72151 BD |
98 | /** |
99 | * struct s3c2410_nand_mtd - driver MTD structure | |
100 | * @mtd: The MTD instance to pass to the MTD layer. | |
101 | * @chip: The NAND chip information. | |
102 | * @set: The platform information supplied for this set of NAND chips. | |
103 | * @info: Link back to the hardware information. | |
104 | * @scan_res: The result from calling nand_scan_ident(). | |
105 | */ | |
1da177e4 LT |
106 | struct s3c2410_nand_mtd { |
107 | struct mtd_info mtd; | |
108 | struct nand_chip chip; | |
109 | struct s3c2410_nand_set *set; | |
110 | struct s3c2410_nand_info *info; | |
111 | int scan_res; | |
112 | }; | |
113 | ||
2c06a082 BD |
114 | enum s3c_cpu_type { |
115 | TYPE_S3C2410, | |
116 | TYPE_S3C2412, | |
117 | TYPE_S3C2440, | |
118 | }; | |
119 | ||
ac497c16 JP |
120 | enum s3c_nand_clk_state { |
121 | CLOCK_DISABLE = 0, | |
122 | CLOCK_ENABLE, | |
123 | CLOCK_SUSPEND, | |
124 | }; | |
125 | ||
1da177e4 LT |
126 | /* overview of the s3c2410 nand state */ |
127 | ||
3db72151 BD |
128 | /** |
129 | * struct s3c2410_nand_info - NAND controller state. | |
130 | * @mtds: An array of MTD instances on this controoler. | |
131 | * @platform: The platform data for this board. | |
132 | * @device: The platform device we bound to. | |
3db72151 | 133 | * @clk: The clock resource for this controller. |
6f32a3e2 | 134 | * @regs: The area mapped for the hardware registers. |
3db72151 BD |
135 | * @sel_reg: Pointer to the register controlling the NAND selection. |
136 | * @sel_bit: The bit in @sel_reg to select the NAND chip. | |
137 | * @mtd_count: The number of MTDs created from this controller. | |
138 | * @save_sel: The contents of @sel_reg to be saved over suspend. | |
139 | * @clk_rate: The clock rate from @clk. | |
ac497c16 | 140 | * @clk_state: The current clock state. |
3db72151 BD |
141 | * @cpu_type: The exact type of this controller. |
142 | */ | |
1da177e4 LT |
143 | struct s3c2410_nand_info { |
144 | /* mtd info */ | |
145 | struct nand_hw_control controller; | |
146 | struct s3c2410_nand_mtd *mtds; | |
147 | struct s3c2410_platform_nand *platform; | |
148 | ||
149 | /* device info */ | |
150 | struct device *device; | |
1da177e4 | 151 | struct clk *clk; |
fdf2fd52 | 152 | void __iomem *regs; |
2c06a082 BD |
153 | void __iomem *sel_reg; |
154 | int sel_bit; | |
1da177e4 | 155 | int mtd_count; |
09160832 | 156 | unsigned long save_sel; |
30821fee | 157 | unsigned long clk_rate; |
ac497c16 | 158 | enum s3c_nand_clk_state clk_state; |
03680b1e | 159 | |
2c06a082 | 160 | enum s3c_cpu_type cpu_type; |
30821fee BD |
161 | |
162 | #ifdef CONFIG_CPU_FREQ | |
163 | struct notifier_block freq_transition; | |
164 | #endif | |
1da177e4 LT |
165 | }; |
166 | ||
167 | /* conversion functions */ | |
168 | ||
169 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
170 | { | |
171 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); | |
172 | } | |
173 | ||
174 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
175 | { | |
176 | return s3c2410_nand_mtd_toours(mtd)->info; | |
177 | } | |
178 | ||
3ae5eaec | 179 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 180 | { |
3ae5eaec | 181 | return platform_get_drvdata(dev); |
1da177e4 LT |
182 | } |
183 | ||
3ae5eaec | 184 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 185 | { |
453810b7 | 186 | return dev_get_platdata(&dev->dev); |
1da177e4 LT |
187 | } |
188 | ||
ac497c16 | 189 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
d1fef3c5 | 190 | { |
a68c5ec8 SK |
191 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
192 | return 1; | |
193 | #else | |
194 | return 0; | |
195 | #endif | |
d1fef3c5 BD |
196 | } |
197 | ||
ac497c16 JP |
198 | /** |
199 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. | |
200 | * @info: The controller instance. | |
201 | * @new_state: State to which clock should be set. | |
202 | */ | |
203 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, | |
204 | enum s3c_nand_clk_state new_state) | |
205 | { | |
206 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) | |
207 | return; | |
208 | ||
209 | if (info->clk_state == CLOCK_ENABLE) { | |
210 | if (new_state != CLOCK_ENABLE) | |
887957b4 | 211 | clk_disable_unprepare(info->clk); |
ac497c16 JP |
212 | } else { |
213 | if (new_state == CLOCK_ENABLE) | |
887957b4 | 214 | clk_prepare_enable(info->clk); |
ac497c16 JP |
215 | } |
216 | ||
217 | info->clk_state = new_state; | |
218 | } | |
219 | ||
1da177e4 LT |
220 | /* timing calculations */ |
221 | ||
cfd320fb | 222 | #define NS_IN_KHZ 1000000 |
1da177e4 | 223 | |
3db72151 BD |
224 | /** |
225 | * s3c_nand_calc_rate - calculate timing data. | |
226 | * @wanted: The cycle time in nanoseconds. | |
227 | * @clk: The clock rate in kHz. | |
228 | * @max: The maximum divider value. | |
229 | * | |
230 | * Calculate the timing value from the given parameters. | |
231 | */ | |
2c06a082 | 232 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
1da177e4 LT |
233 | { |
234 | int result; | |
235 | ||
947391cf | 236 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
1da177e4 LT |
237 | |
238 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
239 | ||
240 | if (result > max) { | |
92aeb5d2 SK |
241 | pr_err("%d ns is too big for current clock rate %ld\n", |
242 | wanted, clk); | |
1da177e4 LT |
243 | return -1; |
244 | } | |
245 | ||
246 | if (result < 1) | |
247 | result = 1; | |
248 | ||
249 | return result; | |
250 | } | |
251 | ||
54cd0208 | 252 | #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
253 | |
254 | /* controller setup */ | |
255 | ||
3db72151 BD |
256 | /** |
257 | * s3c2410_nand_setrate - setup controller timing information. | |
258 | * @info: The controller instance. | |
259 | * | |
260 | * Given the information supplied by the platform, calculate and set | |
261 | * the necessary timing registers in the hardware to generate the | |
262 | * necessary timing cycles to the hardware. | |
263 | */ | |
30821fee | 264 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
1da177e4 | 265 | { |
30821fee | 266 | struct s3c2410_platform_nand *plat = info->platform; |
2c06a082 | 267 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
cfd320fb | 268 | int tacls, twrph0, twrph1; |
30821fee | 269 | unsigned long clkrate = clk_get_rate(info->clk); |
2612e523 | 270 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
30821fee | 271 | unsigned long flags; |
1da177e4 LT |
272 | |
273 | /* calculate the timing information for the controller */ | |
274 | ||
30821fee | 275 | info->clk_rate = clkrate; |
cfd320fb BD |
276 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
277 | ||
1da177e4 | 278 | if (plat != NULL) { |
2c06a082 BD |
279 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
280 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); | |
281 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); | |
1da177e4 LT |
282 | } else { |
283 | /* default timings */ | |
2c06a082 | 284 | tacls = tacls_max; |
1da177e4 LT |
285 | twrph0 = 8; |
286 | twrph1 = 8; | |
287 | } | |
61b03bd7 | 288 | |
1da177e4 | 289 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
99974c62 | 290 | dev_err(info->device, "cannot get suitable timings\n"); |
1da177e4 LT |
291 | return -EINVAL; |
292 | } | |
293 | ||
99974c62 | 294 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
54cd0208 SK |
295 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), |
296 | twrph1, to_ns(twrph1, clkrate)); | |
1da177e4 | 297 | |
30821fee BD |
298 | switch (info->cpu_type) { |
299 | case TYPE_S3C2410: | |
300 | mask = (S3C2410_NFCONF_TACLS(3) | | |
301 | S3C2410_NFCONF_TWRPH0(7) | | |
302 | S3C2410_NFCONF_TWRPH1(7)); | |
303 | set = S3C2410_NFCONF_EN; | |
304 | set |= S3C2410_NFCONF_TACLS(tacls - 1); | |
305 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
306 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
307 | break; | |
308 | ||
309 | case TYPE_S3C2440: | |
310 | case TYPE_S3C2412: | |
a755a385 PK |
311 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
312 | S3C2440_NFCONF_TWRPH0(7) | | |
313 | S3C2440_NFCONF_TWRPH1(7)); | |
30821fee BD |
314 | |
315 | set = S3C2440_NFCONF_TACLS(tacls - 1); | |
316 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
317 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
318 | break; | |
319 | ||
320 | default: | |
30821fee BD |
321 | BUG(); |
322 | } | |
323 | ||
30821fee BD |
324 | local_irq_save(flags); |
325 | ||
326 | cfg = readl(info->regs + S3C2410_NFCONF); | |
327 | cfg &= ~mask; | |
328 | cfg |= set; | |
329 | writel(cfg, info->regs + S3C2410_NFCONF); | |
330 | ||
331 | local_irq_restore(flags); | |
332 | ||
ae7304e5 AG |
333 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
334 | ||
30821fee BD |
335 | return 0; |
336 | } | |
337 | ||
3db72151 BD |
338 | /** |
339 | * s3c2410_nand_inithw - basic hardware initialisation | |
340 | * @info: The hardware state. | |
341 | * | |
342 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() | |
343 | * to setup the hardware access speeds and set the controller to be enabled. | |
344 | */ | |
30821fee BD |
345 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
346 | { | |
347 | int ret; | |
348 | ||
349 | ret = s3c2410_nand_setrate(info); | |
350 | if (ret < 0) | |
351 | return ret; | |
352 | ||
54cd0208 SK |
353 | switch (info->cpu_type) { |
354 | case TYPE_S3C2410: | |
30821fee | 355 | default: |
2c06a082 BD |
356 | break; |
357 | ||
54cd0208 SK |
358 | case TYPE_S3C2440: |
359 | case TYPE_S3C2412: | |
d1fef3c5 BD |
360 | /* enable the controller and de-assert nFCE */ |
361 | ||
2c06a082 | 362 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
a4f957f1 | 363 | } |
1da177e4 | 364 | |
1da177e4 LT |
365 | return 0; |
366 | } | |
367 | ||
3db72151 BD |
368 | /** |
369 | * s3c2410_nand_select_chip - select the given nand chip | |
370 | * @mtd: The MTD instance for this chip. | |
371 | * @chip: The chip number. | |
372 | * | |
373 | * This is called by the MTD layer to either select a given chip for the | |
374 | * @mtd instance, or to indicate that the access has finished and the | |
375 | * chip can be de-selected. | |
376 | * | |
377 | * The routine ensures that the nFCE line is correctly setup, and any | |
378 | * platform specific selection code is called to route nFCE to the specific | |
379 | * chip. | |
380 | */ | |
1da177e4 LT |
381 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
382 | { | |
383 | struct s3c2410_nand_info *info; | |
61b03bd7 | 384 | struct s3c2410_nand_mtd *nmtd; |
1da177e4 LT |
385 | struct nand_chip *this = mtd->priv; |
386 | unsigned long cur; | |
387 | ||
388 | nmtd = this->priv; | |
389 | info = nmtd->info; | |
390 | ||
ac497c16 JP |
391 | if (chip != -1) |
392 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); | |
d1fef3c5 | 393 | |
2c06a082 | 394 | cur = readl(info->sel_reg); |
1da177e4 LT |
395 | |
396 | if (chip == -1) { | |
2c06a082 | 397 | cur |= info->sel_bit; |
1da177e4 | 398 | } else { |
fb8d82a8 | 399 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
99974c62 | 400 | dev_err(info->device, "invalid chip %d\n", chip); |
1da177e4 LT |
401 | return; |
402 | } | |
403 | ||
404 | if (info->platform != NULL) { | |
405 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 406 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
407 | } |
408 | ||
2c06a082 | 409 | cur &= ~info->sel_bit; |
1da177e4 LT |
410 | } |
411 | ||
2c06a082 | 412 | writel(cur, info->sel_reg); |
d1fef3c5 | 413 | |
ac497c16 JP |
414 | if (chip == -1) |
415 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); | |
1da177e4 LT |
416 | } |
417 | ||
ad3b5fb7 | 418 | /* s3c2410_nand_hwcontrol |
a4f957f1 | 419 | * |
ad3b5fb7 | 420 | * Issue command and address cycles to the chip |
a4f957f1 | 421 | */ |
1da177e4 | 422 | |
7abd3ef9 | 423 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
f9068876 | 424 | unsigned int ctrl) |
1da177e4 LT |
425 | { |
426 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
c9ac5977 | 427 | |
7abd3ef9 TG |
428 | if (cmd == NAND_CMD_NONE) |
429 | return; | |
430 | ||
f9068876 | 431 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
432 | writeb(cmd, info->regs + S3C2410_NFCMD); |
433 | else | |
434 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
435 | } |
436 | ||
437 | /* command and control functions */ | |
438 | ||
f9068876 DW |
439 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
440 | unsigned int ctrl) | |
a4f957f1 BD |
441 | { |
442 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 | 443 | |
7abd3ef9 TG |
444 | if (cmd == NAND_CMD_NONE) |
445 | return; | |
446 | ||
f9068876 | 447 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
448 | writeb(cmd, info->regs + S3C2440_NFCMD); |
449 | else | |
450 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
451 | } |
452 | ||
1da177e4 LT |
453 | /* s3c2410_nand_devready() |
454 | * | |
455 | * returns 0 if the nand is busy, 1 if it is ready | |
456 | */ | |
457 | ||
458 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
459 | { | |
460 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 LT |
461 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
462 | } | |
463 | ||
2c06a082 BD |
464 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
465 | { | |
466 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
467 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
468 | } | |
469 | ||
470 | static int s3c2412_nand_devready(struct mtd_info *mtd) | |
471 | { | |
472 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
473 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; | |
474 | } | |
475 | ||
1da177e4 LT |
476 | /* ECC handling functions */ |
477 | ||
19da4158 | 478 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
2c06a082 BD |
479 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
480 | u_char *read_ecc, u_char *calc_ecc) | |
1da177e4 | 481 | { |
a2593247 BD |
482 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
483 | unsigned int diff0, diff1, diff2; | |
484 | unsigned int bit, byte; | |
485 | ||
486 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); | |
487 | ||
488 | diff0 = read_ecc[0] ^ calc_ecc[0]; | |
489 | diff1 = read_ecc[1] ^ calc_ecc[1]; | |
490 | diff2 = read_ecc[2] ^ calc_ecc[2]; | |
491 | ||
13e85974 AS |
492 | pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", |
493 | __func__, 3, read_ecc, 3, calc_ecc, | |
a2593247 BD |
494 | diff0, diff1, diff2); |
495 | ||
496 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) | |
497 | return 0; /* ECC is ok */ | |
498 | ||
c45c6c68 BD |
499 | /* sometimes people do not think about using the ECC, so check |
500 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore | |
501 | * the error, on the assumption that this is an un-eccd page. | |
502 | */ | |
503 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff | |
504 | && info->platform->ignore_unset_ecc) | |
505 | return 0; | |
506 | ||
a2593247 BD |
507 | /* Can we correct this ECC (ie, one row and column change). |
508 | * Note, this is similar to the 256 error code on smartmedia */ | |
509 | ||
510 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && | |
511 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && | |
512 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { | |
513 | /* calculate the bit position of the error */ | |
514 | ||
d0bf3793 MR |
515 | bit = ((diff2 >> 3) & 1) | |
516 | ((diff2 >> 4) & 2) | | |
517 | ((diff2 >> 5) & 4); | |
1da177e4 | 518 | |
a2593247 | 519 | /* calculate the byte position of the error */ |
1da177e4 | 520 | |
d0bf3793 MR |
521 | byte = ((diff2 << 7) & 0x100) | |
522 | ((diff1 << 0) & 0x80) | | |
523 | ((diff1 << 1) & 0x40) | | |
524 | ((diff1 << 2) & 0x20) | | |
525 | ((diff1 << 3) & 0x10) | | |
526 | ((diff0 >> 4) & 0x08) | | |
527 | ((diff0 >> 3) & 0x04) | | |
528 | ((diff0 >> 2) & 0x02) | | |
529 | ((diff0 >> 1) & 0x01); | |
a2593247 BD |
530 | |
531 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", | |
532 | bit, byte); | |
533 | ||
534 | dat[byte] ^= (1 << bit); | |
535 | return 1; | |
536 | } | |
537 | ||
538 | /* if there is only one bit difference in the ECC, then | |
539 | * one of only a row or column parity has changed, which | |
540 | * means the error is most probably in the ECC itself */ | |
541 | ||
542 | diff0 |= (diff1 << 8); | |
543 | diff0 |= (diff2 << 16); | |
544 | ||
545 | if ((diff0 & ~(1<<fls(diff0))) == 0) | |
546 | return 1; | |
547 | ||
4fac9f69 | 548 | return -1; |
1da177e4 LT |
549 | } |
550 | ||
a4f957f1 BD |
551 | /* ECC functions |
552 | * | |
553 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
554 | * generator block to ECC the data as it passes through] | |
555 | */ | |
556 | ||
1da177e4 LT |
557 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
558 | { | |
559 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
560 | unsigned long ctrl; | |
561 | ||
562 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
563 | ctrl |= S3C2410_NFCONF_INITECC; | |
564 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
565 | } | |
566 | ||
4f659923 MC |
567 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
568 | { | |
569 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
570 | unsigned long ctrl; | |
571 | ||
572 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
f938bc56 SK |
573 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, |
574 | info->regs + S3C2440_NFCONT); | |
4f659923 MC |
575 | } |
576 | ||
a4f957f1 BD |
577 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
578 | { | |
579 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
580 | unsigned long ctrl; | |
581 | ||
582 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
583 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
584 | } | |
585 | ||
f938bc56 SK |
586 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
587 | u_char *ecc_code) | |
1da177e4 LT |
588 | { |
589 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
590 | ||
591 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
592 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
593 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
594 | ||
13e85974 | 595 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
1da177e4 LT |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
f938bc56 SK |
600 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
601 | u_char *ecc_code) | |
4f659923 MC |
602 | { |
603 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
604 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); | |
605 | ||
606 | ecc_code[0] = ecc; | |
607 | ecc_code[1] = ecc >> 8; | |
608 | ecc_code[2] = ecc >> 16; | |
609 | ||
13e85974 | 610 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
4f659923 MC |
611 | |
612 | return 0; | |
613 | } | |
614 | ||
f938bc56 SK |
615 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
616 | u_char *ecc_code) | |
a4f957f1 BD |
617 | { |
618 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
619 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
620 | ||
621 | ecc_code[0] = ecc; | |
622 | ecc_code[1] = ecc >> 8; | |
623 | ecc_code[2] = ecc >> 16; | |
624 | ||
71d54f38 | 625 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
a4f957f1 BD |
626 | |
627 | return 0; | |
628 | } | |
19da4158 | 629 | #endif |
a4f957f1 | 630 | |
a4f957f1 BD |
631 | /* over-ride the standard functions for a little more speed. We can |
632 | * use read/write block to move the data buffers to/from the controller | |
633 | */ | |
1da177e4 LT |
634 | |
635 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
636 | { | |
637 | struct nand_chip *this = mtd->priv; | |
638 | readsb(this->IO_ADDR_R, buf, len); | |
639 | } | |
640 | ||
b773bb2e MR |
641 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
642 | { | |
643 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
644 | |
645 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
646 | ||
647 | /* cleanup if we've got less than a word to do */ | |
648 | if (len & 3) { | |
649 | buf += len & ~3; | |
650 | ||
651 | for (; len & 3; len--) | |
652 | *buf++ = readb(info->regs + S3C2440_NFDATA); | |
653 | } | |
b773bb2e MR |
654 | } |
655 | ||
f938bc56 SK |
656 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
657 | int len) | |
1da177e4 LT |
658 | { |
659 | struct nand_chip *this = mtd->priv; | |
660 | writesb(this->IO_ADDR_W, buf, len); | |
661 | } | |
662 | ||
f938bc56 SK |
663 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
664 | int len) | |
b773bb2e MR |
665 | { |
666 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
667 | |
668 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
669 | ||
670 | /* cleanup any fractional write */ | |
671 | if (len & 3) { | |
672 | buf += len & ~3; | |
673 | ||
674 | for (; len & 3; len--, buf++) | |
675 | writeb(*buf, info->regs + S3C2440_NFDATA); | |
676 | } | |
b773bb2e MR |
677 | } |
678 | ||
30821fee BD |
679 | /* cpufreq driver support */ |
680 | ||
681 | #ifdef CONFIG_CPU_FREQ | |
682 | ||
683 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, | |
684 | unsigned long val, void *data) | |
685 | { | |
686 | struct s3c2410_nand_info *info; | |
687 | unsigned long newclk; | |
688 | ||
689 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); | |
690 | newclk = clk_get_rate(info->clk); | |
691 | ||
692 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || | |
693 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { | |
694 | s3c2410_nand_setrate(info); | |
695 | } | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
701 | { | |
702 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; | |
703 | ||
704 | return cpufreq_register_notifier(&info->freq_transition, | |
705 | CPUFREQ_TRANSITION_NOTIFIER); | |
706 | } | |
707 | ||
f938bc56 SK |
708 | static inline void |
709 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
710 | { |
711 | cpufreq_unregister_notifier(&info->freq_transition, | |
712 | CPUFREQ_TRANSITION_NOTIFIER); | |
713 | } | |
714 | ||
715 | #else | |
716 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
717 | { | |
718 | return 0; | |
719 | } | |
720 | ||
f938bc56 SK |
721 | static inline void |
722 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
723 | { |
724 | } | |
725 | #endif | |
726 | ||
1da177e4 LT |
727 | /* device management functions */ |
728 | ||
ec0482e6 | 729 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
1da177e4 | 730 | { |
3ae5eaec | 731 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 732 | |
61b03bd7 | 733 | if (info == NULL) |
1da177e4 LT |
734 | return 0; |
735 | ||
30821fee BD |
736 | s3c2410_nand_cpufreq_deregister(info); |
737 | ||
738 | /* Release all our mtds and their partitions, then go through | |
739 | * freeing the resources used | |
1da177e4 | 740 | */ |
61b03bd7 | 741 | |
1da177e4 LT |
742 | if (info->mtds != NULL) { |
743 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
744 | int mtdno; | |
745 | ||
746 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
747 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
748 | nand_release(&ptr->mtd); | |
749 | } | |
1da177e4 LT |
750 | } |
751 | ||
752 | /* free the common resources */ | |
753 | ||
6f32a3e2 | 754 | if (!IS_ERR(info->clk)) |
ac497c16 | 755 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
1da177e4 LT |
756 | |
757 | return 0; | |
758 | } | |
759 | ||
1da177e4 LT |
760 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
761 | struct s3c2410_nand_mtd *mtd, | |
762 | struct s3c2410_nand_set *set) | |
763 | { | |
ded4c55d | 764 | if (set) { |
599501a7 | 765 | mtd->mtd.name = set->name; |
ed27f028 | 766 | |
ded4c55d | 767 | return mtd_device_parse_register(&mtd->mtd, NULL, NULL, |
42d7fbe2 | 768 | set->partitions, set->nr_partitions); |
ded4c55d SK |
769 | } |
770 | ||
771 | return -ENODEV; | |
1da177e4 | 772 | } |
1da177e4 | 773 | |
3db72151 BD |
774 | /** |
775 | * s3c2410_nand_init_chip - initialise a single instance of an chip | |
776 | * @info: The base NAND controller the chip is on. | |
777 | * @nmtd: The new controller MTD instance to fill in. | |
778 | * @set: The information passed from the board specific platform data. | |
1da177e4 | 779 | * |
3db72151 BD |
780 | * Initialise the given @nmtd from the information in @info and @set. This |
781 | * readies the structure for use with the MTD layer functions by ensuring | |
782 | * all pointers are setup and the necessary control routines selected. | |
783 | */ | |
1da177e4 LT |
784 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
785 | struct s3c2410_nand_mtd *nmtd, | |
786 | struct s3c2410_nand_set *set) | |
787 | { | |
788 | struct nand_chip *chip = &nmtd->chip; | |
2c06a082 | 789 | void __iomem *regs = info->regs; |
1da177e4 | 790 | |
1da177e4 LT |
791 | chip->write_buf = s3c2410_nand_write_buf; |
792 | chip->read_buf = s3c2410_nand_read_buf; | |
793 | chip->select_chip = s3c2410_nand_select_chip; | |
794 | chip->chip_delay = 50; | |
795 | chip->priv = nmtd; | |
74218fed | 796 | chip->options = set->options; |
1da177e4 LT |
797 | chip->controller = &info->controller; |
798 | ||
2c06a082 BD |
799 | switch (info->cpu_type) { |
800 | case TYPE_S3C2410: | |
801 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; | |
802 | info->sel_reg = regs + S3C2410_NFCONF; | |
803 | info->sel_bit = S3C2410_NFCONF_nFCE; | |
804 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; | |
805 | chip->dev_ready = s3c2410_nand_devready; | |
806 | break; | |
807 | ||
808 | case TYPE_S3C2440: | |
809 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
810 | info->sel_reg = regs + S3C2440_NFCONT; | |
811 | info->sel_bit = S3C2440_NFCONT_nFCE; | |
812 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
813 | chip->dev_ready = s3c2440_nand_devready; | |
b773bb2e MR |
814 | chip->read_buf = s3c2440_nand_read_buf; |
815 | chip->write_buf = s3c2440_nand_write_buf; | |
2c06a082 BD |
816 | break; |
817 | ||
818 | case TYPE_S3C2412: | |
819 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
820 | info->sel_reg = regs + S3C2440_NFCONT; | |
821 | info->sel_bit = S3C2412_NFCONT_nFCE0; | |
822 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
823 | chip->dev_ready = s3c2412_nand_devready; | |
824 | ||
825 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) | |
826 | dev_info(info->device, "System booted from NAND\n"); | |
827 | ||
828 | break; | |
54cd0208 | 829 | } |
2c06a082 BD |
830 | |
831 | chip->IO_ADDR_R = chip->IO_ADDR_W; | |
a4f957f1 | 832 | |
1da177e4 LT |
833 | nmtd->info = info; |
834 | nmtd->mtd.priv = chip; | |
835 | nmtd->set = set; | |
836 | ||
a68c5ec8 SK |
837 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
838 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
839 | chip->ecc.correct = s3c2410_nand_correct_data; | |
840 | chip->ecc.mode = NAND_ECC_HW; | |
841 | chip->ecc.strength = 1; | |
842 | ||
843 | switch (info->cpu_type) { | |
844 | case TYPE_S3C2410: | |
845 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
6dfc6d25 | 846 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
a68c5ec8 | 847 | break; |
2c06a082 | 848 | |
a68c5ec8 SK |
849 | case TYPE_S3C2412: |
850 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; | |
851 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | |
852 | break; | |
853 | ||
854 | case TYPE_S3C2440: | |
855 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | |
856 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
857 | break; | |
1da177e4 | 858 | } |
a68c5ec8 SK |
859 | #else |
860 | chip->ecc.mode = NAND_ECC_SOFT; | |
861 | #endif | |
1c21ab67 BD |
862 | |
863 | if (set->ecc_layout != NULL) | |
864 | chip->ecc.layout = set->ecc_layout; | |
37e5ffa3 BD |
865 | |
866 | if (set->disable_ecc) | |
867 | chip->ecc.mode = NAND_ECC_NONE; | |
8c3e843d AG |
868 | |
869 | switch (chip->ecc.mode) { | |
870 | case NAND_ECC_NONE: | |
871 | dev_info(info->device, "NAND ECC disabled\n"); | |
872 | break; | |
873 | case NAND_ECC_SOFT: | |
874 | dev_info(info->device, "NAND soft ECC\n"); | |
875 | break; | |
876 | case NAND_ECC_HW: | |
877 | dev_info(info->device, "NAND hardware ECC\n"); | |
878 | break; | |
879 | default: | |
880 | dev_info(info->device, "NAND ECC UNKNOWN\n"); | |
881 | break; | |
882 | } | |
9db41f9e MP |
883 | |
884 | /* If you use u-boot BBT creation code, specifying this flag will | |
885 | * let the kernel fish out the BBT from the NAND, and also skip the | |
886 | * full NAND scan that can take 1/2s or so. Little things... */ | |
a40f7341 | 887 | if (set->flash_bbt) { |
bb9ebd4e | 888 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 BN |
889 | chip->options |= NAND_SKIP_BBTSCAN; |
890 | } | |
1da177e4 LT |
891 | } |
892 | ||
3db72151 BD |
893 | /** |
894 | * s3c2410_nand_update_chip - post probe update | |
895 | * @info: The controller instance. | |
896 | * @nmtd: The driver version of the MTD instance. | |
71d54f38 | 897 | * |
af901ca1 | 898 | * This routine is called after the chip probe has successfully completed |
3db72151 BD |
899 | * and the relevant per-chip information updated. This call ensure that |
900 | * we update the internal state accordingly. | |
901 | * | |
902 | * The internal state is currently limited to the ECC state information. | |
903 | */ | |
71d54f38 BD |
904 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
905 | struct s3c2410_nand_mtd *nmtd) | |
906 | { | |
907 | struct nand_chip *chip = &nmtd->chip; | |
908 | ||
451d3399 BD |
909 | dev_dbg(info->device, "chip %p => page shift %d\n", |
910 | chip, chip->page_shift); | |
71d54f38 | 911 | |
8c3e843d AG |
912 | if (chip->ecc.mode != NAND_ECC_HW) |
913 | return; | |
914 | ||
48fc7f7e | 915 | /* change the behaviour depending on whether we are using |
71d54f38 BD |
916 | * the large or small page nand device */ |
917 | ||
8c3e843d AG |
918 | if (chip->page_shift > 10) { |
919 | chip->ecc.size = 256; | |
920 | chip->ecc.bytes = 3; | |
921 | } else { | |
922 | chip->ecc.size = 512; | |
923 | chip->ecc.bytes = 3; | |
924 | chip->ecc.layout = &nand_hw_eccoob; | |
71d54f38 BD |
925 | } |
926 | } | |
927 | ||
ec0482e6 | 928 | /* s3c24xx_nand_probe |
1da177e4 LT |
929 | * |
930 | * called by device layer when it finds a device matching | |
931 | * one our driver can handled. This code checks to see if | |
932 | * it can allocate all necessary resources then calls the | |
933 | * nand layer to look for devices | |
934 | */ | |
ec0482e6 | 935 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
1da177e4 | 936 | { |
3ae5eaec | 937 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
54cd0208 | 938 | enum s3c_cpu_type cpu_type; |
1da177e4 LT |
939 | struct s3c2410_nand_info *info; |
940 | struct s3c2410_nand_mtd *nmtd; | |
941 | struct s3c2410_nand_set *sets; | |
942 | struct resource *res; | |
943 | int err = 0; | |
944 | int size; | |
945 | int nr_sets; | |
946 | int setno; | |
947 | ||
ec0482e6 BD |
948 | cpu_type = platform_get_device_id(pdev)->driver_data; |
949 | ||
6f32a3e2 | 950 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
1da177e4 | 951 | if (info == NULL) { |
1da177e4 LT |
952 | err = -ENOMEM; |
953 | goto exit_error; | |
954 | } | |
955 | ||
3ae5eaec | 956 | platform_set_drvdata(pdev, info); |
1da177e4 LT |
957 | |
958 | spin_lock_init(&info->controller.lock); | |
a4f957f1 | 959 | init_waitqueue_head(&info->controller.wq); |
1da177e4 LT |
960 | |
961 | /* get the clock source and enable it */ | |
962 | ||
6f32a3e2 | 963 | info->clk = devm_clk_get(&pdev->dev, "nand"); |
1da177e4 | 964 | if (IS_ERR(info->clk)) { |
898eb71c | 965 | dev_err(&pdev->dev, "failed to get clock\n"); |
1da177e4 LT |
966 | err = -ENOENT; |
967 | goto exit_error; | |
968 | } | |
969 | ||
ac497c16 | 970 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
1da177e4 LT |
971 | |
972 | /* allocate and map the resource */ | |
973 | ||
a4f957f1 | 974 | /* currently we assume we have the one resource */ |
6f32a3e2 | 975 | res = pdev->resource; |
fc161c4e | 976 | size = resource_size(res); |
1da177e4 | 977 | |
6f32a3e2 SK |
978 | info->device = &pdev->dev; |
979 | info->platform = plat; | |
980 | info->cpu_type = cpu_type; | |
1da177e4 | 981 | |
b0de774c TR |
982 | info->regs = devm_ioremap_resource(&pdev->dev, res); |
983 | if (IS_ERR(info->regs)) { | |
984 | err = PTR_ERR(info->regs); | |
1da177e4 | 985 | goto exit_error; |
61b03bd7 | 986 | } |
1da177e4 | 987 | |
3ae5eaec | 988 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
989 | |
990 | /* initialise the hardware */ | |
991 | ||
30821fee | 992 | err = s3c2410_nand_inithw(info); |
1da177e4 LT |
993 | if (err != 0) |
994 | goto exit_error; | |
995 | ||
996 | sets = (plat != NULL) ? plat->sets : NULL; | |
997 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
998 | ||
999 | info->mtd_count = nr_sets; | |
1000 | ||
1001 | /* allocate our information */ | |
1002 | ||
1003 | size = nr_sets * sizeof(*info->mtds); | |
6f32a3e2 | 1004 | info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
1da177e4 | 1005 | if (info->mtds == NULL) { |
1da177e4 LT |
1006 | err = -ENOMEM; |
1007 | goto exit_error; | |
1008 | } | |
1009 | ||
1da177e4 LT |
1010 | /* initialise all possible chips */ |
1011 | ||
1012 | nmtd = info->mtds; | |
1013 | ||
1014 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
f938bc56 SK |
1015 | pr_debug("initialising set %d (%p, info %p)\n", |
1016 | setno, nmtd, info); | |
61b03bd7 | 1017 | |
40acbab6 | 1018 | nmtd->mtd.dev.parent = &pdev->dev; |
1da177e4 LT |
1019 | s3c2410_nand_init_chip(info, nmtd, sets); |
1020 | ||
71d54f38 | 1021 | nmtd->scan_res = nand_scan_ident(&nmtd->mtd, |
5e81e88a DW |
1022 | (sets) ? sets->nr_chips : 1, |
1023 | NULL); | |
1da177e4 LT |
1024 | |
1025 | if (nmtd->scan_res == 0) { | |
71d54f38 BD |
1026 | s3c2410_nand_update_chip(info, nmtd); |
1027 | nand_scan_tail(&nmtd->mtd); | |
1da177e4 LT |
1028 | s3c2410_nand_add_partition(info, nmtd, sets); |
1029 | } | |
1030 | ||
1031 | if (sets != NULL) | |
1032 | sets++; | |
1033 | } | |
61b03bd7 | 1034 | |
30821fee BD |
1035 | err = s3c2410_nand_cpufreq_register(info); |
1036 | if (err < 0) { | |
1037 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); | |
1038 | goto exit_error; | |
1039 | } | |
1040 | ||
ac497c16 | 1041 | if (allow_clk_suspend(info)) { |
d1fef3c5 | 1042 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
ac497c16 | 1043 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1044 | } |
1045 | ||
1da177e4 LT |
1046 | return 0; |
1047 | ||
1048 | exit_error: | |
ec0482e6 | 1049 | s3c24xx_nand_remove(pdev); |
1da177e4 LT |
1050 | |
1051 | if (err == 0) | |
1052 | err = -EINVAL; | |
1053 | return err; | |
1054 | } | |
1055 | ||
d1fef3c5 BD |
1056 | /* PM Support */ |
1057 | #ifdef CONFIG_PM | |
1058 | ||
1059 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
1060 | { | |
1061 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
1062 | ||
1063 | if (info) { | |
09160832 | 1064 | info->save_sel = readl(info->sel_reg); |
03680b1e BD |
1065 | |
1066 | /* For the moment, we must ensure nFCE is high during | |
1067 | * the time we are suspended. This really should be | |
1068 | * handled by suspending the MTDs we are using, but | |
1069 | * that is currently not the case. */ | |
1070 | ||
09160832 | 1071 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
03680b1e | 1072 | |
ac497c16 | 1073 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
d1fef3c5 BD |
1074 | } |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static int s3c24xx_nand_resume(struct platform_device *dev) | |
1080 | { | |
1081 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
09160832 | 1082 | unsigned long sel; |
d1fef3c5 BD |
1083 | |
1084 | if (info) { | |
ac497c16 | 1085 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
30821fee | 1086 | s3c2410_nand_inithw(info); |
d1fef3c5 | 1087 | |
03680b1e BD |
1088 | /* Restore the state of the nFCE line. */ |
1089 | ||
09160832 BD |
1090 | sel = readl(info->sel_reg); |
1091 | sel &= ~info->sel_bit; | |
1092 | sel |= info->save_sel & info->sel_bit; | |
1093 | writel(sel, info->sel_reg); | |
03680b1e | 1094 | |
ac497c16 | 1095 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1096 | } |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | #else | |
1102 | #define s3c24xx_nand_suspend NULL | |
1103 | #define s3c24xx_nand_resume NULL | |
1104 | #endif | |
1105 | ||
a4f957f1 BD |
1106 | /* driver device registration */ |
1107 | ||
0abe75d2 | 1108 | static const struct platform_device_id s3c24xx_driver_ids[] = { |
ec0482e6 BD |
1109 | { |
1110 | .name = "s3c2410-nand", | |
1111 | .driver_data = TYPE_S3C2410, | |
1112 | }, { | |
1113 | .name = "s3c2440-nand", | |
1114 | .driver_data = TYPE_S3C2440, | |
1115 | }, { | |
1116 | .name = "s3c2412-nand", | |
1117 | .driver_data = TYPE_S3C2412, | |
9dbc0902 PK |
1118 | }, { |
1119 | .name = "s3c6400-nand", | |
1120 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ | |
3ae5eaec | 1121 | }, |
ec0482e6 | 1122 | { } |
1da177e4 LT |
1123 | }; |
1124 | ||
ec0482e6 | 1125 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
a4f957f1 | 1126 | |
ec0482e6 BD |
1127 | static struct platform_driver s3c24xx_nand_driver = { |
1128 | .probe = s3c24xx_nand_probe, | |
1129 | .remove = s3c24xx_nand_remove, | |
2c06a082 BD |
1130 | .suspend = s3c24xx_nand_suspend, |
1131 | .resume = s3c24xx_nand_resume, | |
ec0482e6 | 1132 | .id_table = s3c24xx_driver_ids, |
2c06a082 | 1133 | .driver = { |
ec0482e6 | 1134 | .name = "s3c24xx-nand", |
2c06a082 BD |
1135 | }, |
1136 | }; | |
1137 | ||
056fcab5 | 1138 | module_platform_driver(s3c24xx_nand_driver); |
1da177e4 LT |
1139 | |
1140 | MODULE_LICENSE("GPL"); | |
1141 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 1142 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |