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ec43b816 IM |
1 | /* |
2 | * Toshiba TMIO NAND flash controller driver | |
3 | * | |
4 | * Slightly murky pre-git history of the driver: | |
5 | * | |
6 | * Copyright (c) Ian Molton 2004, 2005, 2008 | |
25985edc | 7 | * Original work, independent of sharps code. Included hardware ECC support. |
ec43b816 IM |
8 | * Hard ECC did not work for writes in the early revisions. |
9 | * Copyright (c) Dirk Opfer 2005. | |
10 | * Modifications developed from sharps code but | |
11 | * NOT containing any, ported onto Ians base. | |
12 | * Copyright (c) Chris Humbert 2005 | |
13 | * Copyright (c) Dmitry Baryshkov 2008 | |
14 | * Minor fixes | |
15 | * | |
16 | * Parts copyright Sebastian Carlier | |
17 | * | |
18 | * This file is licensed under | |
19 | * the terms of the GNU General Public License version 2. This program | |
20 | * is licensed "as is" without any warranty of any kind, whether express | |
21 | * or implied. | |
22 | * | |
23 | */ | |
24 | ||
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/mfd/core.h> | |
30 | #include <linux/mfd/tmio.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/irq.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/mtd/mtd.h> | |
d4092d76 | 37 | #include <linux/mtd/rawnand.h> |
ec43b816 IM |
38 | #include <linux/mtd/nand_ecc.h> |
39 | #include <linux/mtd/partitions.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
ec43b816 IM |
41 | |
42 | /*--------------------------------------------------------------------------*/ | |
43 | ||
44 | /* | |
45 | * NAND Flash Host Controller Configuration Register | |
46 | */ | |
47 | #define CCR_COMMAND 0x04 /* w Command */ | |
48 | #define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */ | |
49 | #define CCR_INTP 0x3d /* b Interrupt Pin */ | |
50 | #define CCR_INTE 0x48 /* b Interrupt Enable */ | |
51 | #define CCR_EC 0x4a /* b Event Control */ | |
52 | #define CCR_ICC 0x4c /* b Internal Clock Control */ | |
53 | #define CCR_ECCC 0x5b /* b ECC Control */ | |
54 | #define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */ | |
55 | #define CCR_NFM 0x61 /* b NAND Flash Monitor */ | |
56 | #define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */ | |
57 | #define CCR_NFDC 0x63 /* b NAND Flash Detect Control */ | |
58 | ||
59 | /* | |
60 | * NAND Flash Control Register | |
61 | */ | |
62 | #define FCR_DATA 0x00 /* bwl Data Register */ | |
63 | #define FCR_MODE 0x04 /* b Mode Register */ | |
64 | #define FCR_STATUS 0x05 /* b Status Register */ | |
65 | #define FCR_ISR 0x06 /* b Interrupt Status Register */ | |
66 | #define FCR_IMR 0x07 /* b Interrupt Mask Register */ | |
67 | ||
68 | /* FCR_MODE Register Command List */ | |
69 | #define FCR_MODE_DATA 0x94 /* Data Data_Mode */ | |
70 | #define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */ | |
71 | #define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */ | |
72 | ||
73 | #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */ | |
74 | #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */ | |
75 | #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */ | |
76 | ||
77 | #define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */ | |
78 | #define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */ | |
79 | ||
80 | #define FCR_MODE_LED_OFF 0x00 /* LED OFF */ | |
81 | #define FCR_MODE_LED_ON 0x04 /* LED ON */ | |
82 | ||
83 | #define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */ | |
84 | #define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */ | |
85 | ||
86 | #define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */ | |
87 | #define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */ | |
88 | ||
89 | #define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */ | |
90 | #define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */ | |
91 | ||
92 | #define FCR_MODE_WE 0x80 | |
93 | #define FCR_MODE_ECC1 0x40 | |
94 | #define FCR_MODE_ECC0 0x20 | |
95 | #define FCR_MODE_CE 0x10 | |
96 | #define FCR_MODE_PCNT1 0x08 | |
97 | #define FCR_MODE_PCNT0 0x04 | |
98 | #define FCR_MODE_ALE 0x02 | |
99 | #define FCR_MODE_CLE 0x01 | |
100 | ||
101 | #define FCR_STATUS_BUSY 0x80 | |
102 | ||
103 | /*--------------------------------------------------------------------------*/ | |
104 | ||
105 | struct tmio_nand { | |
ec43b816 | 106 | struct nand_chip chip; |
a0916c94 | 107 | struct completion comp; |
ec43b816 IM |
108 | |
109 | struct platform_device *dev; | |
110 | ||
111 | void __iomem *ccr; | |
112 | void __iomem *fcr; | |
076c7f4c | 113 | unsigned long fcr_base; |
ec43b816 IM |
114 | |
115 | unsigned int irq; | |
116 | ||
117 | /* for tmio_nand_read_byte */ | |
118 | u8 read; | |
119 | unsigned read_good:1; | |
120 | }; | |
121 | ||
66c9595d BB |
122 | static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd) |
123 | { | |
124 | return container_of(mtd_to_nand(mtd), struct tmio_nand, chip); | |
125 | } | |
ec43b816 | 126 | |
ec43b816 IM |
127 | |
128 | /*--------------------------------------------------------------------------*/ | |
129 | ||
0f808c16 BB |
130 | static void tmio_nand_hwcontrol(struct nand_chip *chip, int cmd, |
131 | unsigned int ctrl) | |
ec43b816 | 132 | { |
0f808c16 | 133 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
134 | |
135 | if (ctrl & NAND_CTRL_CHANGE) { | |
136 | u8 mode; | |
137 | ||
138 | if (ctrl & NAND_NCE) { | |
139 | mode = FCR_MODE_DATA; | |
140 | ||
141 | if (ctrl & NAND_CLE) | |
142 | mode |= FCR_MODE_CLE; | |
143 | else | |
144 | mode &= ~FCR_MODE_CLE; | |
145 | ||
146 | if (ctrl & NAND_ALE) | |
147 | mode |= FCR_MODE_ALE; | |
148 | else | |
149 | mode &= ~FCR_MODE_ALE; | |
150 | } else { | |
151 | mode = FCR_MODE_STANDBY; | |
152 | } | |
153 | ||
154 | tmio_iowrite8(mode, tmio->fcr + FCR_MODE); | |
155 | tmio->read_good = 0; | |
156 | } | |
157 | ||
158 | if (cmd != NAND_CMD_NONE) | |
82fc5099 | 159 | tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W); |
ec43b816 IM |
160 | } |
161 | ||
50a487e7 | 162 | static int tmio_nand_dev_ready(struct nand_chip *chip) |
ec43b816 | 163 | { |
50a487e7 | 164 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
165 | |
166 | return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); | |
167 | } | |
168 | ||
169 | static irqreturn_t tmio_irq(int irq, void *__tmio) | |
170 | { | |
171 | struct tmio_nand *tmio = __tmio; | |
ec43b816 IM |
172 | |
173 | /* disable RDYREQ interrupt */ | |
174 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); | |
a0916c94 | 175 | complete(&tmio->comp); |
ec43b816 | 176 | |
ec43b816 IM |
177 | return IRQ_HANDLED; |
178 | } | |
179 | ||
180 | /* | |
181 | *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB. | |
182 | *This interrupt is normally disabled, but for long operations like | |
183 | *erase and write, we enable it to wake us up. The irq handler | |
184 | *disables the interrupt. | |
185 | */ | |
f1d46942 | 186 | static int tmio_nand_wait(struct nand_chip *nand_chip) |
ec43b816 | 187 | { |
f1d46942 | 188 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(nand_chip)); |
ec43b816 | 189 | long timeout; |
97d90da8 | 190 | u8 status; |
ec43b816 IM |
191 | |
192 | /* enable RDYREQ interrupt */ | |
a0916c94 | 193 | |
ec43b816 | 194 | tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); |
a0916c94 | 195 | reinit_completion(&tmio->comp); |
ec43b816 IM |
196 | tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); |
197 | ||
a0916c94 BB |
198 | timeout = nand_chip->state == FL_ERASING ? 400 : 20; |
199 | timeout = wait_for_completion_timeout(&tmio->comp, | |
200 | msecs_to_jiffies(timeout)); | |
ec43b816 | 201 | |
50a487e7 | 202 | if (unlikely(!tmio_nand_dev_ready(nand_chip))) { |
ec43b816 IM |
203 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); |
204 | dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n", | |
205 | nand_chip->state == FL_ERASING ? "erase" : "program", | |
206 | nand_chip->state == FL_ERASING ? 400 : 20); | |
207 | ||
208 | } else if (unlikely(!timeout)) { | |
209 | tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); | |
210 | dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n"); | |
211 | } | |
212 | ||
97d90da8 BB |
213 | nand_status_op(nand_chip, &status); |
214 | return status; | |
ec43b816 IM |
215 | } |
216 | ||
217 | /* | |
218 | *The TMIO controller combines two 8-bit data bytes into one 16-bit | |
219 | *word. This function separates them so nand_base.c works as expected, | |
220 | *especially its NAND_CMD_READID routines. | |
221 | * | |
222 | *To prevent stale data from being read, tmio_nand_hwcontrol() clears | |
223 | *tmio->read_good. | |
224 | */ | |
7e534323 | 225 | static u_char tmio_nand_read_byte(struct nand_chip *chip) |
ec43b816 | 226 | { |
7e534323 | 227 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
228 | unsigned int data; |
229 | ||
230 | if (tmio->read_good--) | |
231 | return tmio->read; | |
232 | ||
233 | data = tmio_ioread16(tmio->fcr + FCR_DATA); | |
234 | tmio->read = data >> 8; | |
235 | return data; | |
236 | } | |
237 | ||
238 | /* | |
239 | *The TMIO controller converts an 8-bit NAND interface to a 16-bit | |
240 | *bus interface, so all data reads and writes must be 16-bit wide. | |
241 | *Thus, we implement 16-bit versions of the read, write, and verify | |
242 | *buffer functions. | |
243 | */ | |
244 | static void | |
c0739d85 | 245 | tmio_nand_write_buf(struct nand_chip *chip, const u_char *buf, int len) |
ec43b816 | 246 | { |
c0739d85 | 247 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
248 | |
249 | tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); | |
250 | } | |
251 | ||
7e534323 | 252 | static void tmio_nand_read_buf(struct nand_chip *chip, u_char *buf, int len) |
ec43b816 | 253 | { |
7e534323 | 254 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
255 | |
256 | tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); | |
257 | } | |
258 | ||
ec47636c | 259 | static void tmio_nand_enable_hwecc(struct nand_chip *chip, int mode) |
ec43b816 | 260 | { |
ec47636c | 261 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
262 | |
263 | tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE); | |
264 | tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */ | |
265 | tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE); | |
266 | } | |
267 | ||
af37d2c3 BB |
268 | static int tmio_nand_calculate_ecc(struct nand_chip *chip, const u_char *dat, |
269 | u_char *ecc_code) | |
ec43b816 | 270 | { |
af37d2c3 | 271 | struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip)); |
ec43b816 IM |
272 | unsigned int ecc; |
273 | ||
274 | tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE); | |
275 | ||
276 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); | |
277 | ecc_code[1] = ecc; /* 000-255 LP7-0 */ | |
278 | ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */ | |
279 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); | |
280 | ecc_code[2] = ecc; /* 000-255 CP5-0,11b */ | |
281 | ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */ | |
282 | ecc = tmio_ioread16(tmio->fcr + FCR_DATA); | |
283 | ecc_code[3] = ecc; /* 256-511 LP15-8 */ | |
284 | ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */ | |
285 | ||
286 | tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE); | |
287 | return 0; | |
288 | } | |
289 | ||
00da2ea9 BB |
290 | static int tmio_nand_correct_data(struct nand_chip *chip, unsigned char *buf, |
291 | unsigned char *read_ecc, | |
292 | unsigned char *calc_ecc) | |
0f777fb9 AN |
293 | { |
294 | int r0, r1; | |
295 | ||
296 | /* assume ecc.size = 512 and ecc.bytes = 6 */ | |
309600c1 | 297 | r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256, false); |
0f777fb9 AN |
298 | if (r0 < 0) |
299 | return r0; | |
309600c1 BB |
300 | r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256, |
301 | false); | |
0f777fb9 AN |
302 | if (r1 < 0) |
303 | return r1; | |
304 | return r0 + r1; | |
305 | } | |
306 | ||
ec43b816 IM |
307 | static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio) |
308 | { | |
944dc035 | 309 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
310 | int ret; |
311 | ||
312 | if (cell->enable) { | |
313 | ret = cell->enable(dev); | |
314 | if (ret) | |
315 | return ret; | |
316 | } | |
317 | ||
318 | /* (4Ch) CLKRUN Enable 1st spcrunc */ | |
319 | tmio_iowrite8(0x81, tmio->ccr + CCR_ICC); | |
320 | ||
321 | /* (10h)BaseAddress 0x1000 spba.spba2 */ | |
076c7f4c DB |
322 | tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE); |
323 | tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2); | |
ec43b816 IM |
324 | |
325 | /* (04h)Command Register I/O spcmd */ | |
326 | tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND); | |
327 | ||
328 | /* (62h) Power Supply Control ssmpwc */ | |
329 | /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */ | |
330 | tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC); | |
331 | ||
332 | /* (63h) Detect Control ssmdtc */ | |
333 | tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC); | |
334 | ||
335 | /* Interrupt status register clear sintst */ | |
336 | tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); | |
337 | ||
338 | /* After power supply, Media are reset smode */ | |
339 | tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE); | |
340 | tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE); | |
341 | tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA); | |
342 | ||
343 | /* Standby Mode smode */ | |
344 | tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE); | |
345 | ||
346 | mdelay(5); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio) | |
352 | { | |
944dc035 | 353 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
354 | |
355 | tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE); | |
356 | if (cell->disable) | |
357 | cell->disable(dev); | |
358 | } | |
359 | ||
360 | static int tmio_probe(struct platform_device *dev) | |
361 | { | |
453810b7 | 362 | struct tmio_nand_data *data = dev_get_platdata(&dev->dev); |
ec43b816 IM |
363 | struct resource *fcr = platform_get_resource(dev, |
364 | IORESOURCE_MEM, 0); | |
365 | struct resource *ccr = platform_get_resource(dev, | |
366 | IORESOURCE_MEM, 1); | |
367 | int irq = platform_get_irq(dev, 0); | |
368 | struct tmio_nand *tmio; | |
369 | struct mtd_info *mtd; | |
370 | struct nand_chip *nand_chip; | |
ec43b816 IM |
371 | int retval; |
372 | ||
373 | if (data == NULL) | |
374 | dev_warn(&dev->dev, "NULL platform data!\n"); | |
375 | ||
8f91fb68 JH |
376 | tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL); |
377 | if (!tmio) | |
378 | return -ENOMEM; | |
ec43b816 | 379 | |
a0916c94 BB |
380 | init_completion(&tmio->comp); |
381 | ||
ec43b816 IM |
382 | tmio->dev = dev; |
383 | ||
384 | platform_set_drvdata(dev, tmio); | |
ec43b816 | 385 | nand_chip = &tmio->chip; |
66c9595d | 386 | mtd = nand_to_mtd(nand_chip); |
ec43b816 | 387 | mtd->name = "tmio-nand"; |
7b679053 | 388 | mtd->dev.parent = &dev->dev; |
ec43b816 | 389 | |
8f91fb68 JH |
390 | tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr)); |
391 | if (!tmio->ccr) | |
392 | return -EIO; | |
ec43b816 | 393 | |
076c7f4c | 394 | tmio->fcr_base = fcr->start & 0xfffff; |
8f91fb68 JH |
395 | tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr)); |
396 | if (!tmio->fcr) | |
397 | return -EIO; | |
ec43b816 IM |
398 | |
399 | retval = tmio_hw_init(dev, tmio); | |
400 | if (retval) | |
8f91fb68 | 401 | return retval; |
ec43b816 IM |
402 | |
403 | /* Set address of NAND IO lines */ | |
82fc5099 BB |
404 | nand_chip->legacy.IO_ADDR_R = tmio->fcr; |
405 | nand_chip->legacy.IO_ADDR_W = tmio->fcr; | |
ec43b816 IM |
406 | |
407 | /* Set address of hardware control function */ | |
bf6065c6 | 408 | nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol; |
8395b753 | 409 | nand_chip->legacy.dev_ready = tmio_nand_dev_ready; |
716bbbab BB |
410 | nand_chip->legacy.read_byte = tmio_nand_read_byte; |
411 | nand_chip->legacy.write_buf = tmio_nand_write_buf; | |
412 | nand_chip->legacy.read_buf = tmio_nand_read_buf; | |
ec43b816 IM |
413 | |
414 | /* set eccmode using hardware ECC */ | |
415 | nand_chip->ecc.mode = NAND_ECC_HW; | |
416 | nand_chip->ecc.size = 512; | |
417 | nand_chip->ecc.bytes = 6; | |
6a918bad | 418 | nand_chip->ecc.strength = 2; |
ec43b816 IM |
419 | nand_chip->ecc.hwctl = tmio_nand_enable_hwecc; |
420 | nand_chip->ecc.calculate = tmio_nand_calculate_ecc; | |
0f777fb9 | 421 | nand_chip->ecc.correct = tmio_nand_correct_data; |
ec43b816 IM |
422 | |
423 | if (data) | |
424 | nand_chip->badblock_pattern = data->badblock_pattern; | |
425 | ||
426 | /* 15 us command delay time */ | |
3cece3ab | 427 | nand_chip->legacy.chip_delay = 15; |
ec43b816 | 428 | |
8f91fb68 JH |
429 | retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0, |
430 | dev_name(&dev->dev), tmio); | |
ec43b816 IM |
431 | if (retval) { |
432 | dev_err(&dev->dev, "request_irq error %d\n", retval); | |
433 | goto err_irq; | |
434 | } | |
435 | ||
436 | tmio->irq = irq; | |
8395b753 | 437 | nand_chip->legacy.waitfunc = tmio_nand_wait; |
ec43b816 IM |
438 | |
439 | /* Scan to find existence of the device */ | |
00ad378f | 440 | retval = nand_scan(nand_chip, 1); |
43358c17 | 441 | if (retval) |
8f91fb68 | 442 | goto err_irq; |
43358c17 | 443 | |
ec43b816 | 444 | /* Register the partitions */ |
311bba10 AA |
445 | retval = mtd_device_parse_register(mtd, |
446 | data ? data->part_parsers : NULL, | |
447 | NULL, | |
42d7fbe2 AB |
448 | data ? data->partition : NULL, |
449 | data ? data->num_partitions : 0); | |
ec43b816 IM |
450 | if (!retval) |
451 | return retval; | |
452 | ||
59ac276f | 453 | nand_release(nand_chip); |
ec43b816 | 454 | |
ec43b816 IM |
455 | err_irq: |
456 | tmio_hw_stop(dev, tmio); | |
ec43b816 IM |
457 | return retval; |
458 | } | |
459 | ||
460 | static int tmio_remove(struct platform_device *dev) | |
461 | { | |
462 | struct tmio_nand *tmio = platform_get_drvdata(dev); | |
463 | ||
59ac276f | 464 | nand_release(&tmio->chip); |
ec43b816 | 465 | tmio_hw_stop(dev, tmio); |
ec43b816 IM |
466 | return 0; |
467 | } | |
468 | ||
469 | #ifdef CONFIG_PM | |
470 | static int tmio_suspend(struct platform_device *dev, pm_message_t state) | |
471 | { | |
944dc035 | 472 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
473 | |
474 | if (cell->suspend) | |
475 | cell->suspend(dev); | |
476 | ||
477 | tmio_hw_stop(dev, platform_get_drvdata(dev)); | |
478 | return 0; | |
479 | } | |
480 | ||
481 | static int tmio_resume(struct platform_device *dev) | |
482 | { | |
944dc035 | 483 | const struct mfd_cell *cell = mfd_get_cell(dev); |
ec43b816 IM |
484 | |
485 | /* FIXME - is this required or merely another attack of the broken | |
486 | * SHARP platform? Looks suspicious. | |
487 | */ | |
488 | tmio_hw_init(dev, platform_get_drvdata(dev)); | |
489 | ||
490 | if (cell->resume) | |
491 | cell->resume(dev); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | #else | |
496 | #define tmio_suspend NULL | |
497 | #define tmio_resume NULL | |
498 | #endif | |
499 | ||
500 | static struct platform_driver tmio_driver = { | |
501 | .driver.name = "tmio-nand", | |
502 | .driver.owner = THIS_MODULE, | |
503 | .probe = tmio_probe, | |
504 | .remove = tmio_remove, | |
505 | .suspend = tmio_suspend, | |
506 | .resume = tmio_resume, | |
507 | }; | |
508 | ||
f99640de | 509 | module_platform_driver(tmio_driver); |
ec43b816 IM |
510 | |
511 | MODULE_LICENSE("GPL v2"); | |
512 | MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov"); | |
513 | MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller"); | |
514 | MODULE_ALIAS("platform:tmio-nand"); |