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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
59dbc86c MG |
2 | /* |
3 | * Copyright (C) 2016 Sigma Designs | |
59dbc86c MG |
4 | */ |
5 | ||
6956e238 MG |
6 | #include <linux/io.h> |
7 | #include <linux/of.h> | |
8 | #include <linux/clk.h> | |
9 | #include <linux/iopoll.h> | |
10 | #include <linux/module.h> | |
d4092d76 | 11 | #include <linux/mtd/rawnand.h> |
6956e238 MG |
12 | #include <linux/dmaengine.h> |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/platform_device.h> | |
15 | ||
16 | /* Offsets relative to chip->base */ | |
17 | #define PBUS_CMD 0 | |
18 | #define PBUS_ADDR 4 | |
19 | #define PBUS_DATA 8 | |
20 | ||
21 | /* Offsets relative to reg_base */ | |
22 | #define NFC_STATUS 0x00 | |
23 | #define NFC_FLASH_CMD 0x04 | |
24 | #define NFC_DEVICE_CFG 0x08 | |
25 | #define NFC_TIMING1 0x0c | |
26 | #define NFC_TIMING2 0x10 | |
27 | #define NFC_XFER_CFG 0x14 | |
28 | #define NFC_PKT_0_CFG 0x18 | |
29 | #define NFC_PKT_N_CFG 0x1c | |
30 | #define NFC_BB_CFG 0x20 | |
31 | #define NFC_ADDR_PAGE 0x24 | |
32 | #define NFC_ADDR_OFFSET 0x28 | |
33 | #define NFC_XFER_STATUS 0x2c | |
34 | ||
35 | /* NFC_STATUS values */ | |
36 | #define CMD_READY BIT(31) | |
37 | ||
38 | /* NFC_FLASH_CMD values */ | |
39 | #define NFC_READ 1 | |
40 | #define NFC_WRITE 2 | |
41 | ||
42 | /* NFC_XFER_STATUS values */ | |
43 | #define PAGE_IS_EMPTY BIT(16) | |
44 | ||
45 | /* Offsets relative to mem_base */ | |
46 | #define METADATA 0x000 | |
47 | #define ERROR_REPORT 0x1c0 | |
48 | ||
49 | /* | |
50 | * Error reports are split in two bytes: | |
51 | * byte 0 for the first packet in the page (PKT_0) | |
52 | * byte 1 for other packets in the page (PKT_N, for N > 0) | |
53 | * ERR_COUNT_PKT_N is the max error count over all but the first packet. | |
54 | */ | |
6956e238 MG |
55 | #define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) |
56 | #define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) | |
60cf0ce1 MG |
57 | #define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0) |
58 | #define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0) | |
6956e238 MG |
59 | |
60 | /* Offsets relative to pbus_base */ | |
61 | #define PBUS_CS_CTRL 0x83c | |
62 | #define PBUS_PAD_MODE 0x8f0 | |
63 | ||
64 | /* PBUS_CS_CTRL values */ | |
65 | #define PBUS_IORDY BIT(31) | |
66 | ||
67 | /* | |
68 | * PBUS_PAD_MODE values | |
69 | * In raw mode, the driver communicates directly with the NAND chips. | |
70 | * In NFC mode, the NAND Flash controller manages the communication. | |
71 | * We use NFC mode for read and write; raw mode for everything else. | |
72 | */ | |
73 | #define MODE_RAW 0 | |
74 | #define MODE_NFC BIT(31) | |
75 | ||
76 | #define METADATA_SIZE 4 | |
77 | #define BBM_SIZE 6 | |
78 | #define FIELD_ORDER 15 | |
79 | ||
80 | #define MAX_CS 4 | |
81 | ||
82 | struct tango_nfc { | |
7da45139 | 83 | struct nand_controller hw; |
6956e238 MG |
84 | void __iomem *reg_base; |
85 | void __iomem *mem_base; | |
86 | void __iomem *pbus_base; | |
87 | struct tango_chip *chips[MAX_CS]; | |
88 | struct dma_chan *chan; | |
89 | int freq_kHz; | |
90 | }; | |
91 | ||
92 | #define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) | |
93 | ||
94 | struct tango_chip { | |
95 | struct nand_chip nand_chip; | |
96 | void __iomem *base; | |
97 | u32 timing1; | |
98 | u32 timing2; | |
99 | u32 xfer_cfg; | |
100 | u32 pkt_0_cfg; | |
101 | u32 pkt_n_cfg; | |
102 | u32 bb_cfg; | |
103 | }; | |
104 | ||
105 | #define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) | |
106 | ||
107 | #define XFER_CFG(cs, page_count, steps, metadata_size) \ | |
108 | ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) | |
109 | ||
110 | #define PKT_CFG(size, strength) ((size) << 16 | (strength)) | |
111 | ||
112 | #define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) | |
113 | ||
114 | #define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) | |
115 | ||
0f808c16 | 116 | static void tango_cmd_ctrl(struct nand_chip *chip, int dat, unsigned int ctrl) |
6956e238 | 117 | { |
0f808c16 | 118 | struct tango_chip *tchip = to_tango_chip(chip); |
6956e238 MG |
119 | |
120 | if (ctrl & NAND_CLE) | |
121 | writeb_relaxed(dat, tchip->base + PBUS_CMD); | |
122 | ||
123 | if (ctrl & NAND_ALE) | |
124 | writeb_relaxed(dat, tchip->base + PBUS_ADDR); | |
125 | } | |
126 | ||
50a487e7 | 127 | static int tango_dev_ready(struct nand_chip *chip) |
6956e238 | 128 | { |
6956e238 MG |
129 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
130 | ||
131 | return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY; | |
132 | } | |
133 | ||
7e534323 | 134 | static u8 tango_read_byte(struct nand_chip *chip) |
6956e238 | 135 | { |
7e534323 | 136 | struct tango_chip *tchip = to_tango_chip(chip); |
6956e238 MG |
137 | |
138 | return readb_relaxed(tchip->base + PBUS_DATA); | |
139 | } | |
140 | ||
7e534323 | 141 | static void tango_read_buf(struct nand_chip *chip, u8 *buf, int len) |
6956e238 | 142 | { |
7e534323 | 143 | struct tango_chip *tchip = to_tango_chip(chip); |
6956e238 MG |
144 | |
145 | ioread8_rep(tchip->base + PBUS_DATA, buf, len); | |
146 | } | |
147 | ||
c0739d85 | 148 | static void tango_write_buf(struct nand_chip *chip, const u8 *buf, int len) |
6956e238 | 149 | { |
c0739d85 | 150 | struct tango_chip *tchip = to_tango_chip(chip); |
6956e238 MG |
151 | |
152 | iowrite8_rep(tchip->base + PBUS_DATA, buf, len); | |
153 | } | |
154 | ||
758b56f5 | 155 | static void tango_select_chip(struct nand_chip *chip, int idx) |
6956e238 | 156 | { |
6956e238 MG |
157 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
158 | struct tango_chip *tchip = to_tango_chip(chip); | |
159 | ||
160 | if (idx < 0) | |
161 | return; /* No "chip unselect" function */ | |
162 | ||
163 | writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); | |
164 | writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); | |
165 | writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); | |
166 | writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); | |
167 | writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); | |
168 | writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); | |
169 | } | |
170 | ||
171 | /* | |
172 | * The controller does not check for bitflips in erased pages, | |
173 | * therefore software must check instead. | |
174 | */ | |
175 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
176 | { | |
8fcfba07 | 177 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 MG |
178 | u8 *meta = chip->oob_poi + BBM_SIZE; |
179 | u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; | |
180 | const int ecc_size = chip->ecc.bytes; | |
181 | const int pkt_size = chip->ecc.size; | |
182 | int i, res, meta_len, bitflips = 0; | |
183 | ||
184 | for (i = 0; i < chip->ecc.steps; ++i) { | |
185 | meta_len = i ? 0 : METADATA_SIZE; | |
186 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
187 | meta, meta_len, | |
188 | chip->ecc.strength); | |
189 | if (res < 0) | |
8fcfba07 | 190 | mtd->ecc_stats.failed++; |
60cf0ce1 MG |
191 | else |
192 | mtd->ecc_stats.corrected += res; | |
6956e238 MG |
193 | |
194 | bitflips = max(res, bitflips); | |
195 | buf += pkt_size; | |
196 | ecc += ecc_size; | |
197 | } | |
198 | ||
199 | return bitflips; | |
200 | } | |
201 | ||
60cf0ce1 | 202 | static int decode_error_report(struct nand_chip *chip) |
6956e238 MG |
203 | { |
204 | u32 status, res; | |
60cf0ce1 MG |
205 | struct mtd_info *mtd = nand_to_mtd(chip); |
206 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
6956e238 MG |
207 | |
208 | status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); | |
209 | if (status & PAGE_IS_EMPTY) | |
210 | return 0; | |
211 | ||
212 | res = readl_relaxed(nfc->mem_base + ERROR_REPORT); | |
213 | ||
60cf0ce1 MG |
214 | if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res)) |
215 | return -EBADMSG; | |
216 | ||
217 | /* ERR_COUNT_PKT_N is max, not sum, but that's all we have */ | |
218 | mtd->ecc_stats.corrected += | |
219 | ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res); | |
6956e238 | 220 | |
60cf0ce1 | 221 | return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); |
6956e238 MG |
222 | } |
223 | ||
224 | static void tango_dma_callback(void *arg) | |
225 | { | |
226 | complete(arg); | |
227 | } | |
228 | ||
1932a964 BB |
229 | static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, |
230 | const void *buf, int len, int page) | |
6956e238 MG |
231 | { |
232 | void __iomem *addr = nfc->reg_base + NFC_STATUS; | |
233 | struct dma_chan *chan = nfc->chan; | |
234 | struct dma_async_tx_descriptor *desc; | |
1932a964 | 235 | enum dma_transfer_direction tdir; |
6956e238 MG |
236 | struct scatterlist sg; |
237 | struct completion tx_done; | |
238 | int err = -EIO; | |
239 | u32 res, val; | |
240 | ||
241 | sg_init_one(&sg, buf, len); | |
242 | if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) | |
243 | return -EIO; | |
244 | ||
1932a964 BB |
245 | tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; |
246 | desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT); | |
6956e238 MG |
247 | if (!desc) |
248 | goto dma_unmap; | |
249 | ||
250 | desc->callback = tango_dma_callback; | |
251 | desc->callback_param = &tx_done; | |
252 | init_completion(&tx_done); | |
253 | ||
254 | writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); | |
255 | ||
256 | writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); | |
257 | writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); | |
258 | writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); | |
259 | ||
260 | dmaengine_submit(desc); | |
261 | dma_async_issue_pending(chan); | |
262 | ||
263 | res = wait_for_completion_timeout(&tx_done, HZ); | |
264 | if (res > 0) | |
265 | err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); | |
266 | ||
267 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); | |
268 | ||
269 | dma_unmap: | |
270 | dma_unmap_sg(chan->device->dev, &sg, 1, dir); | |
271 | ||
272 | return err; | |
273 | } | |
274 | ||
b9761687 BB |
275 | static int tango_read_page(struct nand_chip *chip, u8 *buf, |
276 | int oob_required, int page) | |
6956e238 | 277 | { |
b9761687 | 278 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 MG |
279 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
280 | int err, res, len = mtd->writesize; | |
281 | ||
282 | if (oob_required) | |
b9761687 | 283 | chip->ecc.read_oob(chip, page); |
6956e238 MG |
284 | |
285 | err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); | |
286 | if (err) | |
287 | return err; | |
288 | ||
60cf0ce1 | 289 | res = decode_error_report(chip); |
6956e238 | 290 | if (res < 0) { |
b9761687 | 291 | chip->ecc.read_oob_raw(chip, page); |
6956e238 MG |
292 | res = check_erased_page(chip, buf); |
293 | } | |
294 | ||
295 | return res; | |
296 | } | |
297 | ||
767eb6fb BB |
298 | static int tango_write_page(struct nand_chip *chip, const u8 *buf, |
299 | int oob_required, int page) | |
6956e238 | 300 | { |
767eb6fb | 301 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 302 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
41145649 | 303 | int err, status, len = mtd->writesize; |
6956e238 MG |
304 | |
305 | /* Calling tango_write_oob() would send PAGEPROG twice */ | |
306 | if (oob_required) | |
307 | return -ENOTSUPP; | |
308 | ||
309 | writel_relaxed(0xffffffff, nfc->mem_base + METADATA); | |
310 | err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); | |
311 | if (err) | |
312 | return err; | |
313 | ||
8395b753 | 314 | status = chip->legacy.waitfunc(chip); |
41145649 BB |
315 | if (status & NAND_STATUS_FAIL) |
316 | return -EIO; | |
317 | ||
6956e238 MG |
318 | return 0; |
319 | } | |
320 | ||
321 | static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) | |
322 | { | |
323 | *pos += len; | |
324 | ||
325 | if (!*buf) { | |
326 | /* skip over "len" bytes */ | |
97d90da8 | 327 | nand_change_read_column_op(chip, *pos, NULL, 0, false); |
6956e238 | 328 | } else { |
7e534323 | 329 | tango_read_buf(chip, *buf, len); |
6956e238 MG |
330 | *buf += len; |
331 | } | |
332 | } | |
333 | ||
334 | static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) | |
335 | { | |
336 | *pos += len; | |
337 | ||
338 | if (!*buf) { | |
339 | /* skip over "len" bytes */ | |
97d90da8 | 340 | nand_change_write_column_op(chip, *pos, NULL, 0, false); |
6956e238 | 341 | } else { |
c0739d85 | 342 | tango_write_buf(chip, *buf, len); |
6956e238 MG |
343 | *buf += len; |
344 | } | |
345 | } | |
346 | ||
347 | /* | |
348 | * Physical page layout (not drawn to scale) | |
349 | * | |
350 | * NB: Bad Block Marker area splits PKT_N in two (N1, N2). | |
351 | * | |
352 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
353 | * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | | |
354 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
355 | * | |
356 | * Logical page layout: | |
357 | * | |
358 | * +-----+---+-------+-----+-------+ | |
359 | * oob = | BBM | M | ECC_0 | ... | ECC_N | | |
360 | * +-----+---+-------+-----+-------+ | |
361 | * | |
362 | * +-----------------+-----+-----------------+ | |
363 | * buf = | PKT_0 | ... | PKT_N | | |
364 | * +-----------------+-----+-----------------+ | |
365 | */ | |
37871abd | 366 | static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) |
6956e238 | 367 | { |
8fcfba07 | 368 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 369 | u8 *oob_orig = oob; |
8fcfba07 | 370 | const int page_size = mtd->writesize; |
6956e238 MG |
371 | const int ecc_size = chip->ecc.bytes; |
372 | const int pkt_size = chip->ecc.size; | |
373 | int pos = 0; /* position within physical page */ | |
374 | int rem = page_size; /* bytes remaining until BBM area */ | |
375 | ||
376 | if (oob) | |
377 | oob += BBM_SIZE; | |
378 | ||
379 | aux_read(chip, &oob, METADATA_SIZE, &pos); | |
380 | ||
381 | while (rem > pkt_size) { | |
382 | aux_read(chip, &buf, pkt_size, &pos); | |
383 | aux_read(chip, &oob, ecc_size, &pos); | |
384 | rem = page_size - pos; | |
385 | } | |
386 | ||
387 | aux_read(chip, &buf, rem, &pos); | |
388 | aux_read(chip, &oob_orig, BBM_SIZE, &pos); | |
389 | aux_read(chip, &buf, pkt_size - rem, &pos); | |
390 | aux_read(chip, &oob, ecc_size, &pos); | |
6956e238 MG |
391 | } |
392 | ||
37871abd | 393 | static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) |
6956e238 | 394 | { |
8fcfba07 | 395 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 396 | const u8 *oob_orig = oob; |
8fcfba07 | 397 | const int page_size = mtd->writesize; |
6956e238 MG |
398 | const int ecc_size = chip->ecc.bytes; |
399 | const int pkt_size = chip->ecc.size; | |
400 | int pos = 0; /* position within physical page */ | |
401 | int rem = page_size; /* bytes remaining until BBM area */ | |
402 | ||
403 | if (oob) | |
404 | oob += BBM_SIZE; | |
405 | ||
406 | aux_write(chip, &oob, METADATA_SIZE, &pos); | |
407 | ||
408 | while (rem > pkt_size) { | |
409 | aux_write(chip, &buf, pkt_size, &pos); | |
410 | aux_write(chip, &oob, ecc_size, &pos); | |
411 | rem = page_size - pos; | |
412 | } | |
413 | ||
414 | aux_write(chip, &buf, rem, &pos); | |
415 | aux_write(chip, &oob_orig, BBM_SIZE, &pos); | |
416 | aux_write(chip, &buf, pkt_size - rem, &pos); | |
417 | aux_write(chip, &oob, ecc_size, &pos); | |
6956e238 MG |
418 | } |
419 | ||
b9761687 BB |
420 | static int tango_read_page_raw(struct nand_chip *chip, u8 *buf, |
421 | int oob_required, int page) | |
6956e238 | 422 | { |
97d90da8 | 423 | nand_read_page_op(chip, page, 0, NULL, 0); |
37871abd MG |
424 | raw_read(chip, buf, chip->oob_poi); |
425 | return 0; | |
6956e238 MG |
426 | } |
427 | ||
767eb6fb BB |
428 | static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf, |
429 | int oob_required, int page) | |
6956e238 | 430 | { |
97d90da8 | 431 | nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
ff9e9eae | 432 | raw_write(chip, buf, chip->oob_poi); |
97d90da8 | 433 | return nand_prog_page_end_op(chip); |
6956e238 MG |
434 | } |
435 | ||
b9761687 | 436 | static int tango_read_oob(struct nand_chip *chip, int page) |
6956e238 | 437 | { |
97d90da8 | 438 | nand_read_page_op(chip, page, 0, NULL, 0); |
37871abd MG |
439 | raw_read(chip, NULL, chip->oob_poi); |
440 | return 0; | |
6956e238 MG |
441 | } |
442 | ||
767eb6fb | 443 | static int tango_write_oob(struct nand_chip *chip, int page) |
6956e238 | 444 | { |
97d90da8 | 445 | nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
6956e238 | 446 | raw_write(chip, NULL, chip->oob_poi); |
97d90da8 | 447 | return nand_prog_page_end_op(chip); |
6956e238 MG |
448 | } |
449 | ||
450 | static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
451 | { | |
452 | struct nand_chip *chip = mtd_to_nand(mtd); | |
453 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
454 | ||
455 | if (idx >= ecc->steps) | |
456 | return -ERANGE; | |
457 | ||
458 | res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; | |
459 | res->length = ecc->bytes; | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
465 | { | |
466 | return -ERANGE; /* no free space in spare area */ | |
467 | } | |
468 | ||
469 | static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { | |
470 | .ecc = oob_ecc, | |
471 | .free = oob_free, | |
472 | }; | |
473 | ||
474 | static u32 to_ticks(int kHz, int ps) | |
475 | { | |
476 | return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); | |
477 | } | |
478 | ||
858838b8 | 479 | static int tango_set_timings(struct nand_chip *chip, int csline, |
104e442a | 480 | const struct nand_data_interface *conf) |
6956e238 MG |
481 | { |
482 | const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); | |
6956e238 MG |
483 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
484 | struct tango_chip *tchip = to_tango_chip(chip); | |
485 | u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; | |
486 | int kHz = nfc->freq_kHz; | |
487 | ||
488 | if (IS_ERR(sdr)) | |
489 | return PTR_ERR(sdr); | |
490 | ||
104e442a | 491 | if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
6956e238 MG |
492 | return 0; |
493 | ||
494 | Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); | |
495 | Textw = to_ticks(kHz, sdr->tWB_max); | |
496 | Twc = to_ticks(kHz, sdr->tWC_min); | |
497 | Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); | |
498 | ||
499 | Tacc = to_ticks(kHz, sdr->tREA_max); | |
500 | Thold = to_ticks(kHz, sdr->tREH_min); | |
501 | Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); | |
502 | Textr = to_ticks(kHz, sdr->tRHZ_max); | |
503 | ||
504 | tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); | |
505 | tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
6a9035ce MR |
510 | static int tango_attach_chip(struct nand_chip *chip) |
511 | { | |
512 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
513 | ||
514 | ecc->mode = NAND_ECC_HW; | |
515 | ecc->algo = NAND_ECC_BCH; | |
516 | ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); | |
517 | ||
518 | ecc->read_page_raw = tango_read_page_raw; | |
519 | ecc->write_page_raw = tango_write_page_raw; | |
520 | ecc->read_page = tango_read_page; | |
521 | ecc->write_page = tango_write_page; | |
522 | ecc->read_oob = tango_read_oob; | |
523 | ecc->write_oob = tango_write_oob; | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | static const struct nand_controller_ops tango_controller_ops = { | |
529 | .attach_chip = tango_attach_chip, | |
7a08dbae | 530 | .setup_data_interface = tango_set_timings, |
6a9035ce MR |
531 | }; |
532 | ||
6956e238 MG |
533 | static int chip_init(struct device *dev, struct device_node *np) |
534 | { | |
535 | u32 cs; | |
536 | int err, res; | |
537 | struct mtd_info *mtd; | |
538 | struct nand_chip *chip; | |
539 | struct tango_chip *tchip; | |
540 | struct nand_ecc_ctrl *ecc; | |
541 | struct tango_nfc *nfc = dev_get_drvdata(dev); | |
542 | ||
543 | tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); | |
544 | if (!tchip) | |
545 | return -ENOMEM; | |
546 | ||
547 | res = of_property_count_u32_elems(np, "reg"); | |
548 | if (res < 0) | |
549 | return res; | |
550 | ||
551 | if (res != 1) | |
552 | return -ENOTSUPP; /* Multi-CS chips are not supported */ | |
553 | ||
554 | err = of_property_read_u32_index(np, "reg", 0, &cs); | |
555 | if (err) | |
556 | return err; | |
557 | ||
558 | if (cs >= MAX_CS) | |
559 | return -EINVAL; | |
560 | ||
561 | chip = &tchip->nand_chip; | |
562 | ecc = &chip->ecc; | |
8fcfba07 | 563 | mtd = nand_to_mtd(chip); |
6956e238 | 564 | |
716bbbab BB |
565 | chip->legacy.read_byte = tango_read_byte; |
566 | chip->legacy.write_buf = tango_write_buf; | |
567 | chip->legacy.read_buf = tango_read_buf; | |
7d6c37e9 | 568 | chip->legacy.select_chip = tango_select_chip; |
bf6065c6 | 569 | chip->legacy.cmd_ctrl = tango_cmd_ctrl; |
8395b753 | 570 | chip->legacy.dev_ready = tango_dev_ready; |
6956e238 MG |
571 | chip->options = NAND_USE_BOUNCE_BUFFER | |
572 | NAND_NO_SUBPAGE_WRITE | | |
573 | NAND_WAIT_TCCS; | |
574 | chip->controller = &nfc->hw; | |
575 | tchip->base = nfc->pbus_base + (cs * 256); | |
576 | ||
577 | nand_set_flash_node(chip, np); | |
578 | mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); | |
579 | mtd->dev.parent = dev; | |
580 | ||
00ad378f | 581 | err = nand_scan(chip, 1); |
6956e238 MG |
582 | if (err) |
583 | return err; | |
584 | ||
585 | tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); | |
586 | tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); | |
587 | tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); | |
588 | tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); | |
589 | ||
590 | err = mtd_device_register(mtd, NULL, 0); | |
0eaa879b MR |
591 | if (err) { |
592 | nand_cleanup(chip); | |
6956e238 | 593 | return err; |
0eaa879b | 594 | } |
6956e238 MG |
595 | |
596 | nfc->chips[cs] = tchip; | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | static int tango_nand_remove(struct platform_device *pdev) | |
602 | { | |
603 | int cs; | |
604 | struct tango_nfc *nfc = platform_get_drvdata(pdev); | |
605 | ||
606 | dma_release_channel(nfc->chan); | |
607 | ||
608 | for (cs = 0; cs < MAX_CS; ++cs) { | |
609 | if (nfc->chips[cs]) | |
59ac276f | 610 | nand_release(&nfc->chips[cs]->nand_chip); |
6956e238 MG |
611 | } |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | static int tango_nand_probe(struct platform_device *pdev) | |
617 | { | |
618 | int err; | |
619 | struct clk *clk; | |
620 | struct resource *res; | |
621 | struct tango_nfc *nfc; | |
622 | struct device_node *np; | |
623 | ||
624 | nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); | |
625 | if (!nfc) | |
626 | return -ENOMEM; | |
627 | ||
628 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
629 | nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
630 | if (IS_ERR(nfc->reg_base)) | |
631 | return PTR_ERR(nfc->reg_base); | |
632 | ||
633 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
634 | nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); | |
635 | if (IS_ERR(nfc->mem_base)) | |
636 | return PTR_ERR(nfc->mem_base); | |
637 | ||
638 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
639 | nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); | |
640 | if (IS_ERR(nfc->pbus_base)) | |
641 | return PTR_ERR(nfc->pbus_base); | |
642 | ||
8043d25b MG |
643 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); |
644 | ||
007b4e8b | 645 | clk = devm_clk_get(&pdev->dev, NULL); |
6956e238 MG |
646 | if (IS_ERR(clk)) |
647 | return PTR_ERR(clk); | |
648 | ||
7165b8ad | 649 | nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); |
6956e238 MG |
650 | if (IS_ERR(nfc->chan)) |
651 | return PTR_ERR(nfc->chan); | |
652 | ||
653 | platform_set_drvdata(pdev, nfc); | |
7da45139 | 654 | nand_controller_init(&nfc->hw); |
6a9035ce | 655 | nfc->hw.ops = &tango_controller_ops; |
6956e238 MG |
656 | nfc->freq_kHz = clk_get_rate(clk) / 1000; |
657 | ||
658 | for_each_child_of_node(pdev->dev.of_node, np) { | |
659 | err = chip_init(&pdev->dev, np); | |
660 | if (err) { | |
661 | tango_nand_remove(pdev); | |
662 | return err; | |
663 | } | |
664 | } | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static const struct of_device_id tango_nand_ids[] = { | |
670 | { .compatible = "sigma,smp8758-nand" }, | |
671 | { /* sentinel */ } | |
672 | }; | |
2761b4f1 | 673 | MODULE_DEVICE_TABLE(of, tango_nand_ids); |
6956e238 MG |
674 | |
675 | static struct platform_driver tango_nand_driver = { | |
676 | .probe = tango_nand_probe, | |
677 | .remove = tango_nand_remove, | |
678 | .driver = { | |
679 | .name = "tango-nand", | |
680 | .of_match_table = tango_nand_ids, | |
681 | }, | |
682 | }; | |
683 | ||
684 | module_platform_driver(tango_nand_driver); | |
685 | ||
686 | MODULE_LICENSE("GPL"); | |
687 | MODULE_AUTHOR("Sigma Designs"); | |
688 | MODULE_DESCRIPTION("Tango4 NAND Flash controller driver"); |