Commit | Line | Data |
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59dbc86c MG |
1 | /* |
2 | * Copyright (C) 2016 Sigma Designs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
6956e238 MG |
9 | #include <linux/io.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/iopoll.h> | |
13 | #include <linux/module.h> | |
d4092d76 | 14 | #include <linux/mtd/rawnand.h> |
6956e238 MG |
15 | #include <linux/dmaengine.h> |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/platform_device.h> | |
18 | ||
19 | /* Offsets relative to chip->base */ | |
20 | #define PBUS_CMD 0 | |
21 | #define PBUS_ADDR 4 | |
22 | #define PBUS_DATA 8 | |
23 | ||
24 | /* Offsets relative to reg_base */ | |
25 | #define NFC_STATUS 0x00 | |
26 | #define NFC_FLASH_CMD 0x04 | |
27 | #define NFC_DEVICE_CFG 0x08 | |
28 | #define NFC_TIMING1 0x0c | |
29 | #define NFC_TIMING2 0x10 | |
30 | #define NFC_XFER_CFG 0x14 | |
31 | #define NFC_PKT_0_CFG 0x18 | |
32 | #define NFC_PKT_N_CFG 0x1c | |
33 | #define NFC_BB_CFG 0x20 | |
34 | #define NFC_ADDR_PAGE 0x24 | |
35 | #define NFC_ADDR_OFFSET 0x28 | |
36 | #define NFC_XFER_STATUS 0x2c | |
37 | ||
38 | /* NFC_STATUS values */ | |
39 | #define CMD_READY BIT(31) | |
40 | ||
41 | /* NFC_FLASH_CMD values */ | |
42 | #define NFC_READ 1 | |
43 | #define NFC_WRITE 2 | |
44 | ||
45 | /* NFC_XFER_STATUS values */ | |
46 | #define PAGE_IS_EMPTY BIT(16) | |
47 | ||
48 | /* Offsets relative to mem_base */ | |
49 | #define METADATA 0x000 | |
50 | #define ERROR_REPORT 0x1c0 | |
51 | ||
52 | /* | |
53 | * Error reports are split in two bytes: | |
54 | * byte 0 for the first packet in the page (PKT_0) | |
55 | * byte 1 for other packets in the page (PKT_N, for N > 0) | |
56 | * ERR_COUNT_PKT_N is the max error count over all but the first packet. | |
57 | */ | |
6956e238 MG |
58 | #define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) |
59 | #define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) | |
60cf0ce1 MG |
60 | #define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0) |
61 | #define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0) | |
6956e238 MG |
62 | |
63 | /* Offsets relative to pbus_base */ | |
64 | #define PBUS_CS_CTRL 0x83c | |
65 | #define PBUS_PAD_MODE 0x8f0 | |
66 | ||
67 | /* PBUS_CS_CTRL values */ | |
68 | #define PBUS_IORDY BIT(31) | |
69 | ||
70 | /* | |
71 | * PBUS_PAD_MODE values | |
72 | * In raw mode, the driver communicates directly with the NAND chips. | |
73 | * In NFC mode, the NAND Flash controller manages the communication. | |
74 | * We use NFC mode for read and write; raw mode for everything else. | |
75 | */ | |
76 | #define MODE_RAW 0 | |
77 | #define MODE_NFC BIT(31) | |
78 | ||
79 | #define METADATA_SIZE 4 | |
80 | #define BBM_SIZE 6 | |
81 | #define FIELD_ORDER 15 | |
82 | ||
83 | #define MAX_CS 4 | |
84 | ||
85 | struct tango_nfc { | |
7da45139 | 86 | struct nand_controller hw; |
6956e238 MG |
87 | void __iomem *reg_base; |
88 | void __iomem *mem_base; | |
89 | void __iomem *pbus_base; | |
90 | struct tango_chip *chips[MAX_CS]; | |
91 | struct dma_chan *chan; | |
92 | int freq_kHz; | |
93 | }; | |
94 | ||
95 | #define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) | |
96 | ||
97 | struct tango_chip { | |
98 | struct nand_chip nand_chip; | |
99 | void __iomem *base; | |
100 | u32 timing1; | |
101 | u32 timing2; | |
102 | u32 xfer_cfg; | |
103 | u32 pkt_0_cfg; | |
104 | u32 pkt_n_cfg; | |
105 | u32 bb_cfg; | |
106 | }; | |
107 | ||
108 | #define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) | |
109 | ||
110 | #define XFER_CFG(cs, page_count, steps, metadata_size) \ | |
111 | ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) | |
112 | ||
113 | #define PKT_CFG(size, strength) ((size) << 16 | (strength)) | |
114 | ||
115 | #define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) | |
116 | ||
117 | #define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) | |
118 | ||
119 | static void tango_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) | |
120 | { | |
121 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
122 | ||
123 | if (ctrl & NAND_CLE) | |
124 | writeb_relaxed(dat, tchip->base + PBUS_CMD); | |
125 | ||
126 | if (ctrl & NAND_ALE) | |
127 | writeb_relaxed(dat, tchip->base + PBUS_ADDR); | |
128 | } | |
129 | ||
130 | static int tango_dev_ready(struct mtd_info *mtd) | |
131 | { | |
132 | struct nand_chip *chip = mtd_to_nand(mtd); | |
133 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
134 | ||
135 | return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY; | |
136 | } | |
137 | ||
7e534323 | 138 | static u8 tango_read_byte(struct nand_chip *chip) |
6956e238 | 139 | { |
7e534323 | 140 | struct tango_chip *tchip = to_tango_chip(chip); |
6956e238 MG |
141 | |
142 | return readb_relaxed(tchip->base + PBUS_DATA); | |
143 | } | |
144 | ||
7e534323 | 145 | static void tango_read_buf(struct nand_chip *chip, u8 *buf, int len) |
6956e238 | 146 | { |
7e534323 | 147 | struct tango_chip *tchip = to_tango_chip(chip); |
6956e238 MG |
148 | |
149 | ioread8_rep(tchip->base + PBUS_DATA, buf, len); | |
150 | } | |
151 | ||
152 | static void tango_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
153 | { | |
154 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
155 | ||
156 | iowrite8_rep(tchip->base + PBUS_DATA, buf, len); | |
157 | } | |
158 | ||
159 | static void tango_select_chip(struct mtd_info *mtd, int idx) | |
160 | { | |
161 | struct nand_chip *chip = mtd_to_nand(mtd); | |
162 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
163 | struct tango_chip *tchip = to_tango_chip(chip); | |
164 | ||
165 | if (idx < 0) | |
166 | return; /* No "chip unselect" function */ | |
167 | ||
168 | writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); | |
169 | writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); | |
170 | writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); | |
171 | writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); | |
172 | writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); | |
173 | writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); | |
174 | } | |
175 | ||
176 | /* | |
177 | * The controller does not check for bitflips in erased pages, | |
178 | * therefore software must check instead. | |
179 | */ | |
180 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
181 | { | |
8fcfba07 | 182 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 MG |
183 | u8 *meta = chip->oob_poi + BBM_SIZE; |
184 | u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; | |
185 | const int ecc_size = chip->ecc.bytes; | |
186 | const int pkt_size = chip->ecc.size; | |
187 | int i, res, meta_len, bitflips = 0; | |
188 | ||
189 | for (i = 0; i < chip->ecc.steps; ++i) { | |
190 | meta_len = i ? 0 : METADATA_SIZE; | |
191 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
192 | meta, meta_len, | |
193 | chip->ecc.strength); | |
194 | if (res < 0) | |
8fcfba07 | 195 | mtd->ecc_stats.failed++; |
60cf0ce1 MG |
196 | else |
197 | mtd->ecc_stats.corrected += res; | |
6956e238 MG |
198 | |
199 | bitflips = max(res, bitflips); | |
200 | buf += pkt_size; | |
201 | ecc += ecc_size; | |
202 | } | |
203 | ||
204 | return bitflips; | |
205 | } | |
206 | ||
60cf0ce1 | 207 | static int decode_error_report(struct nand_chip *chip) |
6956e238 MG |
208 | { |
209 | u32 status, res; | |
60cf0ce1 MG |
210 | struct mtd_info *mtd = nand_to_mtd(chip); |
211 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
6956e238 MG |
212 | |
213 | status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); | |
214 | if (status & PAGE_IS_EMPTY) | |
215 | return 0; | |
216 | ||
217 | res = readl_relaxed(nfc->mem_base + ERROR_REPORT); | |
218 | ||
60cf0ce1 MG |
219 | if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res)) |
220 | return -EBADMSG; | |
221 | ||
222 | /* ERR_COUNT_PKT_N is max, not sum, but that's all we have */ | |
223 | mtd->ecc_stats.corrected += | |
224 | ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res); | |
6956e238 | 225 | |
60cf0ce1 | 226 | return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); |
6956e238 MG |
227 | } |
228 | ||
229 | static void tango_dma_callback(void *arg) | |
230 | { | |
231 | complete(arg); | |
232 | } | |
233 | ||
1932a964 BB |
234 | static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, |
235 | const void *buf, int len, int page) | |
6956e238 MG |
236 | { |
237 | void __iomem *addr = nfc->reg_base + NFC_STATUS; | |
238 | struct dma_chan *chan = nfc->chan; | |
239 | struct dma_async_tx_descriptor *desc; | |
1932a964 | 240 | enum dma_transfer_direction tdir; |
6956e238 MG |
241 | struct scatterlist sg; |
242 | struct completion tx_done; | |
243 | int err = -EIO; | |
244 | u32 res, val; | |
245 | ||
246 | sg_init_one(&sg, buf, len); | |
247 | if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) | |
248 | return -EIO; | |
249 | ||
1932a964 BB |
250 | tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; |
251 | desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT); | |
6956e238 MG |
252 | if (!desc) |
253 | goto dma_unmap; | |
254 | ||
255 | desc->callback = tango_dma_callback; | |
256 | desc->callback_param = &tx_done; | |
257 | init_completion(&tx_done); | |
258 | ||
259 | writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); | |
260 | ||
261 | writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); | |
262 | writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); | |
263 | writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); | |
264 | ||
265 | dmaengine_submit(desc); | |
266 | dma_async_issue_pending(chan); | |
267 | ||
268 | res = wait_for_completion_timeout(&tx_done, HZ); | |
269 | if (res > 0) | |
270 | err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); | |
271 | ||
272 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); | |
273 | ||
274 | dma_unmap: | |
275 | dma_unmap_sg(chan->device->dev, &sg, 1, dir); | |
276 | ||
277 | return err; | |
278 | } | |
279 | ||
b9761687 BB |
280 | static int tango_read_page(struct nand_chip *chip, u8 *buf, |
281 | int oob_required, int page) | |
6956e238 | 282 | { |
b9761687 | 283 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 MG |
284 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
285 | int err, res, len = mtd->writesize; | |
286 | ||
287 | if (oob_required) | |
b9761687 | 288 | chip->ecc.read_oob(chip, page); |
6956e238 MG |
289 | |
290 | err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); | |
291 | if (err) | |
292 | return err; | |
293 | ||
60cf0ce1 | 294 | res = decode_error_report(chip); |
6956e238 | 295 | if (res < 0) { |
b9761687 | 296 | chip->ecc.read_oob_raw(chip, page); |
6956e238 MG |
297 | res = check_erased_page(chip, buf); |
298 | } | |
299 | ||
300 | return res; | |
301 | } | |
302 | ||
767eb6fb BB |
303 | static int tango_write_page(struct nand_chip *chip, const u8 *buf, |
304 | int oob_required, int page) | |
6956e238 | 305 | { |
767eb6fb | 306 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 307 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
41145649 | 308 | int err, status, len = mtd->writesize; |
6956e238 MG |
309 | |
310 | /* Calling tango_write_oob() would send PAGEPROG twice */ | |
311 | if (oob_required) | |
312 | return -ENOTSUPP; | |
313 | ||
314 | writel_relaxed(0xffffffff, nfc->mem_base + METADATA); | |
315 | err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); | |
316 | if (err) | |
317 | return err; | |
318 | ||
41145649 BB |
319 | status = chip->waitfunc(mtd, chip); |
320 | if (status & NAND_STATUS_FAIL) | |
321 | return -EIO; | |
322 | ||
6956e238 MG |
323 | return 0; |
324 | } | |
325 | ||
326 | static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) | |
327 | { | |
328 | *pos += len; | |
329 | ||
330 | if (!*buf) { | |
331 | /* skip over "len" bytes */ | |
97d90da8 | 332 | nand_change_read_column_op(chip, *pos, NULL, 0, false); |
6956e238 | 333 | } else { |
7e534323 | 334 | tango_read_buf(chip, *buf, len); |
6956e238 MG |
335 | *buf += len; |
336 | } | |
337 | } | |
338 | ||
339 | static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) | |
340 | { | |
8fcfba07 BB |
341 | struct mtd_info *mtd = nand_to_mtd(chip); |
342 | ||
6956e238 MG |
343 | *pos += len; |
344 | ||
345 | if (!*buf) { | |
346 | /* skip over "len" bytes */ | |
97d90da8 | 347 | nand_change_write_column_op(chip, *pos, NULL, 0, false); |
6956e238 | 348 | } else { |
8fcfba07 | 349 | tango_write_buf(mtd, *buf, len); |
6956e238 MG |
350 | *buf += len; |
351 | } | |
352 | } | |
353 | ||
354 | /* | |
355 | * Physical page layout (not drawn to scale) | |
356 | * | |
357 | * NB: Bad Block Marker area splits PKT_N in two (N1, N2). | |
358 | * | |
359 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
360 | * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | | |
361 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
362 | * | |
363 | * Logical page layout: | |
364 | * | |
365 | * +-----+---+-------+-----+-------+ | |
366 | * oob = | BBM | M | ECC_0 | ... | ECC_N | | |
367 | * +-----+---+-------+-----+-------+ | |
368 | * | |
369 | * +-----------------+-----+-----------------+ | |
370 | * buf = | PKT_0 | ... | PKT_N | | |
371 | * +-----------------+-----+-----------------+ | |
372 | */ | |
37871abd | 373 | static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) |
6956e238 | 374 | { |
8fcfba07 | 375 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 376 | u8 *oob_orig = oob; |
8fcfba07 | 377 | const int page_size = mtd->writesize; |
6956e238 MG |
378 | const int ecc_size = chip->ecc.bytes; |
379 | const int pkt_size = chip->ecc.size; | |
380 | int pos = 0; /* position within physical page */ | |
381 | int rem = page_size; /* bytes remaining until BBM area */ | |
382 | ||
383 | if (oob) | |
384 | oob += BBM_SIZE; | |
385 | ||
386 | aux_read(chip, &oob, METADATA_SIZE, &pos); | |
387 | ||
388 | while (rem > pkt_size) { | |
389 | aux_read(chip, &buf, pkt_size, &pos); | |
390 | aux_read(chip, &oob, ecc_size, &pos); | |
391 | rem = page_size - pos; | |
392 | } | |
393 | ||
394 | aux_read(chip, &buf, rem, &pos); | |
395 | aux_read(chip, &oob_orig, BBM_SIZE, &pos); | |
396 | aux_read(chip, &buf, pkt_size - rem, &pos); | |
397 | aux_read(chip, &oob, ecc_size, &pos); | |
6956e238 MG |
398 | } |
399 | ||
37871abd | 400 | static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) |
6956e238 | 401 | { |
8fcfba07 | 402 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 403 | const u8 *oob_orig = oob; |
8fcfba07 | 404 | const int page_size = mtd->writesize; |
6956e238 MG |
405 | const int ecc_size = chip->ecc.bytes; |
406 | const int pkt_size = chip->ecc.size; | |
407 | int pos = 0; /* position within physical page */ | |
408 | int rem = page_size; /* bytes remaining until BBM area */ | |
409 | ||
410 | if (oob) | |
411 | oob += BBM_SIZE; | |
412 | ||
413 | aux_write(chip, &oob, METADATA_SIZE, &pos); | |
414 | ||
415 | while (rem > pkt_size) { | |
416 | aux_write(chip, &buf, pkt_size, &pos); | |
417 | aux_write(chip, &oob, ecc_size, &pos); | |
418 | rem = page_size - pos; | |
419 | } | |
420 | ||
421 | aux_write(chip, &buf, rem, &pos); | |
422 | aux_write(chip, &oob_orig, BBM_SIZE, &pos); | |
423 | aux_write(chip, &buf, pkt_size - rem, &pos); | |
424 | aux_write(chip, &oob, ecc_size, &pos); | |
6956e238 MG |
425 | } |
426 | ||
b9761687 BB |
427 | static int tango_read_page_raw(struct nand_chip *chip, u8 *buf, |
428 | int oob_required, int page) | |
6956e238 | 429 | { |
97d90da8 | 430 | nand_read_page_op(chip, page, 0, NULL, 0); |
37871abd MG |
431 | raw_read(chip, buf, chip->oob_poi); |
432 | return 0; | |
6956e238 MG |
433 | } |
434 | ||
767eb6fb BB |
435 | static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf, |
436 | int oob_required, int page) | |
6956e238 | 437 | { |
97d90da8 | 438 | nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
ff9e9eae | 439 | raw_write(chip, buf, chip->oob_poi); |
97d90da8 | 440 | return nand_prog_page_end_op(chip); |
6956e238 MG |
441 | } |
442 | ||
b9761687 | 443 | static int tango_read_oob(struct nand_chip *chip, int page) |
6956e238 | 444 | { |
97d90da8 | 445 | nand_read_page_op(chip, page, 0, NULL, 0); |
37871abd MG |
446 | raw_read(chip, NULL, chip->oob_poi); |
447 | return 0; | |
6956e238 MG |
448 | } |
449 | ||
767eb6fb | 450 | static int tango_write_oob(struct nand_chip *chip, int page) |
6956e238 | 451 | { |
97d90da8 | 452 | nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
6956e238 | 453 | raw_write(chip, NULL, chip->oob_poi); |
97d90da8 | 454 | return nand_prog_page_end_op(chip); |
6956e238 MG |
455 | } |
456 | ||
457 | static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
458 | { | |
459 | struct nand_chip *chip = mtd_to_nand(mtd); | |
460 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
461 | ||
462 | if (idx >= ecc->steps) | |
463 | return -ERANGE; | |
464 | ||
465 | res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; | |
466 | res->length = ecc->bytes; | |
467 | ||
468 | return 0; | |
469 | } | |
470 | ||
471 | static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
472 | { | |
473 | return -ERANGE; /* no free space in spare area */ | |
474 | } | |
475 | ||
476 | static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { | |
477 | .ecc = oob_ecc, | |
478 | .free = oob_free, | |
479 | }; | |
480 | ||
481 | static u32 to_ticks(int kHz, int ps) | |
482 | { | |
483 | return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); | |
484 | } | |
485 | ||
104e442a BB |
486 | static int tango_set_timings(struct mtd_info *mtd, int csline, |
487 | const struct nand_data_interface *conf) | |
6956e238 MG |
488 | { |
489 | const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); | |
490 | struct nand_chip *chip = mtd_to_nand(mtd); | |
491 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
492 | struct tango_chip *tchip = to_tango_chip(chip); | |
493 | u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; | |
494 | int kHz = nfc->freq_kHz; | |
495 | ||
496 | if (IS_ERR(sdr)) | |
497 | return PTR_ERR(sdr); | |
498 | ||
104e442a | 499 | if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
6956e238 MG |
500 | return 0; |
501 | ||
502 | Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); | |
503 | Textw = to_ticks(kHz, sdr->tWB_max); | |
504 | Twc = to_ticks(kHz, sdr->tWC_min); | |
505 | Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); | |
506 | ||
507 | Tacc = to_ticks(kHz, sdr->tREA_max); | |
508 | Thold = to_ticks(kHz, sdr->tREH_min); | |
509 | Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); | |
510 | Textr = to_ticks(kHz, sdr->tRHZ_max); | |
511 | ||
512 | tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); | |
513 | tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
6a9035ce MR |
518 | static int tango_attach_chip(struct nand_chip *chip) |
519 | { | |
520 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
521 | ||
522 | ecc->mode = NAND_ECC_HW; | |
523 | ecc->algo = NAND_ECC_BCH; | |
524 | ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); | |
525 | ||
526 | ecc->read_page_raw = tango_read_page_raw; | |
527 | ecc->write_page_raw = tango_write_page_raw; | |
528 | ecc->read_page = tango_read_page; | |
529 | ecc->write_page = tango_write_page; | |
530 | ecc->read_oob = tango_read_oob; | |
531 | ecc->write_oob = tango_write_oob; | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static const struct nand_controller_ops tango_controller_ops = { | |
537 | .attach_chip = tango_attach_chip, | |
538 | }; | |
539 | ||
6956e238 MG |
540 | static int chip_init(struct device *dev, struct device_node *np) |
541 | { | |
542 | u32 cs; | |
543 | int err, res; | |
544 | struct mtd_info *mtd; | |
545 | struct nand_chip *chip; | |
546 | struct tango_chip *tchip; | |
547 | struct nand_ecc_ctrl *ecc; | |
548 | struct tango_nfc *nfc = dev_get_drvdata(dev); | |
549 | ||
550 | tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); | |
551 | if (!tchip) | |
552 | return -ENOMEM; | |
553 | ||
554 | res = of_property_count_u32_elems(np, "reg"); | |
555 | if (res < 0) | |
556 | return res; | |
557 | ||
558 | if (res != 1) | |
559 | return -ENOTSUPP; /* Multi-CS chips are not supported */ | |
560 | ||
561 | err = of_property_read_u32_index(np, "reg", 0, &cs); | |
562 | if (err) | |
563 | return err; | |
564 | ||
565 | if (cs >= MAX_CS) | |
566 | return -EINVAL; | |
567 | ||
568 | chip = &tchip->nand_chip; | |
569 | ecc = &chip->ecc; | |
8fcfba07 | 570 | mtd = nand_to_mtd(chip); |
6956e238 MG |
571 | |
572 | chip->read_byte = tango_read_byte; | |
573 | chip->write_buf = tango_write_buf; | |
574 | chip->read_buf = tango_read_buf; | |
575 | chip->select_chip = tango_select_chip; | |
576 | chip->cmd_ctrl = tango_cmd_ctrl; | |
577 | chip->dev_ready = tango_dev_ready; | |
578 | chip->setup_data_interface = tango_set_timings; | |
579 | chip->options = NAND_USE_BOUNCE_BUFFER | | |
580 | NAND_NO_SUBPAGE_WRITE | | |
581 | NAND_WAIT_TCCS; | |
582 | chip->controller = &nfc->hw; | |
583 | tchip->base = nfc->pbus_base + (cs * 256); | |
584 | ||
585 | nand_set_flash_node(chip, np); | |
586 | mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); | |
587 | mtd->dev.parent = dev; | |
588 | ||
00ad378f | 589 | err = nand_scan(chip, 1); |
6956e238 MG |
590 | if (err) |
591 | return err; | |
592 | ||
593 | tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); | |
594 | tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); | |
595 | tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); | |
596 | tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); | |
597 | ||
598 | err = mtd_device_register(mtd, NULL, 0); | |
0eaa879b MR |
599 | if (err) { |
600 | nand_cleanup(chip); | |
6956e238 | 601 | return err; |
0eaa879b | 602 | } |
6956e238 MG |
603 | |
604 | nfc->chips[cs] = tchip; | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static int tango_nand_remove(struct platform_device *pdev) | |
610 | { | |
611 | int cs; | |
612 | struct tango_nfc *nfc = platform_get_drvdata(pdev); | |
613 | ||
614 | dma_release_channel(nfc->chan); | |
615 | ||
616 | for (cs = 0; cs < MAX_CS; ++cs) { | |
617 | if (nfc->chips[cs]) | |
59ac276f | 618 | nand_release(&nfc->chips[cs]->nand_chip); |
6956e238 MG |
619 | } |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
624 | static int tango_nand_probe(struct platform_device *pdev) | |
625 | { | |
626 | int err; | |
627 | struct clk *clk; | |
628 | struct resource *res; | |
629 | struct tango_nfc *nfc; | |
630 | struct device_node *np; | |
631 | ||
632 | nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); | |
633 | if (!nfc) | |
634 | return -ENOMEM; | |
635 | ||
636 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
637 | nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
638 | if (IS_ERR(nfc->reg_base)) | |
639 | return PTR_ERR(nfc->reg_base); | |
640 | ||
641 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
642 | nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); | |
643 | if (IS_ERR(nfc->mem_base)) | |
644 | return PTR_ERR(nfc->mem_base); | |
645 | ||
646 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
647 | nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); | |
648 | if (IS_ERR(nfc->pbus_base)) | |
649 | return PTR_ERR(nfc->pbus_base); | |
650 | ||
8043d25b MG |
651 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); |
652 | ||
007b4e8b | 653 | clk = devm_clk_get(&pdev->dev, NULL); |
6956e238 MG |
654 | if (IS_ERR(clk)) |
655 | return PTR_ERR(clk); | |
656 | ||
7165b8ad | 657 | nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); |
6956e238 MG |
658 | if (IS_ERR(nfc->chan)) |
659 | return PTR_ERR(nfc->chan); | |
660 | ||
661 | platform_set_drvdata(pdev, nfc); | |
7da45139 | 662 | nand_controller_init(&nfc->hw); |
6a9035ce | 663 | nfc->hw.ops = &tango_controller_ops; |
6956e238 MG |
664 | nfc->freq_kHz = clk_get_rate(clk) / 1000; |
665 | ||
666 | for_each_child_of_node(pdev->dev.of_node, np) { | |
667 | err = chip_init(&pdev->dev, np); | |
668 | if (err) { | |
669 | tango_nand_remove(pdev); | |
670 | return err; | |
671 | } | |
672 | } | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | static const struct of_device_id tango_nand_ids[] = { | |
678 | { .compatible = "sigma,smp8758-nand" }, | |
679 | { /* sentinel */ } | |
680 | }; | |
2761b4f1 | 681 | MODULE_DEVICE_TABLE(of, tango_nand_ids); |
6956e238 MG |
682 | |
683 | static struct platform_driver tango_nand_driver = { | |
684 | .probe = tango_nand_probe, | |
685 | .remove = tango_nand_remove, | |
686 | .driver = { | |
687 | .name = "tango-nand", | |
688 | .of_match_table = tango_nand_ids, | |
689 | }, | |
690 | }; | |
691 | ||
692 | module_platform_driver(tango_nand_driver); | |
693 | ||
694 | MODULE_LICENSE("GPL"); | |
695 | MODULE_AUTHOR("Sigma Designs"); | |
696 | MODULE_DESCRIPTION("Tango4 NAND Flash controller driver"); |