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mtd: rawnand: Pass a nand_chip object to chip->select_chip()
[linux-2.6-block.git] / drivers / mtd / nand / raw / sh_flctl.c
CommitLineData
6028aa01
YS		 1/*
2 * SuperH FLCTL nand controller
3 *
b79c7adf
MD		 4 * Copyright (c) 2008 Renesas Solutions Corp.
5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd.
6028aa01 6 *
b79c7adf 7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor
6028aa01
YS		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
83738d87 26#include <linux/completion.h>
6028aa01 27#include <linux/delay.h>
83738d87
BH		 28#include <linux/dmaengine.h>
29#include <linux/dma-mapping.h>
3c7ea4ec 30#include <linux/interrupt.h>
6028aa01 31#include <linux/io.h>
7c8f680e
BH		 32#include <linux/of.h>
33#include <linux/of_device.h>
6028aa01 34#include <linux/platform_device.h>
cfe78194 35#include <linux/pm_runtime.h>
83738d87 36#include <linux/sh_dma.h>
5a0e3ad6 37#include <linux/slab.h>
d76236f3 38#include <linux/string.h>
6028aa01
YS		 39
40#include <linux/mtd/mtd.h>
d4092d76 41#include <linux/mtd/rawnand.h>
6028aa01
YS		 42#include <linux/mtd/partitions.h>
43#include <linux/mtd/sh_flctl.h>
44
e7049f29
BB		 45static int flctl_4secc_ooblayout_sp_ecc(struct mtd_info *mtd, int section,
46 struct mtd_oob_region *oobregion)
47{
48 struct nand_chip *chip = mtd_to_nand(mtd);
49
50 if (section)
51 return -ERANGE;
52
53 oobregion->offset = 0;
54 oobregion->length = chip->ecc.bytes;
55
56 return 0;
57}
58
59static int flctl_4secc_ooblayout_sp_free(struct mtd_info *mtd, int section,
60 struct mtd_oob_region *oobregion)
61{
62 if (section)
63 return -ERANGE;
64
65 oobregion->offset = 12;
66 oobregion->length = 4;
67
68 return 0;
69}
70
71static const struct mtd_ooblayout_ops flctl_4secc_oob_smallpage_ops = {
72 .ecc = flctl_4secc_ooblayout_sp_ecc,
73 .free = flctl_4secc_ooblayout_sp_free,
6028aa01
YS		 74};
75
e7049f29
BB		 76static int flctl_4secc_ooblayout_lp_ecc(struct mtd_info *mtd, int section,
77 struct mtd_oob_region *oobregion)
78{
79 struct nand_chip *chip = mtd_to_nand(mtd);
80
81 if (section >= chip->ecc.steps)
82 return -ERANGE;
83
84 oobregion->offset = (section * 16) + 6;
85 oobregion->length = chip->ecc.bytes;
86
87 return 0;
88}
89
90static int flctl_4secc_ooblayout_lp_free(struct mtd_info *mtd, int section,
91 struct mtd_oob_region *oobregion)
92{
93 struct nand_chip *chip = mtd_to_nand(mtd);
94
95 if (section >= chip->ecc.steps)
96 return -ERANGE;
97
98 oobregion->offset = section * 16;
99 oobregion->length = 6;
100
101 if (!section) {
102 oobregion->offset += 2;
103 oobregion->length -= 2;
104 }
105
106 return 0;
107}
108
109static const struct mtd_ooblayout_ops flctl_4secc_oob_largepage_ops = {
110 .ecc = flctl_4secc_ooblayout_lp_ecc,
111 .free = flctl_4secc_ooblayout_lp_free,
6028aa01
YS		 112};
113
114static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
115
116static struct nand_bbt_descr flctl_4secc_smallpage = {
117 .options = NAND_BBT_SCAN2NDPAGE,
118 .offs = 11,
119 .len = 1,
120 .pattern = scan_ff_pattern,
121};
122
123static struct nand_bbt_descr flctl_4secc_largepage = {
c0e6616a 124 .options = NAND_BBT_SCAN2NDPAGE,
aa32d1f0 125 .offs = 0,
6028aa01
YS		 126 .len = 2,
127 .pattern = scan_ff_pattern,
128};
129
130static void empty_fifo(struct sh_flctl *flctl)
131{
3c7ea4ec
BH		 132 writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl));
133 writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
6028aa01
YS		 134}
135
136static void start_translation(struct sh_flctl *flctl)
137{
138 writeb(TRSTRT, FLTRCR(flctl));
139}
140
b79c7adf
MD		 141static void timeout_error(struct sh_flctl *flctl, const char *str)
142{
25985edc 143 dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str);
b79c7adf
MD		 144}
145
6028aa01
YS		 146static void wait_completion(struct sh_flctl *flctl)
147{
148 uint32_t timeout = LOOP_TIMEOUT_MAX;
149
150 while (timeout--) {
151 if (readb(FLTRCR(flctl)) & TREND) {
152 writeb(0x0, FLTRCR(flctl));
153 return;
154 }
155 udelay(1);
156 }
157
b79c7adf 158 timeout_error(flctl, __func__);
6028aa01
YS		 159 writeb(0x0, FLTRCR(flctl));
160}
161
83738d87
BH		 162static void flctl_dma_complete(void *param)
163{
164 struct sh_flctl *flctl = param;
165
166 complete(&flctl->dma_complete);
167}
168
169static void flctl_release_dma(struct sh_flctl *flctl)
170{
171 if (flctl->chan_fifo0_rx) {
172 dma_release_channel(flctl->chan_fifo0_rx);
173 flctl->chan_fifo0_rx = NULL;
174 }
175 if (flctl->chan_fifo0_tx) {
176 dma_release_channel(flctl->chan_fifo0_tx);
177 flctl->chan_fifo0_tx = NULL;
178 }
179}
180
181static void flctl_setup_dma(struct sh_flctl *flctl)
182{
183 dma_cap_mask_t mask;
184 struct dma_slave_config cfg;
185 struct platform_device *pdev = flctl->pdev;
453810b7 186 struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev);
83738d87
BH		 187 int ret;
188
189 if (!pdata)
190 return;
191
192 if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
193 return;
194
195 /* We can only either use DMA for both Tx and Rx or not use it at all */
196 dma_cap_zero(mask);
197 dma_cap_set(DMA_SLAVE, mask);
198
199 flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
82ae816e 200 (void *)(uintptr_t)pdata->slave_id_fifo0_tx);
83738d87
BH		 201 dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
202 flctl->chan_fifo0_tx);
203
204 if (!flctl->chan_fifo0_tx)
205 return;
206
207 memset(&cfg, 0, sizeof(cfg));
83738d87 208 cfg.direction = DMA_MEM_TO_DEV;
1873315f 209 cfg.dst_addr = flctl->fifo;
83738d87
BH		 210 cfg.src_addr = 0;
211 ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
212 if (ret < 0)
213 goto err;
214
215 flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
82ae816e 216 (void *)(uintptr_t)pdata->slave_id_fifo0_rx);
83738d87
BH		 217 dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
218 flctl->chan_fifo0_rx);
219
220 if (!flctl->chan_fifo0_rx)
221 goto err;
222
83738d87
BH		 223 cfg.direction = DMA_DEV_TO_MEM;
224 cfg.dst_addr = 0;
1873315f 225 cfg.src_addr = flctl->fifo;
83738d87
BH		 226 ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
227 if (ret < 0)
228 goto err;
229
230 init_completion(&flctl->dma_complete);
231
232 return;
233
234err:
235 flctl_release_dma(flctl);
236}
237
6028aa01
YS		 238static void set_addr(struct mtd_info *mtd, int column, int page_addr)
239{
240 struct sh_flctl *flctl = mtd_to_flctl(mtd);
241 uint32_t addr = 0;
242
243 if (column == -1) {
244 addr = page_addr; /* ERASE1 */
245 } else if (page_addr != -1) {
246 /* SEQIN, READ0, etc.. */
010ab820
MD		 247 if (flctl->chip.options & NAND_BUSWIDTH_16)
248 column >>= 1;
6028aa01
YS		 249 if (flctl->page_size) {
250 addr = column & 0x0FFF;
251 addr |= (page_addr & 0xff) << 16;
252 addr |= ((page_addr >> 8) & 0xff) << 24;
253 /* big than 128MB */
254 if (flctl->rw_ADRCNT == ADRCNT2_E) {
255 uint32_t addr2;
256 addr2 = (page_addr >> 16) & 0xff;
257 writel(addr2, FLADR2(flctl));
258 }
259 } else {
260 addr = column;
261 addr |= (page_addr & 0xff) << 8;
262 addr |= ((page_addr >> 8) & 0xff) << 16;
263 addr |= ((page_addr >> 16) & 0xff) << 24;
264 }
265 }
266 writel(addr, FLADR(flctl));
267}
268
269static void wait_rfifo_ready(struct sh_flctl *flctl)
270{
271 uint32_t timeout = LOOP_TIMEOUT_MAX;
272
273 while (timeout--) {
274 uint32_t val;
275 /* check FIFO */
276 val = readl(FLDTCNTR(flctl)) >> 16;
277 if (val & 0xFF)
278 return;
279 udelay(1);
280 }
b79c7adf 281 timeout_error(flctl, __func__);
6028aa01
YS		 282}
283
284static void wait_wfifo_ready(struct sh_flctl *flctl)
285{
286 uint32_t len, timeout = LOOP_TIMEOUT_MAX;
287
288 while (timeout--) {
289 /* check FIFO */
290 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
291 if (len >= 4)
292 return;
293 udelay(1);
294 }
b79c7adf 295 timeout_error(flctl, __func__);
6028aa01
YS		 296}
297
6667a6d5
BH		 298static enum flctl_ecc_res_t wait_recfifo_ready
299 (struct sh_flctl *flctl, int sector_number)
6028aa01
YS		 300{
301 uint32_t timeout = LOOP_TIMEOUT_MAX;
6028aa01
YS		 302 void __iomem *ecc_reg[4];
303 int i;
6667a6d5 304 int state = FL_SUCCESS;
6028aa01
YS		 305 uint32_t data, size;
306
6667a6d5
BH		 307 /*
308 * First this loops checks in FLDTCNTR if we are ready to read out the
309 * oob data. This is the case if either all went fine without errors or
310 * if the bottom part of the loop corrected the errors or marked them as
311 * uncorrectable and the controller is given time to push the data into
312 * the FIFO.
313 */
6028aa01 314 while (timeout--) {
6667a6d5 315 /* check if all is ok and we can read out the OOB */
6028aa01 316 size = readl(FLDTCNTR(flctl)) >> 24;
6667a6d5
BH		 317 if ((size & 0xFF) == 4)
318 return state;
319
320 /* check if a correction code has been calculated */
321 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) {
322 /*
323 * either we wait for the fifo to be filled or a
324 * correction pattern is being generated
325 */
326 udelay(1);
327 continue;
328 }
6028aa01 329
6667a6d5
BH		 330 /* check for an uncorrectable error */
331 if (readl(FL4ECCCR(flctl)) & _4ECCFA) {
332 /* check if we face a non-empty page */
333 for (i = 0; i < 512; i++) {
334 if (flctl->done_buff[i] != 0xff) {
335 state = FL_ERROR; /* can't correct */
336 break;
337 }
338 }
6028aa01 339
6667a6d5
BH		 340 if (state == FL_SUCCESS)
341 dev_dbg(&flctl->pdev->dev,
342 "reading empty sector %d, ecc error ignored\n",
343 sector_number);
344
345 writel(0, FL4ECCCR(flctl));
6028aa01 346 continue;
6667a6d5 347 }
6028aa01
YS		 348
349 /* start error correction */
350 ecc_reg[0] = FL4ECCRESULT0(flctl);
351 ecc_reg[1] = FL4ECCRESULT1(flctl);
352 ecc_reg[2] = FL4ECCRESULT2(flctl);
353 ecc_reg[3] = FL4ECCRESULT3(flctl);
354
355 for (i = 0; i < 3; i++) {
6667a6d5 356 uint8_t org;
e8a9d8f3 357 unsigned int index;
6667a6d5 358
6028aa01 359 data = readl(ecc_reg[i]);
6028aa01 360
6667a6d5
BH		 361 if (flctl->page_size)
362 index = (512 * sector_number) +
363 (data >> 16);
364 else
365 index = data >> 16;
366
367 org = flctl->done_buff[index];
368 flctl->done_buff[index] = org ^ (data & 0xFF);
369 }
370 state = FL_REPAIRABLE;
6028aa01
YS		 371 writel(0, FL4ECCCR(flctl));
372 }
373
b79c7adf 374 timeout_error(flctl, __func__);
6667a6d5 375 return FL_TIMEOUT; /* timeout */
6028aa01
YS		 376}
377
378static void wait_wecfifo_ready(struct sh_flctl *flctl)
379{
380 uint32_t timeout = LOOP_TIMEOUT_MAX;
381 uint32_t len;
382
383 while (timeout--) {
384 /* check FLECFIFO */
385 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
386 if (len >= 4)
387 return;
388 udelay(1);
389 }
b79c7adf 390 timeout_error(flctl, __func__);
6028aa01
YS		 391}
392
83738d87
BH		 393static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
394 int len, enum dma_data_direction dir)
395{
396 struct dma_async_tx_descriptor *desc = NULL;
397 struct dma_chan *chan;
398 enum dma_transfer_direction tr_dir;
399 dma_addr_t dma_addr;
3fe4f900 400 dma_cookie_t cookie;
83738d87
BH		 401 uint32_t reg;
402 int ret;
403
404 if (dir == DMA_FROM_DEVICE) {
405 chan = flctl->chan_fifo0_rx;
406 tr_dir = DMA_DEV_TO_MEM;
407 } else {
408 chan = flctl->chan_fifo0_tx;
409 tr_dir = DMA_MEM_TO_DEV;
410 }
411
412 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
413
dbf5f642 414 if (!dma_mapping_error(chan->device->dev, dma_addr))
83738d87
BH		 415 desc = dmaengine_prep_slave_single(chan, dma_addr, len,
416 tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
417
418 if (desc) {
419 reg = readl(FLINTDMACR(flctl));
420 reg |= DREQ0EN;
421 writel(reg, FLINTDMACR(flctl));
422
423 desc->callback = flctl_dma_complete;
424 desc->callback_param = flctl;
425 cookie = dmaengine_submit(desc);
3fe4f900
BN		 426 if (dma_submit_error(cookie)) {
427 ret = dma_submit_error(cookie);
428 dev_warn(&flctl->pdev->dev,
429 "DMA submit failed, falling back to PIO\n");
430 goto out;
431 }
83738d87
BH		 432
433 dma_async_issue_pending(chan);
434 } else {
435 /* DMA failed, fall back to PIO */
436 flctl_release_dma(flctl);
437 dev_warn(&flctl->pdev->dev,
438 "DMA failed, falling back to PIO\n");
439 ret = -EIO;
440 goto out;
441 }
442
443 ret =
444 wait_for_completion_timeout(&flctl->dma_complete,
445 msecs_to_jiffies(3000));
446
447 if (ret <= 0) {
0e497c36 448 dmaengine_terminate_all(chan);
83738d87
BH		 449 dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
450 }
451
452out:
453 reg = readl(FLINTDMACR(flctl));
454 reg &= ~DREQ0EN;
455 writel(reg, FLINTDMACR(flctl));
456
457 dma_unmap_single(chan->device->dev, dma_addr, len, dir);
458
459 /* ret > 0 is success */
460 return ret;
461}
462
6028aa01
YS		 463static void read_datareg(struct sh_flctl *flctl, int offset)
464{
465 unsigned long data;
466 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
467
468 wait_completion(flctl);
469
470 data = readl(FLDATAR(flctl));
471 *buf = le32_to_cpu(data);
472}
473
474static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
475{
476 int i, len_4align;
477 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
6028aa01
YS		 478
479 len_4align = (rlen + 3) / 4;
480
83738d87
BH		 481 /* initiate DMA transfer */
482 if (flctl->chan_fifo0_rx && rlen >= 32 &&
483 flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM) > 0)
484 goto convert; /* DMA success */
485
486 /* do polling transfer */
6028aa01
YS		 487 for (i = 0; i < len_4align; i++) {
488 wait_rfifo_ready(flctl);
3166df0d 489 buf[i] = readl(FLDTFIFO(flctl));
6028aa01 490 }
83738d87
BH		 491
492convert:
493 for (i = 0; i < len_4align; i++)
494 buf[i] = be32_to_cpu(buf[i]);
6028aa01
YS		 495}
496
6667a6d5
BH		 497static enum flctl_ecc_res_t read_ecfiforeg
498 (struct sh_flctl *flctl, uint8_t *buff, int sector)
6028aa01
YS		 499{
500 int i;
6667a6d5 501 enum flctl_ecc_res_t res;
6028aa01 502 unsigned long *ecc_buf = (unsigned long *)buff;
6028aa01 503
6667a6d5
BH		 504 res = wait_recfifo_ready(flctl , sector);
505
506 if (res != FL_ERROR) {
507 for (i = 0; i < 4; i++) {
508 ecc_buf[i] = readl(FLECFIFO(flctl));
509 ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
510 }
6028aa01
YS		 511 }
512
6667a6d5 513 return res;
6028aa01
YS		 514}
515
e8a9d8f3
BH		 516static void write_fiforeg(struct sh_flctl *flctl, int rlen,
517 unsigned int offset)
6028aa01
YS		 518{
519 int i, len_4align;
e8a9d8f3 520 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
6028aa01
YS		 521
522 len_4align = (rlen + 3) / 4;
523 for (i = 0; i < len_4align; i++) {
524 wait_wfifo_ready(flctl);
e8a9d8f3 525 writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
6028aa01
YS		 526 }
527}
528
e8a9d8f3
BH		 529static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen,
530 unsigned int offset)
3166df0d
BH		 531{
532 int i, len_4align;
e8a9d8f3 533 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
3166df0d
BH		 534
535 len_4align = (rlen + 3) / 4;
83738d87
BH		 536
537 for (i = 0; i < len_4align; i++)
538 buf[i] = cpu_to_be32(buf[i]);
539
540 /* initiate DMA transfer */
541 if (flctl->chan_fifo0_tx && rlen >= 32 &&
542 flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV) > 0)
543 return; /* DMA success */
544
545 /* do polling transfer */
3166df0d
BH		 546 for (i = 0; i < len_4align; i++) {
547 wait_wecfifo_ready(flctl);
83738d87 548 writel(buf[i], FLECFIFO(flctl));
3166df0d
BH		 549 }
550}
551
6028aa01
YS		 552static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
553{
554 struct sh_flctl *flctl = mtd_to_flctl(mtd);
0b3f0d12 555 uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT;
6028aa01
YS		 556 uint32_t flcmdcr_val, addr_len_bytes = 0;
557
558 /* Set SNAND bit if page size is 2048byte */
559 if (flctl->page_size)
560 flcmncr_val |= SNAND_E;
561 else
562 flcmncr_val &= ~SNAND_E;
563
564 /* default FLCMDCR val */
565 flcmdcr_val = DOCMD1_E | DOADR_E;
566
567 /* Set for FLCMDCR */
568 switch (cmd) {
569 case NAND_CMD_ERASE1:
570 addr_len_bytes = flctl->erase_ADRCNT;
571 flcmdcr_val |= DOCMD2_E;
572 break;
573 case NAND_CMD_READ0:
574 case NAND_CMD_READOOB:
dd5ab248 575 case NAND_CMD_RNDOUT:
6028aa01
YS		 576 addr_len_bytes = flctl->rw_ADRCNT;
577 flcmdcr_val |= CDSRC_E;
010ab820
MD		 578 if (flctl->chip.options & NAND_BUSWIDTH_16)
579 flcmncr_val |= SEL_16BIT;
6028aa01
YS		 580 break;
581 case NAND_CMD_SEQIN:
582 /* This case is that cmd is READ0 or READ1 or READ00 */
583 flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
584 break;
585 case NAND_CMD_PAGEPROG:
586 addr_len_bytes = flctl->rw_ADRCNT;
35a34799 587 flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW;
010ab820
MD		 588 if (flctl->chip.options & NAND_BUSWIDTH_16)
589 flcmncr_val |= SEL_16BIT;
35a34799
YS		 590 break;
591 case NAND_CMD_READID:
592 flcmncr_val &= ~SNAND_E;
7b6b2303 593 flcmdcr_val |= CDSRC_E;
35a34799
YS		 594 addr_len_bytes = ADRCNT_1;
595 break;
596 case NAND_CMD_STATUS:
597 case NAND_CMD_RESET:
598 flcmncr_val &= ~SNAND_E;
599 flcmdcr_val &= ~(DOADR_E | DOSR_E);
600 break;
601 default:
602 break;
603 }
604
605 /* Set address bytes parameter */
606 flcmdcr_val |= addr_len_bytes;
607
608 /* Now actually write */
609 writel(flcmncr_val, FLCMNCR(flctl));
610 writel(flcmdcr_val, FLCMDCR(flctl));
611 writel(flcmcdr_val, FLCMCDR(flctl));
612}
613
b9761687
BB		 614static int flctl_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
615 int oob_required, int page)
35a34799 616{
b9761687
BB		 617 struct mtd_info *mtd = nand_to_mtd(chip);
618
25f815f6 619 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
894824f9 620 if (oob_required)
7e534323 621 chip->read_buf(chip, chip->oob_poi, mtd->oobsize);
35a34799
YS		 622 return 0;
623}
624
767eb6fb
BB		 625static int flctl_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
626 int oob_required, int page)
35a34799 627{
767eb6fb
BB		 628 struct mtd_info *mtd = nand_to_mtd(chip);
629
25f815f6 630 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
c0739d85 631 chip->write_buf(chip, chip->oob_poi, mtd->oobsize);
25f815f6 632 return nand_prog_page_end_op(chip);
35a34799
YS		 633}
634
635static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr)
636{
637 struct sh_flctl *flctl = mtd_to_flctl(mtd);
638 int sector, page_sectors;
6667a6d5 639 enum flctl_ecc_res_t ecc_result;
35a34799 640
623c55ca
BH		 641 page_sectors = flctl->page_size ? 4 : 1;
642
643 set_cmd_regs(mtd, NAND_CMD_READ0,
644 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
35a34799
YS		 645
646 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
647 FLCMNCR(flctl));
623c55ca
BH		 648 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
649 writel(page_addr << 2, FLADR(flctl));
35a34799 650
623c55ca
BH		 651 empty_fifo(flctl);
652 start_translation(flctl);
35a34799
YS		 653
654 for (sector = 0; sector < page_sectors; sector++) {
35a34799
YS		 655 read_fiforeg(flctl, 512, 512 * sector);
656
6667a6d5 657 ecc_result = read_ecfiforeg(flctl,
c0e6616a
YS		 658 &flctl->done_buff[mtd->writesize + 16 * sector],
659 sector);
35a34799 660
6667a6d5
BH		 661 switch (ecc_result) {
662 case FL_REPAIRABLE:
663 dev_info(&flctl->pdev->dev,
664 "applied ecc on page 0x%x", page_addr);
9c9eef89 665 mtd->ecc_stats.corrected++;
6667a6d5
BH		 666 break;
667 case FL_ERROR:
668 dev_warn(&flctl->pdev->dev,
669 "page 0x%x contains corrupted data\n",
670 page_addr);
9c9eef89 671 mtd->ecc_stats.failed++;
6667a6d5
BH		 672 break;
673 default:
674 ;
675 }
35a34799 676 }
623c55ca
BH		 677
678 wait_completion(flctl);
679
35a34799
YS		 680 writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
681 FLCMNCR(flctl));
682}
683
684static void execmd_read_oob(struct mtd_info *mtd, int page_addr)
685{
686 struct sh_flctl *flctl = mtd_to_flctl(mtd);
ef4ce0bc
BH		 687 int page_sectors = flctl->page_size ? 4 : 1;
688 int i;
35a34799
YS		 689
690 set_cmd_regs(mtd, NAND_CMD_READ0,
691 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0);
692
693 empty_fifo(flctl);
35a34799 694
ef4ce0bc
BH		 695 for (i = 0; i < page_sectors; i++) {
696 set_addr(mtd, (512 + 16) * i + 512 , page_addr);
35a34799
YS		 697 writel(16, FLDTCNTR(flctl));
698
699 start_translation(flctl);
ef4ce0bc 700 read_fiforeg(flctl, 16, 16 * i);
35a34799
YS		 701 wait_completion(flctl);
702 }
703}
704
705static void execmd_write_page_sector(struct mtd_info *mtd)
706{
707 struct sh_flctl *flctl = mtd_to_flctl(mtd);
3166df0d 708 int page_addr = flctl->seqin_page_addr;
35a34799
YS		 709 int sector, page_sectors;
710
623c55ca 711 page_sectors = flctl->page_size ? 4 : 1;
35a34799
YS		 712
713 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
714 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
715
623c55ca
BH		 716 empty_fifo(flctl);
717 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
718 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
719 writel(page_addr << 2, FLADR(flctl));
720 start_translation(flctl);
35a34799 721
623c55ca 722 for (sector = 0; sector < page_sectors; sector++) {
35a34799 723 write_fiforeg(flctl, 512, 512 * sector);
3166df0d 724 write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector);
35a34799
YS		 725 }
726
623c55ca 727 wait_completion(flctl);
35a34799
YS		 728 writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
729}
730
731static void execmd_write_oob(struct mtd_info *mtd)
732{
733 struct sh_flctl *flctl = mtd_to_flctl(mtd);
734 int page_addr = flctl->seqin_page_addr;
735 int sector, page_sectors;
736
ef4ce0bc 737 page_sectors = flctl->page_size ? 4 : 1;
35a34799
YS		 738
739 set_cmd_regs(mtd, NAND_CMD_PAGEPROG,
740 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN);
741
ef4ce0bc 742 for (sector = 0; sector < page_sectors; sector++) {
35a34799
YS		 743 empty_fifo(flctl);
744 set_addr(mtd, sector * 528 + 512, page_addr);
745 writel(16, FLDTCNTR(flctl)); /* set read size */
746
747 start_translation(flctl);
748 write_fiforeg(flctl, 16, 16 * sector);
749 wait_completion(flctl);
750 }
751}
752
753static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command,
754 int column, int page_addr)
755{
756 struct sh_flctl *flctl = mtd_to_flctl(mtd);
757 uint32_t read_cmd = 0;
758
cfe78194
BH		 759 pm_runtime_get_sync(&flctl->pdev->dev);
760
35a34799
YS		 761 flctl->read_bytes = 0;
762 if (command != NAND_CMD_PAGEPROG)
763 flctl->index = 0;
764
765 switch (command) {
766 case NAND_CMD_READ1:
767 case NAND_CMD_READ0:
768 if (flctl->hwecc) {
769 /* read page with hwecc */
770 execmd_read_page_sector(mtd, page_addr);
771 break;
772 }
35a34799
YS		 773 if (flctl->page_size)
774 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
775 | command);
776 else
777 set_cmd_regs(mtd, command, command);
778
779 set_addr(mtd, 0, page_addr);
780
781 flctl->read_bytes = mtd->writesize + mtd->oobsize;
010ab820
MD		 782 if (flctl->chip.options & NAND_BUSWIDTH_16)
783 column >>= 1;
35a34799
YS		 784 flctl->index += column;
785 goto read_normal_exit;
786
787 case NAND_CMD_READOOB:
788 if (flctl->hwecc) {
789 /* read page with hwecc */
790 execmd_read_oob(mtd, page_addr);
791 break;
792 }
793
35a34799
YS		 794 if (flctl->page_size) {
795 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8)
796 | NAND_CMD_READ0);
797 set_addr(mtd, mtd->writesize, page_addr);
798 } else {
799 set_cmd_regs(mtd, command, command);
800 set_addr(mtd, 0, page_addr);
801 }
802 flctl->read_bytes = mtd->oobsize;
803 goto read_normal_exit;
804
dd5ab248
BH		 805 case NAND_CMD_RNDOUT:
806 if (flctl->hwecc)
807 break;
808
809 if (flctl->page_size)
810 set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8)
811 | command);
812 else
813 set_cmd_regs(mtd, command, command);
814
815 set_addr(mtd, column, 0);
816
817 flctl->read_bytes = mtd->writesize + mtd->oobsize - column;
818 goto read_normal_exit;
819
35a34799 820 case NAND_CMD_READID:
35a34799 821 set_cmd_regs(mtd, command, command);
35a34799 822
7b6b2303
BH		 823 /* READID is always performed using an 8-bit bus */
824 if (flctl->chip.options & NAND_BUSWIDTH_16)
825 column <<= 1;
826 set_addr(mtd, column, 0);
827
828 flctl->read_bytes = 8;
35a34799 829 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
abb59ef3 830 empty_fifo(flctl);
35a34799 831 start_translation(flctl);
7b6b2303
BH		 832 read_fiforeg(flctl, flctl->read_bytes, 0);
833 wait_completion(flctl);
35a34799
YS		 834 break;
835
836 case NAND_CMD_ERASE1:
837 flctl->erase1_page_addr = page_addr;
838 break;
839
840 case NAND_CMD_ERASE2:
841 set_cmd_regs(mtd, NAND_CMD_ERASE1,
842 (command << 8) | NAND_CMD_ERASE1);
843 set_addr(mtd, -1, flctl->erase1_page_addr);
844 start_translation(flctl);
845 wait_completion(flctl);
846 break;
847
848 case NAND_CMD_SEQIN:
849 if (!flctl->page_size) {
850 /* output read command */
851 if (column >= mtd->writesize) {
852 column -= mtd->writesize;
853 read_cmd = NAND_CMD_READOOB;
854 } else if (column < 256) {
855 read_cmd = NAND_CMD_READ0;
856 } else {
857 column -= 256;
858 read_cmd = NAND_CMD_READ1;
859 }
860 }
861 flctl->seqin_column = column;
862 flctl->seqin_page_addr = page_addr;
863 flctl->seqin_read_cmd = read_cmd;
864 break;
865
866 case NAND_CMD_PAGEPROG:
867 empty_fifo(flctl);
868 if (!flctl->page_size) {
869 set_cmd_regs(mtd, NAND_CMD_SEQIN,
870 flctl->seqin_read_cmd);
871 set_addr(mtd, -1, -1);
872 writel(0, FLDTCNTR(flctl)); /* set 0 size */
873 start_translation(flctl);
874 wait_completion(flctl);
875 }
876 if (flctl->hwecc) {
877 /* write page with hwecc */
878 if (flctl->seqin_column == mtd->writesize)
879 execmd_write_oob(mtd);
880 else if (!flctl->seqin_column)
881 execmd_write_page_sector(mtd);
882 else
63fa37f0 883 pr_err("Invalid address !?\n");
35a34799
YS		 884 break;
885 }
886 set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN);
887 set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr);
888 writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
889 start_translation(flctl);
890 write_fiforeg(flctl, flctl->index, 0);
891 wait_completion(flctl);
892 break;
893
894 case NAND_CMD_STATUS:
895 set_cmd_regs(mtd, command, command);
896 set_addr(mtd, -1, -1);
897
898 flctl->read_bytes = 1;
899 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
900 start_translation(flctl);
901 read_datareg(flctl, 0); /* read and end */
902 break;
903
904 case NAND_CMD_RESET:
905 set_cmd_regs(mtd, command, command);
906 set_addr(mtd, -1, -1);
907
908 writel(0, FLDTCNTR(flctl)); /* set 0 size */
909 start_translation(flctl);
910 wait_completion(flctl);
911 break;
912
913 default:
914 break;
915 }
cfe78194 916 goto runtime_exit;
35a34799
YS		 917
918read_normal_exit:
919 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
abb59ef3 920 empty_fifo(flctl);
35a34799
YS		 921 start_translation(flctl);
922 read_fiforeg(flctl, flctl->read_bytes, 0);
923 wait_completion(flctl);
cfe78194
BH		 924runtime_exit:
925 pm_runtime_put_sync(&flctl->pdev->dev);
35a34799
YS		 926 return;
927}
928
758b56f5 929static void flctl_select_chip(struct nand_chip *chip, int chipnr)
35a34799 930{
758b56f5 931 struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
cfe78194 932 int ret;
35a34799
YS		 933
934 switch (chipnr) {
935 case -1:
0b3f0d12 936 flctl->flcmncr_base &= ~CE0_ENABLE;
cfe78194
BH		 937
938 pm_runtime_get_sync(&flctl->pdev->dev);
0b3f0d12 939 writel(flctl->flcmncr_base, FLCMNCR(flctl));
cfe78194
BH		 940
941 if (flctl->qos_request) {
942 dev_pm_qos_remove_request(&flctl->pm_qos);
943 flctl->qos_request = 0;
944 }
945
946 pm_runtime_put_sync(&flctl->pdev->dev);
35a34799
YS		 947 break;
948 case 0:
0b3f0d12 949 flctl->flcmncr_base |= CE0_ENABLE;
cfe78194
BH		 950
951 if (!flctl->qos_request) {
952 ret = dev_pm_qos_add_request(&flctl->pdev->dev,
ae0fb4b7 953 &flctl->pm_qos,
b02f6695 954 DEV_PM_QOS_RESUME_LATENCY,
ae0fb4b7 955 100);
cfe78194
BH		 956 if (ret < 0)
957 dev_err(&flctl->pdev->dev,
958 "PM QoS request failed: %d\n", ret);
959 flctl->qos_request = 1;
960 }
961
962 if (flctl->holden) {
963 pm_runtime_get_sync(&flctl->pdev->dev);
3f2e924b 964 writel(HOLDEN, FLHOLDCR(flctl));
cfe78194
BH		 965 pm_runtime_put_sync(&flctl->pdev->dev);
966 }
35a34799
YS		 967 break;
968 default:
969 BUG();
970 }
971}
972
c0739d85 973static void flctl_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
35a34799 974{
c0739d85 975 struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
35a34799 976
e8a9d8f3 977 memcpy(&flctl->done_buff[flctl->index], buf, len);
35a34799
YS		 978 flctl->index += len;
979}
980
7e534323 981static uint8_t flctl_read_byte(struct nand_chip *chip)
35a34799 982{
7e534323 983 struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
35a34799
YS		 984 uint8_t data;
985
e8a9d8f3 986 data = flctl->done_buff[flctl->index];
35a34799
YS		 987 flctl->index++;
988 return data;
989}
990
7e534323 991static void flctl_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
35a34799 992{
7e534323 993 struct sh_flctl *flctl = mtd_to_flctl(nand_to_mtd(chip));
35a34799 994
e8a9d8f3 995 memcpy(buf, &flctl->done_buff[flctl->index], len);
d76236f3 996 flctl->index += len;
35a34799
YS		 997}
998
5f20da0f 999static int flctl_chip_attach_chip(struct nand_chip *chip)
35a34799 1000{
5f20da0f 1001 struct mtd_info *mtd = nand_to_mtd(chip);
35a34799 1002 struct sh_flctl *flctl = mtd_to_flctl(mtd);
5f20da0f
MR		 1003
1004 /*
1005 * NAND_BUSWIDTH_16 may have been set by nand_scan_ident().
1006 * Add the SEL_16BIT flag in flctl->flcmncr_base.
1007 */
1008 if (chip->options & NAND_BUSWIDTH_16)
1009 flctl->flcmncr_base |= SEL_16BIT;
35a34799
YS		 1010
1011 if (mtd->writesize == 512) {
1012 flctl->page_size = 0;
1013 if (chip->chipsize > (32 << 20)) {
1014 /* big than 32MB */
1015 flctl->rw_ADRCNT = ADRCNT_4;
1016 flctl->erase_ADRCNT = ADRCNT_3;
1017 } else if (chip->chipsize > (2 << 16)) {
1018 /* big than 128KB */
1019 flctl->rw_ADRCNT = ADRCNT_3;
1020 flctl->erase_ADRCNT = ADRCNT_2;
1021 } else {
1022 flctl->rw_ADRCNT = ADRCNT_2;
1023 flctl->erase_ADRCNT = ADRCNT_1;
1024 }
1025 } else {
1026 flctl->page_size = 1;
1027 if (chip->chipsize > (128 << 20)) {
1028 /* big than 128MB */
1029 flctl->rw_ADRCNT = ADRCNT2_E;
1030 flctl->erase_ADRCNT = ADRCNT_3;
1031 } else if (chip->chipsize > (8 << 16)) {
1032 /* big than 512KB */
1033 flctl->rw_ADRCNT = ADRCNT_4;
1034 flctl->erase_ADRCNT = ADRCNT_2;
1035 } else {
1036 flctl->rw_ADRCNT = ADRCNT_3;
1037 flctl->erase_ADRCNT = ADRCNT_1;
1038 }
1039 }
1040
1041 if (flctl->hwecc) {
1042 if (mtd->writesize == 512) {
e7049f29 1043 mtd_set_ooblayout(mtd, &flctl_4secc_oob_smallpage_ops);
35a34799
YS		 1044 chip->badblock_pattern = &flctl_4secc_smallpage;
1045 } else {
e7049f29 1046 mtd_set_ooblayout(mtd, &flctl_4secc_oob_largepage_ops);
35a34799
YS		 1047 chip->badblock_pattern = &flctl_4secc_largepage;
1048 }
1049
1050 chip->ecc.size = 512;
1051 chip->ecc.bytes = 10;
6a918bad 1052 chip->ecc.strength = 4;
35a34799
YS		 1053 chip->ecc.read_page = flctl_read_page_hwecc;
1054 chip->ecc.write_page = flctl_write_page_hwecc;
1055 chip->ecc.mode = NAND_ECC_HW;
1056
1057 /* 4 symbols ECC enabled */
aa32d1f0 1058 flctl->flcmncr_base |= _4ECCEN;
35a34799
YS		 1059 } else {
1060 chip->ecc.mode = NAND_ECC_SOFT;
e020cc05 1061 chip->ecc.algo = NAND_ECC_HAMMING;
35a34799
YS		 1062 }
1063
1064 return 0;
1065}
1066
5f20da0f
MR		 1067static const struct nand_controller_ops flctl_nand_controller_ops = {
1068 .attach_chip = flctl_chip_attach_chip,
1069};
1070
3c7ea4ec
BH		 1071static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
1072{
1073 struct sh_flctl *flctl = dev_id;
1074
1075 dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl)));
1076 writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
1077
1078 return IRQ_HANDLED;
1079}
1080
7c8f680e
BH		 1081struct flctl_soc_config {
1082 unsigned long flcmncr_val;
1083 unsigned has_hwecc:1;
1084 unsigned use_holden:1;
1085};
1086
1087static struct flctl_soc_config flctl_sh7372_config = {
1088 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
1089 .has_hwecc = 1,
1090 .use_holden = 1,
1091};
1092
1093static const struct of_device_id of_flctl_match[] = {
1094 { .compatible = "renesas,shmobile-flctl-sh7372",
1095 .data = &flctl_sh7372_config },
1096 {},
1097};
1098MODULE_DEVICE_TABLE(of, of_flctl_match);
1099
1100static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
1101{
b8640c5b 1102 const struct flctl_soc_config *config;
7c8f680e 1103 struct sh_flctl_platform_data *pdata;
7c8f680e 1104
b8640c5b
GU		 1105 config = of_device_get_match_data(dev);
1106 if (!config) {
7c8f680e
BH		 1107 dev_err(dev, "%s: no OF configuration attached\n", __func__);
1108 return NULL;
1109 }
1110
1111 pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
1112 GFP_KERNEL);
b5d306c0 1113 if (!pdata)
7c8f680e 1114 return NULL;
7c8f680e
BH		 1115
1116 /* set SoC specific options */
1117 pdata->flcmncr_val = config->flcmncr_val;
1118 pdata->has_hwecc = config->has_hwecc;
1119 pdata->use_holden = config->use_holden;
1120
7c8f680e
BH		 1121 return pdata;
1122}
7c8f680e 1123
06f25510 1124static int flctl_probe(struct platform_device *pdev)
35a34799
YS		 1125{
1126 struct resource *res;
1127 struct sh_flctl *flctl;
1128 struct mtd_info *flctl_mtd;
1129 struct nand_chip *nand;
1130 struct sh_flctl_platform_data *pdata;
f7b5e849 1131 int ret;
3c7ea4ec 1132 int irq;
35a34799 1133
f7b5e849 1134 flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
b5d306c0 1135 if (!flctl)
35a34799 1136 return -ENOMEM;
35a34799
YS		 1137
1138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f7b5e849
LP		 1139 flctl->reg = devm_ioremap_resource(&pdev->dev, res);
1140 if (IS_ERR(flctl->reg))
1141 return PTR_ERR(flctl->reg);
1873315f 1142 flctl->fifo = res->start + 0x24; /* FLDTFIFO */
35a34799 1143
3c7ea4ec
BH		 1144 irq = platform_get_irq(pdev, 0);
1145 if (irq < 0) {
2192a8dd
GS		 1146 dev_err(&pdev->dev, "failed to get flste irq data: %d\n", irq);
1147 return irq;
3c7ea4ec
BH		 1148 }
1149
f7b5e849
LP		 1150 ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED,
1151 "flste", flctl);
3c7ea4ec
BH		 1152 if (ret) {
1153 dev_err(&pdev->dev, "request interrupt failed.\n");
f7b5e849 1154 return ret;
3c7ea4ec
BH		 1155 }
1156
7c8f680e
BH		 1157 if (pdev->dev.of_node)
1158 pdata = flctl_parse_dt(&pdev->dev);
1159 else
453810b7 1160 pdata = dev_get_platdata(&pdev->dev);
7c8f680e
BH		 1161
1162 if (!pdata) {
1163 dev_err(&pdev->dev, "no setup data defined\n");
f7b5e849 1164 return -EINVAL;
7c8f680e
BH		 1165 }
1166
35a34799 1167 platform_set_drvdata(pdev, flctl);
35a34799 1168 nand = &flctl->chip;
9c9eef89 1169 flctl_mtd = nand_to_mtd(nand);
a61ae81a 1170 nand_set_flash_node(nand, pdev->dev.of_node);
c4f7dc72 1171 flctl_mtd->dev.parent = &pdev->dev;
b79c7adf 1172 flctl->pdev = pdev;
35a34799 1173 flctl->hwecc = pdata->has_hwecc;
3f2e924b 1174 flctl->holden = pdata->use_holden;
3c7ea4ec
BH		 1175 flctl->flcmncr_base = pdata->flcmncr_val;
1176 flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
35a34799 1177
35a34799
YS		 1178 /* Set address of hardware control function */
1179 /* 20 us command delay time */
1180 nand->chip_delay = 20;
1181
1182 nand->read_byte = flctl_read_byte;
1183 nand->write_buf = flctl_write_buf;
1184 nand->read_buf = flctl_read_buf;
35a34799
YS		 1185 nand->select_chip = flctl_select_chip;
1186 nand->cmdfunc = flctl_cmdfunc;
b958758e
MR		 1187 nand->set_features = nand_get_set_features_notsupp;
1188 nand->get_features = nand_get_set_features_notsupp;
35a34799 1189
14667d8d 1190 if (pdata->flcmncr_val & SEL_16BIT)
010ab820 1191 nand->options |= NAND_BUSWIDTH_16;
010ab820 1192
cfe78194
BH		 1193 pm_runtime_enable(&pdev->dev);
1194 pm_runtime_resume(&pdev->dev);
1195
83738d87
BH		 1196 flctl_setup_dma(flctl);
1197
5f20da0f 1198 nand->dummy_controller.ops = &flctl_nand_controller_ops;
00ad378f 1199 ret = nand_scan(nand, 1);
35a34799 1200 if (ret)
cfe78194 1201 goto err_chip;
35a34799 1202
a61ae81a 1203 ret = mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
5a3e8cde
MR		 1204 if (ret)
1205 goto cleanup_nand;
35a34799
YS		 1206
1207 return 0;
1208
5a3e8cde
MR		 1209cleanup_nand:
1210 nand_cleanup(nand);
cfe78194 1211err_chip:
83738d87 1212 flctl_release_dma(flctl);
cfe78194 1213 pm_runtime_disable(&pdev->dev);
35a34799
YS		 1214 return ret;
1215}
1216
810b7e06 1217static int flctl_remove(struct platform_device *pdev)
35a34799
YS		 1218{
1219 struct sh_flctl *flctl = platform_get_drvdata(pdev);
1220
83738d87 1221 flctl_release_dma(flctl);
59ac276f 1222 nand_release(&flctl->chip);
cfe78194 1223 pm_runtime_disable(&pdev->dev);
35a34799
YS		 1224
1225 return 0;
1226}
1227
1228static struct platform_driver flctl_driver = {
35a34799
YS		 1229 .remove = flctl_remove,
1230 .driver = {
1231 .name = "sh_flctl",
bd247acb 1232 .of_match_table = of_match_ptr(of_flctl_match),
35a34799
YS		 1233 },
1234};
1235
14ec6dae 1236module_platform_driver_probe(flctl_driver, flctl_probe);
35a34799
YS		 1237
1238MODULE_LICENSE("GPL");
1239MODULE_AUTHOR("Yoshihiro Shimoda");
1240MODULE_DESCRIPTION("SuperH FLCTL driver");
1241MODULE_ALIAS("platform:sh_flctl");
Linux 6.x block layer and io_uring tree(s)