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[linux-2.6-block.git] / drivers / mtd / nand / raw / marvell_nand.c
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02f26ecf
MR		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Marvell NAND flash controller driver
4 *
5 * Copyright (C) 2017 Marvell
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
7 *
33c1c5fe
MR		 8 *
9 * This NAND controller driver handles two versions of the hardware,
10 * one is called NFCv1 and is available on PXA SoCs and the other is
11 * called NFCv2 and is available on Armada SoCs.
12 *
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
15 * is not used with NFCv2.
16 *
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
18 * is a brief description.
19 *
20 * When using Hamming, the data is split in 512B chunks (either 1, 2
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
22 * beginning of the OOB area and eventually the remaining free OOB
23 * bytes (also called "spare" bytes in the driver). This engine
24 * corrects up to 1 bit per chunk and detects reliably an error if
25 * there are at most 2 bitflips. Here is the page layout used by the
26 * controller when Hamming is chosen:
27 *
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
31 *
32 * When using the BCH engine, there are N identical (data + free OOB +
33 * ECC) sections and potentially an extra one to deal with
34 * configurations where the chosen (data + free OOB + ECC) sizes do
35 * not align with the page (data + OOB) size. ECC bytes are always
36 * 30B per ECC chunk. Here is the page layout used by the controller
37 * when BCH is chosen:
38 *
39 * +-----------------------------------------
40 * | Data 1 | Free OOB bytes 1 | ECC 1 | ...
41 * +-----------------------------------------
42 *
43 * -------------------------------------------
44 * ... | Data N | Free OOB bytes N | ECC N |
45 * -------------------------------------------
46 *
47 * --------------------------------------------+
48 * Last Data | Last Free OOB bytes | Last ECC |
49 * --------------------------------------------+
50 *
51 * In both cases, the layout seen by the user is always: all data
52 * first, then all free OOB bytes and finally all ECC bytes. With BCH,
53 * ECC bytes are 30B long and are padded with 0xFF to align on 32
54 * bytes.
55 *
56 * The controller has certain limitations that are handled by the
57 * driver:
58 * - It can only read 2k at a time. To overcome this limitation, the
59 * driver issues data cycles on the bus, without issuing new
60 * CMD + ADDR cycles. The Marvell term is "naked" operations.
61 * - The ECC strength in BCH mode cannot be tuned. It is fixed 16
62 * bits. What can be tuned is the ECC block size as long as it
63 * stays between 512B and 2kiB. It's usually chosen based on the
64 * chip ECC requirements. For instance, using 2kiB ECC chunks
65 * provides 4b/512B correctability.
66 * - The controller will always treat data bytes, free OOB bytes
67 * and ECC bytes in that order, no matter what the real layout is
68 * (which is usually all data then all OOB bytes). The
69 * marvell_nfc_layouts array below contains the currently
70 * supported layouts.
71 * - Because of these weird layouts, the Bad Block Markers can be
72 * located in data section. In this case, the NAND_BBT_NO_OOB_BBM
73 * option must be set to prevent scanning/writing bad block
74 * markers.
02f26ecf
MR		 75 */
76
77#include <linux/module.h>
78#include <linux/clk.h>
79#include <linux/mtd/rawnand.h>
c2fc6b69 80#include <linux/of.h>
02f26ecf
MR		 81#include <linux/iopoll.h>
82#include <linux/interrupt.h>
c2fc6b69 83#include <linux/platform_device.h>
02f26ecf
MR		 84#include <linux/slab.h>
85#include <linux/mfd/syscon.h>
86#include <linux/regmap.h>
87#include <asm/unaligned.h>
88
89#include <linux/dmaengine.h>
90#include <linux/dma-mapping.h>
91#include <linux/dma/pxa-dma.h>
92#include <linux/platform_data/mtd-nand-pxa3xx.h>
93
94/* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */
95#define FIFO_DEPTH 8
96#define FIFO_REP(x) (x / sizeof(u32))
97#define BCH_SEQ_READS (32 / FIFO_DEPTH)
98/* NFC does not support transfers of larger chunks at a time */
99#define MAX_CHUNK_SIZE 2112
100/* NFCv1 cannot read more that 7 bytes of ID */
101#define NFCV1_READID_LEN 7
102/* Polling is done at a pace of POLL_PERIOD us until POLL_TIMEOUT is reached */
103#define POLL_PERIOD 0
104#define POLL_TIMEOUT 100000
105/* Interrupt maximum wait period in ms */
106#define IRQ_TIMEOUT 1000
107/* Latency in clock cycles between SoC pins and NFC logic */
108#define MIN_RD_DEL_CNT 3
109/* Maximum number of contiguous address cycles */
110#define MAX_ADDRESS_CYC_NFCV1 5
111#define MAX_ADDRESS_CYC_NFCV2 7
112/* System control registers/bits to enable the NAND controller on some SoCs */
113#define GENCONF_SOC_DEVICE_MUX 0x208
114#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0)
115#define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20)
116#define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21)
117#define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25)
c13bf589 118#define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27)
02f26ecf
MR		 119#define GENCONF_CLK_GATING_CTRL 0x220
120#define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2)
121#define GENCONF_ND_CLK_CTRL 0x700
122#define GENCONF_ND_CLK_CTRL_EN BIT(0)
123
124/* NAND controller data flash control register */
125#define NDCR 0x00
126#define NDCR_ALL_INT GENMASK(11, 0)
127#define NDCR_CS1_CMDDM BIT(7)
128#define NDCR_CS0_CMDDM BIT(8)
129#define NDCR_RDYM BIT(11)
130#define NDCR_ND_ARB_EN BIT(12)
131#define NDCR_RA_START BIT(15)
132#define NDCR_RD_ID_CNT(x) (min_t(unsigned int, x, 0x7) << 16)
133#define NDCR_PAGE_SZ(x) (x >= 2048 ? BIT(24) : 0)
134#define NDCR_DWIDTH_M BIT(26)
135#define NDCR_DWIDTH_C BIT(27)
136#define NDCR_ND_RUN BIT(28)
137#define NDCR_DMA_EN BIT(29)
138#define NDCR_ECC_EN BIT(30)
139#define NDCR_SPARE_EN BIT(31)
140#define NDCR_GENERIC_FIELDS_MASK (~(NDCR_RA_START | NDCR_PAGE_SZ(2048) | \
141 NDCR_DWIDTH_M | NDCR_DWIDTH_C))
142
143/* NAND interface timing parameter 0 register */
144#define NDTR0 0x04
145#define NDTR0_TRP(x) ((min_t(unsigned int, x, 0xF) & 0x7) << 0)
146#define NDTR0_TRH(x) (min_t(unsigned int, x, 0x7) << 3)
147#define NDTR0_ETRP(x) ((min_t(unsigned int, x, 0xF) & 0x8) << 3)
148#define NDTR0_SEL_NRE_EDGE BIT(7)
149#define NDTR0_TWP(x) (min_t(unsigned int, x, 0x7) << 8)
150#define NDTR0_TWH(x) (min_t(unsigned int, x, 0x7) << 11)
151#define NDTR0_TCS(x) (min_t(unsigned int, x, 0x7) << 16)
152#define NDTR0_TCH(x) (min_t(unsigned int, x, 0x7) << 19)
153#define NDTR0_RD_CNT_DEL(x) (min_t(unsigned int, x, 0xF) << 22)
154#define NDTR0_SELCNTR BIT(26)
155#define NDTR0_TADL(x) (min_t(unsigned int, x, 0x1F) << 27)
156
157/* NAND interface timing parameter 1 register */
158#define NDTR1 0x0C
159#define NDTR1_TAR(x) (min_t(unsigned int, x, 0xF) << 0)
160#define NDTR1_TWHR(x) (min_t(unsigned int, x, 0xF) << 4)
161#define NDTR1_TRHW(x) (min_t(unsigned int, x / 16, 0x3) << 8)
162#define NDTR1_PRESCALE BIT(14)
163#define NDTR1_WAIT_MODE BIT(15)
164#define NDTR1_TR(x) (min_t(unsigned int, x, 0xFFFF) << 16)
165
166/* NAND controller status register */
167#define NDSR 0x14
168#define NDSR_WRCMDREQ BIT(0)
169#define NDSR_RDDREQ BIT(1)
170#define NDSR_WRDREQ BIT(2)
171#define NDSR_CORERR BIT(3)
172#define NDSR_UNCERR BIT(4)
173#define NDSR_CMDD(cs) BIT(8 - cs)
174#define NDSR_RDY(rb) BIT(11 + rb)
175#define NDSR_ERRCNT(x) ((x >> 16) & 0x1F)
176
177/* NAND ECC control register */
178#define NDECCCTRL 0x28
179#define NDECCCTRL_BCH_EN BIT(0)
180
181/* NAND controller data buffer register */
182#define NDDB 0x40
183
184/* NAND controller command buffer 0 register */
185#define NDCB0 0x48
186#define NDCB0_CMD1(x) ((x & 0xFF) << 0)
187#define NDCB0_CMD2(x) ((x & 0xFF) << 8)
188#define NDCB0_ADDR_CYC(x) ((x & 0x7) << 16)
189#define NDCB0_ADDR_GET_NUM_CYC(x) (((x) >> 16) & 0x7)
190#define NDCB0_DBC BIT(19)
191#define NDCB0_CMD_TYPE(x) ((x & 0x7) << 21)
192#define NDCB0_CSEL BIT(24)
193#define NDCB0_RDY_BYP BIT(27)
194#define NDCB0_LEN_OVRD BIT(28)
195#define NDCB0_CMD_XTYPE(x) ((x & 0x7) << 29)
196
197/* NAND controller command buffer 1 register */
198#define NDCB1 0x4C
199#define NDCB1_COLS(x) ((x & 0xFFFF) << 0)
200#define NDCB1_ADDRS_PAGE(x) (x << 16)
201
202/* NAND controller command buffer 2 register */
203#define NDCB2 0x50
204#define NDCB2_ADDR5_PAGE(x) (((x >> 16) & 0xFF) << 0)
205#define NDCB2_ADDR5_CYC(x) ((x & 0xFF) << 0)
206
207/* NAND controller command buffer 3 register */
208#define NDCB3 0x54
209#define NDCB3_ADDR6_CYC(x) ((x & 0xFF) << 16)
210#define NDCB3_ADDR7_CYC(x) ((x & 0xFF) << 24)
211
212/* NAND controller command buffer 0 register 'type' and 'xtype' fields */
213#define TYPE_READ 0
214#define TYPE_WRITE 1
215#define TYPE_ERASE 2
216#define TYPE_READ_ID 3
217#define TYPE_STATUS 4
218#define TYPE_RESET 5
219#define TYPE_NAKED_CMD 6
220#define TYPE_NAKED_ADDR 7
221#define TYPE_MASK 7
222#define XTYPE_MONOLITHIC_RW 0
223#define XTYPE_LAST_NAKED_RW 1
224#define XTYPE_FINAL_COMMAND 3
225#define XTYPE_READ 4
226#define XTYPE_WRITE_DISPATCH 4
227#define XTYPE_NAKED_RW 5
228#define XTYPE_COMMAND_DISPATCH 6
229#define XTYPE_MASK 7
230
231/**
c4bc1ec9
KK		 232 * struct marvell_hw_ecc_layout - layout of Marvell ECC
233 *
02f26ecf
MR		 234 * Marvell ECC engine works differently than the others, in order to limit the
235 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
236 * per subpage, and depending on a the desired strength needed by the NAND chip,
237 * a particular layout mixing data/spare/ecc is defined, with a possible last
238 * chunk smaller that the others.
239 *
240 * @writesize: Full page size on which the layout applies
241 * @chunk: Desired ECC chunk size on which the layout applies
242 * @strength: Desired ECC strength (per chunk size bytes) on which the
243 * layout applies
244 * @nchunks: Total number of chunks
245 * @full_chunk_cnt: Number of full-sized chunks, which is the number of
246 * repetitions of the pattern:
247 * (data_bytes + spare_bytes + ecc_bytes).
248 * @data_bytes: Number of data bytes per chunk
249 * @spare_bytes: Number of spare bytes per chunk
250 * @ecc_bytes: Number of ecc bytes per chunk
251 * @last_data_bytes: Number of data bytes in the last chunk
252 * @last_spare_bytes: Number of spare bytes in the last chunk
253 * @last_ecc_bytes: Number of ecc bytes in the last chunk
254 */
255struct marvell_hw_ecc_layout {
256 /* Constraints */
257 int writesize;
258 int chunk;
259 int strength;
260 /* Corresponding layout */
261 int nchunks;
262 int full_chunk_cnt;
263 int data_bytes;
264 int spare_bytes;
265 int ecc_bytes;
266 int last_data_bytes;
267 int last_spare_bytes;
268 int last_ecc_bytes;
269};
270
271#define MARVELL_LAYOUT(ws, dc, ds, nc, fcc, db, sb, eb, ldb, lsb, leb) \
272 { \
273 .writesize = ws, \
274 .chunk = dc, \
275 .strength = ds, \
276 .nchunks = nc, \
277 .full_chunk_cnt = fcc, \
278 .data_bytes = db, \
279 .spare_bytes = sb, \
280 .ecc_bytes = eb, \
281 .last_data_bytes = ldb, \
282 .last_spare_bytes = lsb, \
283 .last_ecc_bytes = leb, \
284 }
285
286/* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
287static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
288 MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0),
289 MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0),
290 MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0),
7fd130f7 291 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30),
68c18dae
AD		 292 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,64, 30),
293 MARVELL_LAYOUT( 2048, 512, 12, 3, 2, 704, 0, 30,640, 0, 30),
294 MARVELL_LAYOUT( 2048, 512, 16, 5, 4, 512, 0, 30, 0, 32, 30),
02f26ecf
MR		 295 MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0),
296 MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30),
68c18dae
AD		 297 MARVELL_LAYOUT( 4096, 512, 12, 6, 5, 704, 0, 30,576, 32, 30),
298 MARVELL_LAYOUT( 4096, 512, 16, 9, 8, 512, 0, 30, 0, 32, 30),
e8237bfa
KP		 299 MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0),
300 MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30),
68c18dae
AD		 301 MARVELL_LAYOUT( 8192, 512, 12, 12, 11, 704, 0, 30,448, 64, 30),
302 MARVELL_LAYOUT( 8192, 512, 16, 17, 16, 512, 0, 30, 0, 32, 30),
02f26ecf
MR		 303};
304
305/**
c4bc1ec9
KK		 306 * struct marvell_nand_chip_sel - CS line description
307 *
02f26ecf
MR		 308 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
309 * is made by a field in NDCB0 register, and in another field in NDCB2 register.
310 * The datasheet describes the logic with an error: ADDR5 field is once
311 * declared at the beginning of NDCB2, and another time at its end. Because the
312 * ADDR5 field of NDCB2 may be used by other bytes, it would be more logical
313 * to use the last bit of this field instead of the first ones.
314 *
315 * @cs: Wanted CE lane.
316 * @ndcb0_csel: Value of the NDCB0 register with or without the flag
317 * selecting the wanted CE lane. This is set once when
318 * the Device Tree is probed.
319 * @rb: Ready/Busy pin for the flash chip
320 */
321struct marvell_nand_chip_sel {
322 unsigned int cs;
323 u32 ndcb0_csel;
324 unsigned int rb;
325};
326
327/**
c4bc1ec9 328 * struct marvell_nand_chip - stores NAND chip device related information
02f26ecf
MR		 329 *
330 * @chip: Base NAND chip structure
331 * @node: Used to store NAND chips into a list
c4bc1ec9 332 * @layout: NAND layout when using hardware ECC
02f26ecf
MR		 333 * @ndcr: Controller register value for this NAND chip
334 * @ndtr0: Timing registers 0 value for this NAND chip
335 * @ndtr1: Timing registers 1 value for this NAND chip
c4bc1ec9 336 * @addr_cyc: Amount of cycles needed to pass column address
02f26ecf
MR		 337 * @selected_die: Current active CS
338 * @nsels: Number of CS lines required by the NAND chip
339 * @sels: Array of CS lines descriptions
340 */
341struct marvell_nand_chip {
342 struct nand_chip chip;
343 struct list_head node;
344 const struct marvell_hw_ecc_layout *layout;
345 u32 ndcr;
346 u32 ndtr0;
347 u32 ndtr1;
348 int addr_cyc;
349 int selected_die;
350 unsigned int nsels;
49f1c330 351 struct marvell_nand_chip_sel sels[];
02f26ecf
MR		 352};
353
354static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
355{
356 return container_of(chip, struct marvell_nand_chip, chip);
357}
358
359static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip
360 *nand)
361{
362 return &nand->sels[nand->selected_die];
363}
364
365/**
c4bc1ec9
KK		 366 * struct marvell_nfc_caps - NAND controller capabilities for distinction
367 * between compatible strings
02f26ecf
MR		 368 *
369 * @max_cs_nb: Number of Chip Select lines available
370 * @max_rb_nb: Number of Ready/Busy lines available
371 * @need_system_controller: Indicates if the SoC needs to have access to the
372 * system controller (ie. to enable the NAND controller)
373 * @legacy_of_bindings: Indicates if DT parsing must be done using the old
374 * fashion way
375 * @is_nfcv2: NFCv2 has numerous enhancements compared to NFCv1, ie.
376 * BCH error detection and correction algorithm,
377 * NDCB3 register has been added
378 * @use_dma: Use dma for data transfers
72b9a3fc 379 * @max_mode_number: Maximum timing mode supported by the controller
02f26ecf
MR		 380 */
381struct marvell_nfc_caps {
382 unsigned int max_cs_nb;
383 unsigned int max_rb_nb;
384 bool need_system_controller;
385 bool legacy_of_bindings;
386 bool is_nfcv2;
387 bool use_dma;
72b9a3fc 388 unsigned int max_mode_number;
02f26ecf
MR		 389};
390
391/**
c4bc1ec9 392 * struct marvell_nfc - stores Marvell NAND controller information
02f26ecf
MR		 393 *
394 * @controller: Base controller structure
395 * @dev: Parent device (used to print error messages)
396 * @regs: NAND controller registers
6b6de654 397 * @core_clk: Core clock
1b489eff 398 * @reg_clk: Registers clock
02f26ecf
MR		 399 * @complete: Completion object to wait for NAND controller events
400 * @assigned_cs: Bitmask describing already assigned CS lines
401 * @chips: List containing all the NAND chips attached to
402 * this NAND controller
c4bc1ec9 403 * @selected_chip: Currently selected target chip
02f26ecf 404 * @caps: NAND controller capabilities for each compatible string
c4bc1ec9 405 * @use_dma: Whetner DMA is used
02f26ecf
MR		 406 * @dma_chan: DMA channel (NFCv1 only)
407 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only)
408 */
409struct marvell_nfc {
7da45139 410 struct nand_controller controller;
02f26ecf
MR		 411 struct device *dev;
412 void __iomem *regs;
6b6de654 413 struct clk *core_clk;
961ba15c 414 struct clk *reg_clk;
02f26ecf
MR		 415 struct completion complete;
416 unsigned long assigned_cs;
417 struct list_head chips;
418 struct nand_chip *selected_chip;
419 const struct marvell_nfc_caps *caps;
420
421 /* DMA (NFCv1 only) */
422 bool use_dma;
423 struct dma_chan *dma_chan;
424 u8 *dma_buf;
425};
426
7da45139 427static inline struct marvell_nfc *to_marvell_nfc(struct nand_controller *ctrl)
02f26ecf
MR		 428{
429 return container_of(ctrl, struct marvell_nfc, controller);
430}
431
432/**
c4bc1ec9
KK		 433 * struct marvell_nfc_timings - NAND controller timings expressed in NAND
434 * Controller clock cycles
02f26ecf
MR		 435 *
436 * @tRP: ND_nRE pulse width
437 * @tRH: ND_nRE high duration
438 * @tWP: ND_nWE pulse time
439 * @tWH: ND_nWE high duration
440 * @tCS: Enable signal setup time
441 * @tCH: Enable signal hold time
442 * @tADL: Address to write data delay
443 * @tAR: ND_ALE low to ND_nRE low delay
444 * @tWHR: ND_nWE high to ND_nRE low for status read
445 * @tRHW: ND_nRE high duration, read to write delay
446 * @tR: ND_nWE high to ND_nRE low for read
447 */
448struct marvell_nfc_timings {
449 /* NDTR0 fields */
450 unsigned int tRP;
451 unsigned int tRH;
452 unsigned int tWP;
453 unsigned int tWH;
454 unsigned int tCS;
455 unsigned int tCH;
456 unsigned int tADL;
457 /* NDTR1 fields */
458 unsigned int tAR;
459 unsigned int tWHR;
460 unsigned int tRHW;
461 unsigned int tR;
462};
463
464/**
f856c4e9 465 * TO_CYCLES() - Derives a duration in numbers of clock cycles.
02f26ecf
MR		 466 *
467 * @ps: Duration in pico-seconds
468 * @period_ns: Clock period in nano-seconds
469 *
470 * Convert the duration in nano-seconds, then divide by the period and
471 * return the number of clock periods.
472 */
473#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP(ps / 1000, period_ns))
07ad5a72
MR		 474#define TO_CYCLES64(ps, period_ns) (DIV_ROUND_UP_ULL(div_u64(ps, 1000), \
475 period_ns))
02f26ecf
MR		 476
477/**
c4bc1ec9
KK		 478 * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
479 * subop subset of instructions.
02f26ecf
MR		 480 *
481 * @ndcb: Array of values written to NDCBx registers
482 * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle
483 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin
484 * @rdy_delay_ns: Optional delay after waiting for the RB pin
485 * @data_delay_ns: Optional delay after the data xfer
486 * @data_instr_idx: Index of the data instruction in the subop
487 * @data_instr: Pointer to the data instruction in the subop
488 */
489struct marvell_nfc_op {
490 u32 ndcb[4];
491 unsigned int cle_ale_delay_ns;
492 unsigned int rdy_timeout_ms;
493 unsigned int rdy_delay_ns;
494 unsigned int data_delay_ns;
495 unsigned int data_instr_idx;
496 const struct nand_op_instr *data_instr;
497};
498
499/*
500 * Internal helper to conditionnally apply a delay (from the above structure,
501 * most of the time).
502 */
503static void cond_delay(unsigned int ns)
504{
505 if (!ns)
506 return;
507
508 if (ns < 10000)
509 ndelay(ns);
510 else
511 udelay(DIV_ROUND_UP(ns, 1000));
512}
513
514/*
515 * The controller has many flags that could generate interrupts, most of them
516 * are disabled and polling is used. For the very slow signals, using interrupts
517 * may relax the CPU charge.
518 */
519static void marvell_nfc_disable_int(struct marvell_nfc *nfc, u32 int_mask)
520{
521 u32 reg;
522
523 /* Writing 1 disables the interrupt */
524 reg = readl_relaxed(nfc->regs + NDCR);
525 writel_relaxed(reg | int_mask, nfc->regs + NDCR);
526}
527
528static void marvell_nfc_enable_int(struct marvell_nfc *nfc, u32 int_mask)
529{
530 u32 reg;
531
532 /* Writing 0 enables the interrupt */
533 reg = readl_relaxed(nfc->regs + NDCR);
534 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
535}
536
cafb56dd 537static u32 marvell_nfc_clear_int(struct marvell_nfc *nfc, u32 int_mask)
02f26ecf 538{
cafb56dd
MR		 539 u32 reg;
540
541 reg = readl_relaxed(nfc->regs + NDSR);
02f26ecf 542 writel_relaxed(int_mask, nfc->regs + NDSR);
cafb56dd
MR		 543
544 return reg & int_mask;
02f26ecf
MR		 545}
546
547static void marvell_nfc_force_byte_access(struct nand_chip *chip,
548 bool force_8bit)
549{
550 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
551 u32 ndcr;
552
553 /*
554 * Callers of this function do not verify if the NAND is using a 16-bit
555 * an 8-bit bus for normal operations, so we need to take care of that
556 * here by leaving the configuration unchanged if the NAND does not have
557 * the NAND_BUSWIDTH_16 flag set.
558 */
559 if (!(chip->options & NAND_BUSWIDTH_16))
560 return;
561
562 ndcr = readl_relaxed(nfc->regs + NDCR);
563
564 if (force_8bit)
565 ndcr &= ~(NDCR_DWIDTH_M | NDCR_DWIDTH_C);
566 else
567 ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
568
569 writel_relaxed(ndcr, nfc->regs + NDCR);
570}
571
572static int marvell_nfc_wait_ndrun(struct nand_chip *chip)
573{
574 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
575 u32 val;
576 int ret;
577
578 /*
579 * The command is being processed, wait for the ND_RUN bit to be
580 * cleared by the NFC. If not, we must clear it by hand.
581 */
582 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
583 (val & NDCR_ND_RUN) == 0,
584 POLL_PERIOD, POLL_TIMEOUT);
585 if (ret) {
586 dev_err(nfc->dev, "Timeout on NAND controller run mode\n");
587 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
588 nfc->regs + NDCR);
589 return ret;
590 }
591
592 return 0;
593}
594
595/*
596 * Any time a command has to be sent to the controller, the following sequence
597 * has to be followed:
598 * - call marvell_nfc_prepare_cmd()
599 * -> activate the ND_RUN bit that will kind of 'start a job'
600 * -> wait the signal indicating the NFC is waiting for a command
601 * - send the command (cmd and address cycles)
602 * - enventually send or receive the data
603 * - call marvell_nfc_end_cmd() with the corresponding flag
604 * -> wait the flag to be triggered or cancel the job with a timeout
605 *
606 * The following helpers are here to factorize the code a bit so that
607 * specialized functions responsible for executing the actual NAND
608 * operations do not have to replicate the same code blocks.
609 */
610static int marvell_nfc_prepare_cmd(struct nand_chip *chip)
611{
612 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
613 u32 ndcr, val;
614 int ret;
615
616 /* Poll ND_RUN and clear NDSR before issuing any command */
617 ret = marvell_nfc_wait_ndrun(chip);
618 if (ret) {
a76497dc 619 dev_err(nfc->dev, "Last operation did not succeed\n");
02f26ecf
MR		 620 return ret;
621 }
622
623 ndcr = readl_relaxed(nfc->regs + NDCR);
624 writel_relaxed(readl(nfc->regs + NDSR), nfc->regs + NDSR);
625
626 /* Assert ND_RUN bit and wait the NFC to be ready */
627 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
628 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
629 val & NDSR_WRCMDREQ,
630 POLL_PERIOD, POLL_TIMEOUT);
631 if (ret) {
632 dev_err(nfc->dev, "Timeout on WRCMDRE\n");
633 return -ETIMEDOUT;
634 }
635
636 /* Command may be written, clear WRCMDREQ status bit */
637 writel_relaxed(NDSR_WRCMDREQ, nfc->regs + NDSR);
638
639 return 0;
640}
641
642static void marvell_nfc_send_cmd(struct nand_chip *chip,
643 struct marvell_nfc_op *nfc_op)
644{
645 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
646 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
647
648 dev_dbg(nfc->dev, "\nNDCR: 0x%08x\n"
649 "NDCB0: 0x%08x\nNDCB1: 0x%08x\nNDCB2: 0x%08x\nNDCB3: 0x%08x\n",
650 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
651 nfc_op->ndcb[1], nfc_op->ndcb[2], nfc_op->ndcb[3]);
652
653 writel_relaxed(to_nand_sel(marvell_nand)->ndcb0_csel | nfc_op->ndcb[0],
654 nfc->regs + NDCB0);
655 writel_relaxed(nfc_op->ndcb[1], nfc->regs + NDCB0);
656 writel(nfc_op->ndcb[2], nfc->regs + NDCB0);
657
658 /*
659 * Write NDCB0 four times only if LEN_OVRD is set or if ADDR6 or ADDR7
660 * fields are used (only available on NFCv2).
661 */
662 if (nfc_op->ndcb[0] & NDCB0_LEN_OVRD ||
663 NDCB0_ADDR_GET_NUM_CYC(nfc_op->ndcb[0]) >= 6) {
664 if (!WARN_ON_ONCE(!nfc->caps->is_nfcv2))
665 writel(nfc_op->ndcb[3], nfc->regs + NDCB0);
666 }
667}
668
669static int marvell_nfc_end_cmd(struct nand_chip *chip, int flag,
670 const char *label)
671{
672 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
673 u32 val;
674 int ret;
675
676 ret = readl_relaxed_poll_timeout(nfc->regs + NDSR, val,
677 val & flag,
678 POLL_PERIOD, POLL_TIMEOUT);
679
680 if (ret) {
681 dev_err(nfc->dev, "Timeout on %s (NDSR: 0x%08x)\n",
682 label, val);
683 if (nfc->dma_chan)
684 dmaengine_terminate_all(nfc->dma_chan);
685 return ret;
686 }
687
688 /*
689 * DMA function uses this helper to poll on CMDD bits without wanting
690 * them to be cleared.
691 */
692 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
693 return 0;
694
695 writel_relaxed(flag, nfc->regs + NDSR);
696
697 return 0;
698}
699
700static int marvell_nfc_wait_cmdd(struct nand_chip *chip)
701{
702 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
703 int cs_flag = NDSR_CMDD(to_nand_sel(marvell_nand)->ndcb0_csel);
704
705 return marvell_nfc_end_cmd(chip, cs_flag, "CMDD");
706}
707
85a3ebbb
CP		 708static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask,
709 u32 expected_val, unsigned long timeout_ms)
710{
711 unsigned long limit;
712 u32 st;
713
714 limit = jiffies + msecs_to_jiffies(timeout_ms);
715 do {
716 st = readl_relaxed(nfc->regs + NDSR);
717 if (st & NDSR_RDY(1))
718 st |= NDSR_RDY(0);
719
720 if ((st & mask) == expected_val)
721 return 0;
722
723 cpu_relax();
724 } while (time_after(limit, jiffies));
725
726 return -ETIMEDOUT;
727}
728
02f26ecf
MR		 729static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms)
730{
731 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
85a3ebbb 732 struct mtd_info *mtd = nand_to_mtd(chip);
cafb56dd 733 u32 pending;
02f26ecf
MR		 734 int ret;
735
736 /* Timeout is expressed in ms */
737 if (!timeout_ms)
738 timeout_ms = IRQ_TIMEOUT;
739
85a3ebbb
CP		 740 if (mtd->oops_panic_write) {
741 ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0),
742 NDSR_RDY(0),
743 timeout_ms);
744 } else {
745 init_completion(&nfc->complete);
746
747 marvell_nfc_enable_int(nfc, NDCR_RDYM);
748 ret = wait_for_completion_timeout(&nfc->complete,
749 msecs_to_jiffies(timeout_ms));
750 marvell_nfc_disable_int(nfc, NDCR_RDYM);
751 }
cafb56dd
MR		 752 pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1));
753
754 /*
755 * In case the interrupt was not served in the required time frame,
756 * check if the ISR was not served or if something went actually wrong.
757 */
c2707577 758 if (!ret && !pending) {
02f26ecf
MR		 759 dev_err(nfc->dev, "Timeout waiting for RB signal\n");
760 return -ETIMEDOUT;
761 }
762
763 return 0;
764}
765
b2525141
BB		 766static void marvell_nfc_select_target(struct nand_chip *chip,
767 unsigned int die_nr)
02f26ecf 768{
02f26ecf
MR		 769 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
770 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
771 u32 ndcr_generic;
772
02f26ecf
MR		 773 /*
774 * Reset the NDCR register to a clean state for this particular chip,
775 * also clear ND_RUN bit.
776 */
777 ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
778 NDCR_GENERIC_FIELDS_MASK & ~NDCR_ND_RUN;
779 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
780
781 /* Also reset the interrupt status register */
782 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
783
9a8f612c
MR		 784 if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
785 return;
786
787 writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
788 writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
789
02f26ecf
MR		 790 nfc->selected_chip = chip;
791 marvell_nand->selected_die = die_nr;
792}
793
794static irqreturn_t marvell_nfc_isr(int irq, void *dev_id)
795{
796 struct marvell_nfc *nfc = dev_id;
797 u32 st = readl_relaxed(nfc->regs + NDSR);
798 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
799
800 /*
801 * RDY interrupt mask is one bit in NDCR while there are two status
802 * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]).
803 */
804 if (st & NDSR_RDY(1))
805 st |= NDSR_RDY(0);
806
807 if (!(st & ien))
808 return IRQ_NONE;
809
810 marvell_nfc_disable_int(nfc, st & NDCR_ALL_INT);
811
53c83b59 812 if (st & (NDSR_RDY(0) | NDSR_RDY(1)))
02f26ecf
MR		 813 complete(&nfc->complete);
814
815 return IRQ_HANDLED;
816}
817
818/* HW ECC related functions */
819static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
820{
821 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
822 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
823
824 if (!(ndcr & NDCR_ECC_EN)) {
825 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
826
827 /*
828 * When enabling BCH, set threshold to 0 to always know the
829 * number of corrected bitflips.
830 */
e0a564ae 831 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
02f26ecf
MR		 832 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
833 }
834}
835
836static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
837{
838 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
839 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
840
841 if (ndcr & NDCR_ECC_EN) {
842 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
e0a564ae 843 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
02f26ecf
MR		 844 writel_relaxed(0, nfc->regs + NDECCCTRL);
845 }
846}
847
848/* DMA related helpers */
849static void marvell_nfc_enable_dma(struct marvell_nfc *nfc)
850{
851 u32 reg;
852
853 reg = readl_relaxed(nfc->regs + NDCR);
854 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
855}
856
857static void marvell_nfc_disable_dma(struct marvell_nfc *nfc)
858{
859 u32 reg;
860
861 reg = readl_relaxed(nfc->regs + NDCR);
862 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
863}
864
865/* Read/write PIO/DMA accessors */
866static int marvell_nfc_xfer_data_dma(struct marvell_nfc *nfc,
867 enum dma_data_direction direction,
868 unsigned int len)
869{
870 unsigned int dma_len = min_t(int, ALIGN(len, 32), MAX_CHUNK_SIZE);
871 struct dma_async_tx_descriptor *tx;
872 struct scatterlist sg;
873 dma_cookie_t cookie;
874 int ret;
875
876 marvell_nfc_enable_dma(nfc);
877 /* Prepare the DMA transfer */
878 sg_init_one(&sg, nfc->dma_buf, dma_len);
40c9ba0d
JW		 879 ret = dma_map_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
880 if (!ret) {
881 dev_err(nfc->dev, "Could not map DMA S/G list\n");
882 return -ENXIO;
883 }
884
02f26ecf
MR		 885 tx = dmaengine_prep_slave_sg(nfc->dma_chan, &sg, 1,
886 direction == DMA_FROM_DEVICE ?
887 DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
888 DMA_PREP_INTERRUPT);
889 if (!tx) {
890 dev_err(nfc->dev, "Could not prepare DMA S/G list\n");
40c9ba0d 891 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
02f26ecf
MR		 892 return -ENXIO;
893 }
894
895 /* Do the task and wait for it to finish */
896 cookie = dmaengine_submit(tx);
897 ret = dma_submit_error(cookie);
898 if (ret)
899 return -EIO;
900
901 dma_async_issue_pending(nfc->dma_chan);
902 ret = marvell_nfc_wait_cmdd(nfc->selected_chip);
903 dma_unmap_sg(nfc->dma_chan->device->dev, &sg, 1, direction);
904 marvell_nfc_disable_dma(nfc);
905 if (ret) {
906 dev_err(nfc->dev, "Timeout waiting for DMA (status: %d)\n",
907 dmaengine_tx_status(nfc->dma_chan, cookie, NULL));
908 dmaengine_terminate_all(nfc->dma_chan);
909 return -ETIMEDOUT;
910 }
911
912 return 0;
913}
914
915static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in,
916 unsigned int len)
917{
918 unsigned int last_len = len % FIFO_DEPTH;
919 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
920 int i;
921
922 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
923 ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH));
924
925 if (last_len) {
926 u8 tmp_buf[FIFO_DEPTH];
927
928 ioread32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
929 memcpy(in + last_full_offset, tmp_buf, last_len);
930 }
931
932 return 0;
933}
934
935static int marvell_nfc_xfer_data_out_pio(struct marvell_nfc *nfc, const u8 *out,
936 unsigned int len)
937{
938 unsigned int last_len = len % FIFO_DEPTH;
939 unsigned int last_full_offset = round_down(len, FIFO_DEPTH);
940 int i;
941
942 for (i = 0; i < last_full_offset; i += FIFO_DEPTH)
943 iowrite32_rep(nfc->regs + NDDB, out + i, FIFO_REP(FIFO_DEPTH));
944
945 if (last_len) {
946 u8 tmp_buf[FIFO_DEPTH];
947
948 memcpy(tmp_buf, out + last_full_offset, last_len);
949 iowrite32_rep(nfc->regs + NDDB, tmp_buf, FIFO_REP(FIFO_DEPTH));
950 }
951
952 return 0;
953}
954
955static void marvell_nfc_check_empty_chunk(struct nand_chip *chip,
956 u8 *data, int data_len,
957 u8 *spare, int spare_len,
958 u8 *ecc, int ecc_len,
959 unsigned int *max_bitflips)
960{
961 struct mtd_info *mtd = nand_to_mtd(chip);
962 int bf;
963
964 /*
965 * Blank pages (all 0xFF) that have not been written may be recognized
966 * as bad if bitflips occur, so whenever an uncorrectable error occurs,
967 * check if the entire page (with ECC bytes) is actually blank or not.
968 */
969 if (!data)
970 data_len = 0;
971 if (!spare)
972 spare_len = 0;
973 if (!ecc)
974 ecc_len = 0;
975
976 bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
977 spare, spare_len, chip->ecc.strength);
978 if (bf < 0) {
979 mtd->ecc_stats.failed++;
980 return;
981 }
982
983 /* Update the stats and max_bitflips */
984 mtd->ecc_stats.corrected += bf;
985 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
986}
987
988/*
1617942a 989 * Check if a chunk is correct or not according to the hardware ECC engine.
02f26ecf
MR		 990 * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
991 * mtd->ecc_stats.failure is not, the function will instead return a non-zero
992 * value indicating that a check on the emptyness of the subpage must be
1617942a 993 * performed before actually declaring the subpage as "corrupted".
02f26ecf 994 */
1617942a
MR		 995static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip,
996 unsigned int *max_bitflips)
02f26ecf
MR		 997{
998 struct mtd_info *mtd = nand_to_mtd(chip);
999 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1000 int bf = 0;
1001 u32 ndsr;
1002
1003 ndsr = readl_relaxed(nfc->regs + NDSR);
1004
1005 /* Check uncorrectable error flag */
1006 if (ndsr & NDSR_UNCERR) {
1007 writel_relaxed(ndsr, nfc->regs + NDSR);
1008
1009 /*
1010 * Do not increment ->ecc_stats.failed now, instead, return a
1011 * non-zero value to indicate that this chunk was apparently
1012 * bad, and it should be check to see if it empty or not. If
1013 * the chunk (with ECC bytes) is not declared empty, the calling
1014 * function must increment the failure count.
1015 */
1016 return -EBADMSG;
1017 }
1018
1019 /* Check correctable error flag */
1020 if (ndsr & NDSR_CORERR) {
1021 writel_relaxed(ndsr, nfc->regs + NDSR);
1022
e0a564ae 1023 if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
02f26ecf
MR		 1024 bf = NDSR_ERRCNT(ndsr);
1025 else
1026 bf = 1;
1027 }
1028
1029 /* Update the stats and max_bitflips */
1030 mtd->ecc_stats.corrected += bf;
1031 *max_bitflips = max_t(unsigned int, *max_bitflips, bf);
1032
1033 return 0;
1034}
1035
1036/* Hamming read helpers */
1037static int marvell_nfc_hw_ecc_hmg_do_read_page(struct nand_chip *chip,
1038 u8 *data_buf, u8 *oob_buf,
1039 bool raw, int page)
1040{
1041 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1042 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1043 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1044 struct marvell_nfc_op nfc_op = {
1045 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
1046 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1047 NDCB0_DBC |
1048 NDCB0_CMD1(NAND_CMD_READ0) |
1049 NDCB0_CMD2(NAND_CMD_READSTART),
1050 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1051 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1052 };
1053 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
1054 int ret;
1055
1056 /* NFCv2 needs more information about the operation being executed */
1057 if (nfc->caps->is_nfcv2)
1058 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1059
1060 ret = marvell_nfc_prepare_cmd(chip);
1061 if (ret)
1062 return ret;
1063
1064 marvell_nfc_send_cmd(chip, &nfc_op);
1065 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1066 "RDDREQ while draining FIFO (data/oob)");
1067 if (ret)
1068 return ret;
1069
1070 /*
1071 * Read the page then the OOB area. Unlike what is shown in current
1072 * documentation, spare bytes are protected by the ECC engine, and must
1073 * be at the beginning of the OOB area or running this driver on legacy
1074 * systems will prevent the discovery of the BBM/BBT.
1075 */
1076 if (nfc->use_dma) {
1077 marvell_nfc_xfer_data_dma(nfc, DMA_FROM_DEVICE,
1078 lt->data_bytes + oob_bytes);
1079 memcpy(data_buf, nfc->dma_buf, lt->data_bytes);
1080 memcpy(oob_buf, nfc->dma_buf + lt->data_bytes, oob_bytes);
1081 } else {
1082 marvell_nfc_xfer_data_in_pio(nfc, data_buf, lt->data_bytes);
1083 marvell_nfc_xfer_data_in_pio(nfc, oob_buf, oob_bytes);
1084 }
1085
1086 ret = marvell_nfc_wait_cmdd(chip);
02f26ecf
MR		 1087 return ret;
1088}
1089
b9761687 1090static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf,
02f26ecf
MR		 1091 int oob_required, int page)
1092{
b2525141 1093 marvell_nfc_select_target(chip, chip->cur_cs);
02f26ecf
MR		 1094 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
1095 true, page);
1096}
1097
b9761687
BB		 1098static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf,
1099 int oob_required, int page)
02f26ecf
MR		 1100{
1101 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1102 unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1103 int max_bitflips = 0, ret;
1104 u8 *raw_buf;
1105
b2525141 1106 marvell_nfc_select_target(chip, chip->cur_cs);
02f26ecf
MR		 1107 marvell_nfc_enable_hw_ecc(chip);
1108 marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
1109 page);
1617942a 1110 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
02f26ecf
MR		 1111 marvell_nfc_disable_hw_ecc(chip);
1112
1113 if (!ret)
1114 return max_bitflips;
1115
1116 /*
1117 * When ECC failures are detected, check if the full page has been
1118 * written or not. Ignore the failure if it is actually empty.
1119 */
1120 raw_buf = kmalloc(full_sz, GFP_KERNEL);
1121 if (!raw_buf)
1122 return -ENOMEM;
1123
1124 marvell_nfc_hw_ecc_hmg_do_read_page(chip, raw_buf, raw_buf +
1125 lt->data_bytes, true, page);
1126 marvell_nfc_check_empty_chunk(chip, raw_buf, full_sz, NULL, 0, NULL, 0,
1127 &max_bitflips);
1128 kfree(raw_buf);
1129
1130 return max_bitflips;
1131}
1132
1133/*
1134 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1135 * it appears before the ECC bytes when reading), the ->read_oob_raw() function
1136 * also stands for ->read_oob().
1137 */
b9761687 1138static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page)
02f26ecf 1139{
eeab7174 1140 u8 *buf = nand_get_data_buf(chip);
02f26ecf 1141
b2525141 1142 marvell_nfc_select_target(chip, chip->cur_cs);
eeab7174
BB		 1143 return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
1144 true, page);
02f26ecf
MR		 1145}
1146
1147/* Hamming write helpers */
1148static int marvell_nfc_hw_ecc_hmg_do_write_page(struct nand_chip *chip,
1149 const u8 *data_buf,
1150 const u8 *oob_buf, bool raw,
1151 int page)
1152{
e0160cd4
MR		 1153 const struct nand_sdr_timings *sdr =
1154 nand_get_sdr_timings(nand_get_interface_config(chip));
02f26ecf
MR		 1155 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1156 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1157 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1158 struct marvell_nfc_op nfc_op = {
1159 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) |
1160 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1161 NDCB0_CMD1(NAND_CMD_SEQIN) |
1162 NDCB0_CMD2(NAND_CMD_PAGEPROG) |
1163 NDCB0_DBC,
1164 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1165 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1166 };
1167 unsigned int oob_bytes = lt->spare_bytes + (raw ? lt->ecc_bytes : 0);
1168 int ret;
1169
1170 /* NFCv2 needs more information about the operation being executed */
1171 if (nfc->caps->is_nfcv2)
1172 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
1173
1174 ret = marvell_nfc_prepare_cmd(chip);
1175 if (ret)
1176 return ret;
1177
1178 marvell_nfc_send_cmd(chip, &nfc_op);
1179 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1180 "WRDREQ while loading FIFO (data)");
1181 if (ret)
1182 return ret;
1183
1184 /* Write the page then the OOB area */
1185 if (nfc->use_dma) {
1186 memcpy(nfc->dma_buf, data_buf, lt->data_bytes);
1187 memcpy(nfc->dma_buf + lt->data_bytes, oob_buf, oob_bytes);
1188 marvell_nfc_xfer_data_dma(nfc, DMA_TO_DEVICE, lt->data_bytes +
1189 lt->ecc_bytes + lt->spare_bytes);
1190 } else {
1191 marvell_nfc_xfer_data_out_pio(nfc, data_buf, lt->data_bytes);
1192 marvell_nfc_xfer_data_out_pio(nfc, oob_buf, oob_bytes);
1193 }
1194
1195 ret = marvell_nfc_wait_cmdd(chip);
1196 if (ret)
1197 return ret;
1198
1199 ret = marvell_nfc_wait_op(chip,
e0160cd4 1200 PSEC_TO_MSEC(sdr->tPROG_max));
02f26ecf
MR		 1201 return ret;
1202}
1203
767eb6fb 1204static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip,
02f26ecf
MR		 1205 const u8 *buf,
1206 int oob_required, int page)
1207{
b2525141 1208 marvell_nfc_select_target(chip, chip->cur_cs);
02f26ecf
MR		 1209 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1210 true, page);
1211}
1212
767eb6fb 1213static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip,
02f26ecf
MR		 1214 const u8 *buf,
1215 int oob_required, int page)
1216{
1217 int ret;
1218
b2525141 1219 marvell_nfc_select_target(chip, chip->cur_cs);
02f26ecf
MR		 1220 marvell_nfc_enable_hw_ecc(chip);
1221 ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1222 false, page);
1223 marvell_nfc_disable_hw_ecc(chip);
1224
1225 return ret;
1226}
1227
1228/*
1229 * Spare area in Hamming layouts is not protected by the ECC engine (even if
1230 * it appears before the ECC bytes when reading), the ->write_oob_raw() function
1231 * also stands for ->write_oob().
1232 */
767eb6fb 1233static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip,
02f26ecf
MR		 1234 int page)
1235{
767eb6fb 1236 struct mtd_info *mtd = nand_to_mtd(chip);
eeab7174 1237 u8 *buf = nand_get_data_buf(chip);
767eb6fb 1238
eeab7174 1239 memset(buf, 0xFF, mtd->writesize);
02f26ecf 1240
b2525141 1241 marvell_nfc_select_target(chip, chip->cur_cs);
eeab7174
BB		 1242 return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1243 true, page);
02f26ecf
MR		 1244}
1245
1246/* BCH read helpers */
b9761687 1247static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf,
02f26ecf
MR		 1248 int oob_required, int page)
1249{
b9761687 1250 struct mtd_info *mtd = nand_to_mtd(chip);
02f26ecf
MR		 1251 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1252 u8 *oob = chip->oob_poi;
1253 int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1254 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1255 lt->last_spare_bytes;
1256 int data_len = lt->data_bytes;
1257 int spare_len = lt->spare_bytes;
1258 int ecc_len = lt->ecc_bytes;
1259 int chunk;
1260
b2525141
BB		 1261 marvell_nfc_select_target(chip, chip->cur_cs);
1262
02f26ecf
MR		 1263 if (oob_required)
1264 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1265
1266 nand_read_page_op(chip, page, 0, NULL, 0);
1267
1268 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1269 /* Update last chunk length */
1270 if (chunk >= lt->full_chunk_cnt) {
1271 data_len = lt->last_data_bytes;
1272 spare_len = lt->last_spare_bytes;
1273 ecc_len = lt->last_ecc_bytes;
1274 }
1275
1276 /* Read data bytes*/
1277 nand_change_read_column_op(chip, chunk * chunk_size,
1278 buf + (lt->data_bytes * chunk),
1279 data_len, false);
1280
1281 /* Read spare bytes */
1282 nand_read_data_op(chip, oob + (lt->spare_bytes * chunk),
b451f5be 1283 spare_len, false, false);
02f26ecf
MR		 1284
1285 /* Read ECC bytes */
1286 nand_read_data_op(chip, oob + ecc_offset +
1287 (ALIGN(lt->ecc_bytes, 32) * chunk),
b451f5be 1288 ecc_len, false, false);
02f26ecf
MR		 1289 }
1290
1291 return 0;
1292}
1293
1294static void marvell_nfc_hw_ecc_bch_read_chunk(struct nand_chip *chip, int chunk,
1295 u8 *data, unsigned int data_len,
1296 u8 *spare, unsigned int spare_len,
1297 int page)
1298{
1299 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1300 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1301 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1302 int i, ret;
1303 struct marvell_nfc_op nfc_op = {
1304 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_READ) |
1305 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1306 NDCB0_LEN_OVRD,
1307 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1308 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1309 .ndcb[3] = data_len + spare_len,
1310 };
1311
1312 ret = marvell_nfc_prepare_cmd(chip);
1313 if (ret)
1314 return;
1315
1316 if (chunk == 0)
1317 nfc_op.ndcb[0] |= NDCB0_DBC |
1318 NDCB0_CMD1(NAND_CMD_READ0) |
1319 NDCB0_CMD2(NAND_CMD_READSTART);
1320
1321 /*
90d61763
BB		 1322 * Trigger the monolithic read on the first chunk, then naked read on
1323 * intermediate chunks and finally a last naked read on the last chunk.
02f26ecf 1324 */
90d61763 1325 if (chunk == 0)
02f26ecf 1326 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW);
90d61763
BB		 1327 else if (chunk < lt->nchunks - 1)
1328 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
02f26ecf
MR		 1329 else
1330 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1331
1332 marvell_nfc_send_cmd(chip, &nfc_op);
1333
1334 /*
1335 * According to the datasheet, when reading from NDDB
1336 * with BCH enabled, after each 32 bytes reads, we
1337 * have to make sure that the NDSR.RDDREQ bit is set.
1338 *
1339 * Drain the FIFO, 8 32-bit reads at a time, and skip
1340 * the polling on the last read.
1341 *
1342 * Length is a multiple of 32 bytes, hence it is a multiple of 8 too.
1343 */
1344 for (i = 0; i < data_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1345 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1346 "RDDREQ while draining FIFO (data)");
1347 marvell_nfc_xfer_data_in_pio(nfc, data,
1348 FIFO_DEPTH * BCH_SEQ_READS);
1349 data += FIFO_DEPTH * BCH_SEQ_READS;
1350 }
1351
1352 for (i = 0; i < spare_len; i += FIFO_DEPTH * BCH_SEQ_READS) {
1353 marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1354 "RDDREQ while draining FIFO (OOB)");
1355 marvell_nfc_xfer_data_in_pio(nfc, spare,
1356 FIFO_DEPTH * BCH_SEQ_READS);
1357 spare += FIFO_DEPTH * BCH_SEQ_READS;
1358 }
1359}
1360
b9761687 1361static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip,
02f26ecf
MR		 1362 u8 *buf, int oob_required,
1363 int page)
1364{
b9761687 1365 struct mtd_info *mtd = nand_to_mtd(chip);
02f26ecf 1366 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
dbfc6718
MR		 1367 int data_len = lt->data_bytes, spare_len = lt->spare_bytes;
1368 u8 *data = buf, *spare = chip->oob_poi;
02f26ecf
MR		 1369 int max_bitflips = 0;
1370 u32 failure_mask = 0;
dbfc6718 1371 int chunk, ret;
02f26ecf 1372
b2525141
BB		 1373 marvell_nfc_select_target(chip, chip->cur_cs);
1374
02f26ecf
MR		 1375 /*
1376 * With BCH, OOB is not fully used (and thus not read entirely), not
1377 * expected bytes could show up at the end of the OOB buffer if not
1378 * explicitly erased.
1379 */
1380 if (oob_required)
1381 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1382
1383 marvell_nfc_enable_hw_ecc(chip);
1384
1385 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1386 /* Update length for the last chunk */
1387 if (chunk >= lt->full_chunk_cnt) {
1388 data_len = lt->last_data_bytes;
1389 spare_len = lt->last_spare_bytes;
1390 }
1391
1392 /* Read the chunk and detect number of bitflips */
1393 marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len,
1394 spare, spare_len, page);
1617942a 1395 ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
02f26ecf
MR		 1396 if (ret)
1397 failure_mask |= BIT(chunk);
1398
1399 data += data_len;
1400 spare += spare_len;
1401 }
1402
1403 marvell_nfc_disable_hw_ecc(chip);
1404
1405 if (!failure_mask)
1406 return max_bitflips;
1407
1408 /*
1409 * Please note that dumping the ECC bytes during a normal read with OOB
1410 * area would add a significant overhead as ECC bytes are "consumed" by
1411 * the controller in normal mode and must be re-read in raw mode. To
1412 * avoid dropping the performances, we prefer not to include them. The
1413 * user should re-read the page in raw mode if ECC bytes are required.
dbfc6718
MR		 1414 */
1415
1416 /*
1617942a
MR		 1417 * In case there is any subpage read error, we usually re-read only ECC
1418 * bytes in raw mode and check if the whole page is empty. In this case,
1419 * it is normal that the ECC check failed and we just ignore the error.
02f26ecf 1420 *
7fd130f7
MR		 1421 * However, it has been empirically observed that for some layouts (e.g
1422 * 2k page, 8b strength per 512B chunk), the controller tries to correct
1423 * bits and may create itself bitflips in the erased area. To overcome
1424 * this strange behavior, the whole page is re-read in raw mode, not
1425 * only the ECC bytes.
02f26ecf
MR		 1426 */
1427 for (chunk = 0; chunk < lt->nchunks; chunk++) {
dbfc6718
MR		 1428 int data_off_in_page, spare_off_in_page, ecc_off_in_page;
1429 int data_off, spare_off, ecc_off;
1430 int data_len, spare_len, ecc_len;
1431
02f26ecf
MR		 1432 /* No failure reported for this chunk, move to the next one */
1433 if (!(failure_mask & BIT(chunk)))
1434 continue;
1435
dbfc6718
MR		 1436 data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes +
1437 lt->ecc_bytes);
1438 spare_off_in_page = data_off_in_page +
1439 (chunk < lt->full_chunk_cnt ? lt->data_bytes :
1440 lt->last_data_bytes);
1441 ecc_off_in_page = spare_off_in_page +
1442 (chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1443 lt->last_spare_bytes);
1444
1445 data_off = chunk * lt->data_bytes;
1446 spare_off = chunk * lt->spare_bytes;
1447 ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) +
1448 lt->last_spare_bytes +
1449 (chunk * (lt->ecc_bytes + 2));
1450
1451 data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes :
1452 lt->last_data_bytes;
1453 spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1454 lt->last_spare_bytes;
1455 ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes :
1456 lt->last_ecc_bytes;
1457
7fd130f7
MR		 1458 /*
1459 * Only re-read the ECC bytes, unless we are using the 2k/8b
1460 * layout which is buggy in the sense that the ECC engine will
1461 * try to correct data bytes anyway, creating bitflips. In this
1462 * case, re-read the entire page.
1463 */
1464 if (lt->writesize == 2048 && lt->strength == 8) {
1465 nand_change_read_column_op(chip, data_off_in_page,
1466 buf + data_off, data_len,
1467 false);
1468 nand_change_read_column_op(chip, spare_off_in_page,
1469 chip->oob_poi + spare_off, spare_len,
1470 false);
1471 }
1472
dbfc6718
MR		 1473 nand_change_read_column_op(chip, ecc_off_in_page,
1474 chip->oob_poi + ecc_off, ecc_len,
1475 false);
02f26ecf
MR		 1476
1477 /* Check the entire chunk (data + spare + ecc) for emptyness */
dbfc6718
MR		 1478 marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len,
1479 chip->oob_poi + spare_off, spare_len,
1480 chip->oob_poi + ecc_off, ecc_len,
02f26ecf
MR		 1481 &max_bitflips);
1482 }
1483
1484 return max_bitflips;
1485}
1486
b9761687 1487static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
02f26ecf 1488{
eeab7174 1489 u8 *buf = nand_get_data_buf(chip);
02f26ecf 1490
eeab7174 1491 return chip->ecc.read_page_raw(chip, buf, true, page);
02f26ecf
MR		 1492}
1493
b9761687 1494static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page)
02f26ecf 1495{
eeab7174 1496 u8 *buf = nand_get_data_buf(chip);
02f26ecf 1497
eeab7174 1498 return chip->ecc.read_page(chip, buf, true, page);
02f26ecf
MR		 1499}
1500
1501/* BCH write helpers */
767eb6fb 1502static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip,
02f26ecf
MR		 1503 const u8 *buf,
1504 int oob_required, int page)
1505{
1506 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1507 int full_chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
1508 int data_len = lt->data_bytes;
1509 int spare_len = lt->spare_bytes;
1510 int ecc_len = lt->ecc_bytes;
02f26ecf
MR		 1511 int spare_offset = 0;
1512 int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
1513 lt->last_spare_bytes;
1514 int chunk;
1515
b2525141
BB		 1516 marvell_nfc_select_target(chip, chip->cur_cs);
1517
02f26ecf
MR		 1518 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1519
1520 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1521 if (chunk >= lt->full_chunk_cnt) {
1522 data_len = lt->last_data_bytes;
1523 spare_len = lt->last_spare_bytes;
1524 ecc_len = lt->last_ecc_bytes;
02f26ecf
MR		 1525 }
1526
1527 /* Point to the column of the next chunk */
1528 nand_change_write_column_op(chip, chunk * full_chunk_size,
1529 NULL, 0, false);
1530
1531 /* Write the data */
1532 nand_write_data_op(chip, buf + (chunk * lt->data_bytes),
1533 data_len, false);
1534
1535 if (!oob_required)
1536 continue;
1537
1538 /* Write the spare bytes */
1539 if (spare_len)
1540 nand_write_data_op(chip, chip->oob_poi + spare_offset,
1541 spare_len, false);
1542
1543 /* Write the ECC bytes */
1544 if (ecc_len)
1545 nand_write_data_op(chip, chip->oob_poi + ecc_offset,
1546 ecc_len, false);
1547
1548 spare_offset += spare_len;
1549 ecc_offset += ALIGN(ecc_len, 32);
1550 }
1551
1552 return nand_prog_page_end_op(chip);
1553}
1554
1555static int
1556marvell_nfc_hw_ecc_bch_write_chunk(struct nand_chip *chip, int chunk,
1557 const u8 *data, unsigned int data_len,
1558 const u8 *spare, unsigned int spare_len,
1559 int page)
1560{
1561 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
1562 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1563 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
a2ee41fd 1564 u32 xtype;
02f26ecf
MR		 1565 int ret;
1566 struct marvell_nfc_op nfc_op = {
1567 .ndcb[0] = NDCB0_CMD_TYPE(TYPE_WRITE) | NDCB0_LEN_OVRD,
1568 .ndcb[3] = data_len + spare_len,
1569 };
1570
1571 /*
1572 * First operation dispatches the CMD_SEQIN command, issue the address
1573 * cycles and asks for the first chunk of data.
1574 * All operations in the middle (if any) will issue a naked write and
1575 * also ask for data.
1576 * Last operation (if any) asks for the last chunk of data through a
1577 * last naked write.
1578 */
1579 if (chunk == 0) {
a2ee41fd
MR		 1580 if (lt->nchunks == 1)
1581 xtype = XTYPE_MONOLITHIC_RW;
1582 else
1583 xtype = XTYPE_WRITE_DISPATCH;
1584
1585 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(xtype) |
02f26ecf
MR		 1586 NDCB0_ADDR_CYC(marvell_nand->addr_cyc) |
1587 NDCB0_CMD1(NAND_CMD_SEQIN);
1588 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
1589 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
1590 } else if (chunk < lt->nchunks - 1) {
1591 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_NAKED_RW);
1592 } else {
1593 nfc_op.ndcb[0] |= NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1594 }
1595
1596 /* Always dispatch the PAGEPROG command on the last chunk */
1597 if (chunk == lt->nchunks - 1)
1598 nfc_op.ndcb[0] |= NDCB0_CMD2(NAND_CMD_PAGEPROG) | NDCB0_DBC;
1599
1600 ret = marvell_nfc_prepare_cmd(chip);
1601 if (ret)
1602 return ret;
1603
1604 marvell_nfc_send_cmd(chip, &nfc_op);
1605 ret = marvell_nfc_end_cmd(chip, NDSR_WRDREQ,
1606 "WRDREQ while loading FIFO (data)");
1607 if (ret)
1608 return ret;
1609
1610 /* Transfer the contents */
1611 iowrite32_rep(nfc->regs + NDDB, data, FIFO_REP(data_len));
1612 iowrite32_rep(nfc->regs + NDDB, spare, FIFO_REP(spare_len));
1613
1614 return 0;
1615}
1616
767eb6fb 1617static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
02f26ecf
MR		 1618 const u8 *buf,
1619 int oob_required, int page)
1620{
e0160cd4
MR		 1621 const struct nand_sdr_timings *sdr =
1622 nand_get_sdr_timings(nand_get_interface_config(chip));
767eb6fb 1623 struct mtd_info *mtd = nand_to_mtd(chip);
02f26ecf
MR		 1624 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1625 const u8 *data = buf;
1626 const u8 *spare = chip->oob_poi;
1627 int data_len = lt->data_bytes;
1628 int spare_len = lt->spare_bytes;
1629 int chunk, ret;
1630
b2525141
BB		 1631 marvell_nfc_select_target(chip, chip->cur_cs);
1632
02f26ecf
MR		 1633 /* Spare data will be written anyway, so clear it to avoid garbage */
1634 if (!oob_required)
1635 memset(chip->oob_poi, 0xFF, mtd->oobsize);
1636
1637 marvell_nfc_enable_hw_ecc(chip);
1638
1639 for (chunk = 0; chunk < lt->nchunks; chunk++) {
1640 if (chunk >= lt->full_chunk_cnt) {
1641 data_len = lt->last_data_bytes;
1642 spare_len = lt->last_spare_bytes;
1643 }
1644
1645 marvell_nfc_hw_ecc_bch_write_chunk(chip, chunk, data, data_len,
1646 spare, spare_len, page);
1647 data += data_len;
1648 spare += spare_len;
1649
1650 /*
1651 * Waiting only for CMDD or PAGED is not enough, ECC are
1652 * partially written. No flag is set once the operation is
1653 * really finished but the ND_RUN bit is cleared, so wait for it
1654 * before stepping into the next command.
1655 */
1656 marvell_nfc_wait_ndrun(chip);
1657 }
1658
e0160cd4 1659 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
02f26ecf
MR		 1660
1661 marvell_nfc_disable_hw_ecc(chip);
1662
1663 if (ret)
1664 return ret;
1665
1666 return 0;
1667}
1668
767eb6fb 1669static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip,
02f26ecf
MR		 1670 int page)
1671{
767eb6fb 1672 struct mtd_info *mtd = nand_to_mtd(chip);
eeab7174 1673 u8 *buf = nand_get_data_buf(chip);
767eb6fb 1674
eeab7174 1675 memset(buf, 0xFF, mtd->writesize);
02f26ecf 1676
eeab7174 1677 return chip->ecc.write_page_raw(chip, buf, true, page);
02f26ecf
MR		 1678}
1679
767eb6fb 1680static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
02f26ecf 1681{
767eb6fb 1682 struct mtd_info *mtd = nand_to_mtd(chip);
eeab7174 1683 u8 *buf = nand_get_data_buf(chip);
767eb6fb 1684
eeab7174 1685 memset(buf, 0xFF, mtd->writesize);
02f26ecf 1686
eeab7174 1687 return chip->ecc.write_page(chip, buf, true, page);
02f26ecf
MR		 1688}
1689
1690/* NAND framework ->exec_op() hooks and related helpers */
1691static void marvell_nfc_parse_instructions(struct nand_chip *chip,
1692 const struct nand_subop *subop,
1693 struct marvell_nfc_op *nfc_op)
1694{
1695 const struct nand_op_instr *instr = NULL;
1696 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1697 bool first_cmd = true;
1698 unsigned int op_id;
1699 int i;
1700
1701 /* Reset the input structure as most of its fields will be OR'ed */
1702 memset(nfc_op, 0, sizeof(struct marvell_nfc_op));
1703
1704 for (op_id = 0; op_id < subop->ninstrs; op_id++) {
1705 unsigned int offset, naddrs;
1706 const u8 *addrs;
21a26806 1707 int len;
02f26ecf
MR		 1708
1709 instr = &subop->instrs[op_id];
1710
1711 switch (instr->type) {
1712 case NAND_OP_CMD_INSTR:
1713 if (first_cmd)
1714 nfc_op->ndcb[0] |=
1715 NDCB0_CMD1(instr->ctx.cmd.opcode);
1716 else
1717 nfc_op->ndcb[0] |=
1718 NDCB0_CMD2(instr->ctx.cmd.opcode) |
1719 NDCB0_DBC;
1720
1721 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1722 first_cmd = false;
1723 break;
1724
1725 case NAND_OP_ADDR_INSTR:
1726 offset = nand_subop_get_addr_start_off(subop, op_id);
1727 naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
1728 addrs = &instr->ctx.addr.addrs[offset];
1729
1730 nfc_op->ndcb[0] |= NDCB0_ADDR_CYC(naddrs);
1731
1732 for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
1733 nfc_op->ndcb[1] |= addrs[i] << (8 * i);
1734
1735 if (naddrs >= 5)
1736 nfc_op->ndcb[2] |= NDCB2_ADDR5_CYC(addrs[4]);
1737 if (naddrs >= 6)
1738 nfc_op->ndcb[3] |= NDCB3_ADDR6_CYC(addrs[5]);
1739 if (naddrs == 7)
1740 nfc_op->ndcb[3] |= NDCB3_ADDR7_CYC(addrs[6]);
1741
1742 nfc_op->cle_ale_delay_ns = instr->delay_ns;
1743 break;
1744
1745 case NAND_OP_DATA_IN_INSTR:
1746 nfc_op->data_instr = instr;
1747 nfc_op->data_instr_idx = op_id;
1748 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ);
1749 if (nfc->caps->is_nfcv2) {
1750 nfc_op->ndcb[0] |=
1751 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1752 NDCB0_LEN_OVRD;
21a26806 1753 len = nand_subop_get_data_len(subop, op_id);
02f26ecf
MR		 1754 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1755 }
1756 nfc_op->data_delay_ns = instr->delay_ns;
1757 break;
1758
1759 case NAND_OP_DATA_OUT_INSTR:
1760 nfc_op->data_instr = instr;
1761 nfc_op->data_instr_idx = op_id;
1762 nfc_op->ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE);
1763 if (nfc->caps->is_nfcv2) {
1764 nfc_op->ndcb[0] |=
1765 NDCB0_CMD_XTYPE(XTYPE_MONOLITHIC_RW) |
1766 NDCB0_LEN_OVRD;
21a26806 1767 len = nand_subop_get_data_len(subop, op_id);
02f26ecf
MR		 1768 nfc_op->ndcb[3] |= round_up(len, FIFO_DEPTH);
1769 }
1770 nfc_op->data_delay_ns = instr->delay_ns;
1771 break;
1772
1773 case NAND_OP_WAITRDY_INSTR:
1774 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
1775 nfc_op->rdy_delay_ns = instr->delay_ns;
1776 break;
1777 }
1778 }
1779}
1780
1781static int marvell_nfc_xfer_data_pio(struct nand_chip *chip,
1782 const struct nand_subop *subop,
1783 struct marvell_nfc_op *nfc_op)
1784{
1785 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1786 const struct nand_op_instr *instr = nfc_op->data_instr;
1787 unsigned int op_id = nfc_op->data_instr_idx;
1788 unsigned int len = nand_subop_get_data_len(subop, op_id);
1789 unsigned int offset = nand_subop_get_data_start_off(subop, op_id);
1790 bool reading = (instr->type == NAND_OP_DATA_IN_INSTR);
1791 int ret;
1792
1793 if (instr->ctx.data.force_8bit)
1794 marvell_nfc_force_byte_access(chip, true);
1795
1796 if (reading) {
1797 u8 *in = instr->ctx.data.buf.in + offset;
1798
1799 ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
1800 } else {
1801 const u8 *out = instr->ctx.data.buf.out + offset;
1802
1803 ret = marvell_nfc_xfer_data_out_pio(nfc, out, len);
1804 }
1805
1806 if (instr->ctx.data.force_8bit)
1807 marvell_nfc_force_byte_access(chip, false);
1808
1809 return ret;
1810}
1811
1812static int marvell_nfc_monolithic_access_exec(struct nand_chip *chip,
1813 const struct nand_subop *subop)
1814{
1815 struct marvell_nfc_op nfc_op;
1816 bool reading;
1817 int ret;
1818
1819 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1820 reading = (nfc_op.data_instr->type == NAND_OP_DATA_IN_INSTR);
1821
1822 ret = marvell_nfc_prepare_cmd(chip);
1823 if (ret)
1824 return ret;
1825
1826 marvell_nfc_send_cmd(chip, &nfc_op);
1827 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1828 "RDDREQ/WRDREQ while draining raw data");
1829 if (ret)
1830 return ret;
1831
1832 cond_delay(nfc_op.cle_ale_delay_ns);
1833
1834 if (reading) {
1835 if (nfc_op.rdy_timeout_ms) {
1836 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1837 if (ret)
1838 return ret;
1839 }
1840
1841 cond_delay(nfc_op.rdy_delay_ns);
1842 }
1843
1844 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1845 ret = marvell_nfc_wait_cmdd(chip);
1846 if (ret)
1847 return ret;
1848
1849 cond_delay(nfc_op.data_delay_ns);
1850
1851 if (!reading) {
1852 if (nfc_op.rdy_timeout_ms) {
1853 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1854 if (ret)
1855 return ret;
1856 }
1857
1858 cond_delay(nfc_op.rdy_delay_ns);
1859 }
1860
1861 /*
1862 * NDCR ND_RUN bit should be cleared automatically at the end of each
1863 * operation but experience shows that the behavior is buggy when it
1864 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1865 */
1866 if (!reading) {
1867 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1868
1869 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1870 nfc->regs + NDCR);
1871 }
1872
1873 return 0;
1874}
1875
1876static int marvell_nfc_naked_access_exec(struct nand_chip *chip,
1877 const struct nand_subop *subop)
1878{
1879 struct marvell_nfc_op nfc_op;
1880 int ret;
1881
1882 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1883
1884 /*
1885 * Naked access are different in that they need to be flagged as naked
1886 * by the controller. Reset the controller registers fields that inform
1887 * on the type and refill them according to the ongoing operation.
1888 */
1889 nfc_op.ndcb[0] &= ~(NDCB0_CMD_TYPE(TYPE_MASK) |
1890 NDCB0_CMD_XTYPE(XTYPE_MASK));
1891 switch (subop->instrs[0].type) {
1892 case NAND_OP_CMD_INSTR:
1893 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_CMD);
1894 break;
1895 case NAND_OP_ADDR_INSTR:
1896 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_NAKED_ADDR);
1897 break;
1898 case NAND_OP_DATA_IN_INSTR:
1899 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ) |
1900 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1901 break;
1902 case NAND_OP_DATA_OUT_INSTR:
1903 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_WRITE) |
1904 NDCB0_CMD_XTYPE(XTYPE_LAST_NAKED_RW);
1905 break;
1906 default:
1907 /* This should never happen */
1908 break;
1909 }
1910
1911 ret = marvell_nfc_prepare_cmd(chip);
1912 if (ret)
1913 return ret;
1914
1915 marvell_nfc_send_cmd(chip, &nfc_op);
1916
1917 if (!nfc_op.data_instr) {
1918 ret = marvell_nfc_wait_cmdd(chip);
1919 cond_delay(nfc_op.cle_ale_delay_ns);
1920 return ret;
1921 }
1922
1923 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ | NDSR_WRDREQ,
1924 "RDDREQ/WRDREQ while draining raw data");
1925 if (ret)
1926 return ret;
1927
1928 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1929 ret = marvell_nfc_wait_cmdd(chip);
1930 if (ret)
1931 return ret;
1932
1933 /*
1934 * NDCR ND_RUN bit should be cleared automatically at the end of each
1935 * operation but experience shows that the behavior is buggy when it
1936 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1937 */
1938 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) {
1939 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
1940
1941 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1942 nfc->regs + NDCR);
1943 }
1944
1945 return 0;
1946}
1947
1948static int marvell_nfc_naked_waitrdy_exec(struct nand_chip *chip,
1949 const struct nand_subop *subop)
1950{
1951 struct marvell_nfc_op nfc_op;
1952 int ret;
1953
1954 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1955
1956 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1957 cond_delay(nfc_op.rdy_delay_ns);
1958
1959 return ret;
1960}
1961
1962static int marvell_nfc_read_id_type_exec(struct nand_chip *chip,
1963 const struct nand_subop *subop)
1964{
1965 struct marvell_nfc_op nfc_op;
1966 int ret;
1967
1968 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
1969 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
1970 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_READ_ID);
1971
1972 ret = marvell_nfc_prepare_cmd(chip);
1973 if (ret)
1974 return ret;
1975
1976 marvell_nfc_send_cmd(chip, &nfc_op);
1977 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
1978 "RDDREQ while reading ID");
1979 if (ret)
1980 return ret;
1981
1982 cond_delay(nfc_op.cle_ale_delay_ns);
1983
1984 if (nfc_op.rdy_timeout_ms) {
1985 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
1986 if (ret)
1987 return ret;
1988 }
1989
1990 cond_delay(nfc_op.rdy_delay_ns);
1991
1992 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
1993 ret = marvell_nfc_wait_cmdd(chip);
1994 if (ret)
1995 return ret;
1996
1997 cond_delay(nfc_op.data_delay_ns);
1998
1999 return 0;
2000}
2001
2002static int marvell_nfc_read_status_exec(struct nand_chip *chip,
2003 const struct nand_subop *subop)
2004{
2005 struct marvell_nfc_op nfc_op;
2006 int ret;
2007
2008 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
2009 nfc_op.ndcb[0] &= ~NDCB0_CMD_TYPE(TYPE_READ);
2010 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_STATUS);
2011
2012 ret = marvell_nfc_prepare_cmd(chip);
2013 if (ret)
2014 return ret;
2015
2016 marvell_nfc_send_cmd(chip, &nfc_op);
2017 ret = marvell_nfc_end_cmd(chip, NDSR_RDDREQ,
2018 "RDDREQ while reading status");
2019 if (ret)
2020 return ret;
2021
2022 cond_delay(nfc_op.cle_ale_delay_ns);
2023
2024 if (nfc_op.rdy_timeout_ms) {
2025 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2026 if (ret)
2027 return ret;
2028 }
2029
2030 cond_delay(nfc_op.rdy_delay_ns);
2031
2032 marvell_nfc_xfer_data_pio(chip, subop, &nfc_op);
2033 ret = marvell_nfc_wait_cmdd(chip);
2034 if (ret)
2035 return ret;
2036
2037 cond_delay(nfc_op.data_delay_ns);
2038
2039 return 0;
2040}
2041
2042static int marvell_nfc_reset_cmd_type_exec(struct nand_chip *chip,
2043 const struct nand_subop *subop)
2044{
2045 struct marvell_nfc_op nfc_op;
2046 int ret;
2047
2048 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
2049 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_RESET);
2050
2051 ret = marvell_nfc_prepare_cmd(chip);
2052 if (ret)
2053 return ret;
2054
2055 marvell_nfc_send_cmd(chip, &nfc_op);
2056 ret = marvell_nfc_wait_cmdd(chip);
2057 if (ret)
2058 return ret;
2059
2060 cond_delay(nfc_op.cle_ale_delay_ns);
2061
2062 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2063 if (ret)
2064 return ret;
2065
2066 cond_delay(nfc_op.rdy_delay_ns);
2067
2068 return 0;
2069}
2070
2071static int marvell_nfc_erase_cmd_type_exec(struct nand_chip *chip,
2072 const struct nand_subop *subop)
2073{
2074 struct marvell_nfc_op nfc_op;
2075 int ret;
2076
2077 marvell_nfc_parse_instructions(chip, subop, &nfc_op);
2078 nfc_op.ndcb[0] |= NDCB0_CMD_TYPE(TYPE_ERASE);
2079
2080 ret = marvell_nfc_prepare_cmd(chip);
2081 if (ret)
2082 return ret;
2083
2084 marvell_nfc_send_cmd(chip, &nfc_op);
2085 ret = marvell_nfc_wait_cmdd(chip);
2086 if (ret)
2087 return ret;
2088
2089 cond_delay(nfc_op.cle_ale_delay_ns);
2090
2091 ret = marvell_nfc_wait_op(chip, nfc_op.rdy_timeout_ms);
2092 if (ret)
2093 return ret;
2094
2095 cond_delay(nfc_op.rdy_delay_ns);
2096
2097 return 0;
2098}
2099
2100static const struct nand_op_parser marvell_nfcv2_op_parser = NAND_OP_PARSER(
2101 /* Monolithic reads/writes */
2102 NAND_OP_PARSER_PATTERN(
2103 marvell_nfc_monolithic_access_exec,
2104 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2105 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC_NFCV2),
2106 NAND_OP_PARSER_PAT_CMD_ELEM(true),
2107 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
2108 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
2109 NAND_OP_PARSER_PATTERN(
2110 marvell_nfc_monolithic_access_exec,
2111 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2112 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2),
2113 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE),
2114 NAND_OP_PARSER_PAT_CMD_ELEM(true),
2115 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
2116 /* Naked commands */
2117 NAND_OP_PARSER_PATTERN(
2118 marvell_nfc_naked_access_exec,
2119 NAND_OP_PARSER_PAT_CMD_ELEM(false)),
2120 NAND_OP_PARSER_PATTERN(
2121 marvell_nfc_naked_access_exec,
2122 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV2)),
2123 NAND_OP_PARSER_PATTERN(
2124 marvell_nfc_naked_access_exec,
2125 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, MAX_CHUNK_SIZE)),
2126 NAND_OP_PARSER_PATTERN(
2127 marvell_nfc_naked_access_exec,
2128 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_CHUNK_SIZE)),
2129 NAND_OP_PARSER_PATTERN(
2130 marvell_nfc_naked_waitrdy_exec,
2131 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2132 );
2133
2134static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
2135 /* Naked commands not supported, use a function for each pattern */
2136 NAND_OP_PARSER_PATTERN(
2137 marvell_nfc_read_id_type_exec,
2138 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2139 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
2140 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)),
2141 NAND_OP_PARSER_PATTERN(
2142 marvell_nfc_erase_cmd_type_exec,
2143 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2144 NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYC_NFCV1),
2145 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2146 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2147 NAND_OP_PARSER_PATTERN(
2148 marvell_nfc_read_status_exec,
2149 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2150 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)),
2151 NAND_OP_PARSER_PATTERN(
2152 marvell_nfc_reset_cmd_type_exec,
2153 NAND_OP_PARSER_PAT_CMD_ELEM(false),
2154 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2155 NAND_OP_PARSER_PATTERN(
2156 marvell_nfc_naked_waitrdy_exec,
2157 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
2158 );
2159
2160static int marvell_nfc_exec_op(struct nand_chip *chip,
2161 const struct nand_operation *op,
2162 bool check_only)
2163{
2164 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2165
ce446b4b
BB		 2166 if (!check_only)
2167 marvell_nfc_select_target(chip, op->cs);
b2525141 2168
02f26ecf
MR		 2169 if (nfc->caps->is_nfcv2)
2170 return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser,
2171 op, check_only);
2172 else
2173 return nand_op_parser_exec_op(chip, &marvell_nfcv1_op_parser,
2174 op, check_only);
2175}
2176
2177/*
2178 * Layouts were broken in old pxa3xx_nand driver, these are supposed to be
2179 * usable.
2180 */
2181static int marvell_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
2182 struct mtd_oob_region *oobregion)
2183{
2184 struct nand_chip *chip = mtd_to_nand(mtd);
2185 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2186
2187 if (section)
2188 return -ERANGE;
2189
2190 oobregion->length = (lt->full_chunk_cnt * lt->ecc_bytes) +
2191 lt->last_ecc_bytes;
2192 oobregion->offset = mtd->oobsize - oobregion->length;
2193
2194 return 0;
2195}
2196
2197static int marvell_nand_ooblayout_free(struct mtd_info *mtd, int section,
2198 struct mtd_oob_region *oobregion)
2199{
2200 struct nand_chip *chip = mtd_to_nand(mtd);
2201 const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2202
2203 if (section)
2204 return -ERANGE;
2205
2206 /*
2207 * Bootrom looks in bytes 0 & 5 for bad blocks for the
2208 * 4KB page / 4bit BCH combination.
2209 */
2210 if (mtd->writesize == SZ_4K && lt->data_bytes == SZ_2K)
2211 oobregion->offset = 6;
2212 else
2213 oobregion->offset = 2;
2214
2215 oobregion->length = (lt->full_chunk_cnt * lt->spare_bytes) +
2216 lt->last_spare_bytes - oobregion->offset;
2217
2218 return 0;
2219}
2220
2221static const struct mtd_ooblayout_ops marvell_nand_ooblayout_ops = {
2222 .ecc = marvell_nand_ooblayout_ecc,
2223 .free = marvell_nand_ooblayout_free,
2224};
2225
82c6c04e
MR		 2226static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
2227 struct nand_ecc_ctrl *ecc)
02f26ecf
MR		 2228{
2229 struct nand_chip *chip = mtd_to_nand(mtd);
2230 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2231 const struct marvell_hw_ecc_layout *l;
2232 int i;
2233
2234 if (!nfc->caps->is_nfcv2 &&
2235 (mtd->writesize + mtd->oobsize > MAX_CHUNK_SIZE)) {
2236 dev_err(nfc->dev,
2237 "NFCv1: writesize (%d) cannot be bigger than a chunk (%d)\n",
2238 mtd->writesize, MAX_CHUNK_SIZE - mtd->oobsize);
2239 return -ENOTSUPP;
2240 }
2241
2242 to_marvell_nand(chip)->layout = NULL;
2243 for (i = 0; i < ARRAY_SIZE(marvell_nfc_layouts); i++) {
2244 l = &marvell_nfc_layouts[i];
2245 if (mtd->writesize == l->writesize &&
2246 ecc->size == l->chunk && ecc->strength == l->strength) {
2247 to_marvell_nand(chip)->layout = l;
2248 break;
2249 }
2250 }
2251
2252 if (!to_marvell_nand(chip)->layout ||
2253 (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
2254 dev_err(nfc->dev,
2255 "ECC strength %d at page size %d is not supported\n",
2256 ecc->strength, mtd->writesize);
2257 return -ENOTSUPP;
2258 }
2259
7fd130f7
MR		 2260 /* Special care for the layout 2k/8-bit/512B */
2261 if (l->writesize == 2048 && l->strength == 8) {
2262 if (mtd->oobsize < 128) {
2263 dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n");
2264 return -ENOTSUPP;
2265 } else {
2266 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2267 }
2268 }
2269
02f26ecf
MR		 2270 mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops);
2271 ecc->steps = l->nchunks;
2272 ecc->size = l->data_bytes;
2273
2274 if (ecc->strength == 1) {
e0a564ae 2275 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
02f26ecf
MR		 2276 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
2277 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
2278 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
2279 ecc->read_oob = ecc->read_oob_raw;
2280 ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
2281 ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
2282 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
2283 ecc->write_oob = ecc->write_oob_raw;
2284 } else {
e0a564ae 2285 chip->ecc.algo = NAND_ECC_ALGO_BCH;
02f26ecf
MR		 2286 ecc->strength = 16;
2287 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
2288 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
2289 ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
2290 ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
2291 ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
2292 ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
2293 ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
2294 ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
2295 }
2296
2297 return 0;
2298}
2299
2300static int marvell_nand_ecc_init(struct mtd_info *mtd,
2301 struct nand_ecc_ctrl *ecc)
2302{
2303 struct nand_chip *chip = mtd_to_nand(mtd);
53576c7b
MR		 2304 const struct nand_ecc_props *requirements =
2305 nanddev_get_ecc_requirements(&chip->base);
02f26ecf
MR		 2306 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2307 int ret;
2308
bace41f8
MR		 2309 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2310 (!ecc->size || !ecc->strength)) {
53576c7b
MR		 2311 if (requirements->step_size && requirements->strength) {
2312 ecc->size = requirements->step_size;
2313 ecc->strength = requirements->strength;
02f26ecf
MR		 2314 } else {
2315 dev_info(nfc->dev,
2316 "No minimum ECC strength, using 1b/512B\n");
2317 ecc->size = 512;
2318 ecc->strength = 1;
2319 }
2320 }
2321
bace41f8
MR		 2322 switch (ecc->engine_type) {
2323 case NAND_ECC_ENGINE_TYPE_ON_HOST:
82c6c04e 2324 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
02f26ecf
MR		 2325 if (ret)
2326 return ret;
2327 break;
bace41f8
MR		 2328 case NAND_ECC_ENGINE_TYPE_NONE:
2329 case NAND_ECC_ENGINE_TYPE_SOFT:
2330 case NAND_ECC_ENGINE_TYPE_ON_DIE:
02f26ecf
MR		 2331 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
2332 mtd->writesize != SZ_2K) {
2333 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
2334 mtd->writesize);
2335 return -EINVAL;
2336 }
2337 break;
2338 default:
2339 return -EINVAL;
2340 }
2341
2342 return 0;
2343}
2344
2345static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
2346static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
2347
2348static struct nand_bbt_descr bbt_main_descr = {
2349 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2350 NAND_BBT_2BIT | NAND_BBT_VERSION,
2351 .offs = 8,
2352 .len = 6,
2353 .veroffs = 14,
2354 .maxblocks = 8, /* Last 8 blocks in each chip */
2355 .pattern = bbt_pattern
2356};
2357
2358static struct nand_bbt_descr bbt_mirror_descr = {
2359 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
2360 NAND_BBT_2BIT | NAND_BBT_VERSION,
2361 .offs = 8,
2362 .len = 6,
2363 .veroffs = 14,
2364 .maxblocks = 8, /* Last 8 blocks in each chip */
2365 .pattern = bbt_mirror_pattern
2366};
2367
4c46667b
MR		 2368static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
2369 const struct nand_interface_config *conf)
02f26ecf 2370{
02f26ecf
MR		 2371 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2372 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
6b6de654 2373 unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2;
02f26ecf
MR		 2374 const struct nand_sdr_timings *sdr;
2375 struct marvell_nfc_timings nfc_tmg;
2376 int read_delay;
2377
2378 sdr = nand_get_sdr_timings(conf);
2379 if (IS_ERR(sdr))
2380 return PTR_ERR(sdr);
2381
72b9a3fc
CP		 2382 if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode)
2383 return -EOPNOTSUPP;
2384
02f26ecf
MR		 2385 /*
2386 * SDR timings are given in pico-seconds while NFC timings must be
2387 * expressed in NAND controller clock cycles, which is half of the
2388 * frequency of the accessible ECC clock retrieved by clk_get_rate().
2389 * This is not written anywhere in the datasheet but was observed
2390 * with an oscilloscope.
2391 *
2392 * NFC datasheet gives equations from which thoses calculations
2393 * are derived, they tend to be slightly more restrictives than the
2394 * given core timings and may improve the overall speed.
2395 */
2396 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
2397 nfc_tmg.tRH = nfc_tmg.tRP;
2398 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
2399 nfc_tmg.tWH = nfc_tmg.tWP;
2400 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
2401 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
2402 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
2403 /*
2404 * Read delay is the time of propagation from SoC pins to NFC internal
2405 * logic. With non-EDO timings, this is MIN_RD_DEL_CNT clock cycles. In
2406 * EDO mode, an additional delay of tRH must be taken into account so
2407 * the data is sampled on the falling edge instead of the rising edge.
2408 */
2409 read_delay = sdr->tRC_min >= 30000 ?
2410 MIN_RD_DEL_CNT : MIN_RD_DEL_CNT + nfc_tmg.tRH;
2411
2412 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
2413 /*
2414 * tWHR and tRHW are supposed to be read to write delays (and vice
2415 * versa) but in some cases, ie. when doing a change column, they must
2416 * be greater than that to be sure tCCS delay is respected.
2417 */
2418 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
e64ab8e8 2419 period_ns) - 2;
02f26ecf
MR		 2420 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
2421 period_ns);
2422
07ad5a72
MR		 2423 /*
2424 * NFCv2: Use WAIT_MODE (wait for RB line), do not rely only on delays.
2425 * NFCv1: No WAIT_MODE, tR must be maximal.
2426 */
2427 if (nfc->caps->is_nfcv2) {
2428 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
2429 } else {
2430 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,
2431 period_ns);
2432 if (nfc_tmg.tR + 3 > nfc_tmg.tCH)
2433 nfc_tmg.tR = nfc_tmg.tCH - 3;
2434 else
2435 nfc_tmg.tR = 0;
2436 }
02f26ecf
MR		 2437
2438 if (chipnr < 0)
2439 return 0;
2440
2441 marvell_nand->ndtr0 =
2442 NDTR0_TRP(nfc_tmg.tRP) |
2443 NDTR0_TRH(nfc_tmg.tRH) |
2444 NDTR0_ETRP(nfc_tmg.tRP) |
2445 NDTR0_TWP(nfc_tmg.tWP) |
2446 NDTR0_TWH(nfc_tmg.tWH) |
2447 NDTR0_TCS(nfc_tmg.tCS) |
07ad5a72 2448 NDTR0_TCH(nfc_tmg.tCH);
02f26ecf
MR		 2449
2450 marvell_nand->ndtr1 =
2451 NDTR1_TAR(nfc_tmg.tAR) |
2452 NDTR1_TWHR(nfc_tmg.tWHR) |
02f26ecf
MR		 2453 NDTR1_TR(nfc_tmg.tR);
2454
07ad5a72
MR		 2455 if (nfc->caps->is_nfcv2) {
2456 marvell_nand->ndtr0 |=
2457 NDTR0_RD_CNT_DEL(read_delay) |
2458 NDTR0_SELCNTR |
2459 NDTR0_TADL(nfc_tmg.tADL);
2460
2461 marvell_nand->ndtr1 |=
2462 NDTR1_TRHW(nfc_tmg.tRHW) |
2463 NDTR1_WAIT_MODE;
2464 }
2465
8a6f4d34
CP		 2466 /*
2467 * Reset nfc->selected_chip so the next command will cause the timing
2468 * registers to be updated in marvell_nfc_select_target().
2469 */
2470 nfc->selected_chip = NULL;
2471
02f26ecf
MR		 2472 return 0;
2473}
2474
8831e48b
MR		 2475static int marvell_nand_attach_chip(struct nand_chip *chip)
2476{
2477 struct mtd_info *mtd = nand_to_mtd(chip);
2478 struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
2479 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
2480 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(nfc->dev);
2481 int ret;
2482
2483 if (pdata && pdata->flash_bbt)
2484 chip->bbt_options |= NAND_BBT_USE_FLASH;
2485
2486 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
2487 /*
2488 * We'll use a bad block table stored in-flash and don't
2489 * allow writing the bad block marker to the flash.
2490 */
2491 chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2492 chip->bbt_td = &bbt_main_descr;
2493 chip->bbt_md = &bbt_mirror_descr;
2494 }
2495
2496 /* Save the chip-specific fields of NDCR */
2497 marvell_nand->ndcr = NDCR_PAGE_SZ(mtd->writesize);
2498 if (chip->options & NAND_BUSWIDTH_16)
2499 marvell_nand->ndcr |= NDCR_DWIDTH_M | NDCR_DWIDTH_C;
2500
2501 /*
2502 * On small page NANDs, only one cycle is needed to pass the
2503 * column address.
2504 */
2505 if (mtd->writesize <= 512) {
2506 marvell_nand->addr_cyc = 1;
2507 } else {
2508 marvell_nand->addr_cyc = 2;
2509 marvell_nand->ndcr |= NDCR_RA_START;
2510 }
2511
2512 /*
2513 * Now add the number of cycles needed to pass the row
2514 * address.
2515 *
2516 * Addressing a chip using CS 2 or 3 should also need the third row
2517 * cycle but due to inconsistance in the documentation and lack of
2518 * hardware to test this situation, this case is not supported.
2519 */
2520 if (chip->options & NAND_ROW_ADDR_3)
2521 marvell_nand->addr_cyc += 3;
2522 else
2523 marvell_nand->addr_cyc += 2;
2524
2525 if (pdata) {
2526 chip->ecc.size = pdata->ecc_step_size;
2527 chip->ecc.strength = pdata->ecc_strength;
2528 }
2529
2530 ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2531 if (ret) {
2532 dev_err(nfc->dev, "ECC init failed: %d\n", ret);
2533 return ret;
2534 }
2535
bace41f8 2536 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
8831e48b
MR		 2537 /*
2538 * Subpage write not available with hardware ECC, prohibit also
2539 * subpage read as in userspace subpage access would still be
2540 * allowed and subpage write, if used, would lead to numerous
2541 * uncorrectable ECC errors.
2542 */
2543 chip->options |= NAND_NO_SUBPAGE_WRITE;
2544 }
2545
2546 if (pdata || nfc->caps->legacy_of_bindings) {
2547 /*
2548 * We keep the MTD name unchanged to avoid breaking platforms
2549 * where the MTD cmdline parser is used and the bootloader
2550 * has not been updated to use the new naming scheme.
2551 */
2552 mtd->name = "pxa3xx_nand-0";
2553 } else if (!mtd->name) {
2554 /*
2555 * If the new bindings are used and the bootloader has not been
2556 * updated to pass a new mtdparts parameter on the cmdline, you
2557 * should define the following property in your NAND node, ie:
2558 *
2559 * label = "main-storage";
2560 *
2561 * This way, mtd->name will be set by the core when
2562 * nand_set_flash_node() is called.
2563 */
2564 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
2565 "%s:nand.%d", dev_name(nfc->dev),
2566 marvell_nand->sels[0].cs);
2567 if (!mtd->name) {
2568 dev_err(nfc->dev, "Failed to allocate mtd->name\n");
2569 return -ENOMEM;
2570 }
2571 }
2572
2573 return 0;
2574}
2575
2576static const struct nand_controller_ops marvell_nand_controller_ops = {
2577 .attach_chip = marvell_nand_attach_chip,
f2abfeb2 2578 .exec_op = marvell_nfc_exec_op,
4c46667b 2579 .setup_interface = marvell_nfc_setup_interface,
8831e48b
MR		 2580};
2581
02f26ecf
MR		 2582static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
2583 struct device_node *np)
2584{
2585 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(dev);
2586 struct marvell_nand_chip *marvell_nand;
2587 struct mtd_info *mtd;
2588 struct nand_chip *chip;
2589 int nsels, ret, i;
2590 u32 cs, rb;
2591
2592 /*
2593 * The legacy "num-cs" property indicates the number of CS on the only
2594 * chip connected to the controller (legacy bindings does not support
f6997bec 2595 * more than one chip). The CS and RB pins are always the #0.
02f26ecf
MR		 2596 *
2597 * When not using legacy bindings, a couple of "reg" and "nand-rb"
2598 * properties must be filled. For each chip, expressed as a subnode,
2599 * "reg" points to the CS lines and "nand-rb" to the RB line.
2600 */
f6997bec 2601 if (pdata || nfc->caps->legacy_of_bindings) {
02f26ecf 2602 nsels = 1;
f6997bec
MR		 2603 } else {
2604 nsels = of_property_count_elems_of_size(np, "reg", sizeof(u32));
2605 if (nsels <= 0) {
2606 dev_err(dev, "missing/invalid reg property\n");
2607 return -EINVAL;
2608 }
02f26ecf
MR		 2609 }
2610
2611 /* Alloc the nand chip structure */
7b301965
GS		 2612 marvell_nand = devm_kzalloc(dev,
2613 struct_size(marvell_nand, sels, nsels),
02f26ecf
MR		 2614 GFP_KERNEL);
2615 if (!marvell_nand) {
2616 dev_err(dev, "could not allocate chip structure\n");
2617 return -ENOMEM;
2618 }
2619
2620 marvell_nand->nsels = nsels;
2621 marvell_nand->selected_die = -1;
2622
2623 for (i = 0; i < nsels; i++) {
2624 if (pdata || nfc->caps->legacy_of_bindings) {
2625 /*
2626 * Legacy bindings use the CS lines in natural
2627 * order (0, 1, ...)
2628 */
2629 cs = i;
2630 } else {
2631 /* Retrieve CS id */
2632 ret = of_property_read_u32_index(np, "reg", i, &cs);
2633 if (ret) {
2634 dev_err(dev, "could not retrieve reg property: %d\n",
2635 ret);
2636 return ret;
2637 }
2638 }
2639
2640 if (cs >= nfc->caps->max_cs_nb) {
2641 dev_err(dev, "invalid reg value: %u (max CS = %d)\n",
2642 cs, nfc->caps->max_cs_nb);
2643 return -EINVAL;
2644 }
2645
2646 if (test_and_set_bit(cs, &nfc->assigned_cs)) {
2647 dev_err(dev, "CS %d already assigned\n", cs);
2648 return -EINVAL;
2649 }
2650
2651 /*
2652 * The cs variable represents the chip select id, which must be
2653 * converted in bit fields for NDCB0 and NDCB2 to select the
2654 * right chip. Unfortunately, due to a lack of information on
2655 * the subject and incoherent documentation, the user should not
2656 * use CS1 and CS3 at all as asserting them is not supported in
2657 * a reliable way (due to multiplexing inside ADDR5 field).
2658 */
2659 marvell_nand->sels[i].cs = cs;
2660 switch (cs) {
2661 case 0:
2662 case 2:
2663 marvell_nand->sels[i].ndcb0_csel = 0;
2664 break;
2665 case 1:
2666 case 3:
2667 marvell_nand->sels[i].ndcb0_csel = NDCB0_CSEL;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672
2673 /* Retrieve RB id */
2674 if (pdata || nfc->caps->legacy_of_bindings) {
2675 /* Legacy bindings always use RB #0 */
2676 rb = 0;
2677 } else {
2678 ret = of_property_read_u32_index(np, "nand-rb", i,
2679 &rb);
2680 if (ret) {
2681 dev_err(dev,
2682 "could not retrieve RB property: %d\n",
2683 ret);
2684 return ret;
2685 }
2686 }
2687
2688 if (rb >= nfc->caps->max_rb_nb) {
2689 dev_err(dev, "invalid reg value: %u (max RB = %d)\n",
2690 rb, nfc->caps->max_rb_nb);
2691 return -EINVAL;
2692 }
2693
2694 marvell_nand->sels[i].rb = rb;
2695 }
2696
2697 chip = &marvell_nand->chip;
2698 chip->controller = &nfc->controller;
2699 nand_set_flash_node(chip, np);
2700
ce107713 2701 if (of_property_read_bool(np, "marvell,nand-keep-config"))
7a08dbae 2702 chip->options |= NAND_KEEP_TIMINGS;
02f26ecf
MR		 2703
2704 mtd = nand_to_mtd(chip);
2705 mtd->dev.parent = dev;
2706
02f26ecf
MR		 2707 /*
2708 * Save a reference value for timing registers before
4c46667b 2709 * ->setup_interface() is called.
02f26ecf
MR		 2710 */
2711 marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
2712 marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
2713
2714 chip->options |= NAND_BUSWIDTH_AUTO;
02f26ecf 2715
00ad378f 2716 ret = nand_scan(chip, marvell_nand->nsels);
02f26ecf 2717 if (ret) {
8831e48b 2718 dev_err(dev, "could not scan the nand chip\n");
02f26ecf
MR		 2719 return ret;
2720 }
2721
2722 if (pdata)
2723 /* Legacy bindings support only one chip */
7576594c 2724 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
02f26ecf
MR		 2725 else
2726 ret = mtd_device_register(mtd, NULL, 0);
2727 if (ret) {
2728 dev_err(dev, "failed to register mtd device: %d\n", ret);
7a0c18fb 2729 nand_cleanup(chip);
02f26ecf
MR		 2730 return ret;
2731 }
2732
2733 list_add_tail(&marvell_nand->node, &nfc->chips);
2734
2735 return 0;
2736}
2737
c525b7af
MR		 2738static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc)
2739{
2740 struct marvell_nand_chip *entry, *temp;
5ecbba61
MR		 2741 struct nand_chip *chip;
2742 int ret;
c525b7af
MR		 2743
2744 list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
5ecbba61
MR		 2745 chip = &entry->chip;
2746 ret = mtd_device_unregister(nand_to_mtd(chip));
2747 WARN_ON(ret);
2748 nand_cleanup(chip);
c525b7af
MR		 2749 list_del(&entry->node);
2750 }
2751}
2752
02f26ecf
MR		 2753static int marvell_nand_chips_init(struct device *dev, struct marvell_nfc *nfc)
2754{
2755 struct device_node *np = dev->of_node;
2756 struct device_node *nand_np;
2757 int max_cs = nfc->caps->max_cs_nb;
2758 int nchips;
2759 int ret;
2760
2761 if (!np)
2762 nchips = 1;
2763 else
2764 nchips = of_get_child_count(np);
2765
2766 if (nchips > max_cs) {
2767 dev_err(dev, "too many NAND chips: %d (max = %d CS)\n", nchips,
2768 max_cs);
2769 return -EINVAL;
2770 }
2771
2772 /*
2773 * Legacy bindings do not use child nodes to exhibit NAND chip
2774 * properties and layout. Instead, NAND properties are mixed with the
2775 * controller ones, and partitions are defined as direct subnodes of the
2776 * NAND controller node.
2777 */
2778 if (nfc->caps->legacy_of_bindings) {
2779 ret = marvell_nand_chip_init(dev, nfc, np);
2780 return ret;
2781 }
2782
2783 for_each_child_of_node(np, nand_np) {
2784 ret = marvell_nand_chip_init(dev, nfc, nand_np);
2785 if (ret) {
2786 of_node_put(nand_np);
c525b7af 2787 goto cleanup_chips;
02f26ecf
MR		 2788 }
2789 }
2790
2791 return 0;
02f26ecf 2792
c525b7af
MR		 2793cleanup_chips:
2794 marvell_nand_chips_cleanup(nfc);
02f26ecf 2795
c525b7af 2796 return ret;
02f26ecf
MR		 2797}
2798
2799static int marvell_nfc_init_dma(struct marvell_nfc *nfc)
2800{
2801 struct platform_device *pdev = container_of(nfc->dev,
2802 struct platform_device,
2803 dev);
2804 struct dma_slave_config config = {};
2805 struct resource *r;
02f26ecf
MR		 2806 int ret;
2807
2808 if (!IS_ENABLED(CONFIG_PXA_DMA)) {
2809 dev_warn(nfc->dev,
2810 "DMA not enabled in configuration\n");
2811 return -ENOTSUPP;
2812 }
2813
2814 ret = dma_set_mask_and_coherent(nfc->dev, DMA_BIT_MASK(32));
2815 if (ret)
2816 return ret;
2817
cf9e2389
PU		 2818 nfc->dma_chan = dma_request_chan(nfc->dev, "data");
2819 if (IS_ERR(nfc->dma_chan)) {
2820 ret = PTR_ERR(nfc->dma_chan);
2821 nfc->dma_chan = NULL;
6ce92fae 2822 return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n");
02f26ecf
MR		 2823 }
2824
2825 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
aafe30ba
PU		 2826 if (!r) {
2827 ret = -ENXIO;
2828 goto release_channel;
2829 }
02f26ecf
MR		 2830
2831 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2832 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2833 config.src_addr = r->start + NDDB;
2834 config.dst_addr = r->start + NDDB;
2835 config.src_maxburst = 32;
2836 config.dst_maxburst = 32;
2837 ret = dmaengine_slave_config(nfc->dma_chan, &config);
2838 if (ret < 0) {
2839 dev_err(nfc->dev, "Failed to configure DMA channel\n");
aafe30ba 2840 goto release_channel;
02f26ecf
MR		 2841 }
2842
2843 /*
2844 * DMA must act on length multiple of 32 and this length may be
2845 * bigger than the destination buffer. Use this buffer instead
2846 * for DMA transfers and then copy the desired amount of data to
2847 * the provided buffer.
2848 */
c495a927 2849 nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
aafe30ba
PU		 2850 if (!nfc->dma_buf) {
2851 ret = -ENOMEM;
2852 goto release_channel;
2853 }
02f26ecf
MR		 2854
2855 nfc->use_dma = true;
2856
2857 return 0;
aafe30ba
PU		 2858
2859release_channel:
2860 dma_release_channel(nfc->dma_chan);
2861 nfc->dma_chan = NULL;
2862
2863 return ret;
02f26ecf
MR		 2864}
2865
bd9c3f9b
DM		 2866static void marvell_nfc_reset(struct marvell_nfc *nfc)
2867{
2868 /*
2869 * ECC operations and interruptions are only enabled when specifically
2870 * needed. ECC shall not be activated in the early stages (fails probe).
2871 * Arbiter flag, even if marked as "reserved", must be set (empirical).
2872 * SPARE_EN bit must always be set or ECC bytes will not be at the same
2873 * offset in the read page and this will fail the protection.
2874 */
2875 writel_relaxed(NDCR_ALL_INT | NDCR_ND_ARB_EN | NDCR_SPARE_EN |
2876 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);
2877 writel_relaxed(0xFFFFFFFF, nfc->regs + NDSR);
2878 writel_relaxed(0, nfc->regs + NDECCCTRL);
2879}
2880
02f26ecf
MR		 2881static int marvell_nfc_init(struct marvell_nfc *nfc)
2882{
2883 struct device_node *np = nfc->dev->of_node;
2884
2885 /*
2886 * Some SoCs like A7k/A8k need to enable manually the NAND
2887 * controller, gated clocks and reset bits to avoid being bootloader
2888 * dependent. This is done through the use of the System Functions
2889 * registers.
2890 */
2891 if (nfc->caps->need_system_controller) {
2892 struct regmap *sysctrl_base =
2893 syscon_regmap_lookup_by_phandle(np,
2894 "marvell,system-controller");
02f26ecf
MR		 2895
2896 if (IS_ERR(sysctrl_base))
2897 return PTR_ERR(sysctrl_base);
2898
88aa3bbf
TP		 2899 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX,
2900 GENCONF_SOC_DEVICE_MUX_NFC_EN |
2901 GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST |
2902 GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST |
c13bf589
HM		 2903 GENCONF_SOC_DEVICE_MUX_NFC_INT_EN |
2904 GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN);
02f26ecf 2905
88aa3bbf
TP		 2906 regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL,
2907 GENCONF_CLK_GATING_CTRL_ND_GATE,
2908 GENCONF_CLK_GATING_CTRL_ND_GATE);
02f26ecf
MR		 2909 }
2910
2911 /* Configure the DMA if appropriate */
2912 if (!nfc->caps->is_nfcv2)
2913 marvell_nfc_init_dma(nfc);
2914
bd9c3f9b 2915 marvell_nfc_reset(nfc);
02f26ecf
MR		 2916
2917 return 0;
2918}
2919
2920static int marvell_nfc_probe(struct platform_device *pdev)
2921{
2922 struct device *dev = &pdev->dev;
02f26ecf
MR		 2923 struct marvell_nfc *nfc;
2924 int ret;
2925 int irq;
2926
2927 nfc = devm_kzalloc(&pdev->dev, sizeof(struct marvell_nfc),
2928 GFP_KERNEL);
2929 if (!nfc)
2930 return -ENOMEM;
2931
2932 nfc->dev = dev;
7da45139 2933 nand_controller_init(&nfc->controller);
8831e48b 2934 nfc->controller.ops = &marvell_nand_controller_ops;
02f26ecf
MR		 2935 INIT_LIST_HEAD(&nfc->chips);
2936
5dcc9976 2937 nfc->regs = devm_platform_ioremap_resource(pdev, 0);
02f26ecf
MR		 2938 if (IS_ERR(nfc->regs))
2939 return PTR_ERR(nfc->regs);
2940
2941 irq = platform_get_irq(pdev, 0);
aab478ca 2942 if (irq < 0)
02f26ecf 2943 return irq;
02f26ecf 2944
6b6de654 2945 nfc->core_clk = devm_clk_get(&pdev->dev, "core");
961ba15c
GC		 2946
2947 /* Managed the legacy case (when the first clock was not named) */
6b6de654
BB		 2948 if (nfc->core_clk == ERR_PTR(-ENOENT))
2949 nfc->core_clk = devm_clk_get(&pdev->dev, NULL);
961ba15c 2950
6b6de654
BB		 2951 if (IS_ERR(nfc->core_clk))
2952 return PTR_ERR(nfc->core_clk);
02f26ecf 2953
6b6de654 2954 ret = clk_prepare_enable(nfc->core_clk);
02f26ecf
MR		 2955 if (ret)
2956 return ret;
2957
961ba15c 2958 nfc->reg_clk = devm_clk_get(&pdev->dev, "reg");
f9e64d61
DM		 2959 if (IS_ERR(nfc->reg_clk)) {
2960 if (PTR_ERR(nfc->reg_clk) != -ENOENT) {
961ba15c 2961 ret = PTR_ERR(nfc->reg_clk);
6b6de654 2962 goto unprepare_core_clk;
961ba15c 2963 }
f9e64d61
DM		 2964
2965 nfc->reg_clk = NULL;
961ba15c
GC		 2966 }
2967
f9e64d61
DM		 2968 ret = clk_prepare_enable(nfc->reg_clk);
2969 if (ret)
2970 goto unprepare_core_clk;
2971
02f26ecf
MR		 2972 marvell_nfc_disable_int(nfc, NDCR_ALL_INT);
2973 marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
2974 ret = devm_request_irq(dev, irq, marvell_nfc_isr,
2975 0, "marvell-nfc", nfc);
2976 if (ret)
961ba15c 2977 goto unprepare_reg_clk;
02f26ecf
MR		 2978
2979 /* Get NAND controller capabilities */
2980 if (pdev->id_entry)
2981 nfc->caps = (void *)pdev->id_entry->driver_data;
2982 else
2983 nfc->caps = of_device_get_match_data(&pdev->dev);
2984
2985 if (!nfc->caps) {
2986 dev_err(dev, "Could not retrieve NFC caps\n");
2987 ret = -EINVAL;
961ba15c 2988 goto unprepare_reg_clk;
02f26ecf
MR		 2989 }
2990
2991 /* Init the controller and then probe the chips */
2992 ret = marvell_nfc_init(nfc);
2993 if (ret)
961ba15c 2994 goto unprepare_reg_clk;
02f26ecf
MR		 2995
2996 platform_set_drvdata(pdev, nfc);
2997
2998 ret = marvell_nand_chips_init(dev, nfc);
2999 if (ret)
aafe30ba 3000 goto release_dma;
02f26ecf
MR		 3001
3002 return 0;
3003
aafe30ba
PU		 3004release_dma:
3005 if (nfc->use_dma)
3006 dma_release_channel(nfc->dma_chan);
961ba15c
GC		 3007unprepare_reg_clk:
3008 clk_disable_unprepare(nfc->reg_clk);
6b6de654
BB		 3009unprepare_core_clk:
3010 clk_disable_unprepare(nfc->core_clk);
02f26ecf
MR		 3011
3012 return ret;
3013}
3014
ec185b18 3015static void marvell_nfc_remove(struct platform_device *pdev)
02f26ecf
MR		 3016{
3017 struct marvell_nfc *nfc = platform_get_drvdata(pdev);
3018
3019 marvell_nand_chips_cleanup(nfc);
3020
3021 if (nfc->use_dma) {
3022 dmaengine_terminate_all(nfc->dma_chan);
3023 dma_release_channel(nfc->dma_chan);
3024 }
3025
961ba15c 3026 clk_disable_unprepare(nfc->reg_clk);
6b6de654 3027 clk_disable_unprepare(nfc->core_clk);
02f26ecf
MR		 3028}
3029
bd9c3f9b
DM		 3030static int __maybe_unused marvell_nfc_suspend(struct device *dev)
3031{
3032 struct marvell_nfc *nfc = dev_get_drvdata(dev);
3033 struct marvell_nand_chip *chip;
3034
3035 list_for_each_entry(chip, &nfc->chips, node)
3036 marvell_nfc_wait_ndrun(&chip->chip);
3037
3038 clk_disable_unprepare(nfc->reg_clk);
3039 clk_disable_unprepare(nfc->core_clk);
3040
3041 return 0;
3042}
3043
3044static int __maybe_unused marvell_nfc_resume(struct device *dev)
3045{
3046 struct marvell_nfc *nfc = dev_get_drvdata(dev);
3047 int ret;
3048
3049 ret = clk_prepare_enable(nfc->core_clk);
3050 if (ret < 0)
3051 return ret;
3052
f9e64d61 3053 ret = clk_prepare_enable(nfc->reg_clk);
ae94c495
YY		 3054 if (ret < 0) {
3055 clk_disable_unprepare(nfc->core_clk);
f9e64d61 3056 return ret;
ae94c495 3057 }
bd9c3f9b
DM		 3058
3059 /*
3060 * Reset nfc->selected_chip so the next command will cause the timing
2e16dc73 3061 * registers to be restored in marvell_nfc_select_target().
bd9c3f9b
DM		 3062 */
3063 nfc->selected_chip = NULL;
3064
3065 /* Reset registers that have lost their contents */
3066 marvell_nfc_reset(nfc);
3067
3068 return 0;
3069}
3070
3071static const struct dev_pm_ops marvell_nfc_pm_ops = {
3072 SET_SYSTEM_SLEEP_PM_OPS(marvell_nfc_suspend, marvell_nfc_resume)
3073};
3074
02f26ecf
MR		 3075static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = {
3076 .max_cs_nb = 4,
3077 .max_rb_nb = 2,
3078 .need_system_controller = true,
3079 .is_nfcv2 = true,
3080};
3081
72b9a3fc
CP		 3082static const struct marvell_nfc_caps marvell_ac5_caps = {
3083 .max_cs_nb = 2,
3084 .max_rb_nb = 1,
3085 .is_nfcv2 = true,
3086 .max_mode_number = 3,
3087};
3088
02f26ecf
MR		 3089static const struct marvell_nfc_caps marvell_armada370_nfc_caps = {
3090 .max_cs_nb = 4,
3091 .max_rb_nb = 2,
3092 .is_nfcv2 = true,
3093};
3094
3095static const struct marvell_nfc_caps marvell_pxa3xx_nfc_caps = {
3096 .max_cs_nb = 2,
3097 .max_rb_nb = 1,
3098 .use_dma = true,
3099};
3100
3101static const struct marvell_nfc_caps marvell_armada_8k_nfc_legacy_caps = {
3102 .max_cs_nb = 4,
3103 .max_rb_nb = 2,
3104 .need_system_controller = true,
3105 .legacy_of_bindings = true,
3106 .is_nfcv2 = true,
3107};
3108
3109static const struct marvell_nfc_caps marvell_armada370_nfc_legacy_caps = {
3110 .max_cs_nb = 4,
3111 .max_rb_nb = 2,
3112 .legacy_of_bindings = true,
3113 .is_nfcv2 = true,
3114};
3115
3116static const struct marvell_nfc_caps marvell_pxa3xx_nfc_legacy_caps = {
3117 .max_cs_nb = 2,
3118 .max_rb_nb = 1,
3119 .legacy_of_bindings = true,
3120 .use_dma = true,
3121};
3122
3123static const struct platform_device_id marvell_nfc_platform_ids[] = {
3124 {
3125 .name = "pxa3xx-nand",
3126 .driver_data = (kernel_ulong_t)&marvell_pxa3xx_nfc_legacy_caps,
3127 },
3128 { /* sentinel */ },
3129};
3130MODULE_DEVICE_TABLE(platform, marvell_nfc_platform_ids);
3131
3132static const struct of_device_id marvell_nfc_of_ids[] = {
3133 {
3134 .compatible = "marvell,armada-8k-nand-controller",
3135 .data = &marvell_armada_8k_nfc_caps,
3136 },
72b9a3fc
CP		 3137 {
3138 .compatible = "marvell,ac5-nand-controller",
3139 .data = &marvell_ac5_caps,
3140 },
02f26ecf
MR		 3141 {
3142 .compatible = "marvell,armada370-nand-controller",
3143 .data = &marvell_armada370_nfc_caps,
3144 },
3145 {
3146 .compatible = "marvell,pxa3xx-nand-controller",
3147 .data = &marvell_pxa3xx_nfc_caps,
3148 },
3149 /* Support for old/deprecated bindings: */
3150 {
3151 .compatible = "marvell,armada-8k-nand",
3152 .data = &marvell_armada_8k_nfc_legacy_caps,
3153 },
3154 {
3155 .compatible = "marvell,armada370-nand",
3156 .data = &marvell_armada370_nfc_legacy_caps,
3157 },
3158 {
3159 .compatible = "marvell,pxa3xx-nand",
3160 .data = &marvell_pxa3xx_nfc_legacy_caps,
3161 },
3162 { /* sentinel */ },
3163};
3164MODULE_DEVICE_TABLE(of, marvell_nfc_of_ids);
3165
3166static struct platform_driver marvell_nfc_driver = {
3167 .driver = {
3168 .name = "marvell-nfc",
3169 .of_match_table = marvell_nfc_of_ids,
bd9c3f9b 3170 .pm = &marvell_nfc_pm_ops,
02f26ecf
MR		 3171 },
3172 .id_table = marvell_nfc_platform_ids,
3173 .probe = marvell_nfc_probe,
ec185b18 3174 .remove_new = marvell_nfc_remove,
02f26ecf
MR		 3175};
3176module_platform_driver(marvell_nfc_driver);
3177
3178MODULE_LICENSE("GPL");
3179MODULE_DESCRIPTION("Marvell NAND controller driver");
Linux 6.x block layer and io_uring tree(s)