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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156
[linux-2.6-block.git] / drivers / mtd / nand / raw / hisi504_nand.c
CommitLineData
54f531f6
ZW		 1/*
2 * Hisilicon NAND Flash controller driver
3 *
4 * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
5 * http://www.hisilicon.com
6 *
7 * Author: Zhou Wang <wangzhou.bry@gmail.com>
8 * The initial developer of the original code is Zhiyong Cai
9 * <caizhiyong@huawei.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21#include <linux/of.h>
54f531f6
ZW		 22#include <linux/mtd/mtd.h>
23#include <linux/sizes.h>
24#include <linux/clk.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
d4092d76 29#include <linux/mtd/rawnand.h>
54f531f6
ZW		 30#include <linux/dma-mapping.h>
31#include <linux/platform_device.h>
32#include <linux/mtd/partitions.h>
33
34#define HINFC504_MAX_CHIP (4)
35#define HINFC504_W_LATCH (5)
36#define HINFC504_R_LATCH (7)
37#define HINFC504_RW_LATCH (3)
38
39#define HINFC504_NFC_TIMEOUT (2 * HZ)
40#define HINFC504_NFC_PM_TIMEOUT (1 * HZ)
41#define HINFC504_NFC_DMA_TIMEOUT (5 * HZ)
42#define HINFC504_CHIP_DELAY (25)
43
44#define HINFC504_REG_BASE_ADDRESS_LEN (0x100)
45#define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128)
46
47#define HINFC504_ADDR_CYCLE_MASK 0x4
48
49#define HINFC504_CON 0x00
50#define HINFC504_CON_OP_MODE_NORMAL BIT(0)
51#define HINFC504_CON_PAGEISZE_SHIFT (1)
52#define HINFC504_CON_PAGESIZE_MASK (0x07)
53#define HINFC504_CON_BUS_WIDTH BIT(4)
54#define HINFC504_CON_READY_BUSY_SEL BIT(8)
55#define HINFC504_CON_ECCTYPE_SHIFT (9)
56#define HINFC504_CON_ECCTYPE_MASK (0x07)
57
58#define HINFC504_PWIDTH 0x04
59#define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
60 ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
61
62#define HINFC504_CMD 0x0C
63#define HINFC504_ADDRL 0x10
64#define HINFC504_ADDRH 0x14
65#define HINFC504_DATA_NUM 0x18
66
67#define HINFC504_OP 0x1C
68#define HINFC504_OP_READ_DATA_EN BIT(1)
69#define HINFC504_OP_WAIT_READY_EN BIT(2)
70#define HINFC504_OP_CMD2_EN BIT(3)
71#define HINFC504_OP_WRITE_DATA_EN BIT(4)
72#define HINFC504_OP_ADDR_EN BIT(5)
73#define HINFC504_OP_CMD1_EN BIT(6)
74#define HINFC504_OP_NF_CS_SHIFT (7)
75#define HINFC504_OP_NF_CS_MASK (3)
76#define HINFC504_OP_ADDR_CYCLE_SHIFT (9)
77#define HINFC504_OP_ADDR_CYCLE_MASK (7)
78
79#define HINFC504_STATUS 0x20
80#define HINFC504_READY BIT(0)
81
82#define HINFC504_INTEN 0x24
83#define HINFC504_INTEN_DMA BIT(9)
84#define HINFC504_INTEN_UE BIT(6)
85#define HINFC504_INTEN_CE BIT(5)
86
87#define HINFC504_INTS 0x28
88#define HINFC504_INTS_DMA BIT(9)
89#define HINFC504_INTS_UE BIT(6)
90#define HINFC504_INTS_CE BIT(5)
91
92#define HINFC504_INTCLR 0x2C
93#define HINFC504_INTCLR_DMA BIT(9)
94#define HINFC504_INTCLR_UE BIT(6)
95#define HINFC504_INTCLR_CE BIT(5)
96
97#define HINFC504_ECC_STATUS 0x5C
98#define HINFC504_ECC_16_BIT_SHIFT 12
99
100#define HINFC504_DMA_CTRL 0x60
101#define HINFC504_DMA_CTRL_DMA_START BIT(0)
102#define HINFC504_DMA_CTRL_WE BIT(1)
103#define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2)
104#define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3)
105#define HINFC504_DMA_CTRL_BURST4_EN BIT(4)
106#define HINFC504_DMA_CTRL_BURST8_EN BIT(5)
107#define HINFC504_DMA_CTRL_BURST16_EN BIT(6)
108#define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7)
109#define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1)
110#define HINFC504_DMA_CTRL_CS_SHIFT (8)
111#define HINFC504_DMA_CTRL_CS_MASK (0x03)
112
113#define HINFC504_DMA_ADDR_DATA 0x64
114#define HINFC504_DMA_ADDR_OOB 0x68
115
116#define HINFC504_DMA_LEN 0x6C
117#define HINFC504_DMA_LEN_OOB_SHIFT (16)
118#define HINFC504_DMA_LEN_OOB_MASK (0xFFF)
119
120#define HINFC504_DMA_PARA 0x70
121#define HINFC504_DMA_PARA_DATA_RW_EN BIT(0)
122#define HINFC504_DMA_PARA_OOB_RW_EN BIT(1)
123#define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2)
124#define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3)
125#define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4)
126#define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5)
127
128#define HINFC_VERSION 0x74
129#define HINFC504_LOG_READ_ADDR 0x7C
130#define HINFC504_LOG_READ_LEN 0x80
131
132#define HINFC504_NANDINFO_LEN 0x10
133
134struct hinfc_host {
135 struct nand_chip chip;
54f531f6
ZW		 136 struct device *dev;
137 void __iomem *iobase;
138 void __iomem *mmio;
139 struct completion cmd_complete;
140 unsigned int offset;
141 unsigned int command;
142 int chipselect;
143 unsigned int addr_cycle;
144 u32 addr_value[2];
145 u32 cache_addr_value[2];
146 char *buffer;
147 dma_addr_t dma_buffer;
148 dma_addr_t dma_oob;
149 int version;
150 unsigned int irq_status; /* interrupt status */
151};
152
153static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
154{
155 return readl(host->iobase + reg);
156}
157
158static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
159 unsigned int reg)
160{
161 writel(value, host->iobase + reg);
162}
163
164static void wait_controller_finished(struct hinfc_host *host)
165{
166 unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT;
167 int val;
168
169 while (time_before(jiffies, timeout)) {
170 val = hinfc_read(host, HINFC504_STATUS);
171 if (host->command == NAND_CMD_ERASE2) {
172 /* nfc is ready */
173 while (!(val & HINFC504_READY)) {
174 usleep_range(500, 1000);
175 val = hinfc_read(host, HINFC504_STATUS);
176 }
177 return;
178 }
179
180 if (val & HINFC504_READY)
181 return;
182 }
183
184 /* wait cmd timeout */
185 dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
186}
187
188static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
189{
fa100163
BB		 190 struct nand_chip *chip = &host->chip;
191 struct mtd_info *mtd = nand_to_mtd(chip);
54f531f6
ZW		 192 unsigned long val;
193 int ret;
194
195 hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
196 hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
197
198 if (chip->ecc.mode == NAND_ECC_NONE) {
199 hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
200 << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN);
201
202 hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
203 | HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA);
204 } else {
205 if (host->command == NAND_CMD_READOOB)
206 hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
207 | HINFC504_DMA_PARA_OOB_EDC_EN
208 | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
209 else
210 hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
211 | HINFC504_DMA_PARA_OOB_RW_EN
212 | HINFC504_DMA_PARA_DATA_EDC_EN
213 | HINFC504_DMA_PARA_OOB_EDC_EN
214 | HINFC504_DMA_PARA_DATA_ECC_EN
215 | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA);
216
217 }
218
219 val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN
220 | HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN
221 | HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN
222 | ((host->addr_cycle == 4 ? 1 : 0)
223 << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT)
224 | ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
225 << HINFC504_DMA_CTRL_CS_SHIFT));
226
227 if (todev)
228 val |= HINFC504_DMA_CTRL_WE;
229
230 init_completion(&host->cmd_complete);
231
232 hinfc_write(host, val, HINFC504_DMA_CTRL);
233 ret = wait_for_completion_timeout(&host->cmd_complete,
234 HINFC504_NFC_DMA_TIMEOUT);
235
236 if (!ret) {
237 dev_err(host->dev, "DMA operation(irq) timeout!\n");
238 /* sanity check */
239 val = hinfc_read(host, HINFC504_DMA_CTRL);
240 if (!(val & HINFC504_DMA_CTRL_DMA_START))
241 dev_err(host->dev, "DMA is already done but without irq ACK!\n");
242 else
243 dev_err(host->dev, "DMA is really timeout!\n");
244 }
245}
246
247static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
248{
249 host->addr_value[0] &= 0xffff0000;
250
251 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
252 hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
253 hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
254 HINFC504_CMD);
255
256 hisi_nfc_dma_transfer(host, 1);
257
258 return 0;
259}
260
261static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
262{
fa100163 263 struct mtd_info *mtd = nand_to_mtd(&host->chip);
54f531f6
ZW		 264
265 if ((host->addr_value[0] == host->cache_addr_value[0]) &&
266 (host->addr_value[1] == host->cache_addr_value[1]))
267 return 0;
268
269 host->addr_value[0] &= 0xffff0000;
270
271 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
272 hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
273 hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
274 HINFC504_CMD);
275
276 hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
277 hinfc_write(host, mtd->writesize + mtd->oobsize,
278 HINFC504_LOG_READ_LEN);
279
280 hisi_nfc_dma_transfer(host, 0);
281
282 host->cache_addr_value[0] = host->addr_value[0];
283 host->cache_addr_value[1] = host->addr_value[1];
284
285 return 0;
286}
287
288static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
289{
290 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
291 hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
292 HINFC504_CMD);
293
294 hinfc_write(host, HINFC504_OP_WAIT_READY_EN
295 | HINFC504_OP_CMD2_EN
296 | HINFC504_OP_CMD1_EN
297 | HINFC504_OP_ADDR_EN
298 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
299 << HINFC504_OP_NF_CS_SHIFT)
300 | ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
301 << HINFC504_OP_ADDR_CYCLE_SHIFT),
302 HINFC504_OP);
303
304 wait_controller_finished(host);
305
306 return 0;
307}
308
309static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
310{
311 hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
312 hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
313 hinfc_write(host, 0, HINFC504_ADDRL);
314
315 hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
316 | HINFC504_OP_READ_DATA_EN
317 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
318 << HINFC504_OP_NF_CS_SHIFT)
319 | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP);
320
321 wait_controller_finished(host);
322
323 return 0;
324}
325
326static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
327{
328 hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
329 hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
330 hinfc_write(host, HINFC504_OP_CMD1_EN
331 | HINFC504_OP_READ_DATA_EN
332 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
333 << HINFC504_OP_NF_CS_SHIFT),
334 HINFC504_OP);
335
336 wait_controller_finished(host);
337
338 return 0;
339}
340
341static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
342{
343 hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
344
345 hinfc_write(host, HINFC504_OP_CMD1_EN
346 | ((chipselect & HINFC504_OP_NF_CS_MASK)
347 << HINFC504_OP_NF_CS_SHIFT)
348 | HINFC504_OP_WAIT_READY_EN,
349 HINFC504_OP);
350
351 wait_controller_finished(host);
352
353 return 0;
354}
355
758b56f5 356static void hisi_nfc_select_chip(struct nand_chip *chip, int chipselect)
54f531f6 357{
d699ed25 358 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 359
360 if (chipselect < 0)
361 return;
362
363 host->chipselect = chipselect;
364}
365
7e534323 366static uint8_t hisi_nfc_read_byte(struct nand_chip *chip)
54f531f6 367{
d699ed25 368 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 369
370 if (host->command == NAND_CMD_STATUS)
371 return *(uint8_t *)(host->mmio);
372
373 host->offset++;
374
375 if (host->command == NAND_CMD_READID)
376 return *(uint8_t *)(host->mmio + host->offset - 1);
377
378 return *(uint8_t *)(host->buffer + host->offset - 1);
379}
380
54f531f6 381static void
c0739d85 382hisi_nfc_write_buf(struct nand_chip *chip, const uint8_t *buf, int len)
54f531f6 383{
d699ed25 384 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 385
386 memcpy(host->buffer + host->offset, buf, len);
387 host->offset += len;
388}
389
7e534323 390static void hisi_nfc_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
54f531f6 391{
d699ed25 392 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 393
394 memcpy(buf, host->buffer + host->offset, len);
395 host->offset += len;
396}
397
398static void set_addr(struct mtd_info *mtd, int column, int page_addr)
399{
4bd4ebcc 400 struct nand_chip *chip = mtd_to_nand(mtd);
d699ed25 401 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 402 unsigned int command = host->command;
403
404 host->addr_cycle = 0;
405 host->addr_value[0] = 0;
406 host->addr_value[1] = 0;
407
408 /* Serially input address */
409 if (column != -1) {
410 /* Adjust columns for 16 bit buswidth */
411 if (chip->options & NAND_BUSWIDTH_16 &&
412 !nand_opcode_8bits(command))
413 column >>= 1;
414
415 host->addr_value[0] = column & 0xffff;
416 host->addr_cycle = 2;
417 }
418 if (page_addr != -1) {
419 host->addr_value[0] |= (page_addr & 0xffff)
420 << (host->addr_cycle * 8);
421 host->addr_cycle += 2;
14157f86 422 if (chip->options & NAND_ROW_ADDR_3) {
54f531f6
ZW		 423 host->addr_cycle += 1;
424 if (host->command == NAND_CMD_ERASE1)
425 host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
426 else
427 host->addr_value[1] |= ((page_addr >> 16) & 0xff);
428 }
429 }
430}
431
5295cf2e
BB		 432static void hisi_nfc_cmdfunc(struct nand_chip *chip, unsigned command,
433 int column, int page_addr)
54f531f6 434{
5295cf2e 435 struct mtd_info *mtd = nand_to_mtd(chip);
d699ed25 436 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 437 int is_cache_invalid = 1;
438 unsigned int flag = 0;
439
440 host->command = command;
441
442 switch (command) {
443 case NAND_CMD_READ0:
444 case NAND_CMD_READOOB:
445 if (command == NAND_CMD_READ0)
446 host->offset = column;
447 else
448 host->offset = column + mtd->writesize;
449
450 is_cache_invalid = 0;
451 set_addr(mtd, column, page_addr);
452 hisi_nfc_send_cmd_readstart(host);
453 break;
454
455 case NAND_CMD_SEQIN:
456 host->offset = column;
457 set_addr(mtd, column, page_addr);
458 break;
459
460 case NAND_CMD_ERASE1:
461 set_addr(mtd, column, page_addr);
462 break;
463
464 case NAND_CMD_PAGEPROG:
465 hisi_nfc_send_cmd_pageprog(host);
466 break;
467
468 case NAND_CMD_ERASE2:
469 hisi_nfc_send_cmd_erase(host);
470 break;
471
472 case NAND_CMD_READID:
473 host->offset = column;
474 memset(host->mmio, 0, 0x10);
475 hisi_nfc_send_cmd_readid(host);
476 break;
477
478 case NAND_CMD_STATUS:
479 flag = hinfc_read(host, HINFC504_CON);
480 if (chip->ecc.mode == NAND_ECC_HW)
481 hinfc_write(host,
dd58d38f 482 flag & ~(HINFC504_CON_ECCTYPE_MASK <<
54f531f6
ZW		 483 HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON);
484
485 host->offset = 0;
486 memset(host->mmio, 0, 0x10);
487 hisi_nfc_send_cmd_status(host);
488 hinfc_write(host, flag, HINFC504_CON);
489 break;
490
491 case NAND_CMD_RESET:
492 hisi_nfc_send_cmd_reset(host, host->chipselect);
493 break;
494
495 default:
496 dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
497 command, column, page_addr);
498 }
499
500 if (is_cache_invalid) {
501 host->cache_addr_value[0] = ~0;
502 host->cache_addr_value[1] = ~0;
503 }
504}
505
506static irqreturn_t hinfc_irq_handle(int irq, void *devid)
507{
508 struct hinfc_host *host = devid;
509 unsigned int flag;
510
511 flag = hinfc_read(host, HINFC504_INTS);
512 /* store interrupts state */
513 host->irq_status |= flag;
514
515 if (flag & HINFC504_INTS_DMA) {
516 hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
517 complete(&host->cmd_complete);
518 } else if (flag & HINFC504_INTS_CE) {
519 hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
520 } else if (flag & HINFC504_INTS_UE) {
521 hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
522 }
523
524 return IRQ_HANDLED;
525}
526
b9761687
BB		 527static int hisi_nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
528 int oob_required, int page)
54f531f6 529{
b9761687 530 struct mtd_info *mtd = nand_to_mtd(chip);
d699ed25 531 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6
ZW		 532 int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc;
533 int stat_1, stat_2;
534
25f815f6 535 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
716bbbab 536 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
54f531f6
ZW		 537
538 /* errors which can not be corrected by ECC */
539 if (host->irq_status & HINFC504_INTS_UE) {
540 mtd->ecc_stats.failed++;
541 } else if (host->irq_status & HINFC504_INTS_CE) {
542 /* TODO: need add other ECC modes! */
543 switch (chip->ecc.strength) {
544 case 16:
545 status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
546 HINFC504_ECC_16_BIT_SHIFT & 0x0fff;
547 stat_2 = status_ecc & 0x3f;
548 stat_1 = status_ecc >> 6 & 0x3f;
549 stat = stat_1 + stat_2;
550 stat_max = max_t(int, stat_1, stat_2);
551 }
552 mtd->ecc_stats.corrected += stat;
553 max_bitflips = max_t(int, max_bitflips, stat_max);
554 }
555 host->irq_status = 0;
556
557 return max_bitflips;
558}
559
b9761687 560static int hisi_nand_read_oob(struct nand_chip *chip, int page)
54f531f6 561{
b9761687 562 struct mtd_info *mtd = nand_to_mtd(chip);
d699ed25 563 struct hinfc_host *host = nand_get_controller_data(chip);
54f531f6 564
97d90da8 565 nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
54f531f6
ZW		 566
567 if (host->irq_status & HINFC504_INTS_UE) {
568 host->irq_status = 0;
569 return -EBADMSG;
570 }
571
572 host->irq_status = 0;
573 return 0;
574}
575
767eb6fb
BB		 576static int hisi_nand_write_page_hwecc(struct nand_chip *chip,
577 const uint8_t *buf, int oob_required,
578 int page)
54f531f6 579{
767eb6fb
BB		 580 struct mtd_info *mtd = nand_to_mtd(chip);
581
25f815f6 582 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
54f531f6 583 if (oob_required)
716bbbab 584 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
54f531f6 585
25f815f6 586 return nand_prog_page_end_op(chip);
54f531f6
ZW		 587}
588
589static void hisi_nfc_host_init(struct hinfc_host *host)
590{
591 struct nand_chip *chip = &host->chip;
592 unsigned int flag = 0;
593
594 host->version = hinfc_read(host, HINFC_VERSION);
595 host->addr_cycle = 0;
596 host->addr_value[0] = 0;
597 host->addr_value[1] = 0;
598 host->cache_addr_value[0] = ~0;
599 host->cache_addr_value[1] = ~0;
600 host->chipselect = 0;
601
602 /* default page size: 2K, ecc_none. need modify */
603 flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL
604 | ((0x001 & HINFC504_CON_PAGESIZE_MASK)
605 << HINFC504_CON_PAGEISZE_SHIFT)
606 | ((0x0 & HINFC504_CON_ECCTYPE_MASK)
607 << HINFC504_CON_ECCTYPE_SHIFT)
608 | ((chip->options & NAND_BUSWIDTH_16) ?
609 HINFC504_CON_BUS_WIDTH : 0);
610 hinfc_write(host, flag, HINFC504_CON);
611
612 memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
613
614 hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
615 HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
616
617 /* enable DMA irq */
618 hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
619}
620
2ca9ec9a
BB		 621static int hisi_ooblayout_ecc(struct mtd_info *mtd, int section,
622 struct mtd_oob_region *oobregion)
623{
624 /* FIXME: add ECC bytes position */
625 return -ENOTSUPP;
626}
627
628static int hisi_ooblayout_free(struct mtd_info *mtd, int section,
629 struct mtd_oob_region *oobregion)
630{
631 if (section)
632 return -ERANGE;
633
634 oobregion->offset = 2;
635 oobregion->length = 6;
636
637 return 0;
638}
639
640static const struct mtd_ooblayout_ops hisi_ooblayout_ops = {
641 .ecc = hisi_ooblayout_ecc,
642 .free = hisi_ooblayout_free,
54f531f6
ZW		 643};
644
645static int hisi_nfc_ecc_probe(struct hinfc_host *host)
646{
647 unsigned int flag;
648 int size, strength, ecc_bits;
649 struct device *dev = host->dev;
650 struct nand_chip *chip = &host->chip;
fa100163 651 struct mtd_info *mtd = nand_to_mtd(chip);
54f531f6 652
2d01922c
BB		 653 size = chip->ecc.size;
654 strength = chip->ecc.strength;
54f531f6
ZW		 655 if (size != 1024) {
656 dev_err(dev, "error ecc size: %d\n", size);
657 return -EINVAL;
658 }
659
660 if ((size == 1024) && ((strength != 8) && (strength != 16) &&
661 (strength != 24) && (strength != 40))) {
662 dev_err(dev, "ecc size and strength do not match\n");
663 return -EINVAL;
664 }
665
666 chip->ecc.size = size;
667 chip->ecc.strength = strength;
668
669 chip->ecc.read_page = hisi_nand_read_page_hwecc;
670 chip->ecc.read_oob = hisi_nand_read_oob;
671 chip->ecc.write_page = hisi_nand_write_page_hwecc;
672
673 switch (chip->ecc.strength) {
674 case 16:
675 ecc_bits = 6;
676 if (mtd->writesize == 2048)
2ca9ec9a 677 mtd_set_ooblayout(mtd, &hisi_ooblayout_ops);
54f531f6
ZW		 678
679 /* TODO: add more page size support */
680 break;
681
682 /* TODO: add more ecc strength support */
683 default:
684 dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
685 return -EINVAL;
686 }
687
688 flag = hinfc_read(host, HINFC504_CON);
689 /* add ecc type configure */
690 flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK)
691 << HINFC504_CON_ECCTYPE_SHIFT);
692 hinfc_write(host, flag, HINFC504_CON);
693
694 /* enable ecc irq */
695 flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
696 hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
697 HINFC504_INTEN);
698
699 return 0;
700}
701
07c1a4b3
MR		 702static int hisi_nfc_attach_chip(struct nand_chip *chip)
703{
704 struct mtd_info *mtd = nand_to_mtd(chip);
705 struct hinfc_host *host = nand_get_controller_data(chip);
706 int flag;
707
708 host->buffer = dmam_alloc_coherent(host->dev,
709 mtd->writesize + mtd->oobsize,
710 &host->dma_buffer, GFP_KERNEL);
711 if (!host->buffer)
712 return -ENOMEM;
713
714 host->dma_oob = host->dma_buffer + mtd->writesize;
715 memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
716
717 flag = hinfc_read(host, HINFC504_CON);
718 flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT);
719 switch (mtd->writesize) {
720 case 2048:
721 flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT);
722 break;
723 /*
724 * TODO: add more pagesize support,
725 * default pagesize has been set in hisi_nfc_host_init
726 */
727 default:
728 dev_err(host->dev, "NON-2KB page size nand flash\n");
729 return -EINVAL;
730 }
731 hinfc_write(host, flag, HINFC504_CON);
732
733 if (chip->ecc.mode == NAND_ECC_HW)
734 hisi_nfc_ecc_probe(host);
735
736 return 0;
737}
738
739static const struct nand_controller_ops hisi_nfc_controller_ops = {
740 .attach_chip = hisi_nfc_attach_chip,
741};
742
54f531f6
ZW		 743static int hisi_nfc_probe(struct platform_device *pdev)
744{
07c1a4b3 745 int ret = 0, irq, max_chips = HINFC504_MAX_CHIP;
54f531f6
ZW		 746 struct device *dev = &pdev->dev;
747 struct hinfc_host *host;
748 struct nand_chip *chip;
749 struct mtd_info *mtd;
750 struct resource *res;
751 struct device_node *np = dev->of_node;
54f531f6
ZW		 752
753 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
754 if (!host)
755 return -ENOMEM;
756 host->dev = dev;
757
758 platform_set_drvdata(pdev, host);
759 chip = &host->chip;
fa100163 760 mtd = nand_to_mtd(chip);
54f531f6
ZW		 761
762 irq = platform_get_irq(pdev, 0);
763 if (irq < 0) {
764 dev_err(dev, "no IRQ resource defined\n");
9326dc75 765 return -ENXIO;
54f531f6
ZW		 766 }
767
768 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769 host->iobase = devm_ioremap_resource(dev, res);
9326dc75
MR		 770 if (IS_ERR(host->iobase))
771 return PTR_ERR(host->iobase);
54f531f6
ZW		 772
773 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
774 host->mmio = devm_ioremap_resource(dev, res);
775 if (IS_ERR(host->mmio)) {
54f531f6 776 dev_err(dev, "devm_ioremap_resource[1] fail\n");
9326dc75 777 return PTR_ERR(host->mmio);
54f531f6
ZW		 778 }
779
54f531f6
ZW		 780 mtd->name = "hisi_nand";
781 mtd->dev.parent = &pdev->dev;
782
d699ed25 783 nand_set_controller_data(chip, host);
a61ae81a 784 nand_set_flash_node(chip, np);
bf6065c6 785 chip->legacy.cmdfunc = hisi_nfc_cmdfunc;
7d6c37e9 786 chip->legacy.select_chip = hisi_nfc_select_chip;
716bbbab
BB		 787 chip->legacy.read_byte = hisi_nfc_read_byte;
788 chip->legacy.write_buf = hisi_nfc_write_buf;
789 chip->legacy.read_buf = hisi_nfc_read_buf;
3cece3ab 790 chip->legacy.chip_delay = HINFC504_CHIP_DELAY;
45240367
BB		 791 chip->legacy.set_features = nand_get_set_features_notsupp;
792 chip->legacy.get_features = nand_get_set_features_notsupp;
54f531f6 793
54f531f6
ZW		 794 hisi_nfc_host_init(host);
795
d8bf368d 796 ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
54f531f6
ZW		 797 if (ret) {
798 dev_err(dev, "failed to request IRQ\n");
9326dc75 799 return ret;
54f531f6
ZW		 800 }
801
7b6a9b28 802 chip->legacy.dummy_controller.ops = &hisi_nfc_controller_ops;
00ad378f 803 ret = nand_scan(chip, max_chips);
c8cae355 804 if (ret)
9326dc75 805 return ret;
54f531f6 806
a61ae81a 807 ret = mtd_device_register(mtd, NULL, 0);
54f531f6
ZW		 808 if (ret) {
809 dev_err(dev, "Err MTD partition=%d\n", ret);
6f533c46 810 nand_cleanup(chip);
9326dc75 811 return ret;
54f531f6
ZW		 812 }
813
814 return 0;
54f531f6
ZW		 815}
816
817static int hisi_nfc_remove(struct platform_device *pdev)
818{
819 struct hinfc_host *host = platform_get_drvdata(pdev);
54f531f6 820
59ac276f 821 nand_release(&host->chip);
54f531f6
ZW		 822
823 return 0;
824}
825
826#ifdef CONFIG_PM_SLEEP
827static int hisi_nfc_suspend(struct device *dev)
828{
829 struct hinfc_host *host = dev_get_drvdata(dev);
830 unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT;
831
832 while (time_before(jiffies, timeout)) {
833 if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
834 (hinfc_read(host, HINFC504_DMA_CTRL) &
835 HINFC504_DMA_CTRL_DMA_START)) {
836 cond_resched();
837 return 0;
838 }
839 }
840
841 dev_err(host->dev, "nand controller suspend timeout.\n");
842
843 return -EAGAIN;
844}
845
846static int hisi_nfc_resume(struct device *dev)
847{
848 int cs;
849 struct hinfc_host *host = dev_get_drvdata(dev);
850 struct nand_chip *chip = &host->chip;
851
32813e28 852 for (cs = 0; cs < nanddev_ntargets(&chip->base); cs++)
54f531f6
ZW		 853 hisi_nfc_send_cmd_reset(host, cs);
854 hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
855 HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH);
856
857 return 0;
858}
859#endif
860static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume);
861
862static const struct of_device_id nfc_id_table[] = {
863 { .compatible = "hisilicon,504-nfc" },
864 {}
865};
866MODULE_DEVICE_TABLE(of, nfc_id_table);
867
868static struct platform_driver hisi_nfc_driver = {
869 .driver = {
870 .name = "hisi_nand",
871 .of_match_table = nfc_id_table,
872 .pm = &hisi_nfc_pm_ops,
873 },
874 .probe = hisi_nfc_probe,
875 .remove = hisi_nfc_remove,
876};
877
878module_platform_driver(hisi_nfc_driver);
879
880MODULE_LICENSE("GPL");
881MODULE_AUTHOR("Zhou Wang");
882MODULE_AUTHOR("Zhiyong Cai");
883MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");
Linux 6.x block layer and io_uring tree(s)