Commit | Line | Data |
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fe69af00 | 1 | /* |
2 | * drivers/mtd/nand/pxa3xx_nand.c | |
3 | * | |
4 | * Copyright © 2005 Intel Corporation | |
5 | * Copyright © 2006 Marvell International Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a88bdbb5 | 12 | #include <linux/kernel.h> |
fe69af00 | 13 | #include <linux/module.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
a1c06ee1 DW |
22 | #include <linux/io.h> |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
fe69af00 | 25 | |
afb5b5c9 | 26 | #include <mach/dma.h> |
82b95ecb | 27 | #include <plat/pxa3xx_nand.h> |
fe69af00 | 28 | |
29 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | |
f8155a40 | 30 | #define NAND_STOP_DELAY (2 * HZ/50) |
4eb2da89 | 31 | #define PAGE_CHUNK_SIZE (2048) |
fe69af00 | 32 | |
33 | /* registers and bit definitions */ | |
34 | #define NDCR (0x00) /* Control register */ | |
35 | #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ | |
36 | #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ | |
37 | #define NDSR (0x14) /* Status Register */ | |
38 | #define NDPCR (0x18) /* Page Count Register */ | |
39 | #define NDBDR0 (0x1C) /* Bad Block Register 0 */ | |
40 | #define NDBDR1 (0x20) /* Bad Block Register 1 */ | |
41 | #define NDDB (0x40) /* Data Buffer */ | |
42 | #define NDCB0 (0x48) /* Command Buffer0 */ | |
43 | #define NDCB1 (0x4C) /* Command Buffer1 */ | |
44 | #define NDCB2 (0x50) /* Command Buffer2 */ | |
45 | ||
46 | #define NDCR_SPARE_EN (0x1 << 31) | |
47 | #define NDCR_ECC_EN (0x1 << 30) | |
48 | #define NDCR_DMA_EN (0x1 << 29) | |
49 | #define NDCR_ND_RUN (0x1 << 28) | |
50 | #define NDCR_DWIDTH_C (0x1 << 27) | |
51 | #define NDCR_DWIDTH_M (0x1 << 26) | |
52 | #define NDCR_PAGE_SZ (0x1 << 24) | |
53 | #define NDCR_NCSX (0x1 << 23) | |
54 | #define NDCR_ND_MODE (0x3 << 21) | |
55 | #define NDCR_NAND_MODE (0x0) | |
56 | #define NDCR_CLR_PG_CNT (0x1 << 20) | |
f8155a40 | 57 | #define NDCR_STOP_ON_UNCOR (0x1 << 19) |
fe69af00 | 58 | #define NDCR_RD_ID_CNT_MASK (0x7 << 16) |
59 | #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) | |
60 | ||
61 | #define NDCR_RA_START (0x1 << 15) | |
62 | #define NDCR_PG_PER_BLK (0x1 << 14) | |
63 | #define NDCR_ND_ARB_EN (0x1 << 12) | |
f8155a40 | 64 | #define NDCR_INT_MASK (0xFFF) |
fe69af00 | 65 | |
66 | #define NDSR_MASK (0xfff) | |
f8155a40 LW |
67 | #define NDSR_RDY (0x1 << 12) |
68 | #define NDSR_FLASH_RDY (0x1 << 11) | |
fe69af00 | 69 | #define NDSR_CS0_PAGED (0x1 << 10) |
70 | #define NDSR_CS1_PAGED (0x1 << 9) | |
71 | #define NDSR_CS0_CMDD (0x1 << 8) | |
72 | #define NDSR_CS1_CMDD (0x1 << 7) | |
73 | #define NDSR_CS0_BBD (0x1 << 6) | |
74 | #define NDSR_CS1_BBD (0x1 << 5) | |
75 | #define NDSR_DBERR (0x1 << 4) | |
76 | #define NDSR_SBERR (0x1 << 3) | |
77 | #define NDSR_WRDREQ (0x1 << 2) | |
78 | #define NDSR_RDDREQ (0x1 << 1) | |
79 | #define NDSR_WRCMDREQ (0x1) | |
80 | ||
4eb2da89 | 81 | #define NDCB0_ST_ROW_EN (0x1 << 26) |
fe69af00 | 82 | #define NDCB0_AUTO_RS (0x1 << 25) |
83 | #define NDCB0_CSEL (0x1 << 24) | |
84 | #define NDCB0_CMD_TYPE_MASK (0x7 << 21) | |
85 | #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) | |
86 | #define NDCB0_NC (0x1 << 20) | |
87 | #define NDCB0_DBC (0x1 << 19) | |
88 | #define NDCB0_ADDR_CYC_MASK (0x7 << 16) | |
89 | #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) | |
90 | #define NDCB0_CMD2_MASK (0xff << 8) | |
91 | #define NDCB0_CMD1_MASK (0xff) | |
92 | #define NDCB0_ADDR_CYC_SHIFT (16) | |
93 | ||
fe69af00 | 94 | /* macros for registers read/write */ |
95 | #define nand_writel(info, off, val) \ | |
96 | __raw_writel((val), (info)->mmio_base + (off)) | |
97 | ||
98 | #define nand_readl(info, off) \ | |
99 | __raw_readl((info)->mmio_base + (off)) | |
100 | ||
101 | /* error code and state */ | |
102 | enum { | |
103 | ERR_NONE = 0, | |
104 | ERR_DMABUSERR = -1, | |
105 | ERR_SENDCMD = -2, | |
106 | ERR_DBERR = -3, | |
107 | ERR_BBERR = -4, | |
223cf6c3 | 108 | ERR_SBERR = -5, |
fe69af00 | 109 | }; |
110 | ||
111 | enum { | |
f8155a40 | 112 | STATE_IDLE = 0, |
d456882b | 113 | STATE_PREPARED, |
fe69af00 | 114 | STATE_CMD_HANDLE, |
115 | STATE_DMA_READING, | |
116 | STATE_DMA_WRITING, | |
117 | STATE_DMA_DONE, | |
118 | STATE_PIO_READING, | |
119 | STATE_PIO_WRITING, | |
f8155a40 LW |
120 | STATE_CMD_DONE, |
121 | STATE_READY, | |
fe69af00 | 122 | }; |
123 | ||
d456882b LW |
124 | struct pxa3xx_nand_host { |
125 | struct nand_chip chip; | |
126 | struct pxa3xx_nand_cmdset *cmdset; | |
127 | struct mtd_info *mtd; | |
128 | void *info_data; | |
129 | ||
130 | /* page size of attached chip */ | |
131 | unsigned int page_size; | |
132 | int use_ecc; | |
fe69af00 | 133 | |
d456882b LW |
134 | /* calculated from pxa3xx_nand_flash data */ |
135 | unsigned int col_addr_cycles; | |
136 | unsigned int row_addr_cycles; | |
137 | size_t read_id_bytes; | |
138 | ||
139 | /* cached register value */ | |
140 | uint32_t reg_ndcr; | |
141 | uint32_t ndtr0cs0; | |
142 | uint32_t ndtr1cs0; | |
143 | }; | |
144 | ||
145 | struct pxa3xx_nand_info { | |
401e67e2 | 146 | struct nand_hw_control controller; |
fe69af00 | 147 | struct platform_device *pdev; |
fe69af00 | 148 | |
149 | struct clk *clk; | |
150 | void __iomem *mmio_base; | |
8638fac8 | 151 | unsigned long mmio_phys; |
d456882b | 152 | struct completion cmd_complete; |
fe69af00 | 153 | |
154 | unsigned int buf_start; | |
155 | unsigned int buf_count; | |
156 | ||
157 | /* DMA information */ | |
158 | int drcmr_dat; | |
159 | int drcmr_cmd; | |
160 | ||
161 | unsigned char *data_buff; | |
18c81b18 | 162 | unsigned char *oob_buff; |
fe69af00 | 163 | dma_addr_t data_buff_phys; |
fe69af00 | 164 | int data_dma_ch; |
165 | struct pxa_dma_desc *data_desc; | |
166 | dma_addr_t data_desc_addr; | |
167 | ||
d456882b | 168 | struct pxa3xx_nand_host *host; |
fe69af00 | 169 | unsigned int state; |
170 | ||
171 | int use_ecc; /* use HW ECC ? */ | |
172 | int use_dma; /* use DMA ? */ | |
401e67e2 | 173 | int is_ready; |
fe69af00 | 174 | |
18c81b18 LW |
175 | unsigned int page_size; /* page size of attached chip */ |
176 | unsigned int data_size; /* data size in FIFO */ | |
d456882b | 177 | unsigned int oob_size; |
fe69af00 | 178 | int retcode; |
fe69af00 | 179 | |
180 | /* generated NDCBx register values */ | |
181 | uint32_t ndcb0; | |
182 | uint32_t ndcb1; | |
183 | uint32_t ndcb2; | |
184 | }; | |
185 | ||
186 | static int use_dma = 1; | |
187 | module_param(use_dma, bool, 0444); | |
25985edc | 188 | MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); |
fe69af00 | 189 | |
f271049e MR |
190 | /* |
191 | * Default NAND flash controller configuration setup by the | |
192 | * bootloader. This configuration is used only when pdata->keep_config is set | |
193 | */ | |
c1f82478 | 194 | static struct pxa3xx_nand_cmdset default_cmdset = { |
fe69af00 | 195 | .read1 = 0x3000, |
196 | .read2 = 0x0050, | |
197 | .program = 0x1080, | |
198 | .read_status = 0x0070, | |
199 | .read_id = 0x0090, | |
200 | .erase = 0xD060, | |
201 | .reset = 0x00FF, | |
202 | .lock = 0x002A, | |
203 | .unlock = 0x2423, | |
204 | .lock_status = 0x007A, | |
205 | }; | |
206 | ||
c1f82478 | 207 | static struct pxa3xx_nand_timing timing[] = { |
227a886c LW |
208 | { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, |
209 | { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, | |
210 | { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, | |
211 | { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, | |
d3490dfd HZ |
212 | }; |
213 | ||
c1f82478 | 214 | static struct pxa3xx_nand_flash builtin_flash_types[] = { |
4332c116 LW |
215 | { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, |
216 | { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, | |
217 | { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, | |
218 | { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, | |
219 | { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, | |
220 | { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, | |
221 | { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, | |
222 | { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, | |
223 | { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, | |
d3490dfd HZ |
224 | }; |
225 | ||
227a886c LW |
226 | /* Define a default flash type setting serve as flash detecting only */ |
227 | #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) | |
228 | ||
401e67e2 LW |
229 | const char *mtd_names[] = {"pxa3xx_nand-0", NULL}; |
230 | ||
fe69af00 | 231 | #define NDTR0_tCH(c) (min((c), 7) << 19) |
232 | #define NDTR0_tCS(c) (min((c), 7) << 16) | |
233 | #define NDTR0_tWH(c) (min((c), 7) << 11) | |
234 | #define NDTR0_tWP(c) (min((c), 7) << 8) | |
235 | #define NDTR0_tRH(c) (min((c), 7) << 3) | |
236 | #define NDTR0_tRP(c) (min((c), 7) << 0) | |
237 | ||
238 | #define NDTR1_tR(c) (min((c), 65535) << 16) | |
239 | #define NDTR1_tWHR(c) (min((c), 15) << 4) | |
240 | #define NDTR1_tAR(c) (min((c), 15) << 0) | |
241 | ||
242 | /* convert nano-seconds to nand flash controller clock cycles */ | |
93b352fc | 243 | #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) |
fe69af00 | 244 | |
d456882b | 245 | static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, |
7dad482e | 246 | const struct pxa3xx_nand_timing *t) |
fe69af00 | 247 | { |
d456882b | 248 | struct pxa3xx_nand_info *info = host->info_data; |
fe69af00 | 249 | unsigned long nand_clk = clk_get_rate(info->clk); |
250 | uint32_t ndtr0, ndtr1; | |
251 | ||
252 | ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | | |
253 | NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | | |
254 | NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | | |
255 | NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | | |
256 | NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | | |
257 | NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); | |
258 | ||
259 | ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | | |
260 | NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | | |
261 | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); | |
262 | ||
d456882b LW |
263 | host->ndtr0cs0 = ndtr0; |
264 | host->ndtr1cs0 = ndtr1; | |
fe69af00 | 265 | nand_writel(info, NDTR0CS0, ndtr0); |
266 | nand_writel(info, NDTR1CS0, ndtr1); | |
267 | } | |
268 | ||
18c81b18 | 269 | static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) |
fe69af00 | 270 | { |
d456882b LW |
271 | struct pxa3xx_nand_host *host = info->host; |
272 | int oob_enable = host->reg_ndcr & NDCR_SPARE_EN; | |
9d8b1043 | 273 | |
d456882b | 274 | info->data_size = host->page_size; |
9d8b1043 LW |
275 | if (!oob_enable) { |
276 | info->oob_size = 0; | |
277 | return; | |
278 | } | |
279 | ||
d456882b | 280 | switch (host->page_size) { |
fe69af00 | 281 | case 2048: |
9d8b1043 | 282 | info->oob_size = (info->use_ecc) ? 40 : 64; |
fe69af00 | 283 | break; |
284 | case 512: | |
9d8b1043 | 285 | info->oob_size = (info->use_ecc) ? 8 : 16; |
fe69af00 | 286 | break; |
fe69af00 | 287 | } |
18c81b18 LW |
288 | } |
289 | ||
f8155a40 LW |
290 | /** |
291 | * NOTE: it is a must to set ND_RUN firstly, then write | |
292 | * command buffer, otherwise, it does not work. | |
293 | * We enable all the interrupt at the same time, and | |
294 | * let pxa3xx_nand_irq to handle all logic. | |
295 | */ | |
296 | static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) | |
297 | { | |
d456882b | 298 | struct pxa3xx_nand_host *host = info->host; |
f8155a40 LW |
299 | uint32_t ndcr; |
300 | ||
d456882b | 301 | ndcr = host->reg_ndcr; |
f8155a40 LW |
302 | ndcr |= info->use_ecc ? NDCR_ECC_EN : 0; |
303 | ndcr |= info->use_dma ? NDCR_DMA_EN : 0; | |
304 | ndcr |= NDCR_ND_RUN; | |
305 | ||
306 | /* clear status bits and run */ | |
307 | nand_writel(info, NDCR, 0); | |
308 | nand_writel(info, NDSR, NDSR_MASK); | |
309 | nand_writel(info, NDCR, ndcr); | |
310 | } | |
311 | ||
312 | static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) | |
313 | { | |
314 | uint32_t ndcr; | |
315 | int timeout = NAND_STOP_DELAY; | |
316 | ||
317 | /* wait RUN bit in NDCR become 0 */ | |
318 | ndcr = nand_readl(info, NDCR); | |
319 | while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { | |
320 | ndcr = nand_readl(info, NDCR); | |
321 | udelay(1); | |
322 | } | |
323 | ||
324 | if (timeout <= 0) { | |
325 | ndcr &= ~NDCR_ND_RUN; | |
326 | nand_writel(info, NDCR, ndcr); | |
327 | } | |
328 | /* clear status bits */ | |
329 | nand_writel(info, NDSR, NDSR_MASK); | |
330 | } | |
331 | ||
fe69af00 | 332 | static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) |
333 | { | |
334 | uint32_t ndcr; | |
335 | ||
336 | ndcr = nand_readl(info, NDCR); | |
337 | nand_writel(info, NDCR, ndcr & ~int_mask); | |
338 | } | |
339 | ||
340 | static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
341 | { | |
342 | uint32_t ndcr; | |
343 | ||
344 | ndcr = nand_readl(info, NDCR); | |
345 | nand_writel(info, NDCR, ndcr | int_mask); | |
346 | } | |
347 | ||
f8155a40 | 348 | static void handle_data_pio(struct pxa3xx_nand_info *info) |
fe69af00 | 349 | { |
fe69af00 | 350 | switch (info->state) { |
351 | case STATE_PIO_WRITING: | |
352 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 353 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
354 | if (info->oob_size > 0) |
355 | __raw_writesl(info->mmio_base + NDDB, info->oob_buff, | |
356 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 357 | break; |
358 | case STATE_PIO_READING: | |
359 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 360 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
361 | if (info->oob_size > 0) |
362 | __raw_readsl(info->mmio_base + NDDB, info->oob_buff, | |
363 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 364 | break; |
365 | default: | |
da675b4e | 366 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
fe69af00 | 367 | info->state); |
f8155a40 | 368 | BUG(); |
fe69af00 | 369 | } |
fe69af00 | 370 | } |
371 | ||
f8155a40 | 372 | static void start_data_dma(struct pxa3xx_nand_info *info) |
fe69af00 | 373 | { |
374 | struct pxa_dma_desc *desc = info->data_desc; | |
9d8b1043 | 375 | int dma_len = ALIGN(info->data_size + info->oob_size, 32); |
fe69af00 | 376 | |
377 | desc->ddadr = DDADR_STOP; | |
378 | desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; | |
379 | ||
f8155a40 LW |
380 | switch (info->state) { |
381 | case STATE_DMA_WRITING: | |
fe69af00 | 382 | desc->dsadr = info->data_buff_phys; |
8638fac8 | 383 | desc->dtadr = info->mmio_phys + NDDB; |
fe69af00 | 384 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
f8155a40 LW |
385 | break; |
386 | case STATE_DMA_READING: | |
fe69af00 | 387 | desc->dtadr = info->data_buff_phys; |
8638fac8 | 388 | desc->dsadr = info->mmio_phys + NDDB; |
fe69af00 | 389 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
f8155a40 LW |
390 | break; |
391 | default: | |
da675b4e | 392 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
f8155a40 LW |
393 | info->state); |
394 | BUG(); | |
fe69af00 | 395 | } |
396 | ||
397 | DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; | |
398 | DDADR(info->data_dma_ch) = info->data_desc_addr; | |
399 | DCSR(info->data_dma_ch) |= DCSR_RUN; | |
400 | } | |
401 | ||
402 | static void pxa3xx_nand_data_dma_irq(int channel, void *data) | |
403 | { | |
404 | struct pxa3xx_nand_info *info = data; | |
405 | uint32_t dcsr; | |
406 | ||
407 | dcsr = DCSR(channel); | |
408 | DCSR(channel) = dcsr; | |
409 | ||
410 | if (dcsr & DCSR_BUSERR) { | |
411 | info->retcode = ERR_DMABUSERR; | |
fe69af00 | 412 | } |
413 | ||
f8155a40 LW |
414 | info->state = STATE_DMA_DONE; |
415 | enable_int(info, NDCR_INT_MASK); | |
416 | nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); | |
fe69af00 | 417 | } |
418 | ||
419 | static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) | |
420 | { | |
421 | struct pxa3xx_nand_info *info = devid; | |
f8155a40 | 422 | unsigned int status, is_completed = 0; |
fe69af00 | 423 | |
424 | status = nand_readl(info, NDSR); | |
425 | ||
f8155a40 LW |
426 | if (status & NDSR_DBERR) |
427 | info->retcode = ERR_DBERR; | |
428 | if (status & NDSR_SBERR) | |
429 | info->retcode = ERR_SBERR; | |
430 | if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { | |
431 | /* whether use dma to transfer data */ | |
fe69af00 | 432 | if (info->use_dma) { |
f8155a40 LW |
433 | disable_int(info, NDCR_INT_MASK); |
434 | info->state = (status & NDSR_RDDREQ) ? | |
435 | STATE_DMA_READING : STATE_DMA_WRITING; | |
436 | start_data_dma(info); | |
437 | goto NORMAL_IRQ_EXIT; | |
fe69af00 | 438 | } else { |
f8155a40 LW |
439 | info->state = (status & NDSR_RDDREQ) ? |
440 | STATE_PIO_READING : STATE_PIO_WRITING; | |
441 | handle_data_pio(info); | |
fe69af00 | 442 | } |
fe69af00 | 443 | } |
f8155a40 LW |
444 | if (status & NDSR_CS0_CMDD) { |
445 | info->state = STATE_CMD_DONE; | |
446 | is_completed = 1; | |
fe69af00 | 447 | } |
401e67e2 LW |
448 | if (status & NDSR_FLASH_RDY) { |
449 | info->is_ready = 1; | |
f8155a40 | 450 | info->state = STATE_READY; |
401e67e2 | 451 | } |
fe69af00 | 452 | |
f8155a40 LW |
453 | if (status & NDSR_WRCMDREQ) { |
454 | nand_writel(info, NDSR, NDSR_WRCMDREQ); | |
455 | status &= ~NDSR_WRCMDREQ; | |
456 | info->state = STATE_CMD_HANDLE; | |
457 | nand_writel(info, NDCB0, info->ndcb0); | |
458 | nand_writel(info, NDCB0, info->ndcb1); | |
459 | nand_writel(info, NDCB0, info->ndcb2); | |
fe69af00 | 460 | } |
461 | ||
f8155a40 LW |
462 | /* clear NDSR to let the controller exit the IRQ */ |
463 | nand_writel(info, NDSR, status); | |
464 | if (is_completed) | |
465 | complete(&info->cmd_complete); | |
466 | NORMAL_IRQ_EXIT: | |
467 | return IRQ_HANDLED; | |
fe69af00 | 468 | } |
469 | ||
fe69af00 | 470 | static inline int is_buf_blank(uint8_t *buf, size_t len) |
471 | { | |
472 | for (; len > 0; len--) | |
473 | if (*buf++ != 0xff) | |
474 | return 0; | |
475 | return 1; | |
476 | } | |
477 | ||
4eb2da89 LW |
478 | static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, |
479 | uint16_t column, int page_addr) | |
fe69af00 | 480 | { |
4eb2da89 | 481 | uint16_t cmd; |
d456882b LW |
482 | int addr_cycle, exec_cmd; |
483 | struct pxa3xx_nand_host *host = info->host; | |
484 | struct mtd_info *mtd = host->mtd; | |
fe69af00 | 485 | |
4eb2da89 LW |
486 | addr_cycle = 0; |
487 | exec_cmd = 1; | |
488 | ||
489 | /* reset data and oob column point to handle data */ | |
401e67e2 LW |
490 | info->buf_start = 0; |
491 | info->buf_count = 0; | |
4eb2da89 LW |
492 | info->oob_size = 0; |
493 | info->use_ecc = 0; | |
401e67e2 | 494 | info->is_ready = 0; |
d456882b | 495 | info->ndcb0 = 0; |
4eb2da89 | 496 | info->retcode = ERR_NONE; |
fe69af00 | 497 | |
498 | switch (command) { | |
4eb2da89 LW |
499 | case NAND_CMD_READ0: |
500 | case NAND_CMD_PAGEPROG: | |
501 | info->use_ecc = 1; | |
fe69af00 | 502 | case NAND_CMD_READOOB: |
4eb2da89 | 503 | pxa3xx_set_datasize(info); |
fe69af00 | 504 | break; |
4eb2da89 LW |
505 | case NAND_CMD_SEQIN: |
506 | exec_cmd = 0; | |
507 | break; | |
508 | default: | |
509 | info->ndcb1 = 0; | |
510 | info->ndcb2 = 0; | |
511 | break; | |
512 | } | |
513 | ||
d456882b LW |
514 | addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles |
515 | + host->col_addr_cycles); | |
fe69af00 | 516 | |
4eb2da89 LW |
517 | switch (command) { |
518 | case NAND_CMD_READOOB: | |
fe69af00 | 519 | case NAND_CMD_READ0: |
d456882b | 520 | cmd = host->cmdset->read1; |
4eb2da89 LW |
521 | if (command == NAND_CMD_READOOB) |
522 | info->buf_start = mtd->writesize + column; | |
523 | else | |
524 | info->buf_start = column; | |
525 | ||
d456882b | 526 | if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) |
4eb2da89 LW |
527 | info->ndcb0 |= NDCB0_CMD_TYPE(0) |
528 | | addr_cycle | |
529 | | (cmd & NDCB0_CMD1_MASK); | |
530 | else | |
531 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
532 | | NDCB0_DBC | |
533 | | addr_cycle | |
534 | | cmd; | |
fe69af00 | 535 | |
fe69af00 | 536 | case NAND_CMD_SEQIN: |
4eb2da89 | 537 | /* small page addr setting */ |
d456882b | 538 | if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) { |
4eb2da89 LW |
539 | info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) |
540 | | (column & 0xFF); | |
541 | ||
542 | info->ndcb2 = 0; | |
543 | } else { | |
544 | info->ndcb1 = ((page_addr & 0xFFFF) << 16) | |
545 | | (column & 0xFFFF); | |
546 | ||
547 | if (page_addr & 0xFF0000) | |
548 | info->ndcb2 = (page_addr & 0xFF0000) >> 16; | |
549 | else | |
550 | info->ndcb2 = 0; | |
551 | } | |
552 | ||
fe69af00 | 553 | info->buf_count = mtd->writesize + mtd->oobsize; |
4eb2da89 | 554 | memset(info->data_buff, 0xFF, info->buf_count); |
fe69af00 | 555 | |
fe69af00 | 556 | break; |
4eb2da89 | 557 | |
fe69af00 | 558 | case NAND_CMD_PAGEPROG: |
4eb2da89 LW |
559 | if (is_buf_blank(info->data_buff, |
560 | (mtd->writesize + mtd->oobsize))) { | |
561 | exec_cmd = 0; | |
562 | break; | |
563 | } | |
fe69af00 | 564 | |
d456882b | 565 | cmd = host->cmdset->program; |
4eb2da89 LW |
566 | info->ndcb0 |= NDCB0_CMD_TYPE(0x1) |
567 | | NDCB0_AUTO_RS | |
568 | | NDCB0_ST_ROW_EN | |
569 | | NDCB0_DBC | |
570 | | cmd | |
571 | | addr_cycle; | |
fe69af00 | 572 | break; |
4eb2da89 | 573 | |
fe69af00 | 574 | case NAND_CMD_READID: |
d456882b LW |
575 | cmd = host->cmdset->read_id; |
576 | info->buf_count = host->read_id_bytes; | |
4eb2da89 LW |
577 | info->ndcb0 |= NDCB0_CMD_TYPE(3) |
578 | | NDCB0_ADDR_CYC(1) | |
579 | | cmd; | |
580 | ||
581 | info->data_size = 8; | |
582 | break; | |
fe69af00 | 583 | case NAND_CMD_STATUS: |
d456882b | 584 | cmd = host->cmdset->read_status; |
4eb2da89 LW |
585 | info->buf_count = 1; |
586 | info->ndcb0 |= NDCB0_CMD_TYPE(4) | |
587 | | NDCB0_ADDR_CYC(1) | |
588 | | cmd; | |
589 | ||
590 | info->data_size = 8; | |
591 | break; | |
592 | ||
593 | case NAND_CMD_ERASE1: | |
d456882b | 594 | cmd = host->cmdset->erase; |
4eb2da89 LW |
595 | info->ndcb0 |= NDCB0_CMD_TYPE(2) |
596 | | NDCB0_AUTO_RS | |
597 | | NDCB0_ADDR_CYC(3) | |
598 | | NDCB0_DBC | |
599 | | cmd; | |
600 | info->ndcb1 = page_addr; | |
601 | info->ndcb2 = 0; | |
602 | ||
fe69af00 | 603 | break; |
604 | case NAND_CMD_RESET: | |
d456882b | 605 | cmd = host->cmdset->reset; |
4eb2da89 LW |
606 | info->ndcb0 |= NDCB0_CMD_TYPE(5) |
607 | | cmd; | |
608 | ||
609 | break; | |
610 | ||
611 | case NAND_CMD_ERASE2: | |
612 | exec_cmd = 0; | |
fe69af00 | 613 | break; |
4eb2da89 | 614 | |
fe69af00 | 615 | default: |
4eb2da89 | 616 | exec_cmd = 0; |
da675b4e LW |
617 | dev_err(&info->pdev->dev, "non-supported command %x\n", |
618 | command); | |
fe69af00 | 619 | break; |
620 | } | |
621 | ||
4eb2da89 LW |
622 | return exec_cmd; |
623 | } | |
624 | ||
625 | static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
626 | int column, int page_addr) | |
627 | { | |
d456882b LW |
628 | struct pxa3xx_nand_host *host = mtd->priv; |
629 | struct pxa3xx_nand_info *info = host->info_data; | |
4eb2da89 LW |
630 | int ret, exec_cmd; |
631 | ||
632 | /* | |
633 | * if this is a x16 device ,then convert the input | |
634 | * "byte" address into a "word" address appropriate | |
635 | * for indexing a word-oriented device | |
636 | */ | |
d456882b | 637 | if (host->reg_ndcr & NDCR_DWIDTH_M) |
4eb2da89 LW |
638 | column /= 2; |
639 | ||
d456882b | 640 | info->state = STATE_PREPARED; |
4eb2da89 | 641 | exec_cmd = prepare_command_pool(info, command, column, page_addr); |
f8155a40 LW |
642 | if (exec_cmd) { |
643 | init_completion(&info->cmd_complete); | |
644 | pxa3xx_nand_start(info); | |
645 | ||
646 | ret = wait_for_completion_timeout(&info->cmd_complete, | |
647 | CHIP_DELAY_TIMEOUT); | |
648 | if (!ret) { | |
da675b4e | 649 | dev_err(&info->pdev->dev, "Wait time out!!!\n"); |
f8155a40 LW |
650 | /* Stop State Machine for next command cycle */ |
651 | pxa3xx_nand_stop(info); | |
652 | } | |
f8155a40 | 653 | } |
d456882b | 654 | info->state = STATE_IDLE; |
f8155a40 LW |
655 | } |
656 | ||
657 | static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, | |
658 | struct nand_chip *chip, const uint8_t *buf) | |
659 | { | |
660 | chip->write_buf(mtd, buf, mtd->writesize); | |
661 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
662 | } | |
663 | ||
664 | static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, | |
665 | struct nand_chip *chip, uint8_t *buf, int page) | |
666 | { | |
d456882b LW |
667 | struct pxa3xx_nand_host *host = mtd->priv; |
668 | struct pxa3xx_nand_info *info = host->info_data; | |
f8155a40 LW |
669 | |
670 | chip->read_buf(mtd, buf, mtd->writesize); | |
671 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
672 | ||
673 | if (info->retcode == ERR_SBERR) { | |
674 | switch (info->use_ecc) { | |
675 | case 1: | |
676 | mtd->ecc_stats.corrected++; | |
677 | break; | |
678 | case 0: | |
679 | default: | |
680 | break; | |
681 | } | |
682 | } else if (info->retcode == ERR_DBERR) { | |
683 | /* | |
684 | * for blank page (all 0xff), HW will calculate its ECC as | |
685 | * 0, which is different from the ECC information within | |
686 | * OOB, ignore such double bit errors | |
687 | */ | |
688 | if (is_buf_blank(buf, mtd->writesize)) | |
543e32d5 DM |
689 | info->retcode = ERR_NONE; |
690 | else | |
f8155a40 | 691 | mtd->ecc_stats.failed++; |
fe69af00 | 692 | } |
f8155a40 LW |
693 | |
694 | return 0; | |
fe69af00 | 695 | } |
696 | ||
697 | static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) | |
698 | { | |
d456882b LW |
699 | struct pxa3xx_nand_host *host = mtd->priv; |
700 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 701 | char retval = 0xFF; |
702 | ||
703 | if (info->buf_start < info->buf_count) | |
704 | /* Has just send a new command? */ | |
705 | retval = info->data_buff[info->buf_start++]; | |
706 | ||
707 | return retval; | |
708 | } | |
709 | ||
710 | static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) | |
711 | { | |
d456882b LW |
712 | struct pxa3xx_nand_host *host = mtd->priv; |
713 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 714 | u16 retval = 0xFFFF; |
715 | ||
716 | if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { | |
717 | retval = *((u16 *)(info->data_buff+info->buf_start)); | |
718 | info->buf_start += 2; | |
719 | } | |
720 | return retval; | |
721 | } | |
722 | ||
723 | static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
724 | { | |
d456882b LW |
725 | struct pxa3xx_nand_host *host = mtd->priv; |
726 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 727 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
728 | ||
729 | memcpy(buf, info->data_buff + info->buf_start, real_len); | |
730 | info->buf_start += real_len; | |
731 | } | |
732 | ||
733 | static void pxa3xx_nand_write_buf(struct mtd_info *mtd, | |
734 | const uint8_t *buf, int len) | |
735 | { | |
d456882b LW |
736 | struct pxa3xx_nand_host *host = mtd->priv; |
737 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 738 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
739 | ||
740 | memcpy(info->data_buff + info->buf_start, buf, real_len); | |
741 | info->buf_start += real_len; | |
742 | } | |
743 | ||
744 | static int pxa3xx_nand_verify_buf(struct mtd_info *mtd, | |
745 | const uint8_t *buf, int len) | |
746 | { | |
747 | return 0; | |
748 | } | |
749 | ||
750 | static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) | |
751 | { | |
752 | return; | |
753 | } | |
754 | ||
755 | static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) | |
756 | { | |
d456882b LW |
757 | struct pxa3xx_nand_host *host = mtd->priv; |
758 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 759 | |
760 | /* pxa3xx_nand_send_command has waited for command complete */ | |
761 | if (this->state == FL_WRITING || this->state == FL_ERASING) { | |
762 | if (info->retcode == ERR_NONE) | |
763 | return 0; | |
764 | else { | |
765 | /* | |
766 | * any error make it return 0x01 which will tell | |
767 | * the caller the erase and write fail | |
768 | */ | |
769 | return 0x01; | |
770 | } | |
771 | } | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
fe69af00 | 776 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
c8c17c88 | 777 | const struct pxa3xx_nand_flash *f) |
fe69af00 | 778 | { |
779 | struct platform_device *pdev = info->pdev; | |
780 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | |
d456882b | 781 | struct pxa3xx_nand_host *host = info->host; |
f8155a40 | 782 | uint32_t ndcr = 0x0; /* enable all interrupts */ |
fe69af00 | 783 | |
da675b4e LW |
784 | if (f->page_size != 2048 && f->page_size != 512) { |
785 | dev_err(&pdev->dev, "Current only support 2048 and 512 size\n"); | |
fe69af00 | 786 | return -EINVAL; |
da675b4e | 787 | } |
fe69af00 | 788 | |
da675b4e LW |
789 | if (f->flash_width != 16 && f->flash_width != 8) { |
790 | dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n"); | |
fe69af00 | 791 | return -EINVAL; |
da675b4e | 792 | } |
fe69af00 | 793 | |
794 | /* calculate flash information */ | |
d456882b LW |
795 | host->cmdset = &default_cmdset; |
796 | host->page_size = f->page_size; | |
797 | host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; | |
fe69af00 | 798 | |
799 | /* calculate addressing information */ | |
d456882b | 800 | host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
fe69af00 | 801 | |
802 | if (f->num_blocks * f->page_per_block > 65536) | |
d456882b | 803 | host->row_addr_cycles = 3; |
fe69af00 | 804 | else |
d456882b | 805 | host->row_addr_cycles = 2; |
fe69af00 | 806 | |
807 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | |
d456882b | 808 | ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
fe69af00 | 809 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
810 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | |
811 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | |
812 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | |
813 | ||
d456882b | 814 | ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); |
fe69af00 | 815 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
816 | ||
d456882b | 817 | host->reg_ndcr = ndcr; |
fe69af00 | 818 | |
d456882b | 819 | pxa3xx_nand_set_timing(host, f->timing); |
fe69af00 | 820 | return 0; |
821 | } | |
822 | ||
f271049e MR |
823 | static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) |
824 | { | |
d456882b | 825 | struct pxa3xx_nand_host *host = info->host; |
f271049e | 826 | uint32_t ndcr = nand_readl(info, NDCR); |
f271049e | 827 | |
d456882b LW |
828 | if (ndcr & NDCR_PAGE_SZ) { |
829 | host->page_size = 2048; | |
830 | host->read_id_bytes = 4; | |
831 | } else { | |
832 | host->page_size = 512; | |
833 | host->read_id_bytes = 2; | |
834 | } | |
835 | ||
836 | host->reg_ndcr = ndcr & ~NDCR_INT_MASK; | |
837 | host->cmdset = &default_cmdset; | |
838 | ||
839 | host->ndtr0cs0 = nand_readl(info, NDTR0CS0); | |
840 | host->ndtr1cs0 = nand_readl(info, NDTR1CS0); | |
f271049e MR |
841 | |
842 | return 0; | |
843 | } | |
844 | ||
fe69af00 | 845 | /* the maximum possible buffer size for large page with OOB data |
846 | * is: 2048 + 64 = 2112 bytes, allocate a page here for both the | |
847 | * data buffer and the DMA descriptor | |
848 | */ | |
849 | #define MAX_BUFF_SIZE PAGE_SIZE | |
850 | ||
851 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) | |
852 | { | |
853 | struct platform_device *pdev = info->pdev; | |
854 | int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc); | |
855 | ||
856 | if (use_dma == 0) { | |
857 | info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL); | |
858 | if (info->data_buff == NULL) | |
859 | return -ENOMEM; | |
860 | return 0; | |
861 | } | |
862 | ||
863 | info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE, | |
864 | &info->data_buff_phys, GFP_KERNEL); | |
865 | if (info->data_buff == NULL) { | |
866 | dev_err(&pdev->dev, "failed to allocate dma buffer\n"); | |
867 | return -ENOMEM; | |
868 | } | |
869 | ||
fe69af00 | 870 | info->data_desc = (void *)info->data_buff + data_desc_offset; |
871 | info->data_desc_addr = info->data_buff_phys + data_desc_offset; | |
872 | ||
873 | info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, | |
874 | pxa3xx_nand_data_dma_irq, info); | |
875 | if (info->data_dma_ch < 0) { | |
876 | dev_err(&pdev->dev, "failed to request data dma\n"); | |
d456882b | 877 | dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, |
fe69af00 | 878 | info->data_buff, info->data_buff_phys); |
879 | return info->data_dma_ch; | |
880 | } | |
881 | ||
882 | return 0; | |
883 | } | |
884 | ||
401e67e2 LW |
885 | static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) |
886 | { | |
d456882b LW |
887 | struct mtd_info *mtd = info->host->mtd; |
888 | int ret; | |
fe69af00 | 889 | |
401e67e2 | 890 | /* use the common timing to make a try */ |
d456882b LW |
891 | ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); |
892 | if (ret) | |
893 | return ret; | |
894 | ||
895 | pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0); | |
401e67e2 | 896 | if (info->is_ready) |
401e67e2 | 897 | return 0; |
d456882b LW |
898 | |
899 | return -ENODEV; | |
401e67e2 | 900 | } |
fe69af00 | 901 | |
401e67e2 | 902 | static int pxa3xx_nand_scan(struct mtd_info *mtd) |
fe69af00 | 903 | { |
d456882b LW |
904 | struct pxa3xx_nand_host *host = mtd->priv; |
905 | struct pxa3xx_nand_info *info = host->info_data; | |
401e67e2 LW |
906 | struct platform_device *pdev = info->pdev; |
907 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | |
0fab028b | 908 | struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; |
401e67e2 LW |
909 | const struct pxa3xx_nand_flash *f = NULL; |
910 | struct nand_chip *chip = mtd->priv; | |
911 | uint32_t id = -1; | |
4332c116 | 912 | uint64_t chipsize; |
401e67e2 LW |
913 | int i, ret, num; |
914 | ||
915 | if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) | |
4332c116 | 916 | goto KEEP_CONFIG; |
401e67e2 LW |
917 | |
918 | ret = pxa3xx_nand_sensing(info); | |
d456882b | 919 | if (ret) { |
da675b4e | 920 | dev_info(&info->pdev->dev, "There is no nand chip on cs 0!\n"); |
401e67e2 | 921 | |
d456882b | 922 | return ret; |
401e67e2 LW |
923 | } |
924 | ||
925 | chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); | |
926 | id = *((uint16_t *)(info->data_buff)); | |
927 | if (id != 0) | |
da675b4e | 928 | dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); |
401e67e2 | 929 | else { |
da675b4e LW |
930 | dev_warn(&info->pdev->dev, |
931 | "Read out ID 0, potential timing set wrong!!\n"); | |
401e67e2 LW |
932 | |
933 | return -EINVAL; | |
934 | } | |
935 | ||
936 | num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; | |
937 | for (i = 0; i < num; i++) { | |
938 | if (i < pdata->num_flash) | |
939 | f = pdata->flash + i; | |
940 | else | |
941 | f = &builtin_flash_types[i - pdata->num_flash + 1]; | |
942 | ||
943 | /* find the chip in default list */ | |
4332c116 | 944 | if (f->chip_id == id) |
401e67e2 | 945 | break; |
401e67e2 LW |
946 | } |
947 | ||
4332c116 | 948 | if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { |
da675b4e | 949 | dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); |
401e67e2 LW |
950 | |
951 | return -EINVAL; | |
952 | } | |
953 | ||
d456882b LW |
954 | ret = pxa3xx_nand_config_flash(info, f); |
955 | if (ret) { | |
956 | dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); | |
957 | return ret; | |
958 | } | |
959 | ||
4332c116 LW |
960 | pxa3xx_flash_ids[0].name = f->name; |
961 | pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff; | |
962 | pxa3xx_flash_ids[0].pagesize = f->page_size; | |
963 | chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; | |
964 | pxa3xx_flash_ids[0].chipsize = chipsize >> 20; | |
965 | pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; | |
966 | if (f->flash_width == 16) | |
967 | pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; | |
0fab028b LW |
968 | pxa3xx_flash_ids[1].name = NULL; |
969 | def = pxa3xx_flash_ids; | |
4332c116 | 970 | KEEP_CONFIG: |
d456882b LW |
971 | chip->ecc.mode = NAND_ECC_HW; |
972 | chip->ecc.size = host->page_size; | |
973 | ||
974 | chip->options = NAND_NO_AUTOINCR; | |
975 | chip->options |= NAND_NO_READRDY; | |
976 | if (host->reg_ndcr & NDCR_DWIDTH_M) | |
977 | chip->options |= NAND_BUSWIDTH_16; | |
978 | ||
0fab028b | 979 | if (nand_scan_ident(mtd, 1, def)) |
4332c116 LW |
980 | return -ENODEV; |
981 | /* calculate addressing information */ | |
d456882b LW |
982 | if (mtd->writesize >= 2048) |
983 | host->col_addr_cycles = 2; | |
984 | else | |
985 | host->col_addr_cycles = 1; | |
986 | ||
4332c116 LW |
987 | info->oob_buff = info->data_buff + mtd->writesize; |
988 | if ((mtd->size >> chip->page_shift) > 65536) | |
d456882b | 989 | host->row_addr_cycles = 3; |
4332c116 | 990 | else |
d456882b | 991 | host->row_addr_cycles = 2; |
fe69af00 | 992 | |
d456882b | 993 | mtd->name = mtd_names[0]; |
401e67e2 | 994 | return nand_scan_tail(mtd); |
fe69af00 | 995 | } |
996 | ||
d456882b | 997 | static int alloc_nand_resource(struct platform_device *pdev) |
fe69af00 | 998 | { |
fe69af00 | 999 | struct pxa3xx_nand_info *info; |
d456882b | 1000 | struct pxa3xx_nand_host *host; |
401e67e2 | 1001 | struct nand_chip *chip; |
fe69af00 | 1002 | struct mtd_info *mtd; |
1003 | struct resource *r; | |
e353a20a | 1004 | int ret, irq; |
fe69af00 | 1005 | |
d456882b | 1006 | info = kzalloc(sizeof(*info) + sizeof(*mtd) + sizeof(*host), |
fe69af00 | 1007 | GFP_KERNEL); |
d456882b | 1008 | if (!info) { |
fe69af00 | 1009 | dev_err(&pdev->dev, "failed to allocate memory\n"); |
d456882b | 1010 | return -ENOMEM; |
a1c06ee1 | 1011 | } |
fe69af00 | 1012 | |
d456882b | 1013 | mtd = (struct mtd_info *)(&info[1]); |
401e67e2 | 1014 | chip = (struct nand_chip *)(&mtd[1]); |
d456882b | 1015 | host = (struct pxa3xx_nand_host *)chip; |
fe69af00 | 1016 | info->pdev = pdev; |
d456882b LW |
1017 | info->host = host; |
1018 | host->mtd = mtd; | |
1019 | host->info_data = info; | |
1020 | mtd->priv = host; | |
82a72d10 | 1021 | mtd->owner = THIS_MODULE; |
fe69af00 | 1022 | |
401e67e2 LW |
1023 | chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; |
1024 | chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; | |
1025 | chip->controller = &info->controller; | |
1026 | chip->waitfunc = pxa3xx_nand_waitfunc; | |
1027 | chip->select_chip = pxa3xx_nand_select_chip; | |
401e67e2 LW |
1028 | chip->cmdfunc = pxa3xx_nand_cmdfunc; |
1029 | chip->read_word = pxa3xx_nand_read_word; | |
1030 | chip->read_byte = pxa3xx_nand_read_byte; | |
1031 | chip->read_buf = pxa3xx_nand_read_buf; | |
1032 | chip->write_buf = pxa3xx_nand_write_buf; | |
1033 | chip->verify_buf = pxa3xx_nand_verify_buf; | |
1034 | ||
1035 | spin_lock_init(&chip->controller->lock); | |
1036 | init_waitqueue_head(&chip->controller->wq); | |
e0d8b13a | 1037 | info->clk = clk_get(&pdev->dev, NULL); |
fe69af00 | 1038 | if (IS_ERR(info->clk)) { |
1039 | dev_err(&pdev->dev, "failed to get nand clock\n"); | |
1040 | ret = PTR_ERR(info->clk); | |
1041 | goto fail_free_mtd; | |
1042 | } | |
1043 | clk_enable(info->clk); | |
1044 | ||
1045 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1046 | if (r == NULL) { | |
1047 | dev_err(&pdev->dev, "no resource defined for data DMA\n"); | |
1048 | ret = -ENXIO; | |
1049 | goto fail_put_clk; | |
1050 | } | |
1051 | info->drcmr_dat = r->start; | |
1052 | ||
1053 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1054 | if (r == NULL) { | |
1055 | dev_err(&pdev->dev, "no resource defined for command DMA\n"); | |
1056 | ret = -ENXIO; | |
1057 | goto fail_put_clk; | |
1058 | } | |
1059 | info->drcmr_cmd = r->start; | |
1060 | ||
1061 | irq = platform_get_irq(pdev, 0); | |
1062 | if (irq < 0) { | |
1063 | dev_err(&pdev->dev, "no IRQ resource defined\n"); | |
1064 | ret = -ENXIO; | |
1065 | goto fail_put_clk; | |
1066 | } | |
1067 | ||
1068 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1069 | if (r == NULL) { | |
1070 | dev_err(&pdev->dev, "no IO memory resource defined\n"); | |
1071 | ret = -ENODEV; | |
1072 | goto fail_put_clk; | |
1073 | } | |
1074 | ||
b2ed3680 | 1075 | r = request_mem_region(r->start, resource_size(r), pdev->name); |
fe69af00 | 1076 | if (r == NULL) { |
1077 | dev_err(&pdev->dev, "failed to request memory resource\n"); | |
1078 | ret = -EBUSY; | |
1079 | goto fail_put_clk; | |
1080 | } | |
1081 | ||
b2ed3680 | 1082 | info->mmio_base = ioremap(r->start, resource_size(r)); |
fe69af00 | 1083 | if (info->mmio_base == NULL) { |
1084 | dev_err(&pdev->dev, "ioremap() failed\n"); | |
1085 | ret = -ENODEV; | |
1086 | goto fail_free_res; | |
1087 | } | |
8638fac8 | 1088 | info->mmio_phys = r->start; |
fe69af00 | 1089 | |
1090 | ret = pxa3xx_nand_init_buff(info); | |
1091 | if (ret) | |
1092 | goto fail_free_io; | |
1093 | ||
346e1259 HZ |
1094 | /* initialize all interrupts to be disabled */ |
1095 | disable_int(info, NDSR_MASK); | |
1096 | ||
dbf5986a HZ |
1097 | ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED, |
1098 | pdev->name, info); | |
fe69af00 | 1099 | if (ret < 0) { |
1100 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
1101 | goto fail_free_buf; | |
1102 | } | |
1103 | ||
e353a20a | 1104 | platform_set_drvdata(pdev, info); |
fe69af00 | 1105 | |
d456882b | 1106 | return 0; |
fe69af00 | 1107 | |
fe69af00 | 1108 | fail_free_buf: |
401e67e2 | 1109 | free_irq(irq, info); |
fe69af00 | 1110 | if (use_dma) { |
1111 | pxa_free_dma(info->data_dma_ch); | |
d456882b | 1112 | dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, |
fe69af00 | 1113 | info->data_buff, info->data_buff_phys); |
1114 | } else | |
1115 | kfree(info->data_buff); | |
1116 | fail_free_io: | |
1117 | iounmap(info->mmio_base); | |
1118 | fail_free_res: | |
b2ed3680 | 1119 | release_mem_region(r->start, resource_size(r)); |
fe69af00 | 1120 | fail_put_clk: |
1121 | clk_disable(info->clk); | |
1122 | clk_put(info->clk); | |
1123 | fail_free_mtd: | |
d456882b LW |
1124 | kfree(info); |
1125 | return ret; | |
fe69af00 | 1126 | } |
1127 | ||
1128 | static int pxa3xx_nand_remove(struct platform_device *pdev) | |
1129 | { | |
e353a20a | 1130 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
82a72d10 | 1131 | struct resource *r; |
dbf5986a | 1132 | int irq; |
fe69af00 | 1133 | |
d456882b LW |
1134 | if (!info) |
1135 | return 0; | |
1136 | ||
fe69af00 | 1137 | platform_set_drvdata(pdev, NULL); |
1138 | ||
dbf5986a HZ |
1139 | irq = platform_get_irq(pdev, 0); |
1140 | if (irq >= 0) | |
1141 | free_irq(irq, info); | |
fe69af00 | 1142 | if (use_dma) { |
1143 | pxa_free_dma(info->data_dma_ch); | |
d456882b | 1144 | dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE, |
fe69af00 | 1145 | info->data_buff, info->data_buff_phys); |
1146 | } else | |
1147 | kfree(info->data_buff); | |
82a72d10 MR |
1148 | |
1149 | iounmap(info->mmio_base); | |
1150 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1151 | release_mem_region(r->start, resource_size(r)); | |
1152 | ||
1153 | clk_disable(info->clk); | |
1154 | clk_put(info->clk); | |
1155 | ||
d456882b LW |
1156 | nand_release(info->host->mtd); |
1157 | kfree(info); | |
fe69af00 | 1158 | return 0; |
1159 | } | |
1160 | ||
e353a20a LW |
1161 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
1162 | { | |
1163 | struct pxa3xx_nand_platform_data *pdata; | |
1164 | struct pxa3xx_nand_info *info; | |
d456882b | 1165 | int ret; |
e353a20a LW |
1166 | |
1167 | pdata = pdev->dev.platform_data; | |
1168 | if (!pdata) { | |
1169 | dev_err(&pdev->dev, "no platform data defined\n"); | |
1170 | return -ENODEV; | |
1171 | } | |
1172 | ||
d456882b LW |
1173 | ret = alloc_nand_resource(pdev); |
1174 | if (ret) { | |
1175 | dev_err(&pdev->dev, "alloc nand resource failed\n"); | |
1176 | return ret; | |
1177 | } | |
e353a20a | 1178 | |
d456882b LW |
1179 | info = platform_get_drvdata(pdev); |
1180 | if (pxa3xx_nand_scan(info->host->mtd)) { | |
e353a20a LW |
1181 | dev_err(&pdev->dev, "failed to scan nand\n"); |
1182 | pxa3xx_nand_remove(pdev); | |
1183 | return -ENODEV; | |
1184 | } | |
1185 | ||
d456882b | 1186 | return mtd_device_parse_register(info->host->mtd, NULL, 0, |
ee0f6a15 | 1187 | pdata->parts, pdata->nr_parts); |
e353a20a LW |
1188 | } |
1189 | ||
fe69af00 | 1190 | #ifdef CONFIG_PM |
1191 | static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) | |
1192 | { | |
e353a20a | 1193 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
051fc41c | 1194 | struct mtd_info *mtd = info->mtd; |
fe69af00 | 1195 | |
f8155a40 | 1196 | if (info->state) { |
fe69af00 | 1197 | dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); |
1198 | return -EAGAIN; | |
1199 | } | |
1200 | ||
051fc41c | 1201 | mtd->suspend(mtd); |
fe69af00 | 1202 | return 0; |
1203 | } | |
1204 | ||
1205 | static int pxa3xx_nand_resume(struct platform_device *pdev) | |
1206 | { | |
e353a20a | 1207 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
051fc41c LW |
1208 | struct mtd_info *mtd = info->mtd; |
1209 | ||
1210 | /* We don't want to handle interrupt without calling mtd routine */ | |
1211 | disable_int(info, NDCR_INT_MASK); | |
fe69af00 | 1212 | |
d456882b LW |
1213 | nand_writel(info, NDTR0CS0, info->host->ndtr0cs0); |
1214 | nand_writel(info, NDTR1CS0, info->host->ndtr1cs0); | |
fe69af00 | 1215 | |
051fc41c LW |
1216 | /* |
1217 | * As the spec says, the NDSR would be updated to 0x1800 when | |
1218 | * doing the nand_clk disable/enable. | |
1219 | * To prevent it damaging state machine of the driver, clear | |
1220 | * all status before resume | |
1221 | */ | |
1222 | nand_writel(info, NDSR, NDSR_MASK); | |
1223 | mtd->resume(mtd); | |
18c81b18 | 1224 | return 0; |
fe69af00 | 1225 | } |
1226 | #else | |
1227 | #define pxa3xx_nand_suspend NULL | |
1228 | #define pxa3xx_nand_resume NULL | |
1229 | #endif | |
1230 | ||
1231 | static struct platform_driver pxa3xx_nand_driver = { | |
1232 | .driver = { | |
1233 | .name = "pxa3xx-nand", | |
1234 | }, | |
1235 | .probe = pxa3xx_nand_probe, | |
1236 | .remove = pxa3xx_nand_remove, | |
1237 | .suspend = pxa3xx_nand_suspend, | |
1238 | .resume = pxa3xx_nand_resume, | |
1239 | }; | |
1240 | ||
1241 | static int __init pxa3xx_nand_init(void) | |
1242 | { | |
1243 | return platform_driver_register(&pxa3xx_nand_driver); | |
1244 | } | |
1245 | module_init(pxa3xx_nand_init); | |
1246 | ||
1247 | static void __exit pxa3xx_nand_exit(void) | |
1248 | { | |
1249 | platform_driver_unregister(&pxa3xx_nand_driver); | |
1250 | } | |
1251 | module_exit(pxa3xx_nand_exit); | |
1252 | ||
1253 | MODULE_LICENSE("GPL"); | |
1254 | MODULE_DESCRIPTION("PXA3xx NAND controller driver"); |