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mtd: nand: pxa3xx: Add a nice comment to pxa3xx_set_datasize()
[linux-2.6-block.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
de484a38
EG		 10 *
11 * See Documentation/mtd/nand/pxa3xx-nand.txt for more details.
fe69af00 12 */
13
a88bdbb5 14#include <linux/kernel.h>
fe69af00 15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/partitions.h>
a1c06ee1
DW		 24#include <linux/io.h>
25#include <linux/irq.h>
5a0e3ad6 26#include <linux/slab.h>
1e7ba630
DM		 27#include <linux/of.h>
28#include <linux/of_device.h>
fe69af00 29
f4db2e3a
EG		 30#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
31#define ARCH_HAS_DMA
32#endif
33
34#ifdef ARCH_HAS_DMA
afb5b5c9 35#include <mach/dma.h>
f4db2e3a
EG		 36#endif
37
293b2da1 38#include <linux/platform_data/mtd-nand-pxa3xx.h>
fe69af00 39
40#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
f8155a40 41#define NAND_STOP_DELAY (2 * HZ/50)
4eb2da89 42#define PAGE_CHUNK_SIZE (2048)
fe69af00 43
62e8b851
EG		 44/*
45 * Define a buffer size for the initial command that detects the flash device:
46 * STATUS, READID and PARAM. The largest of these is the PARAM command,
47 * needing 256 bytes.
48 */
49#define INIT_BUFFER_SIZE 256
50
fe69af00 51/* registers and bit definitions */
52#define NDCR (0x00) /* Control register */
53#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
54#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
55#define NDSR (0x14) /* Status Register */
56#define NDPCR (0x18) /* Page Count Register */
57#define NDBDR0 (0x1C) /* Bad Block Register 0 */
58#define NDBDR1 (0x20) /* Bad Block Register 1 */
59#define NDDB (0x40) /* Data Buffer */
60#define NDCB0 (0x48) /* Command Buffer0 */
61#define NDCB1 (0x4C) /* Command Buffer1 */
62#define NDCB2 (0x50) /* Command Buffer2 */
63
64#define NDCR_SPARE_EN (0x1 << 31)
65#define NDCR_ECC_EN (0x1 << 30)
66#define NDCR_DMA_EN (0x1 << 29)
67#define NDCR_ND_RUN (0x1 << 28)
68#define NDCR_DWIDTH_C (0x1 << 27)
69#define NDCR_DWIDTH_M (0x1 << 26)
70#define NDCR_PAGE_SZ (0x1 << 24)
71#define NDCR_NCSX (0x1 << 23)
72#define NDCR_ND_MODE (0x3 << 21)
73#define NDCR_NAND_MODE (0x0)
74#define NDCR_CLR_PG_CNT (0x1 << 20)
f8155a40 75#define NDCR_STOP_ON_UNCOR (0x1 << 19)
fe69af00 76#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
77#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
78
79#define NDCR_RA_START (0x1 << 15)
80#define NDCR_PG_PER_BLK (0x1 << 14)
81#define NDCR_ND_ARB_EN (0x1 << 12)
f8155a40 82#define NDCR_INT_MASK (0xFFF)
fe69af00 83
84#define NDSR_MASK (0xfff)
f8155a40
LW		 85#define NDSR_RDY (0x1 << 12)
86#define NDSR_FLASH_RDY (0x1 << 11)
fe69af00 87#define NDSR_CS0_PAGED (0x1 << 10)
88#define NDSR_CS1_PAGED (0x1 << 9)
89#define NDSR_CS0_CMDD (0x1 << 8)
90#define NDSR_CS1_CMDD (0x1 << 7)
91#define NDSR_CS0_BBD (0x1 << 6)
92#define NDSR_CS1_BBD (0x1 << 5)
93#define NDSR_DBERR (0x1 << 4)
94#define NDSR_SBERR (0x1 << 3)
95#define NDSR_WRDREQ (0x1 << 2)
96#define NDSR_RDDREQ (0x1 << 1)
97#define NDSR_WRCMDREQ (0x1)
98
41a63430 99#define NDCB0_LEN_OVRD (0x1 << 28)
4eb2da89 100#define NDCB0_ST_ROW_EN (0x1 << 26)
fe69af00 101#define NDCB0_AUTO_RS (0x1 << 25)
102#define NDCB0_CSEL (0x1 << 24)
103#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
104#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
105#define NDCB0_NC (0x1 << 20)
106#define NDCB0_DBC (0x1 << 19)
107#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
108#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
109#define NDCB0_CMD2_MASK (0xff << 8)
110#define NDCB0_CMD1_MASK (0xff)
111#define NDCB0_ADDR_CYC_SHIFT (16)
112
fe69af00 113/* macros for registers read/write */
114#define nand_writel(info, off, val) \
115 __raw_writel((val), (info)->mmio_base + (off))
116
117#define nand_readl(info, off) \
118 __raw_readl((info)->mmio_base + (off))
119
120/* error code and state */
121enum {
122 ERR_NONE = 0,
123 ERR_DMABUSERR = -1,
124 ERR_SENDCMD = -2,
125 ERR_DBERR = -3,
126 ERR_BBERR = -4,
223cf6c3 127 ERR_SBERR = -5,
fe69af00 128};
129
130enum {
f8155a40 131 STATE_IDLE = 0,
d456882b 132 STATE_PREPARED,
fe69af00 133 STATE_CMD_HANDLE,
134 STATE_DMA_READING,
135 STATE_DMA_WRITING,
136 STATE_DMA_DONE,
137 STATE_PIO_READING,
138 STATE_PIO_WRITING,
f8155a40
LW		 139 STATE_CMD_DONE,
140 STATE_READY,
fe69af00 141};
142
c0f3b864
EG		 143enum pxa3xx_nand_variant {
144 PXA3XX_NAND_VARIANT_PXA,
145 PXA3XX_NAND_VARIANT_ARMADA370,
146};
147
d456882b
LW		 148struct pxa3xx_nand_host {
149 struct nand_chip chip;
d456882b
LW		 150 struct mtd_info *mtd;
151 void *info_data;
152
153 /* page size of attached chip */
d456882b 154 int use_ecc;
f3c8cfc2 155 int cs;
fe69af00 156
d456882b
LW		 157 /* calculated from pxa3xx_nand_flash data */
158 unsigned int col_addr_cycles;
159 unsigned int row_addr_cycles;
160 size_t read_id_bytes;
161
d456882b
LW		 162};
163
164struct pxa3xx_nand_info {
401e67e2 165 struct nand_hw_control controller;
fe69af00 166 struct platform_device *pdev;
fe69af00 167
168 struct clk *clk;
169 void __iomem *mmio_base;
8638fac8 170 unsigned long mmio_phys;
d456882b 171 struct completion cmd_complete;
fe69af00 172
173 unsigned int buf_start;
174 unsigned int buf_count;
62e8b851 175 unsigned int buf_size;
fe69af00 176
177 /* DMA information */
178 int drcmr_dat;
179 int drcmr_cmd;
180
181 unsigned char *data_buff;
18c81b18 182 unsigned char *oob_buff;
fe69af00 183 dma_addr_t data_buff_phys;
fe69af00 184 int data_dma_ch;
185 struct pxa_dma_desc *data_desc;
186 dma_addr_t data_desc_addr;
187
f3c8cfc2 188 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
fe69af00 189 unsigned int state;
190
c0f3b864
EG		 191 /*
192 * This driver supports NFCv1 (as found in PXA SoC)
193 * and NFCv2 (as found in Armada 370/XP SoC).
194 */
195 enum pxa3xx_nand_variant variant;
196
f3c8cfc2 197 int cs;
fe69af00 198 int use_ecc; /* use HW ECC ? */
199 int use_dma; /* use DMA ? */
5bb653e8 200 int use_spare; /* use spare ? */
401e67e2 201 int is_ready;
fe69af00 202
2128b08c
EG		 203 unsigned int fifo_size; /* max. data size in the FIFO */
204 unsigned int data_size; /* data to be read from FIFO */
d456882b 205 unsigned int oob_size;
fe69af00 206 int retcode;
fe69af00 207
48cf7efa
EG		 208 /* cached register value */
209 uint32_t reg_ndcr;
210 uint32_t ndtr0cs0;
211 uint32_t ndtr1cs0;
212
fe69af00 213 /* generated NDCBx register values */
214 uint32_t ndcb0;
215 uint32_t ndcb1;
216 uint32_t ndcb2;
3a1a344a 217 uint32_t ndcb3;
fe69af00 218};
219
90ab5ee9 220static bool use_dma = 1;
fe69af00 221module_param(use_dma, bool, 0444);
25985edc 222MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
fe69af00 223
c1f82478 224static struct pxa3xx_nand_timing timing[] = {
227a886c
LW		 225 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
226 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
227 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
228 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
d3490dfd
HZ		 229};
230
c1f82478 231static struct pxa3xx_nand_flash builtin_flash_types[] = {
4332c116
LW		 232{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
233{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
234{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
235{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
236{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
237{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
238{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
239{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
240{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
d3490dfd
HZ		 241};
242
227a886c
LW		 243/* Define a default flash type setting serve as flash detecting only */
244#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
245
fe69af00 246#define NDTR0_tCH(c) (min((c), 7) << 19)
247#define NDTR0_tCS(c) (min((c), 7) << 16)
248#define NDTR0_tWH(c) (min((c), 7) << 11)
249#define NDTR0_tWP(c) (min((c), 7) << 8)
250#define NDTR0_tRH(c) (min((c), 7) << 3)
251#define NDTR0_tRP(c) (min((c), 7) << 0)
252
253#define NDTR1_tR(c) (min((c), 65535) << 16)
254#define NDTR1_tWHR(c) (min((c), 15) << 4)
255#define NDTR1_tAR(c) (min((c), 15) << 0)
256
257/* convert nano-seconds to nand flash controller clock cycles */
93b352fc 258#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
fe69af00 259
c7e9c7e7
EG		 260static struct of_device_id pxa3xx_nand_dt_ids[] = {
261 {
262 .compatible = "marvell,pxa3xx-nand",
263 .data = (void *)PXA3XX_NAND_VARIANT_PXA,
264 },
265 {}
266};
267MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
268
269static enum pxa3xx_nand_variant
270pxa3xx_nand_get_variant(struct platform_device *pdev)
271{
272 const struct of_device_id *of_id =
273 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
274 if (!of_id)
275 return PXA3XX_NAND_VARIANT_PXA;
276 return (enum pxa3xx_nand_variant)of_id->data;
277}
278
d456882b 279static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
7dad482e 280 const struct pxa3xx_nand_timing *t)
fe69af00 281{
d456882b 282 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 283 unsigned long nand_clk = clk_get_rate(info->clk);
284 uint32_t ndtr0, ndtr1;
285
286 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
287 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
288 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
289 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
290 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
291 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
292
293 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
294 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
295 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
296
48cf7efa
EG		 297 info->ndtr0cs0 = ndtr0;
298 info->ndtr1cs0 = ndtr1;
fe69af00 299 nand_writel(info, NDTR0CS0, ndtr0);
300 nand_writel(info, NDTR1CS0, ndtr1);
301}
302
6a3e4865
EG		 303/*
304 * Set the data and OOB size, depending on the selected
305 * spare and ECC configuration.
306 * Only applicable to READ0, READOOB and PAGEPROG commands.
307 */
18c81b18 308static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
fe69af00 309{
48cf7efa 310 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
9d8b1043 311
2128b08c 312 info->data_size = info->fifo_size;
9d8b1043
LW		 313 if (!oob_enable) {
314 info->oob_size = 0;
315 return;
316 }
317
2128b08c 318 switch (info->fifo_size) {
fe69af00 319 case 2048:
9d8b1043 320 info->oob_size = (info->use_ecc) ? 40 : 64;
fe69af00 321 break;
322 case 512:
9d8b1043 323 info->oob_size = (info->use_ecc) ? 8 : 16;
fe69af00 324 break;
fe69af00 325 }
18c81b18
LW		 326}
327
f8155a40
LW		 328/**
329 * NOTE: it is a must to set ND_RUN firstly, then write
330 * command buffer, otherwise, it does not work.
331 * We enable all the interrupt at the same time, and
332 * let pxa3xx_nand_irq to handle all logic.
333 */
334static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
335{
336 uint32_t ndcr;
337
48cf7efa 338 ndcr = info->reg_ndcr;
cd9d1182
EG		 339
340 if (info->use_ecc)
341 ndcr |= NDCR_ECC_EN;
342 else
343 ndcr &= ~NDCR_ECC_EN;
344
345 if (info->use_dma)
346 ndcr |= NDCR_DMA_EN;
347 else
348 ndcr &= ~NDCR_DMA_EN;
349
5bb653e8
EG		 350 if (info->use_spare)
351 ndcr |= NDCR_SPARE_EN;
352 else
353 ndcr &= ~NDCR_SPARE_EN;
354
f8155a40
LW		 355 ndcr |= NDCR_ND_RUN;
356
357 /* clear status bits and run */
358 nand_writel(info, NDCR, 0);
359 nand_writel(info, NDSR, NDSR_MASK);
360 nand_writel(info, NDCR, ndcr);
361}
362
363static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
364{
365 uint32_t ndcr;
366 int timeout = NAND_STOP_DELAY;
367
368 /* wait RUN bit in NDCR become 0 */
369 ndcr = nand_readl(info, NDCR);
370 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
371 ndcr = nand_readl(info, NDCR);
372 udelay(1);
373 }
374
375 if (timeout <= 0) {
376 ndcr &= ~NDCR_ND_RUN;
377 nand_writel(info, NDCR, ndcr);
378 }
379 /* clear status bits */
380 nand_writel(info, NDSR, NDSR_MASK);
381}
382
57ff88f0
EG		 383static void __maybe_unused
384enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
fe69af00 385{
386 uint32_t ndcr;
387
388 ndcr = nand_readl(info, NDCR);
389 nand_writel(info, NDCR, ndcr & ~int_mask);
390}
391
392static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
393{
394 uint32_t ndcr;
395
396 ndcr = nand_readl(info, NDCR);
397 nand_writel(info, NDCR, ndcr | int_mask);
398}
399
f8155a40 400static void handle_data_pio(struct pxa3xx_nand_info *info)
fe69af00 401{
fe69af00 402 switch (info->state) {
403 case STATE_PIO_WRITING:
404 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 405 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 406 if (info->oob_size > 0)
407 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
408 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 409 break;
410 case STATE_PIO_READING:
411 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 412 DIV_ROUND_UP(info->data_size, 4));
9d8b1043
LW		 413 if (info->oob_size > 0)
414 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
415 DIV_ROUND_UP(info->oob_size, 4));
fe69af00 416 break;
417 default:
da675b4e 418 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
fe69af00 419 info->state);
f8155a40 420 BUG();
fe69af00 421 }
fe69af00 422}
423
f4db2e3a 424#ifdef ARCH_HAS_DMA
f8155a40 425static void start_data_dma(struct pxa3xx_nand_info *info)
fe69af00 426{
427 struct pxa_dma_desc *desc = info->data_desc;
9d8b1043 428 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
fe69af00 429
430 desc->ddadr = DDADR_STOP;
431 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
432
f8155a40
LW		 433 switch (info->state) {
434 case STATE_DMA_WRITING:
fe69af00 435 desc->dsadr = info->data_buff_phys;
8638fac8 436 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 437 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
f8155a40
LW		 438 break;
439 case STATE_DMA_READING:
fe69af00 440 desc->dtadr = info->data_buff_phys;
8638fac8 441 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 442 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
f8155a40
LW		 443 break;
444 default:
da675b4e 445 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
f8155a40
LW		 446 info->state);
447 BUG();
fe69af00 448 }
449
450 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
451 DDADR(info->data_dma_ch) = info->data_desc_addr;
452 DCSR(info->data_dma_ch) |= DCSR_RUN;
453}
454
455static void pxa3xx_nand_data_dma_irq(int channel, void *data)
456{
457 struct pxa3xx_nand_info *info = data;
458 uint32_t dcsr;
459
460 dcsr = DCSR(channel);
461 DCSR(channel) = dcsr;
462
463 if (dcsr & DCSR_BUSERR) {
464 info->retcode = ERR_DMABUSERR;
fe69af00 465 }
466
f8155a40
LW		 467 info->state = STATE_DMA_DONE;
468 enable_int(info, NDCR_INT_MASK);
469 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
fe69af00 470}
f4db2e3a
EG		 471#else
472static void start_data_dma(struct pxa3xx_nand_info *info)
473{}
474#endif
fe69af00 475
476static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
477{
478 struct pxa3xx_nand_info *info = devid;
f8155a40 479 unsigned int status, is_completed = 0;
f3c8cfc2
LW		 480 unsigned int ready, cmd_done;
481
482 if (info->cs == 0) {
483 ready = NDSR_FLASH_RDY;
484 cmd_done = NDSR_CS0_CMDD;
485 } else {
486 ready = NDSR_RDY;
487 cmd_done = NDSR_CS1_CMDD;
488 }
fe69af00 489
490 status = nand_readl(info, NDSR);
491
f8155a40
LW		 492 if (status & NDSR_DBERR)
493 info->retcode = ERR_DBERR;
494 if (status & NDSR_SBERR)
495 info->retcode = ERR_SBERR;
496 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
497 /* whether use dma to transfer data */
fe69af00 498 if (info->use_dma) {
f8155a40
LW		 499 disable_int(info, NDCR_INT_MASK);
500 info->state = (status & NDSR_RDDREQ) ?
501 STATE_DMA_READING : STATE_DMA_WRITING;
502 start_data_dma(info);
503 goto NORMAL_IRQ_EXIT;
fe69af00 504 } else {
f8155a40
LW		 505 info->state = (status & NDSR_RDDREQ) ?
506 STATE_PIO_READING : STATE_PIO_WRITING;
507 handle_data_pio(info);
fe69af00 508 }
fe69af00 509 }
f3c8cfc2 510 if (status & cmd_done) {
f8155a40
LW		 511 info->state = STATE_CMD_DONE;
512 is_completed = 1;
fe69af00 513 }
f3c8cfc2 514 if (status & ready) {
401e67e2 515 info->is_ready = 1;
f8155a40 516 info->state = STATE_READY;
401e67e2 517 }
fe69af00 518
f8155a40
LW		 519 if (status & NDSR_WRCMDREQ) {
520 nand_writel(info, NDSR, NDSR_WRCMDREQ);
521 status &= ~NDSR_WRCMDREQ;
522 info->state = STATE_CMD_HANDLE;
3a1a344a
EG		 523
524 /*
525 * Command buffer registers NDCB{0-2} (and optionally NDCB3)
526 * must be loaded by writing directly either 12 or 16
527 * bytes directly to NDCB0, four bytes at a time.
528 *
529 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
530 * but each NDCBx register can be read.
531 */
f8155a40
LW		 532 nand_writel(info, NDCB0, info->ndcb0);
533 nand_writel(info, NDCB0, info->ndcb1);
534 nand_writel(info, NDCB0, info->ndcb2);
3a1a344a
EG		 535
536 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
537 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
538 nand_writel(info, NDCB0, info->ndcb3);
fe69af00 539 }
540
f8155a40
LW		 541 /* clear NDSR to let the controller exit the IRQ */
542 nand_writel(info, NDSR, status);
543 if (is_completed)
544 complete(&info->cmd_complete);
545NORMAL_IRQ_EXIT:
546 return IRQ_HANDLED;
fe69af00 547}
548
fe69af00 549static inline int is_buf_blank(uint8_t *buf, size_t len)
550{
551 for (; len > 0; len--)
552 if (*buf++ != 0xff)
553 return 0;
554 return 1;
555}
556
4eb2da89
LW		 557static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
558 uint16_t column, int page_addr)
fe69af00 559{
d456882b 560 int addr_cycle, exec_cmd;
f3c8cfc2
LW		 561 struct pxa3xx_nand_host *host;
562 struct mtd_info *mtd;
fe69af00 563
f3c8cfc2
LW		 564 host = info->host[info->cs];
565 mtd = host->mtd;
4eb2da89
LW		 566 addr_cycle = 0;
567 exec_cmd = 1;
568
569 /* reset data and oob column point to handle data */
401e67e2
LW		 570 info->buf_start = 0;
571 info->buf_count = 0;
4eb2da89
LW		 572 info->oob_size = 0;
573 info->use_ecc = 0;
5bb653e8 574 info->use_spare = 1;
401e67e2 575 info->is_ready = 0;
4eb2da89 576 info->retcode = ERR_NONE;
f3c8cfc2
LW		 577 if (info->cs != 0)
578 info->ndcb0 = NDCB0_CSEL;
579 else
580 info->ndcb0 = 0;
fe69af00 581
582 switch (command) {
4eb2da89
LW		 583 case NAND_CMD_READ0:
584 case NAND_CMD_PAGEPROG:
585 info->use_ecc = 1;
fe69af00 586 case NAND_CMD_READOOB:
4eb2da89 587 pxa3xx_set_datasize(info);
fe69af00 588 break;
41a63430
EG		 589 case NAND_CMD_PARAM:
590 info->use_spare = 0;
591 break;
4eb2da89
LW		 592 case NAND_CMD_SEQIN:
593 exec_cmd = 0;
594 break;
595 default:
596 info->ndcb1 = 0;
597 info->ndcb2 = 0;
3a1a344a 598 info->ndcb3 = 0;
4eb2da89
LW		 599 break;
600 }
601
d456882b
LW		 602 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
603 + host->col_addr_cycles);
fe69af00 604
4eb2da89
LW		 605 switch (command) {
606 case NAND_CMD_READOOB:
fe69af00 607 case NAND_CMD_READ0:
ec82135a
EG		 608 info->buf_start = column;
609 info->ndcb0 |= NDCB0_CMD_TYPE(0)
610 | addr_cycle
611 | NAND_CMD_READ0;
612
4eb2da89 613 if (command == NAND_CMD_READOOB)
ec82135a 614 info->buf_start += mtd->writesize;
4eb2da89 615
ec82135a 616 /* Second command setting for large pages */
0a3f3a19 617 if (mtd->writesize >= PAGE_CHUNK_SIZE)
ec82135a 618 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
fe69af00 619
fe69af00 620 case NAND_CMD_SEQIN:
4eb2da89 621 /* small page addr setting */
0a3f3a19 622 if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) {
4eb2da89
LW		 623 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
624 | (column & 0xFF);
625
626 info->ndcb2 = 0;
627 } else {
628 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
629 | (column & 0xFFFF);
630
631 if (page_addr & 0xFF0000)
632 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
633 else
634 info->ndcb2 = 0;
635 }
636
fe69af00 637 info->buf_count = mtd->writesize + mtd->oobsize;
4eb2da89 638 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 639
fe69af00 640 break;
4eb2da89 641
fe69af00 642 case NAND_CMD_PAGEPROG:
4eb2da89
LW		 643 if (is_buf_blank(info->data_buff,
644 (mtd->writesize + mtd->oobsize))) {
645 exec_cmd = 0;
646 break;
647 }
fe69af00 648
4eb2da89
LW		 649 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
650 | NDCB0_AUTO_RS
651 | NDCB0_ST_ROW_EN
652 | NDCB0_DBC
ec82135a
EG		 653 | (NAND_CMD_PAGEPROG << 8)
654 | NAND_CMD_SEQIN
4eb2da89 655 | addr_cycle;
fe69af00 656 break;
4eb2da89 657
ce0268f6 658 case NAND_CMD_PARAM:
ce0268f6
EG		 659 info->buf_count = 256;
660 info->ndcb0 |= NDCB0_CMD_TYPE(0)
661 | NDCB0_ADDR_CYC(1)
41a63430 662 | NDCB0_LEN_OVRD
ec82135a 663 | command;
ce0268f6 664 info->ndcb1 = (column & 0xFF);
41a63430 665 info->ndcb3 = 256;
ce0268f6
EG		 666 info->data_size = 256;
667 break;
668
fe69af00 669 case NAND_CMD_READID:
d456882b 670 info->buf_count = host->read_id_bytes;
4eb2da89
LW		 671 info->ndcb0 |= NDCB0_CMD_TYPE(3)
672 | NDCB0_ADDR_CYC(1)
ec82135a 673 | command;
d14231f1 674 info->ndcb1 = (column & 0xFF);
4eb2da89
LW		 675
676 info->data_size = 8;
677 break;
fe69af00 678 case NAND_CMD_STATUS:
4eb2da89
LW		 679 info->buf_count = 1;
680 info->ndcb0 |= NDCB0_CMD_TYPE(4)
681 | NDCB0_ADDR_CYC(1)
ec82135a 682 | command;
4eb2da89
LW		 683
684 info->data_size = 8;
685 break;
686
687 case NAND_CMD_ERASE1:
4eb2da89
LW		 688 info->ndcb0 |= NDCB0_CMD_TYPE(2)
689 | NDCB0_AUTO_RS
690 | NDCB0_ADDR_CYC(3)
691 | NDCB0_DBC
ec82135a
EG		 692 | (NAND_CMD_ERASE2 << 8)
693 | NAND_CMD_ERASE1;
4eb2da89
LW		 694 info->ndcb1 = page_addr;
695 info->ndcb2 = 0;
696
fe69af00 697 break;
698 case NAND_CMD_RESET:
4eb2da89 699 info->ndcb0 |= NDCB0_CMD_TYPE(5)
ec82135a 700 | command;
4eb2da89
LW		 701
702 break;
703
704 case NAND_CMD_ERASE2:
705 exec_cmd = 0;
fe69af00 706 break;
4eb2da89 707
fe69af00 708 default:
4eb2da89 709 exec_cmd = 0;
da675b4e
LW		 710 dev_err(&info->pdev->dev, "non-supported command %x\n",
711 command);
fe69af00 712 break;
713 }
714
4eb2da89
LW		 715 return exec_cmd;
716}
717
718static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
719 int column, int page_addr)
720{
d456882b
LW		 721 struct pxa3xx_nand_host *host = mtd->priv;
722 struct pxa3xx_nand_info *info = host->info_data;
4eb2da89
LW		 723 int ret, exec_cmd;
724
725 /*
726 * if this is a x16 device ,then convert the input
727 * "byte" address into a "word" address appropriate
728 * for indexing a word-oriented device
729 */
48cf7efa 730 if (info->reg_ndcr & NDCR_DWIDTH_M)
4eb2da89
LW		 731 column /= 2;
732
f3c8cfc2
LW		 733 /*
734 * There may be different NAND chip hooked to
735 * different chip select, so check whether
736 * chip select has been changed, if yes, reset the timing
737 */
738 if (info->cs != host->cs) {
739 info->cs = host->cs;
48cf7efa
EG		 740 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
741 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
f3c8cfc2
LW		 742 }
743
d456882b 744 info->state = STATE_PREPARED;
4eb2da89 745 exec_cmd = prepare_command_pool(info, command, column, page_addr);
f8155a40
LW		 746 if (exec_cmd) {
747 init_completion(&info->cmd_complete);
748 pxa3xx_nand_start(info);
749
750 ret = wait_for_completion_timeout(&info->cmd_complete,
751 CHIP_DELAY_TIMEOUT);
752 if (!ret) {
da675b4e 753 dev_err(&info->pdev->dev, "Wait time out!!!\n");
f8155a40
LW		 754 /* Stop State Machine for next command cycle */
755 pxa3xx_nand_stop(info);
756 }
f8155a40 757 }
d456882b 758 info->state = STATE_IDLE;
f8155a40
LW		 759}
760
fdbad98d 761static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
1fbb938d 762 struct nand_chip *chip, const uint8_t *buf, int oob_required)
f8155a40
LW		 763{
764 chip->write_buf(mtd, buf, mtd->writesize);
765 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 766
767 return 0;
f8155a40
LW		 768}
769
770static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
1fbb938d
BN		 771 struct nand_chip *chip, uint8_t *buf, int oob_required,
772 int page)
f8155a40 773{
d456882b
LW		 774 struct pxa3xx_nand_host *host = mtd->priv;
775 struct pxa3xx_nand_info *info = host->info_data;
4e86fd22 776 int max_bitflips = 0;
f8155a40
LW		 777
778 chip->read_buf(mtd, buf, mtd->writesize);
779 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
780
781 if (info->retcode == ERR_SBERR) {
782 switch (info->use_ecc) {
783 case 1:
4e86fd22 784 max_bitflips = 1;
f8155a40
LW		 785 mtd->ecc_stats.corrected++;
786 break;
787 case 0:
788 default:
789 break;
790 }
791 } else if (info->retcode == ERR_DBERR) {
792 /*
793 * for blank page (all 0xff), HW will calculate its ECC as
794 * 0, which is different from the ECC information within
795 * OOB, ignore such double bit errors
796 */
797 if (is_buf_blank(buf, mtd->writesize))
543e32d5
DM		 798 info->retcode = ERR_NONE;
799 else
f8155a40 800 mtd->ecc_stats.failed++;
fe69af00 801 }
f8155a40 802
4e86fd22 803 return max_bitflips;
fe69af00 804}
805
806static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
807{
d456882b
LW		 808 struct pxa3xx_nand_host *host = mtd->priv;
809 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 810 char retval = 0xFF;
811
812 if (info->buf_start < info->buf_count)
813 /* Has just send a new command? */
814 retval = info->data_buff[info->buf_start++];
815
816 return retval;
817}
818
819static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
820{
d456882b
LW		 821 struct pxa3xx_nand_host *host = mtd->priv;
822 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 823 u16 retval = 0xFFFF;
824
825 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
826 retval = *((u16 *)(info->data_buff+info->buf_start));
827 info->buf_start += 2;
828 }
829 return retval;
830}
831
832static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
833{
d456882b
LW		 834 struct pxa3xx_nand_host *host = mtd->priv;
835 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 836 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
837
838 memcpy(buf, info->data_buff + info->buf_start, real_len);
839 info->buf_start += real_len;
840}
841
842static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
843 const uint8_t *buf, int len)
844{
d456882b
LW		 845 struct pxa3xx_nand_host *host = mtd->priv;
846 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 847 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
848
849 memcpy(info->data_buff + info->buf_start, buf, real_len);
850 info->buf_start += real_len;
851}
852
fe69af00 853static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
854{
855 return;
856}
857
858static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
859{
d456882b
LW		 860 struct pxa3xx_nand_host *host = mtd->priv;
861 struct pxa3xx_nand_info *info = host->info_data;
fe69af00 862
863 /* pxa3xx_nand_send_command has waited for command complete */
864 if (this->state == FL_WRITING || this->state == FL_ERASING) {
865 if (info->retcode == ERR_NONE)
866 return 0;
867 else {
868 /*
869 * any error make it return 0x01 which will tell
870 * the caller the erase and write fail
871 */
872 return 0x01;
873 }
874 }
875
876 return 0;
877}
878
fe69af00 879static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 880 const struct pxa3xx_nand_flash *f)
fe69af00 881{
882 struct platform_device *pdev = info->pdev;
453810b7 883 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
f3c8cfc2 884 struct pxa3xx_nand_host *host = info->host[info->cs];
f8155a40 885 uint32_t ndcr = 0x0; /* enable all interrupts */
fe69af00 886
da675b4e
LW		 887 if (f->page_size != 2048 && f->page_size != 512) {
888 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
fe69af00 889 return -EINVAL;
da675b4e 890 }
fe69af00 891
da675b4e
LW		 892 if (f->flash_width != 16 && f->flash_width != 8) {
893 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
fe69af00 894 return -EINVAL;
da675b4e 895 }
fe69af00 896
897 /* calculate flash information */
d456882b 898 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 899
900 /* calculate addressing information */
d456882b 901 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 902
903 if (f->num_blocks * f->page_per_block > 65536)
d456882b 904 host->row_addr_cycles = 3;
fe69af00 905 else
d456882b 906 host->row_addr_cycles = 2;
fe69af00 907
908 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
d456882b 909 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 910 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
911 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
912 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
913 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
914
d456882b 915 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
fe69af00 916 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
917
48cf7efa 918 info->reg_ndcr = ndcr;
fe69af00 919
d456882b 920 pxa3xx_nand_set_timing(host, f->timing);
fe69af00 921 return 0;
922}
923
f271049e
MR		 924static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
925{
f3c8cfc2
LW		 926 /*
927 * We set 0 by hard coding here, for we don't support keep_config
928 * when there is more than one chip attached to the controller
929 */
930 struct pxa3xx_nand_host *host = info->host[0];
f271049e 931 uint32_t ndcr = nand_readl(info, NDCR);
f271049e 932
d456882b 933 if (ndcr & NDCR_PAGE_SZ) {
2128b08c
EG		 934 /* Controller's FIFO size */
935 info->fifo_size = 2048;
d456882b
LW		 936 host->read_id_bytes = 4;
937 } else {
2128b08c 938 info->fifo_size = 512;
d456882b
LW		 939 host->read_id_bytes = 2;
940 }
941
48cf7efa
EG		 942 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
943 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
944 info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
f271049e
MR		 945 return 0;
946}
947
f4db2e3a 948#ifdef ARCH_HAS_DMA
fe69af00 949static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
950{
951 struct platform_device *pdev = info->pdev;
62e8b851 952 int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc);
fe69af00 953
954 if (use_dma == 0) {
62e8b851 955 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
fe69af00 956 if (info->data_buff == NULL)
957 return -ENOMEM;
958 return 0;
959 }
960
62e8b851 961 info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size,
fe69af00 962 &info->data_buff_phys, GFP_KERNEL);
963 if (info->data_buff == NULL) {
964 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
965 return -ENOMEM;
966 }
967
fe69af00 968 info->data_desc = (void *)info->data_buff + data_desc_offset;
969 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
970
971 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
972 pxa3xx_nand_data_dma_irq, info);
973 if (info->data_dma_ch < 0) {
974 dev_err(&pdev->dev, "failed to request data dma\n");
62e8b851 975 dma_free_coherent(&pdev->dev, info->buf_size,
fe69af00 976 info->data_buff, info->data_buff_phys);
977 return info->data_dma_ch;
978 }
979
95b26563
EG		 980 /*
981 * Now that DMA buffers are allocated we turn on
982 * DMA proper for I/O operations.
983 */
984 info->use_dma = 1;
fe69af00 985 return 0;
986}
987
498b6145
EG		 988static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
989{
990 struct platform_device *pdev = info->pdev;
15b540c7 991 if (info->use_dma) {
498b6145 992 pxa_free_dma(info->data_dma_ch);
62e8b851 993 dma_free_coherent(&pdev->dev, info->buf_size,
498b6145
EG		 994 info->data_buff, info->data_buff_phys);
995 } else {
996 kfree(info->data_buff);
997 }
998}
f4db2e3a
EG		 999#else
1000static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1001{
62e8b851 1002 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
f4db2e3a
EG		 1003 if (info->data_buff == NULL)
1004 return -ENOMEM;
1005 return 0;
1006}
1007
1008static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
1009{
1010 kfree(info->data_buff);
1011}
1012#endif
498b6145 1013
401e67e2
LW		 1014static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
1015{
f3c8cfc2 1016 struct mtd_info *mtd;
2d79ab16 1017 struct nand_chip *chip;
d456882b 1018 int ret;
2d79ab16 1019
f3c8cfc2 1020 mtd = info->host[info->cs]->mtd;
2d79ab16
EG		 1021 chip = mtd->priv;
1022
401e67e2 1023 /* use the common timing to make a try */
d456882b
LW		 1024 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
1025 if (ret)
1026 return ret;
1027
2d79ab16 1028 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
401e67e2 1029 if (info->is_ready)
401e67e2 1030 return 0;
d456882b
LW		 1031
1032 return -ENODEV;
401e67e2 1033}
fe69af00 1034
401e67e2 1035static int pxa3xx_nand_scan(struct mtd_info *mtd)
fe69af00 1036{
d456882b
LW		 1037 struct pxa3xx_nand_host *host = mtd->priv;
1038 struct pxa3xx_nand_info *info = host->info_data;
401e67e2 1039 struct platform_device *pdev = info->pdev;
453810b7 1040 struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
0fab028b 1041 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
401e67e2
LW		 1042 const struct pxa3xx_nand_flash *f = NULL;
1043 struct nand_chip *chip = mtd->priv;
1044 uint32_t id = -1;
4332c116 1045 uint64_t chipsize;
401e67e2
LW		 1046 int i, ret, num;
1047
1048 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
4332c116 1049 goto KEEP_CONFIG;
401e67e2
LW		 1050
1051 ret = pxa3xx_nand_sensing(info);
d456882b 1052 if (ret) {
f3c8cfc2
LW		 1053 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
1054 info->cs);
401e67e2 1055
d456882b 1056 return ret;
401e67e2
LW		 1057 }
1058
1059 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
1060 id = *((uint16_t *)(info->data_buff));
1061 if (id != 0)
da675b4e 1062 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
401e67e2 1063 else {
da675b4e
LW		 1064 dev_warn(&info->pdev->dev,
1065 "Read out ID 0, potential timing set wrong!!\n");
401e67e2
LW		 1066
1067 return -EINVAL;
1068 }
1069
1070 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1071 for (i = 0; i < num; i++) {
1072 if (i < pdata->num_flash)
1073 f = pdata->flash + i;
1074 else
1075 f = &builtin_flash_types[i - pdata->num_flash + 1];
1076
1077 /* find the chip in default list */
4332c116 1078 if (f->chip_id == id)
401e67e2 1079 break;
401e67e2
LW		 1080 }
1081
4332c116 1082 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
da675b4e 1083 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
401e67e2
LW		 1084
1085 return -EINVAL;
1086 }
1087
d456882b
LW		 1088 ret = pxa3xx_nand_config_flash(info, f);
1089 if (ret) {
1090 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1091 return ret;
1092 }
1093
4332c116 1094 pxa3xx_flash_ids[0].name = f->name;
68aa352d 1095 pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
4332c116
LW		 1096 pxa3xx_flash_ids[0].pagesize = f->page_size;
1097 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1098 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1099 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1100 if (f->flash_width == 16)
1101 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
0fab028b
LW		 1102 pxa3xx_flash_ids[1].name = NULL;
1103 def = pxa3xx_flash_ids;
4332c116 1104KEEP_CONFIG:
d456882b 1105 chip->ecc.mode = NAND_ECC_HW;
0a3f3a19 1106 chip->ecc.size = info->fifo_size;
6a918bad 1107 chip->ecc.strength = 1;
d456882b 1108
48cf7efa 1109 if (info->reg_ndcr & NDCR_DWIDTH_M)
d456882b
LW		 1110 chip->options |= NAND_BUSWIDTH_16;
1111
0fab028b 1112 if (nand_scan_ident(mtd, 1, def))
4332c116
LW		 1113 return -ENODEV;
1114 /* calculate addressing information */
d456882b
LW		 1115 if (mtd->writesize >= 2048)
1116 host->col_addr_cycles = 2;
1117 else
1118 host->col_addr_cycles = 1;
1119
62e8b851
EG		 1120 /* release the initial buffer */
1121 kfree(info->data_buff);
1122
1123 /* allocate the real data + oob buffer */
1124 info->buf_size = mtd->writesize + mtd->oobsize;
1125 ret = pxa3xx_nand_init_buff(info);
1126 if (ret)
1127 return ret;
4332c116 1128 info->oob_buff = info->data_buff + mtd->writesize;
62e8b851 1129
4332c116 1130 if ((mtd->size >> chip->page_shift) > 65536)
d456882b 1131 host->row_addr_cycles = 3;
4332c116 1132 else
d456882b 1133 host->row_addr_cycles = 2;
401e67e2 1134 return nand_scan_tail(mtd);
fe69af00 1135}
1136
d456882b 1137static int alloc_nand_resource(struct platform_device *pdev)
fe69af00 1138{
f3c8cfc2 1139 struct pxa3xx_nand_platform_data *pdata;
fe69af00 1140 struct pxa3xx_nand_info *info;
d456882b 1141 struct pxa3xx_nand_host *host;
6e308f87 1142 struct nand_chip *chip = NULL;
fe69af00 1143 struct mtd_info *mtd;
1144 struct resource *r;
f3c8cfc2 1145 int ret, irq, cs;
fe69af00 1146
453810b7 1147 pdata = dev_get_platdata(&pdev->dev);
4c073cd2
EG		 1148 info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1149 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1150 if (!info)
d456882b 1151 return -ENOMEM;
fe69af00 1152
fe69af00 1153 info->pdev = pdev;
c7e9c7e7 1154 info->variant = pxa3xx_nand_get_variant(pdev);
f3c8cfc2
LW		 1155 for (cs = 0; cs < pdata->num_cs; cs++) {
1156 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1157 (sizeof(*mtd) + sizeof(*host)) * cs);
1158 chip = (struct nand_chip *)(&mtd[1]);
1159 host = (struct pxa3xx_nand_host *)chip;
1160 info->host[cs] = host;
1161 host->mtd = mtd;
1162 host->cs = cs;
1163 host->info_data = info;
1164 mtd->priv = host;
1165 mtd->owner = THIS_MODULE;
1166
1167 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1168 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1169 chip->controller = &info->controller;
1170 chip->waitfunc = pxa3xx_nand_waitfunc;
1171 chip->select_chip = pxa3xx_nand_select_chip;
1172 chip->cmdfunc = pxa3xx_nand_cmdfunc;
1173 chip->read_word = pxa3xx_nand_read_word;
1174 chip->read_byte = pxa3xx_nand_read_byte;
1175 chip->read_buf = pxa3xx_nand_read_buf;
1176 chip->write_buf = pxa3xx_nand_write_buf;
664c7f5e 1177 chip->options |= NAND_NO_SUBPAGE_WRITE;
f3c8cfc2 1178 }
401e67e2
LW		 1179
1180 spin_lock_init(&chip->controller->lock);
1181 init_waitqueue_head(&chip->controller->wq);
9ca7944d 1182 info->clk = devm_clk_get(&pdev->dev, NULL);
fe69af00 1183 if (IS_ERR(info->clk)) {
1184 dev_err(&pdev->dev, "failed to get nand clock\n");
4c073cd2 1185 return PTR_ERR(info->clk);
fe69af00 1186 }
1f8eaff2
EG		 1187 ret = clk_prepare_enable(info->clk);
1188 if (ret < 0)
1189 return ret;
fe69af00 1190
6b45c1ee
EG		 1191 if (use_dma) {
1192 /*
1193 * This is a dirty hack to make this driver work from
1194 * devicetree bindings. It can be removed once we have
1195 * a prober DMA controller framework for DT.
1196 */
1197 if (pdev->dev.of_node &&
1198 of_machine_is_compatible("marvell,pxa3xx")) {
1199 info->drcmr_dat = 97;
1200 info->drcmr_cmd = 99;
1201 } else {
1202 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1203 if (r == NULL) {
1204 dev_err(&pdev->dev,
1205 "no resource defined for data DMA\n");
1206 ret = -ENXIO;
1207 goto fail_disable_clk;
1208 }
1209 info->drcmr_dat = r->start;
1210
1211 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1212 if (r == NULL) {
1213 dev_err(&pdev->dev,
1214 "no resource defined for cmd DMA\n");
1215 ret = -ENXIO;
1216 goto fail_disable_clk;
1217 }
1218 info->drcmr_cmd = r->start;
1e7ba630 1219 }
fe69af00 1220 }
fe69af00 1221
1222 irq = platform_get_irq(pdev, 0);
1223 if (irq < 0) {
1224 dev_err(&pdev->dev, "no IRQ resource defined\n");
1225 ret = -ENXIO;
9ca7944d 1226 goto fail_disable_clk;
fe69af00 1227 }
1228
1229 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0ddd846f
EG		 1230 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1231 if (IS_ERR(info->mmio_base)) {
1232 ret = PTR_ERR(info->mmio_base);
9ca7944d 1233 goto fail_disable_clk;
fe69af00 1234 }
8638fac8 1235 info->mmio_phys = r->start;
fe69af00 1236
62e8b851
EG		 1237 /* Allocate a buffer to allow flash detection */
1238 info->buf_size = INIT_BUFFER_SIZE;
1239 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
1240 if (info->data_buff == NULL) {
1241 ret = -ENOMEM;
9ca7944d 1242 goto fail_disable_clk;
62e8b851 1243 }
fe69af00 1244
346e1259
HZ		 1245 /* initialize all interrupts to be disabled */
1246 disable_int(info, NDSR_MASK);
1247
b1eb234f 1248 ret = request_irq(irq, pxa3xx_nand_irq, 0, pdev->name, info);
fe69af00 1249 if (ret < 0) {
1250 dev_err(&pdev->dev, "failed to request IRQ\n");
1251 goto fail_free_buf;
1252 }
1253
e353a20a 1254 platform_set_drvdata(pdev, info);
fe69af00 1255
d456882b 1256 return 0;
fe69af00 1257
fe69af00 1258fail_free_buf:
401e67e2 1259 free_irq(irq, info);
62e8b851 1260 kfree(info->data_buff);
9ca7944d 1261fail_disable_clk:
fb32061f 1262 clk_disable_unprepare(info->clk);
d456882b 1263 return ret;
fe69af00 1264}
1265
1266static int pxa3xx_nand_remove(struct platform_device *pdev)
1267{
e353a20a 1268 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2 1269 struct pxa3xx_nand_platform_data *pdata;
f3c8cfc2 1270 int irq, cs;
fe69af00 1271
d456882b
LW		 1272 if (!info)
1273 return 0;
1274
453810b7 1275 pdata = dev_get_platdata(&pdev->dev);
fe69af00 1276
dbf5986a
HZ		 1277 irq = platform_get_irq(pdev, 0);
1278 if (irq >= 0)
1279 free_irq(irq, info);
498b6145 1280 pxa3xx_nand_free_buff(info);
82a72d10 1281
fb32061f 1282 clk_disable_unprepare(info->clk);
82a72d10 1283
f3c8cfc2
LW		 1284 for (cs = 0; cs < pdata->num_cs; cs++)
1285 nand_release(info->host[cs]->mtd);
fe69af00 1286 return 0;
1287}
1288
1e7ba630
DM		 1289static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1290{
1291 struct pxa3xx_nand_platform_data *pdata;
1292 struct device_node *np = pdev->dev.of_node;
1293 const struct of_device_id *of_id =
1294 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1295
1296 if (!of_id)
1297 return 0;
1298
1299 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1300 if (!pdata)
1301 return -ENOMEM;
1302
1303 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1304 pdata->enable_arbiter = 1;
1305 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1306 pdata->keep_config = 1;
1307 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1308
1309 pdev->dev.platform_data = pdata;
1310
1311 return 0;
1312}
1e7ba630 1313
e353a20a
LW		 1314static int pxa3xx_nand_probe(struct platform_device *pdev)
1315{
1316 struct pxa3xx_nand_platform_data *pdata;
1e7ba630 1317 struct mtd_part_parser_data ppdata = {};
e353a20a 1318 struct pxa3xx_nand_info *info;
f3c8cfc2 1319 int ret, cs, probe_success;
e353a20a 1320
f4db2e3a
EG		 1321#ifndef ARCH_HAS_DMA
1322 if (use_dma) {
1323 use_dma = 0;
1324 dev_warn(&pdev->dev,
1325 "This platform can't do DMA on this device\n");
1326 }
1327#endif
1e7ba630
DM		 1328 ret = pxa3xx_nand_probe_dt(pdev);
1329 if (ret)
1330 return ret;
1331
453810b7 1332 pdata = dev_get_platdata(&pdev->dev);
e353a20a
LW		 1333 if (!pdata) {
1334 dev_err(&pdev->dev, "no platform data defined\n");
1335 return -ENODEV;
1336 }
1337
d456882b
LW		 1338 ret = alloc_nand_resource(pdev);
1339 if (ret) {
1340 dev_err(&pdev->dev, "alloc nand resource failed\n");
1341 return ret;
1342 }
e353a20a 1343
d456882b 1344 info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1345 probe_success = 0;
1346 for (cs = 0; cs < pdata->num_cs; cs++) {
b7655bcb 1347 struct mtd_info *mtd = info->host[cs]->mtd;
f455578d 1348
18a84e93
EG		 1349 /*
1350 * The mtd name matches the one used in 'mtdparts' kernel
1351 * parameter. This name cannot be changed or otherwise
1352 * user's mtd partitions configuration would get broken.
1353 */
1354 mtd->name = "pxa3xx_nand-0";
f3c8cfc2 1355 info->cs = cs;
b7655bcb 1356 ret = pxa3xx_nand_scan(mtd);
f3c8cfc2
LW		 1357 if (ret) {
1358 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1359 cs);
1360 continue;
1361 }
1362
1e7ba630 1363 ppdata.of_node = pdev->dev.of_node;
b7655bcb 1364 ret = mtd_device_parse_register(mtd, NULL,
1e7ba630 1365 &ppdata, pdata->parts[cs],
42d7fbe2 1366 pdata->nr_parts[cs]);
f3c8cfc2
LW		 1367 if (!ret)
1368 probe_success = 1;
1369 }
1370
1371 if (!probe_success) {
e353a20a
LW		 1372 pxa3xx_nand_remove(pdev);
1373 return -ENODEV;
1374 }
1375
f3c8cfc2 1376 return 0;
e353a20a
LW		 1377}
1378
fe69af00 1379#ifdef CONFIG_PM
1380static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1381{
e353a20a 1382 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1383 struct pxa3xx_nand_platform_data *pdata;
1384 struct mtd_info *mtd;
1385 int cs;
fe69af00 1386
453810b7 1387 pdata = dev_get_platdata(&pdev->dev);
f8155a40 1388 if (info->state) {
fe69af00 1389 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1390 return -EAGAIN;
1391 }
1392
f3c8cfc2
LW		 1393 for (cs = 0; cs < pdata->num_cs; cs++) {
1394 mtd = info->host[cs]->mtd;
3fe4bae8 1395 mtd_suspend(mtd);
f3c8cfc2
LW		 1396 }
1397
fe69af00 1398 return 0;
1399}
1400
1401static int pxa3xx_nand_resume(struct platform_device *pdev)
1402{
e353a20a 1403 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
f3c8cfc2
LW		 1404 struct pxa3xx_nand_platform_data *pdata;
1405 struct mtd_info *mtd;
1406 int cs;
051fc41c 1407
453810b7 1408 pdata = dev_get_platdata(&pdev->dev);
051fc41c
LW		 1409 /* We don't want to handle interrupt without calling mtd routine */
1410 disable_int(info, NDCR_INT_MASK);
fe69af00 1411
f3c8cfc2
LW		 1412 /*
1413 * Directly set the chip select to a invalid value,
1414 * then the driver would reset the timing according
1415 * to current chip select at the beginning of cmdfunc
1416 */
1417 info->cs = 0xff;
fe69af00 1418
051fc41c
LW		 1419 /*
1420 * As the spec says, the NDSR would be updated to 0x1800 when
1421 * doing the nand_clk disable/enable.
1422 * To prevent it damaging state machine of the driver, clear
1423 * all status before resume
1424 */
1425 nand_writel(info, NDSR, NDSR_MASK);
f3c8cfc2
LW		 1426 for (cs = 0; cs < pdata->num_cs; cs++) {
1427 mtd = info->host[cs]->mtd;
ead995f8 1428 mtd_resume(mtd);
f3c8cfc2
LW		 1429 }
1430
18c81b18 1431 return 0;
fe69af00 1432}
1433#else
1434#define pxa3xx_nand_suspend NULL
1435#define pxa3xx_nand_resume NULL
1436#endif
1437
1438static struct platform_driver pxa3xx_nand_driver = {
1439 .driver = {
1440 .name = "pxa3xx-nand",
5576bc7b 1441 .of_match_table = pxa3xx_nand_dt_ids,
fe69af00 1442 },
1443 .probe = pxa3xx_nand_probe,
1444 .remove = pxa3xx_nand_remove,
1445 .suspend = pxa3xx_nand_suspend,
1446 .resume = pxa3xx_nand_resume,
1447};
1448
f99640de 1449module_platform_driver(pxa3xx_nand_driver);
fe69af00 1450
1451MODULE_LICENSE("GPL");
1452MODULE_DESCRIPTION("PXA3xx NAND controller driver");
Linux 6.x block layer and io_uring tree(s)