Commit | Line | Data |
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fe69af00 | 1 | /* |
2 | * drivers/mtd/nand/pxa3xx_nand.c | |
3 | * | |
4 | * Copyright © 2005 Intel Corporation | |
5 | * Copyright © 2006 Marvell International Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
de484a38 EG |
10 | * |
11 | * See Documentation/mtd/nand/pxa3xx-nand.txt for more details. | |
fe69af00 | 12 | */ |
13 | ||
a88bdbb5 | 14 | #include <linux/kernel.h> |
fe69af00 | 15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/mtd/mtd.h> | |
22 | #include <linux/mtd/nand.h> | |
23 | #include <linux/mtd/partitions.h> | |
a1c06ee1 DW |
24 | #include <linux/io.h> |
25 | #include <linux/irq.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
1e7ba630 DM |
27 | #include <linux/of.h> |
28 | #include <linux/of_device.h> | |
776f265e | 29 | #include <linux/of_mtd.h> |
fe69af00 | 30 | |
f4db2e3a EG |
31 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
32 | #define ARCH_HAS_DMA | |
33 | #endif | |
34 | ||
35 | #ifdef ARCH_HAS_DMA | |
afb5b5c9 | 36 | #include <mach/dma.h> |
f4db2e3a EG |
37 | #endif |
38 | ||
293b2da1 | 39 | #include <linux/platform_data/mtd-nand-pxa3xx.h> |
fe69af00 | 40 | |
55d9fd6e | 41 | #define NAND_DEV_READY_TIMEOUT 50 |
fe69af00 | 42 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) |
f8155a40 | 43 | #define NAND_STOP_DELAY (2 * HZ/50) |
4eb2da89 | 44 | #define PAGE_CHUNK_SIZE (2048) |
fe69af00 | 45 | |
62e8b851 EG |
46 | /* |
47 | * Define a buffer size for the initial command that detects the flash device: | |
48 | * STATUS, READID and PARAM. The largest of these is the PARAM command, | |
49 | * needing 256 bytes. | |
50 | */ | |
51 | #define INIT_BUFFER_SIZE 256 | |
52 | ||
fe69af00 | 53 | /* registers and bit definitions */ |
54 | #define NDCR (0x00) /* Control register */ | |
55 | #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ | |
56 | #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ | |
57 | #define NDSR (0x14) /* Status Register */ | |
58 | #define NDPCR (0x18) /* Page Count Register */ | |
59 | #define NDBDR0 (0x1C) /* Bad Block Register 0 */ | |
60 | #define NDBDR1 (0x20) /* Bad Block Register 1 */ | |
43bcfd2b | 61 | #define NDECCCTRL (0x28) /* ECC control */ |
fe69af00 | 62 | #define NDDB (0x40) /* Data Buffer */ |
63 | #define NDCB0 (0x48) /* Command Buffer0 */ | |
64 | #define NDCB1 (0x4C) /* Command Buffer1 */ | |
65 | #define NDCB2 (0x50) /* Command Buffer2 */ | |
66 | ||
67 | #define NDCR_SPARE_EN (0x1 << 31) | |
68 | #define NDCR_ECC_EN (0x1 << 30) | |
69 | #define NDCR_DMA_EN (0x1 << 29) | |
70 | #define NDCR_ND_RUN (0x1 << 28) | |
71 | #define NDCR_DWIDTH_C (0x1 << 27) | |
72 | #define NDCR_DWIDTH_M (0x1 << 26) | |
73 | #define NDCR_PAGE_SZ (0x1 << 24) | |
74 | #define NDCR_NCSX (0x1 << 23) | |
75 | #define NDCR_ND_MODE (0x3 << 21) | |
76 | #define NDCR_NAND_MODE (0x0) | |
77 | #define NDCR_CLR_PG_CNT (0x1 << 20) | |
f8155a40 | 78 | #define NDCR_STOP_ON_UNCOR (0x1 << 19) |
fe69af00 | 79 | #define NDCR_RD_ID_CNT_MASK (0x7 << 16) |
80 | #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) | |
81 | ||
82 | #define NDCR_RA_START (0x1 << 15) | |
83 | #define NDCR_PG_PER_BLK (0x1 << 14) | |
84 | #define NDCR_ND_ARB_EN (0x1 << 12) | |
f8155a40 | 85 | #define NDCR_INT_MASK (0xFFF) |
fe69af00 | 86 | |
87 | #define NDSR_MASK (0xfff) | |
f8155a40 LW |
88 | #define NDSR_RDY (0x1 << 12) |
89 | #define NDSR_FLASH_RDY (0x1 << 11) | |
fe69af00 | 90 | #define NDSR_CS0_PAGED (0x1 << 10) |
91 | #define NDSR_CS1_PAGED (0x1 << 9) | |
92 | #define NDSR_CS0_CMDD (0x1 << 8) | |
93 | #define NDSR_CS1_CMDD (0x1 << 7) | |
94 | #define NDSR_CS0_BBD (0x1 << 6) | |
95 | #define NDSR_CS1_BBD (0x1 << 5) | |
96 | #define NDSR_DBERR (0x1 << 4) | |
97 | #define NDSR_SBERR (0x1 << 3) | |
98 | #define NDSR_WRDREQ (0x1 << 2) | |
99 | #define NDSR_RDDREQ (0x1 << 1) | |
100 | #define NDSR_WRCMDREQ (0x1) | |
101 | ||
41a63430 | 102 | #define NDCB0_LEN_OVRD (0x1 << 28) |
4eb2da89 | 103 | #define NDCB0_ST_ROW_EN (0x1 << 26) |
fe69af00 | 104 | #define NDCB0_AUTO_RS (0x1 << 25) |
105 | #define NDCB0_CSEL (0x1 << 24) | |
106 | #define NDCB0_CMD_TYPE_MASK (0x7 << 21) | |
107 | #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) | |
108 | #define NDCB0_NC (0x1 << 20) | |
109 | #define NDCB0_DBC (0x1 << 19) | |
110 | #define NDCB0_ADDR_CYC_MASK (0x7 << 16) | |
111 | #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) | |
112 | #define NDCB0_CMD2_MASK (0xff << 8) | |
113 | #define NDCB0_CMD1_MASK (0xff) | |
114 | #define NDCB0_ADDR_CYC_SHIFT (16) | |
115 | ||
fe69af00 | 116 | /* macros for registers read/write */ |
117 | #define nand_writel(info, off, val) \ | |
118 | __raw_writel((val), (info)->mmio_base + (off)) | |
119 | ||
120 | #define nand_readl(info, off) \ | |
121 | __raw_readl((info)->mmio_base + (off)) | |
122 | ||
123 | /* error code and state */ | |
124 | enum { | |
125 | ERR_NONE = 0, | |
126 | ERR_DMABUSERR = -1, | |
127 | ERR_SENDCMD = -2, | |
128 | ERR_DBERR = -3, | |
129 | ERR_BBERR = -4, | |
223cf6c3 | 130 | ERR_SBERR = -5, |
fe69af00 | 131 | }; |
132 | ||
133 | enum { | |
f8155a40 | 134 | STATE_IDLE = 0, |
d456882b | 135 | STATE_PREPARED, |
fe69af00 | 136 | STATE_CMD_HANDLE, |
137 | STATE_DMA_READING, | |
138 | STATE_DMA_WRITING, | |
139 | STATE_DMA_DONE, | |
140 | STATE_PIO_READING, | |
141 | STATE_PIO_WRITING, | |
f8155a40 LW |
142 | STATE_CMD_DONE, |
143 | STATE_READY, | |
fe69af00 | 144 | }; |
145 | ||
c0f3b864 EG |
146 | enum pxa3xx_nand_variant { |
147 | PXA3XX_NAND_VARIANT_PXA, | |
148 | PXA3XX_NAND_VARIANT_ARMADA370, | |
149 | }; | |
150 | ||
d456882b LW |
151 | struct pxa3xx_nand_host { |
152 | struct nand_chip chip; | |
d456882b LW |
153 | struct mtd_info *mtd; |
154 | void *info_data; | |
155 | ||
156 | /* page size of attached chip */ | |
d456882b | 157 | int use_ecc; |
f3c8cfc2 | 158 | int cs; |
fe69af00 | 159 | |
d456882b LW |
160 | /* calculated from pxa3xx_nand_flash data */ |
161 | unsigned int col_addr_cycles; | |
162 | unsigned int row_addr_cycles; | |
163 | size_t read_id_bytes; | |
164 | ||
d456882b LW |
165 | }; |
166 | ||
167 | struct pxa3xx_nand_info { | |
401e67e2 | 168 | struct nand_hw_control controller; |
fe69af00 | 169 | struct platform_device *pdev; |
fe69af00 | 170 | |
171 | struct clk *clk; | |
172 | void __iomem *mmio_base; | |
8638fac8 | 173 | unsigned long mmio_phys; |
55d9fd6e | 174 | struct completion cmd_complete, dev_ready; |
fe69af00 | 175 | |
176 | unsigned int buf_start; | |
177 | unsigned int buf_count; | |
62e8b851 | 178 | unsigned int buf_size; |
fe69af00 | 179 | |
180 | /* DMA information */ | |
181 | int drcmr_dat; | |
182 | int drcmr_cmd; | |
183 | ||
184 | unsigned char *data_buff; | |
18c81b18 | 185 | unsigned char *oob_buff; |
fe69af00 | 186 | dma_addr_t data_buff_phys; |
fe69af00 | 187 | int data_dma_ch; |
188 | struct pxa_dma_desc *data_desc; | |
189 | dma_addr_t data_desc_addr; | |
190 | ||
f3c8cfc2 | 191 | struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; |
fe69af00 | 192 | unsigned int state; |
193 | ||
c0f3b864 EG |
194 | /* |
195 | * This driver supports NFCv1 (as found in PXA SoC) | |
196 | * and NFCv2 (as found in Armada 370/XP SoC). | |
197 | */ | |
198 | enum pxa3xx_nand_variant variant; | |
199 | ||
f3c8cfc2 | 200 | int cs; |
fe69af00 | 201 | int use_ecc; /* use HW ECC ? */ |
43bcfd2b | 202 | int ecc_bch; /* using BCH ECC? */ |
fe69af00 | 203 | int use_dma; /* use DMA ? */ |
5bb653e8 | 204 | int use_spare; /* use spare ? */ |
55d9fd6e | 205 | int need_wait; |
fe69af00 | 206 | |
2128b08c EG |
207 | unsigned int fifo_size; /* max. data size in the FIFO */ |
208 | unsigned int data_size; /* data to be read from FIFO */ | |
d456882b | 209 | unsigned int oob_size; |
43bcfd2b EG |
210 | unsigned int spare_size; |
211 | unsigned int ecc_size; | |
fe69af00 | 212 | int retcode; |
fe69af00 | 213 | |
48cf7efa EG |
214 | /* cached register value */ |
215 | uint32_t reg_ndcr; | |
216 | uint32_t ndtr0cs0; | |
217 | uint32_t ndtr1cs0; | |
218 | ||
fe69af00 | 219 | /* generated NDCBx register values */ |
220 | uint32_t ndcb0; | |
221 | uint32_t ndcb1; | |
222 | uint32_t ndcb2; | |
3a1a344a | 223 | uint32_t ndcb3; |
fe69af00 | 224 | }; |
225 | ||
90ab5ee9 | 226 | static bool use_dma = 1; |
fe69af00 | 227 | module_param(use_dma, bool, 0444); |
25985edc | 228 | MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); |
fe69af00 | 229 | |
c1f82478 | 230 | static struct pxa3xx_nand_timing timing[] = { |
227a886c LW |
231 | { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, |
232 | { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, | |
233 | { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, | |
234 | { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, | |
d3490dfd HZ |
235 | }; |
236 | ||
c1f82478 | 237 | static struct pxa3xx_nand_flash builtin_flash_types[] = { |
4332c116 LW |
238 | { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, |
239 | { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, | |
240 | { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, | |
241 | { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, | |
242 | { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, | |
243 | { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, | |
244 | { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, | |
245 | { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, | |
246 | { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, | |
d3490dfd HZ |
247 | }; |
248 | ||
776f265e EG |
249 | static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; |
250 | static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; | |
251 | ||
252 | static struct nand_bbt_descr bbt_main_descr = { | |
253 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
254 | | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
255 | .offs = 8, | |
256 | .len = 6, | |
257 | .veroffs = 14, | |
258 | .maxblocks = 8, /* Last 8 blocks in each chip */ | |
259 | .pattern = bbt_pattern | |
260 | }; | |
261 | ||
262 | static struct nand_bbt_descr bbt_mirror_descr = { | |
263 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
264 | | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
265 | .offs = 8, | |
266 | .len = 6, | |
267 | .veroffs = 14, | |
268 | .maxblocks = 8, /* Last 8 blocks in each chip */ | |
269 | .pattern = bbt_mirror_pattern | |
270 | }; | |
271 | ||
227a886c LW |
272 | /* Define a default flash type setting serve as flash detecting only */ |
273 | #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) | |
274 | ||
fe69af00 | 275 | #define NDTR0_tCH(c) (min((c), 7) << 19) |
276 | #define NDTR0_tCS(c) (min((c), 7) << 16) | |
277 | #define NDTR0_tWH(c) (min((c), 7) << 11) | |
278 | #define NDTR0_tWP(c) (min((c), 7) << 8) | |
279 | #define NDTR0_tRH(c) (min((c), 7) << 3) | |
280 | #define NDTR0_tRP(c) (min((c), 7) << 0) | |
281 | ||
282 | #define NDTR1_tR(c) (min((c), 65535) << 16) | |
283 | #define NDTR1_tWHR(c) (min((c), 15) << 4) | |
284 | #define NDTR1_tAR(c) (min((c), 15) << 0) | |
285 | ||
286 | /* convert nano-seconds to nand flash controller clock cycles */ | |
93b352fc | 287 | #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) |
fe69af00 | 288 | |
c7e9c7e7 EG |
289 | static struct of_device_id pxa3xx_nand_dt_ids[] = { |
290 | { | |
291 | .compatible = "marvell,pxa3xx-nand", | |
292 | .data = (void *)PXA3XX_NAND_VARIANT_PXA, | |
293 | }, | |
294 | {} | |
295 | }; | |
296 | MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids); | |
297 | ||
298 | static enum pxa3xx_nand_variant | |
299 | pxa3xx_nand_get_variant(struct platform_device *pdev) | |
300 | { | |
301 | const struct of_device_id *of_id = | |
302 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | |
303 | if (!of_id) | |
304 | return PXA3XX_NAND_VARIANT_PXA; | |
305 | return (enum pxa3xx_nand_variant)of_id->data; | |
306 | } | |
307 | ||
d456882b | 308 | static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, |
7dad482e | 309 | const struct pxa3xx_nand_timing *t) |
fe69af00 | 310 | { |
d456882b | 311 | struct pxa3xx_nand_info *info = host->info_data; |
fe69af00 | 312 | unsigned long nand_clk = clk_get_rate(info->clk); |
313 | uint32_t ndtr0, ndtr1; | |
314 | ||
315 | ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | | |
316 | NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | | |
317 | NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | | |
318 | NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | | |
319 | NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | | |
320 | NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); | |
321 | ||
322 | ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | | |
323 | NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | | |
324 | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); | |
325 | ||
48cf7efa EG |
326 | info->ndtr0cs0 = ndtr0; |
327 | info->ndtr1cs0 = ndtr1; | |
fe69af00 | 328 | nand_writel(info, NDTR0CS0, ndtr0); |
329 | nand_writel(info, NDTR1CS0, ndtr1); | |
330 | } | |
331 | ||
6a3e4865 EG |
332 | /* |
333 | * Set the data and OOB size, depending on the selected | |
334 | * spare and ECC configuration. | |
335 | * Only applicable to READ0, READOOB and PAGEPROG commands. | |
336 | */ | |
18c81b18 | 337 | static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) |
fe69af00 | 338 | { |
48cf7efa | 339 | int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; |
9d8b1043 | 340 | |
2128b08c | 341 | info->data_size = info->fifo_size; |
43bcfd2b | 342 | if (!oob_enable) |
9d8b1043 | 343 | return; |
9d8b1043 | 344 | |
43bcfd2b EG |
345 | info->oob_size = info->spare_size; |
346 | if (!info->use_ecc) | |
347 | info->oob_size += info->ecc_size; | |
18c81b18 LW |
348 | } |
349 | ||
f8155a40 LW |
350 | /** |
351 | * NOTE: it is a must to set ND_RUN firstly, then write | |
352 | * command buffer, otherwise, it does not work. | |
353 | * We enable all the interrupt at the same time, and | |
354 | * let pxa3xx_nand_irq to handle all logic. | |
355 | */ | |
356 | static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) | |
357 | { | |
358 | uint32_t ndcr; | |
359 | ||
48cf7efa | 360 | ndcr = info->reg_ndcr; |
cd9d1182 | 361 | |
43bcfd2b | 362 | if (info->use_ecc) { |
cd9d1182 | 363 | ndcr |= NDCR_ECC_EN; |
43bcfd2b EG |
364 | if (info->ecc_bch) |
365 | nand_writel(info, NDECCCTRL, 0x1); | |
366 | } else { | |
cd9d1182 | 367 | ndcr &= ~NDCR_ECC_EN; |
43bcfd2b EG |
368 | if (info->ecc_bch) |
369 | nand_writel(info, NDECCCTRL, 0x0); | |
370 | } | |
cd9d1182 EG |
371 | |
372 | if (info->use_dma) | |
373 | ndcr |= NDCR_DMA_EN; | |
374 | else | |
375 | ndcr &= ~NDCR_DMA_EN; | |
376 | ||
5bb653e8 EG |
377 | if (info->use_spare) |
378 | ndcr |= NDCR_SPARE_EN; | |
379 | else | |
380 | ndcr &= ~NDCR_SPARE_EN; | |
381 | ||
f8155a40 LW |
382 | ndcr |= NDCR_ND_RUN; |
383 | ||
384 | /* clear status bits and run */ | |
385 | nand_writel(info, NDCR, 0); | |
386 | nand_writel(info, NDSR, NDSR_MASK); | |
387 | nand_writel(info, NDCR, ndcr); | |
388 | } | |
389 | ||
390 | static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) | |
391 | { | |
392 | uint32_t ndcr; | |
393 | int timeout = NAND_STOP_DELAY; | |
394 | ||
395 | /* wait RUN bit in NDCR become 0 */ | |
396 | ndcr = nand_readl(info, NDCR); | |
397 | while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { | |
398 | ndcr = nand_readl(info, NDCR); | |
399 | udelay(1); | |
400 | } | |
401 | ||
402 | if (timeout <= 0) { | |
403 | ndcr &= ~NDCR_ND_RUN; | |
404 | nand_writel(info, NDCR, ndcr); | |
405 | } | |
406 | /* clear status bits */ | |
407 | nand_writel(info, NDSR, NDSR_MASK); | |
408 | } | |
409 | ||
57ff88f0 EG |
410 | static void __maybe_unused |
411 | enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
fe69af00 | 412 | { |
413 | uint32_t ndcr; | |
414 | ||
415 | ndcr = nand_readl(info, NDCR); | |
416 | nand_writel(info, NDCR, ndcr & ~int_mask); | |
417 | } | |
418 | ||
419 | static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
420 | { | |
421 | uint32_t ndcr; | |
422 | ||
423 | ndcr = nand_readl(info, NDCR); | |
424 | nand_writel(info, NDCR, ndcr | int_mask); | |
425 | } | |
426 | ||
f8155a40 | 427 | static void handle_data_pio(struct pxa3xx_nand_info *info) |
fe69af00 | 428 | { |
fe69af00 | 429 | switch (info->state) { |
430 | case STATE_PIO_WRITING: | |
431 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 432 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
433 | if (info->oob_size > 0) |
434 | __raw_writesl(info->mmio_base + NDDB, info->oob_buff, | |
435 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 436 | break; |
437 | case STATE_PIO_READING: | |
438 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 439 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
440 | if (info->oob_size > 0) |
441 | __raw_readsl(info->mmio_base + NDDB, info->oob_buff, | |
442 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 443 | break; |
444 | default: | |
da675b4e | 445 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
fe69af00 | 446 | info->state); |
f8155a40 | 447 | BUG(); |
fe69af00 | 448 | } |
fe69af00 | 449 | } |
450 | ||
f4db2e3a | 451 | #ifdef ARCH_HAS_DMA |
f8155a40 | 452 | static void start_data_dma(struct pxa3xx_nand_info *info) |
fe69af00 | 453 | { |
454 | struct pxa_dma_desc *desc = info->data_desc; | |
9d8b1043 | 455 | int dma_len = ALIGN(info->data_size + info->oob_size, 32); |
fe69af00 | 456 | |
457 | desc->ddadr = DDADR_STOP; | |
458 | desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; | |
459 | ||
f8155a40 LW |
460 | switch (info->state) { |
461 | case STATE_DMA_WRITING: | |
fe69af00 | 462 | desc->dsadr = info->data_buff_phys; |
8638fac8 | 463 | desc->dtadr = info->mmio_phys + NDDB; |
fe69af00 | 464 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
f8155a40 LW |
465 | break; |
466 | case STATE_DMA_READING: | |
fe69af00 | 467 | desc->dtadr = info->data_buff_phys; |
8638fac8 | 468 | desc->dsadr = info->mmio_phys + NDDB; |
fe69af00 | 469 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
f8155a40 LW |
470 | break; |
471 | default: | |
da675b4e | 472 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
f8155a40 LW |
473 | info->state); |
474 | BUG(); | |
fe69af00 | 475 | } |
476 | ||
477 | DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; | |
478 | DDADR(info->data_dma_ch) = info->data_desc_addr; | |
479 | DCSR(info->data_dma_ch) |= DCSR_RUN; | |
480 | } | |
481 | ||
482 | static void pxa3xx_nand_data_dma_irq(int channel, void *data) | |
483 | { | |
484 | struct pxa3xx_nand_info *info = data; | |
485 | uint32_t dcsr; | |
486 | ||
487 | dcsr = DCSR(channel); | |
488 | DCSR(channel) = dcsr; | |
489 | ||
490 | if (dcsr & DCSR_BUSERR) { | |
491 | info->retcode = ERR_DMABUSERR; | |
fe69af00 | 492 | } |
493 | ||
f8155a40 LW |
494 | info->state = STATE_DMA_DONE; |
495 | enable_int(info, NDCR_INT_MASK); | |
496 | nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); | |
fe69af00 | 497 | } |
f4db2e3a EG |
498 | #else |
499 | static void start_data_dma(struct pxa3xx_nand_info *info) | |
500 | {} | |
501 | #endif | |
fe69af00 | 502 | |
503 | static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) | |
504 | { | |
505 | struct pxa3xx_nand_info *info = devid; | |
55d9fd6e | 506 | unsigned int status, is_completed = 0, is_ready = 0; |
f3c8cfc2 LW |
507 | unsigned int ready, cmd_done; |
508 | ||
509 | if (info->cs == 0) { | |
510 | ready = NDSR_FLASH_RDY; | |
511 | cmd_done = NDSR_CS0_CMDD; | |
512 | } else { | |
513 | ready = NDSR_RDY; | |
514 | cmd_done = NDSR_CS1_CMDD; | |
515 | } | |
fe69af00 | 516 | |
517 | status = nand_readl(info, NDSR); | |
518 | ||
f8155a40 LW |
519 | if (status & NDSR_DBERR) |
520 | info->retcode = ERR_DBERR; | |
521 | if (status & NDSR_SBERR) | |
522 | info->retcode = ERR_SBERR; | |
523 | if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { | |
524 | /* whether use dma to transfer data */ | |
fe69af00 | 525 | if (info->use_dma) { |
f8155a40 LW |
526 | disable_int(info, NDCR_INT_MASK); |
527 | info->state = (status & NDSR_RDDREQ) ? | |
528 | STATE_DMA_READING : STATE_DMA_WRITING; | |
529 | start_data_dma(info); | |
530 | goto NORMAL_IRQ_EXIT; | |
fe69af00 | 531 | } else { |
f8155a40 LW |
532 | info->state = (status & NDSR_RDDREQ) ? |
533 | STATE_PIO_READING : STATE_PIO_WRITING; | |
534 | handle_data_pio(info); | |
fe69af00 | 535 | } |
fe69af00 | 536 | } |
f3c8cfc2 | 537 | if (status & cmd_done) { |
f8155a40 LW |
538 | info->state = STATE_CMD_DONE; |
539 | is_completed = 1; | |
fe69af00 | 540 | } |
f3c8cfc2 | 541 | if (status & ready) { |
f8155a40 | 542 | info->state = STATE_READY; |
55d9fd6e | 543 | is_ready = 1; |
401e67e2 | 544 | } |
fe69af00 | 545 | |
f8155a40 LW |
546 | if (status & NDSR_WRCMDREQ) { |
547 | nand_writel(info, NDSR, NDSR_WRCMDREQ); | |
548 | status &= ~NDSR_WRCMDREQ; | |
549 | info->state = STATE_CMD_HANDLE; | |
3a1a344a EG |
550 | |
551 | /* | |
552 | * Command buffer registers NDCB{0-2} (and optionally NDCB3) | |
553 | * must be loaded by writing directly either 12 or 16 | |
554 | * bytes directly to NDCB0, four bytes at a time. | |
555 | * | |
556 | * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored | |
557 | * but each NDCBx register can be read. | |
558 | */ | |
f8155a40 LW |
559 | nand_writel(info, NDCB0, info->ndcb0); |
560 | nand_writel(info, NDCB0, info->ndcb1); | |
561 | nand_writel(info, NDCB0, info->ndcb2); | |
3a1a344a EG |
562 | |
563 | /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ | |
564 | if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) | |
565 | nand_writel(info, NDCB0, info->ndcb3); | |
fe69af00 | 566 | } |
567 | ||
f8155a40 LW |
568 | /* clear NDSR to let the controller exit the IRQ */ |
569 | nand_writel(info, NDSR, status); | |
570 | if (is_completed) | |
571 | complete(&info->cmd_complete); | |
55d9fd6e EG |
572 | if (is_ready) |
573 | complete(&info->dev_ready); | |
f8155a40 LW |
574 | NORMAL_IRQ_EXIT: |
575 | return IRQ_HANDLED; | |
fe69af00 | 576 | } |
577 | ||
fe69af00 | 578 | static inline int is_buf_blank(uint8_t *buf, size_t len) |
579 | { | |
580 | for (; len > 0; len--) | |
581 | if (*buf++ != 0xff) | |
582 | return 0; | |
583 | return 1; | |
584 | } | |
585 | ||
4eb2da89 LW |
586 | static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, |
587 | uint16_t column, int page_addr) | |
fe69af00 | 588 | { |
d456882b | 589 | int addr_cycle, exec_cmd; |
f3c8cfc2 LW |
590 | struct pxa3xx_nand_host *host; |
591 | struct mtd_info *mtd; | |
fe69af00 | 592 | |
f3c8cfc2 LW |
593 | host = info->host[info->cs]; |
594 | mtd = host->mtd; | |
4eb2da89 LW |
595 | addr_cycle = 0; |
596 | exec_cmd = 1; | |
597 | ||
598 | /* reset data and oob column point to handle data */ | |
401e67e2 LW |
599 | info->buf_start = 0; |
600 | info->buf_count = 0; | |
4eb2da89 LW |
601 | info->oob_size = 0; |
602 | info->use_ecc = 0; | |
5bb653e8 | 603 | info->use_spare = 1; |
4eb2da89 | 604 | info->retcode = ERR_NONE; |
f3c8cfc2 LW |
605 | if (info->cs != 0) |
606 | info->ndcb0 = NDCB0_CSEL; | |
607 | else | |
608 | info->ndcb0 = 0; | |
fe69af00 | 609 | |
610 | switch (command) { | |
4eb2da89 LW |
611 | case NAND_CMD_READ0: |
612 | case NAND_CMD_PAGEPROG: | |
613 | info->use_ecc = 1; | |
fe69af00 | 614 | case NAND_CMD_READOOB: |
4eb2da89 | 615 | pxa3xx_set_datasize(info); |
fe69af00 | 616 | break; |
41a63430 EG |
617 | case NAND_CMD_PARAM: |
618 | info->use_spare = 0; | |
619 | break; | |
4eb2da89 LW |
620 | case NAND_CMD_SEQIN: |
621 | exec_cmd = 0; | |
622 | break; | |
623 | default: | |
624 | info->ndcb1 = 0; | |
625 | info->ndcb2 = 0; | |
3a1a344a | 626 | info->ndcb3 = 0; |
4eb2da89 LW |
627 | break; |
628 | } | |
629 | ||
d456882b LW |
630 | addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles |
631 | + host->col_addr_cycles); | |
fe69af00 | 632 | |
4eb2da89 LW |
633 | switch (command) { |
634 | case NAND_CMD_READOOB: | |
fe69af00 | 635 | case NAND_CMD_READ0: |
ec82135a EG |
636 | info->buf_start = column; |
637 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
638 | | addr_cycle | |
639 | | NAND_CMD_READ0; | |
640 | ||
4eb2da89 | 641 | if (command == NAND_CMD_READOOB) |
ec82135a | 642 | info->buf_start += mtd->writesize; |
4eb2da89 | 643 | |
ec82135a | 644 | /* Second command setting for large pages */ |
0a3f3a19 | 645 | if (mtd->writesize >= PAGE_CHUNK_SIZE) |
ec82135a | 646 | info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); |
fe69af00 | 647 | |
fe69af00 | 648 | case NAND_CMD_SEQIN: |
4eb2da89 | 649 | /* small page addr setting */ |
0a3f3a19 | 650 | if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) { |
4eb2da89 LW |
651 | info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) |
652 | | (column & 0xFF); | |
653 | ||
654 | info->ndcb2 = 0; | |
655 | } else { | |
656 | info->ndcb1 = ((page_addr & 0xFFFF) << 16) | |
657 | | (column & 0xFFFF); | |
658 | ||
659 | if (page_addr & 0xFF0000) | |
660 | info->ndcb2 = (page_addr & 0xFF0000) >> 16; | |
661 | else | |
662 | info->ndcb2 = 0; | |
663 | } | |
664 | ||
fe69af00 | 665 | info->buf_count = mtd->writesize + mtd->oobsize; |
4eb2da89 | 666 | memset(info->data_buff, 0xFF, info->buf_count); |
fe69af00 | 667 | |
fe69af00 | 668 | break; |
4eb2da89 | 669 | |
fe69af00 | 670 | case NAND_CMD_PAGEPROG: |
4eb2da89 LW |
671 | if (is_buf_blank(info->data_buff, |
672 | (mtd->writesize + mtd->oobsize))) { | |
673 | exec_cmd = 0; | |
674 | break; | |
675 | } | |
fe69af00 | 676 | |
4eb2da89 LW |
677 | info->ndcb0 |= NDCB0_CMD_TYPE(0x1) |
678 | | NDCB0_AUTO_RS | |
679 | | NDCB0_ST_ROW_EN | |
680 | | NDCB0_DBC | |
ec82135a EG |
681 | | (NAND_CMD_PAGEPROG << 8) |
682 | | NAND_CMD_SEQIN | |
4eb2da89 | 683 | | addr_cycle; |
fe69af00 | 684 | break; |
4eb2da89 | 685 | |
ce0268f6 | 686 | case NAND_CMD_PARAM: |
ce0268f6 EG |
687 | info->buf_count = 256; |
688 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
689 | | NDCB0_ADDR_CYC(1) | |
41a63430 | 690 | | NDCB0_LEN_OVRD |
ec82135a | 691 | | command; |
ce0268f6 | 692 | info->ndcb1 = (column & 0xFF); |
41a63430 | 693 | info->ndcb3 = 256; |
ce0268f6 EG |
694 | info->data_size = 256; |
695 | break; | |
696 | ||
fe69af00 | 697 | case NAND_CMD_READID: |
d456882b | 698 | info->buf_count = host->read_id_bytes; |
4eb2da89 LW |
699 | info->ndcb0 |= NDCB0_CMD_TYPE(3) |
700 | | NDCB0_ADDR_CYC(1) | |
ec82135a | 701 | | command; |
d14231f1 | 702 | info->ndcb1 = (column & 0xFF); |
4eb2da89 LW |
703 | |
704 | info->data_size = 8; | |
705 | break; | |
fe69af00 | 706 | case NAND_CMD_STATUS: |
4eb2da89 LW |
707 | info->buf_count = 1; |
708 | info->ndcb0 |= NDCB0_CMD_TYPE(4) | |
709 | | NDCB0_ADDR_CYC(1) | |
ec82135a | 710 | | command; |
4eb2da89 LW |
711 | |
712 | info->data_size = 8; | |
713 | break; | |
714 | ||
715 | case NAND_CMD_ERASE1: | |
4eb2da89 LW |
716 | info->ndcb0 |= NDCB0_CMD_TYPE(2) |
717 | | NDCB0_AUTO_RS | |
718 | | NDCB0_ADDR_CYC(3) | |
719 | | NDCB0_DBC | |
ec82135a EG |
720 | | (NAND_CMD_ERASE2 << 8) |
721 | | NAND_CMD_ERASE1; | |
4eb2da89 LW |
722 | info->ndcb1 = page_addr; |
723 | info->ndcb2 = 0; | |
724 | ||
fe69af00 | 725 | break; |
726 | case NAND_CMD_RESET: | |
4eb2da89 | 727 | info->ndcb0 |= NDCB0_CMD_TYPE(5) |
ec82135a | 728 | | command; |
4eb2da89 LW |
729 | |
730 | break; | |
731 | ||
732 | case NAND_CMD_ERASE2: | |
733 | exec_cmd = 0; | |
fe69af00 | 734 | break; |
4eb2da89 | 735 | |
fe69af00 | 736 | default: |
4eb2da89 | 737 | exec_cmd = 0; |
da675b4e LW |
738 | dev_err(&info->pdev->dev, "non-supported command %x\n", |
739 | command); | |
fe69af00 | 740 | break; |
741 | } | |
742 | ||
4eb2da89 LW |
743 | return exec_cmd; |
744 | } | |
745 | ||
746 | static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
747 | int column, int page_addr) | |
748 | { | |
d456882b LW |
749 | struct pxa3xx_nand_host *host = mtd->priv; |
750 | struct pxa3xx_nand_info *info = host->info_data; | |
4eb2da89 LW |
751 | int ret, exec_cmd; |
752 | ||
753 | /* | |
754 | * if this is a x16 device ,then convert the input | |
755 | * "byte" address into a "word" address appropriate | |
756 | * for indexing a word-oriented device | |
757 | */ | |
48cf7efa | 758 | if (info->reg_ndcr & NDCR_DWIDTH_M) |
4eb2da89 LW |
759 | column /= 2; |
760 | ||
f3c8cfc2 LW |
761 | /* |
762 | * There may be different NAND chip hooked to | |
763 | * different chip select, so check whether | |
764 | * chip select has been changed, if yes, reset the timing | |
765 | */ | |
766 | if (info->cs != host->cs) { | |
767 | info->cs = host->cs; | |
48cf7efa EG |
768 | nand_writel(info, NDTR0CS0, info->ndtr0cs0); |
769 | nand_writel(info, NDTR1CS0, info->ndtr1cs0); | |
f3c8cfc2 LW |
770 | } |
771 | ||
d456882b | 772 | info->state = STATE_PREPARED; |
4eb2da89 | 773 | exec_cmd = prepare_command_pool(info, command, column, page_addr); |
f8155a40 LW |
774 | if (exec_cmd) { |
775 | init_completion(&info->cmd_complete); | |
55d9fd6e EG |
776 | init_completion(&info->dev_ready); |
777 | info->need_wait = 1; | |
f8155a40 LW |
778 | pxa3xx_nand_start(info); |
779 | ||
780 | ret = wait_for_completion_timeout(&info->cmd_complete, | |
781 | CHIP_DELAY_TIMEOUT); | |
782 | if (!ret) { | |
da675b4e | 783 | dev_err(&info->pdev->dev, "Wait time out!!!\n"); |
f8155a40 LW |
784 | /* Stop State Machine for next command cycle */ |
785 | pxa3xx_nand_stop(info); | |
786 | } | |
f8155a40 | 787 | } |
d456882b | 788 | info->state = STATE_IDLE; |
f8155a40 LW |
789 | } |
790 | ||
fdbad98d | 791 | static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, |
1fbb938d | 792 | struct nand_chip *chip, const uint8_t *buf, int oob_required) |
f8155a40 LW |
793 | { |
794 | chip->write_buf(mtd, buf, mtd->writesize); | |
795 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
796 | |
797 | return 0; | |
f8155a40 LW |
798 | } |
799 | ||
800 | static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, | |
1fbb938d BN |
801 | struct nand_chip *chip, uint8_t *buf, int oob_required, |
802 | int page) | |
f8155a40 | 803 | { |
d456882b LW |
804 | struct pxa3xx_nand_host *host = mtd->priv; |
805 | struct pxa3xx_nand_info *info = host->info_data; | |
4e86fd22 | 806 | int max_bitflips = 0; |
f8155a40 LW |
807 | |
808 | chip->read_buf(mtd, buf, mtd->writesize); | |
809 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
810 | ||
811 | if (info->retcode == ERR_SBERR) { | |
812 | switch (info->use_ecc) { | |
813 | case 1: | |
4e86fd22 | 814 | max_bitflips = 1; |
f8155a40 LW |
815 | mtd->ecc_stats.corrected++; |
816 | break; | |
817 | case 0: | |
818 | default: | |
819 | break; | |
820 | } | |
821 | } else if (info->retcode == ERR_DBERR) { | |
822 | /* | |
823 | * for blank page (all 0xff), HW will calculate its ECC as | |
824 | * 0, which is different from the ECC information within | |
825 | * OOB, ignore such double bit errors | |
826 | */ | |
827 | if (is_buf_blank(buf, mtd->writesize)) | |
543e32d5 DM |
828 | info->retcode = ERR_NONE; |
829 | else | |
f8155a40 | 830 | mtd->ecc_stats.failed++; |
fe69af00 | 831 | } |
f8155a40 | 832 | |
4e86fd22 | 833 | return max_bitflips; |
fe69af00 | 834 | } |
835 | ||
836 | static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) | |
837 | { | |
d456882b LW |
838 | struct pxa3xx_nand_host *host = mtd->priv; |
839 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 840 | char retval = 0xFF; |
841 | ||
842 | if (info->buf_start < info->buf_count) | |
843 | /* Has just send a new command? */ | |
844 | retval = info->data_buff[info->buf_start++]; | |
845 | ||
846 | return retval; | |
847 | } | |
848 | ||
849 | static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) | |
850 | { | |
d456882b LW |
851 | struct pxa3xx_nand_host *host = mtd->priv; |
852 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 853 | u16 retval = 0xFFFF; |
854 | ||
855 | if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { | |
856 | retval = *((u16 *)(info->data_buff+info->buf_start)); | |
857 | info->buf_start += 2; | |
858 | } | |
859 | return retval; | |
860 | } | |
861 | ||
862 | static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
863 | { | |
d456882b LW |
864 | struct pxa3xx_nand_host *host = mtd->priv; |
865 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 866 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
867 | ||
868 | memcpy(buf, info->data_buff + info->buf_start, real_len); | |
869 | info->buf_start += real_len; | |
870 | } | |
871 | ||
872 | static void pxa3xx_nand_write_buf(struct mtd_info *mtd, | |
873 | const uint8_t *buf, int len) | |
874 | { | |
d456882b LW |
875 | struct pxa3xx_nand_host *host = mtd->priv; |
876 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 877 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
878 | ||
879 | memcpy(info->data_buff + info->buf_start, buf, real_len); | |
880 | info->buf_start += real_len; | |
881 | } | |
882 | ||
fe69af00 | 883 | static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) |
884 | { | |
885 | return; | |
886 | } | |
887 | ||
888 | static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) | |
889 | { | |
d456882b LW |
890 | struct pxa3xx_nand_host *host = mtd->priv; |
891 | struct pxa3xx_nand_info *info = host->info_data; | |
55d9fd6e EG |
892 | int ret; |
893 | ||
894 | if (info->need_wait) { | |
895 | ret = wait_for_completion_timeout(&info->dev_ready, | |
896 | CHIP_DELAY_TIMEOUT); | |
897 | info->need_wait = 0; | |
898 | if (!ret) { | |
899 | dev_err(&info->pdev->dev, "Ready time out!!!\n"); | |
900 | return NAND_STATUS_FAIL; | |
901 | } | |
902 | } | |
fe69af00 | 903 | |
904 | /* pxa3xx_nand_send_command has waited for command complete */ | |
905 | if (this->state == FL_WRITING || this->state == FL_ERASING) { | |
906 | if (info->retcode == ERR_NONE) | |
907 | return 0; | |
55d9fd6e EG |
908 | else |
909 | return NAND_STATUS_FAIL; | |
fe69af00 | 910 | } |
911 | ||
55d9fd6e | 912 | return NAND_STATUS_READY; |
fe69af00 | 913 | } |
914 | ||
fe69af00 | 915 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
c8c17c88 | 916 | const struct pxa3xx_nand_flash *f) |
fe69af00 | 917 | { |
918 | struct platform_device *pdev = info->pdev; | |
453810b7 | 919 | struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
f3c8cfc2 | 920 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
f8155a40 | 921 | uint32_t ndcr = 0x0; /* enable all interrupts */ |
fe69af00 | 922 | |
da675b4e LW |
923 | if (f->page_size != 2048 && f->page_size != 512) { |
924 | dev_err(&pdev->dev, "Current only support 2048 and 512 size\n"); | |
fe69af00 | 925 | return -EINVAL; |
da675b4e | 926 | } |
fe69af00 | 927 | |
da675b4e LW |
928 | if (f->flash_width != 16 && f->flash_width != 8) { |
929 | dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n"); | |
fe69af00 | 930 | return -EINVAL; |
da675b4e | 931 | } |
fe69af00 | 932 | |
933 | /* calculate flash information */ | |
d456882b | 934 | host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; |
fe69af00 | 935 | |
936 | /* calculate addressing information */ | |
d456882b | 937 | host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
fe69af00 | 938 | |
939 | if (f->num_blocks * f->page_per_block > 65536) | |
d456882b | 940 | host->row_addr_cycles = 3; |
fe69af00 | 941 | else |
d456882b | 942 | host->row_addr_cycles = 2; |
fe69af00 | 943 | |
944 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | |
d456882b | 945 | ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
fe69af00 | 946 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
947 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | |
948 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | |
949 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | |
950 | ||
d456882b | 951 | ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); |
fe69af00 | 952 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
953 | ||
48cf7efa | 954 | info->reg_ndcr = ndcr; |
fe69af00 | 955 | |
d456882b | 956 | pxa3xx_nand_set_timing(host, f->timing); |
fe69af00 | 957 | return 0; |
958 | } | |
959 | ||
f271049e MR |
960 | static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) |
961 | { | |
f3c8cfc2 LW |
962 | /* |
963 | * We set 0 by hard coding here, for we don't support keep_config | |
964 | * when there is more than one chip attached to the controller | |
965 | */ | |
966 | struct pxa3xx_nand_host *host = info->host[0]; | |
f271049e | 967 | uint32_t ndcr = nand_readl(info, NDCR); |
f271049e | 968 | |
d456882b | 969 | if (ndcr & NDCR_PAGE_SZ) { |
2128b08c EG |
970 | /* Controller's FIFO size */ |
971 | info->fifo_size = 2048; | |
d456882b LW |
972 | host->read_id_bytes = 4; |
973 | } else { | |
2128b08c | 974 | info->fifo_size = 512; |
d456882b LW |
975 | host->read_id_bytes = 2; |
976 | } | |
977 | ||
48cf7efa EG |
978 | info->reg_ndcr = ndcr & ~NDCR_INT_MASK; |
979 | info->ndtr0cs0 = nand_readl(info, NDTR0CS0); | |
980 | info->ndtr1cs0 = nand_readl(info, NDTR1CS0); | |
f271049e MR |
981 | return 0; |
982 | } | |
983 | ||
f4db2e3a | 984 | #ifdef ARCH_HAS_DMA |
fe69af00 | 985 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) |
986 | { | |
987 | struct platform_device *pdev = info->pdev; | |
62e8b851 | 988 | int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc); |
fe69af00 | 989 | |
990 | if (use_dma == 0) { | |
62e8b851 | 991 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); |
fe69af00 | 992 | if (info->data_buff == NULL) |
993 | return -ENOMEM; | |
994 | return 0; | |
995 | } | |
996 | ||
62e8b851 | 997 | info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size, |
fe69af00 | 998 | &info->data_buff_phys, GFP_KERNEL); |
999 | if (info->data_buff == NULL) { | |
1000 | dev_err(&pdev->dev, "failed to allocate dma buffer\n"); | |
1001 | return -ENOMEM; | |
1002 | } | |
1003 | ||
fe69af00 | 1004 | info->data_desc = (void *)info->data_buff + data_desc_offset; |
1005 | info->data_desc_addr = info->data_buff_phys + data_desc_offset; | |
1006 | ||
1007 | info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, | |
1008 | pxa3xx_nand_data_dma_irq, info); | |
1009 | if (info->data_dma_ch < 0) { | |
1010 | dev_err(&pdev->dev, "failed to request data dma\n"); | |
62e8b851 | 1011 | dma_free_coherent(&pdev->dev, info->buf_size, |
fe69af00 | 1012 | info->data_buff, info->data_buff_phys); |
1013 | return info->data_dma_ch; | |
1014 | } | |
1015 | ||
95b26563 EG |
1016 | /* |
1017 | * Now that DMA buffers are allocated we turn on | |
1018 | * DMA proper for I/O operations. | |
1019 | */ | |
1020 | info->use_dma = 1; | |
fe69af00 | 1021 | return 0; |
1022 | } | |
1023 | ||
498b6145 EG |
1024 | static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) |
1025 | { | |
1026 | struct platform_device *pdev = info->pdev; | |
15b540c7 | 1027 | if (info->use_dma) { |
498b6145 | 1028 | pxa_free_dma(info->data_dma_ch); |
62e8b851 | 1029 | dma_free_coherent(&pdev->dev, info->buf_size, |
498b6145 EG |
1030 | info->data_buff, info->data_buff_phys); |
1031 | } else { | |
1032 | kfree(info->data_buff); | |
1033 | } | |
1034 | } | |
f4db2e3a EG |
1035 | #else |
1036 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) | |
1037 | { | |
62e8b851 | 1038 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); |
f4db2e3a EG |
1039 | if (info->data_buff == NULL) |
1040 | return -ENOMEM; | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) | |
1045 | { | |
1046 | kfree(info->data_buff); | |
1047 | } | |
1048 | #endif | |
498b6145 | 1049 | |
401e67e2 LW |
1050 | static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) |
1051 | { | |
f3c8cfc2 | 1052 | struct mtd_info *mtd; |
2d79ab16 | 1053 | struct nand_chip *chip; |
d456882b | 1054 | int ret; |
2d79ab16 | 1055 | |
f3c8cfc2 | 1056 | mtd = info->host[info->cs]->mtd; |
2d79ab16 EG |
1057 | chip = mtd->priv; |
1058 | ||
401e67e2 | 1059 | /* use the common timing to make a try */ |
d456882b LW |
1060 | ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); |
1061 | if (ret) | |
1062 | return ret; | |
1063 | ||
2d79ab16 | 1064 | chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0); |
56704d85 EG |
1065 | ret = chip->waitfunc(mtd, chip); |
1066 | if (ret & NAND_STATUS_FAIL) | |
1067 | return -ENODEV; | |
d456882b | 1068 | |
56704d85 | 1069 | return 0; |
401e67e2 | 1070 | } |
fe69af00 | 1071 | |
43bcfd2b EG |
1072 | static int pxa_ecc_init(struct pxa3xx_nand_info *info, |
1073 | struct nand_ecc_ctrl *ecc, | |
1074 | int strength, int page_size) | |
1075 | { | |
1076 | /* | |
1077 | * We don't use strength here as the PXA variant | |
1078 | * is used with non-ONFI compliant devices. | |
1079 | */ | |
1080 | if (page_size == 2048) { | |
1081 | info->spare_size = 40; | |
1082 | info->ecc_size = 24; | |
1083 | ecc->mode = NAND_ECC_HW; | |
1084 | ecc->size = 512; | |
1085 | ecc->strength = 1; | |
1086 | return 1; | |
1087 | ||
1088 | } else if (page_size == 512) { | |
1089 | info->spare_size = 8; | |
1090 | info->ecc_size = 8; | |
1091 | ecc->mode = NAND_ECC_HW; | |
1092 | ecc->size = 512; | |
1093 | ecc->strength = 1; | |
1094 | return 1; | |
1095 | } | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | static int armada370_ecc_init(struct pxa3xx_nand_info *info, | |
1100 | struct nand_ecc_ctrl *ecc, | |
1101 | int strength, int page_size) | |
1102 | { | |
1103 | /* Unimplemented yet */ | |
1104 | return 0; | |
1105 | } | |
1106 | ||
401e67e2 | 1107 | static int pxa3xx_nand_scan(struct mtd_info *mtd) |
fe69af00 | 1108 | { |
d456882b LW |
1109 | struct pxa3xx_nand_host *host = mtd->priv; |
1110 | struct pxa3xx_nand_info *info = host->info_data; | |
401e67e2 | 1111 | struct platform_device *pdev = info->pdev; |
453810b7 | 1112 | struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0fab028b | 1113 | struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; |
401e67e2 LW |
1114 | const struct pxa3xx_nand_flash *f = NULL; |
1115 | struct nand_chip *chip = mtd->priv; | |
1116 | uint32_t id = -1; | |
4332c116 | 1117 | uint64_t chipsize; |
401e67e2 LW |
1118 | int i, ret, num; |
1119 | ||
1120 | if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) | |
4332c116 | 1121 | goto KEEP_CONFIG; |
401e67e2 LW |
1122 | |
1123 | ret = pxa3xx_nand_sensing(info); | |
d456882b | 1124 | if (ret) { |
f3c8cfc2 LW |
1125 | dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", |
1126 | info->cs); | |
401e67e2 | 1127 | |
d456882b | 1128 | return ret; |
401e67e2 LW |
1129 | } |
1130 | ||
1131 | chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); | |
1132 | id = *((uint16_t *)(info->data_buff)); | |
1133 | if (id != 0) | |
da675b4e | 1134 | dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); |
401e67e2 | 1135 | else { |
da675b4e LW |
1136 | dev_warn(&info->pdev->dev, |
1137 | "Read out ID 0, potential timing set wrong!!\n"); | |
401e67e2 LW |
1138 | |
1139 | return -EINVAL; | |
1140 | } | |
1141 | ||
1142 | num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; | |
1143 | for (i = 0; i < num; i++) { | |
1144 | if (i < pdata->num_flash) | |
1145 | f = pdata->flash + i; | |
1146 | else | |
1147 | f = &builtin_flash_types[i - pdata->num_flash + 1]; | |
1148 | ||
1149 | /* find the chip in default list */ | |
4332c116 | 1150 | if (f->chip_id == id) |
401e67e2 | 1151 | break; |
401e67e2 LW |
1152 | } |
1153 | ||
4332c116 | 1154 | if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { |
da675b4e | 1155 | dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); |
401e67e2 LW |
1156 | |
1157 | return -EINVAL; | |
1158 | } | |
1159 | ||
d456882b LW |
1160 | ret = pxa3xx_nand_config_flash(info, f); |
1161 | if (ret) { | |
1162 | dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); | |
1163 | return ret; | |
1164 | } | |
1165 | ||
4332c116 | 1166 | pxa3xx_flash_ids[0].name = f->name; |
68aa352d | 1167 | pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff; |
4332c116 LW |
1168 | pxa3xx_flash_ids[0].pagesize = f->page_size; |
1169 | chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; | |
1170 | pxa3xx_flash_ids[0].chipsize = chipsize >> 20; | |
1171 | pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; | |
1172 | if (f->flash_width == 16) | |
1173 | pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; | |
0fab028b LW |
1174 | pxa3xx_flash_ids[1].name = NULL; |
1175 | def = pxa3xx_flash_ids; | |
4332c116 | 1176 | KEEP_CONFIG: |
48cf7efa | 1177 | if (info->reg_ndcr & NDCR_DWIDTH_M) |
d456882b LW |
1178 | chip->options |= NAND_BUSWIDTH_16; |
1179 | ||
43bcfd2b EG |
1180 | /* Device detection must be done with ECC disabled */ |
1181 | if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) | |
1182 | nand_writel(info, NDECCCTRL, 0x0); | |
1183 | ||
0fab028b | 1184 | if (nand_scan_ident(mtd, 1, def)) |
4332c116 | 1185 | return -ENODEV; |
776f265e EG |
1186 | |
1187 | if (pdata->flash_bbt) { | |
1188 | /* | |
1189 | * We'll use a bad block table stored in-flash and don't | |
1190 | * allow writing the bad block marker to the flash. | |
1191 | */ | |
1192 | chip->bbt_options |= NAND_BBT_USE_FLASH | | |
1193 | NAND_BBT_NO_OOB_BBM; | |
1194 | chip->bbt_td = &bbt_main_descr; | |
1195 | chip->bbt_md = &bbt_mirror_descr; | |
1196 | } | |
1197 | ||
43bcfd2b EG |
1198 | if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) |
1199 | ret = armada370_ecc_init(info, &chip->ecc, | |
1200 | chip->ecc_strength_ds, | |
1201 | mtd->writesize); | |
1202 | else | |
1203 | ret = pxa_ecc_init(info, &chip->ecc, | |
1204 | chip->ecc_strength_ds, | |
1205 | mtd->writesize); | |
1206 | if (!ret) { | |
1207 | dev_err(&info->pdev->dev, | |
1208 | "ECC strength %d at page size %d is not supported\n", | |
1209 | chip->ecc_strength_ds, mtd->writesize); | |
1210 | return -ENODEV; | |
1211 | } | |
1212 | ||
4332c116 | 1213 | /* calculate addressing information */ |
d456882b LW |
1214 | if (mtd->writesize >= 2048) |
1215 | host->col_addr_cycles = 2; | |
1216 | else | |
1217 | host->col_addr_cycles = 1; | |
1218 | ||
62e8b851 EG |
1219 | /* release the initial buffer */ |
1220 | kfree(info->data_buff); | |
1221 | ||
1222 | /* allocate the real data + oob buffer */ | |
1223 | info->buf_size = mtd->writesize + mtd->oobsize; | |
1224 | ret = pxa3xx_nand_init_buff(info); | |
1225 | if (ret) | |
1226 | return ret; | |
4332c116 | 1227 | info->oob_buff = info->data_buff + mtd->writesize; |
62e8b851 | 1228 | |
4332c116 | 1229 | if ((mtd->size >> chip->page_shift) > 65536) |
d456882b | 1230 | host->row_addr_cycles = 3; |
4332c116 | 1231 | else |
d456882b | 1232 | host->row_addr_cycles = 2; |
401e67e2 | 1233 | return nand_scan_tail(mtd); |
fe69af00 | 1234 | } |
1235 | ||
d456882b | 1236 | static int alloc_nand_resource(struct platform_device *pdev) |
fe69af00 | 1237 | { |
f3c8cfc2 | 1238 | struct pxa3xx_nand_platform_data *pdata; |
fe69af00 | 1239 | struct pxa3xx_nand_info *info; |
d456882b | 1240 | struct pxa3xx_nand_host *host; |
6e308f87 | 1241 | struct nand_chip *chip = NULL; |
fe69af00 | 1242 | struct mtd_info *mtd; |
1243 | struct resource *r; | |
f3c8cfc2 | 1244 | int ret, irq, cs; |
fe69af00 | 1245 | |
453810b7 | 1246 | pdata = dev_get_platdata(&pdev->dev); |
4c073cd2 EG |
1247 | info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) + |
1248 | sizeof(*host)) * pdata->num_cs, GFP_KERNEL); | |
1249 | if (!info) | |
d456882b | 1250 | return -ENOMEM; |
fe69af00 | 1251 | |
fe69af00 | 1252 | info->pdev = pdev; |
c7e9c7e7 | 1253 | info->variant = pxa3xx_nand_get_variant(pdev); |
f3c8cfc2 LW |
1254 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1255 | mtd = (struct mtd_info *)((unsigned int)&info[1] + | |
1256 | (sizeof(*mtd) + sizeof(*host)) * cs); | |
1257 | chip = (struct nand_chip *)(&mtd[1]); | |
1258 | host = (struct pxa3xx_nand_host *)chip; | |
1259 | info->host[cs] = host; | |
1260 | host->mtd = mtd; | |
1261 | host->cs = cs; | |
1262 | host->info_data = info; | |
1263 | mtd->priv = host; | |
1264 | mtd->owner = THIS_MODULE; | |
1265 | ||
1266 | chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; | |
1267 | chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; | |
1268 | chip->controller = &info->controller; | |
1269 | chip->waitfunc = pxa3xx_nand_waitfunc; | |
1270 | chip->select_chip = pxa3xx_nand_select_chip; | |
1271 | chip->cmdfunc = pxa3xx_nand_cmdfunc; | |
1272 | chip->read_word = pxa3xx_nand_read_word; | |
1273 | chip->read_byte = pxa3xx_nand_read_byte; | |
1274 | chip->read_buf = pxa3xx_nand_read_buf; | |
1275 | chip->write_buf = pxa3xx_nand_write_buf; | |
664c7f5e | 1276 | chip->options |= NAND_NO_SUBPAGE_WRITE; |
f3c8cfc2 | 1277 | } |
401e67e2 LW |
1278 | |
1279 | spin_lock_init(&chip->controller->lock); | |
1280 | init_waitqueue_head(&chip->controller->wq); | |
9ca7944d | 1281 | info->clk = devm_clk_get(&pdev->dev, NULL); |
fe69af00 | 1282 | if (IS_ERR(info->clk)) { |
1283 | dev_err(&pdev->dev, "failed to get nand clock\n"); | |
4c073cd2 | 1284 | return PTR_ERR(info->clk); |
fe69af00 | 1285 | } |
1f8eaff2 EG |
1286 | ret = clk_prepare_enable(info->clk); |
1287 | if (ret < 0) | |
1288 | return ret; | |
fe69af00 | 1289 | |
6b45c1ee EG |
1290 | if (use_dma) { |
1291 | /* | |
1292 | * This is a dirty hack to make this driver work from | |
1293 | * devicetree bindings. It can be removed once we have | |
1294 | * a prober DMA controller framework for DT. | |
1295 | */ | |
1296 | if (pdev->dev.of_node && | |
1297 | of_machine_is_compatible("marvell,pxa3xx")) { | |
1298 | info->drcmr_dat = 97; | |
1299 | info->drcmr_cmd = 99; | |
1300 | } else { | |
1301 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1302 | if (r == NULL) { | |
1303 | dev_err(&pdev->dev, | |
1304 | "no resource defined for data DMA\n"); | |
1305 | ret = -ENXIO; | |
1306 | goto fail_disable_clk; | |
1307 | } | |
1308 | info->drcmr_dat = r->start; | |
1309 | ||
1310 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1311 | if (r == NULL) { | |
1312 | dev_err(&pdev->dev, | |
1313 | "no resource defined for cmd DMA\n"); | |
1314 | ret = -ENXIO; | |
1315 | goto fail_disable_clk; | |
1316 | } | |
1317 | info->drcmr_cmd = r->start; | |
1e7ba630 | 1318 | } |
fe69af00 | 1319 | } |
fe69af00 | 1320 | |
1321 | irq = platform_get_irq(pdev, 0); | |
1322 | if (irq < 0) { | |
1323 | dev_err(&pdev->dev, "no IRQ resource defined\n"); | |
1324 | ret = -ENXIO; | |
9ca7944d | 1325 | goto fail_disable_clk; |
fe69af00 | 1326 | } |
1327 | ||
1328 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0ddd846f EG |
1329 | info->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
1330 | if (IS_ERR(info->mmio_base)) { | |
1331 | ret = PTR_ERR(info->mmio_base); | |
9ca7944d | 1332 | goto fail_disable_clk; |
fe69af00 | 1333 | } |
8638fac8 | 1334 | info->mmio_phys = r->start; |
fe69af00 | 1335 | |
62e8b851 EG |
1336 | /* Allocate a buffer to allow flash detection */ |
1337 | info->buf_size = INIT_BUFFER_SIZE; | |
1338 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); | |
1339 | if (info->data_buff == NULL) { | |
1340 | ret = -ENOMEM; | |
9ca7944d | 1341 | goto fail_disable_clk; |
62e8b851 | 1342 | } |
fe69af00 | 1343 | |
346e1259 HZ |
1344 | /* initialize all interrupts to be disabled */ |
1345 | disable_int(info, NDSR_MASK); | |
1346 | ||
b1eb234f | 1347 | ret = request_irq(irq, pxa3xx_nand_irq, 0, pdev->name, info); |
fe69af00 | 1348 | if (ret < 0) { |
1349 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
1350 | goto fail_free_buf; | |
1351 | } | |
1352 | ||
e353a20a | 1353 | platform_set_drvdata(pdev, info); |
fe69af00 | 1354 | |
d456882b | 1355 | return 0; |
fe69af00 | 1356 | |
fe69af00 | 1357 | fail_free_buf: |
401e67e2 | 1358 | free_irq(irq, info); |
62e8b851 | 1359 | kfree(info->data_buff); |
9ca7944d | 1360 | fail_disable_clk: |
fb32061f | 1361 | clk_disable_unprepare(info->clk); |
d456882b | 1362 | return ret; |
fe69af00 | 1363 | } |
1364 | ||
1365 | static int pxa3xx_nand_remove(struct platform_device *pdev) | |
1366 | { | |
e353a20a | 1367 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 | 1368 | struct pxa3xx_nand_platform_data *pdata; |
f3c8cfc2 | 1369 | int irq, cs; |
fe69af00 | 1370 | |
d456882b LW |
1371 | if (!info) |
1372 | return 0; | |
1373 | ||
453810b7 | 1374 | pdata = dev_get_platdata(&pdev->dev); |
fe69af00 | 1375 | |
dbf5986a HZ |
1376 | irq = platform_get_irq(pdev, 0); |
1377 | if (irq >= 0) | |
1378 | free_irq(irq, info); | |
498b6145 | 1379 | pxa3xx_nand_free_buff(info); |
82a72d10 | 1380 | |
fb32061f | 1381 | clk_disable_unprepare(info->clk); |
82a72d10 | 1382 | |
f3c8cfc2 LW |
1383 | for (cs = 0; cs < pdata->num_cs; cs++) |
1384 | nand_release(info->host[cs]->mtd); | |
fe69af00 | 1385 | return 0; |
1386 | } | |
1387 | ||
1e7ba630 DM |
1388 | static int pxa3xx_nand_probe_dt(struct platform_device *pdev) |
1389 | { | |
1390 | struct pxa3xx_nand_platform_data *pdata; | |
1391 | struct device_node *np = pdev->dev.of_node; | |
1392 | const struct of_device_id *of_id = | |
1393 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | |
1394 | ||
1395 | if (!of_id) | |
1396 | return 0; | |
1397 | ||
1398 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1399 | if (!pdata) | |
1400 | return -ENOMEM; | |
1401 | ||
1402 | if (of_get_property(np, "marvell,nand-enable-arbiter", NULL)) | |
1403 | pdata->enable_arbiter = 1; | |
1404 | if (of_get_property(np, "marvell,nand-keep-config", NULL)) | |
1405 | pdata->keep_config = 1; | |
1406 | of_property_read_u32(np, "num-cs", &pdata->num_cs); | |
776f265e | 1407 | pdata->flash_bbt = of_get_nand_on_flash_bbt(np); |
1e7ba630 DM |
1408 | |
1409 | pdev->dev.platform_data = pdata; | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1e7ba630 | 1413 | |
e353a20a LW |
1414 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
1415 | { | |
1416 | struct pxa3xx_nand_platform_data *pdata; | |
1e7ba630 | 1417 | struct mtd_part_parser_data ppdata = {}; |
e353a20a | 1418 | struct pxa3xx_nand_info *info; |
f3c8cfc2 | 1419 | int ret, cs, probe_success; |
e353a20a | 1420 | |
f4db2e3a EG |
1421 | #ifndef ARCH_HAS_DMA |
1422 | if (use_dma) { | |
1423 | use_dma = 0; | |
1424 | dev_warn(&pdev->dev, | |
1425 | "This platform can't do DMA on this device\n"); | |
1426 | } | |
1427 | #endif | |
1e7ba630 DM |
1428 | ret = pxa3xx_nand_probe_dt(pdev); |
1429 | if (ret) | |
1430 | return ret; | |
1431 | ||
453810b7 | 1432 | pdata = dev_get_platdata(&pdev->dev); |
e353a20a LW |
1433 | if (!pdata) { |
1434 | dev_err(&pdev->dev, "no platform data defined\n"); | |
1435 | return -ENODEV; | |
1436 | } | |
1437 | ||
d456882b LW |
1438 | ret = alloc_nand_resource(pdev); |
1439 | if (ret) { | |
1440 | dev_err(&pdev->dev, "alloc nand resource failed\n"); | |
1441 | return ret; | |
1442 | } | |
e353a20a | 1443 | |
d456882b | 1444 | info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1445 | probe_success = 0; |
1446 | for (cs = 0; cs < pdata->num_cs; cs++) { | |
b7655bcb | 1447 | struct mtd_info *mtd = info->host[cs]->mtd; |
f455578d | 1448 | |
18a84e93 EG |
1449 | /* |
1450 | * The mtd name matches the one used in 'mtdparts' kernel | |
1451 | * parameter. This name cannot be changed or otherwise | |
1452 | * user's mtd partitions configuration would get broken. | |
1453 | */ | |
1454 | mtd->name = "pxa3xx_nand-0"; | |
f3c8cfc2 | 1455 | info->cs = cs; |
b7655bcb | 1456 | ret = pxa3xx_nand_scan(mtd); |
f3c8cfc2 LW |
1457 | if (ret) { |
1458 | dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", | |
1459 | cs); | |
1460 | continue; | |
1461 | } | |
1462 | ||
1e7ba630 | 1463 | ppdata.of_node = pdev->dev.of_node; |
b7655bcb | 1464 | ret = mtd_device_parse_register(mtd, NULL, |
1e7ba630 | 1465 | &ppdata, pdata->parts[cs], |
42d7fbe2 | 1466 | pdata->nr_parts[cs]); |
f3c8cfc2 LW |
1467 | if (!ret) |
1468 | probe_success = 1; | |
1469 | } | |
1470 | ||
1471 | if (!probe_success) { | |
e353a20a LW |
1472 | pxa3xx_nand_remove(pdev); |
1473 | return -ENODEV; | |
1474 | } | |
1475 | ||
f3c8cfc2 | 1476 | return 0; |
e353a20a LW |
1477 | } |
1478 | ||
fe69af00 | 1479 | #ifdef CONFIG_PM |
1480 | static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) | |
1481 | { | |
e353a20a | 1482 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1483 | struct pxa3xx_nand_platform_data *pdata; |
1484 | struct mtd_info *mtd; | |
1485 | int cs; | |
fe69af00 | 1486 | |
453810b7 | 1487 | pdata = dev_get_platdata(&pdev->dev); |
f8155a40 | 1488 | if (info->state) { |
fe69af00 | 1489 | dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); |
1490 | return -EAGAIN; | |
1491 | } | |
1492 | ||
f3c8cfc2 LW |
1493 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1494 | mtd = info->host[cs]->mtd; | |
3fe4bae8 | 1495 | mtd_suspend(mtd); |
f3c8cfc2 LW |
1496 | } |
1497 | ||
fe69af00 | 1498 | return 0; |
1499 | } | |
1500 | ||
1501 | static int pxa3xx_nand_resume(struct platform_device *pdev) | |
1502 | { | |
e353a20a | 1503 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1504 | struct pxa3xx_nand_platform_data *pdata; |
1505 | struct mtd_info *mtd; | |
1506 | int cs; | |
051fc41c | 1507 | |
453810b7 | 1508 | pdata = dev_get_platdata(&pdev->dev); |
051fc41c LW |
1509 | /* We don't want to handle interrupt without calling mtd routine */ |
1510 | disable_int(info, NDCR_INT_MASK); | |
fe69af00 | 1511 | |
f3c8cfc2 LW |
1512 | /* |
1513 | * Directly set the chip select to a invalid value, | |
1514 | * then the driver would reset the timing according | |
1515 | * to current chip select at the beginning of cmdfunc | |
1516 | */ | |
1517 | info->cs = 0xff; | |
fe69af00 | 1518 | |
051fc41c LW |
1519 | /* |
1520 | * As the spec says, the NDSR would be updated to 0x1800 when | |
1521 | * doing the nand_clk disable/enable. | |
1522 | * To prevent it damaging state machine of the driver, clear | |
1523 | * all status before resume | |
1524 | */ | |
1525 | nand_writel(info, NDSR, NDSR_MASK); | |
f3c8cfc2 LW |
1526 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1527 | mtd = info->host[cs]->mtd; | |
ead995f8 | 1528 | mtd_resume(mtd); |
f3c8cfc2 LW |
1529 | } |
1530 | ||
18c81b18 | 1531 | return 0; |
fe69af00 | 1532 | } |
1533 | #else | |
1534 | #define pxa3xx_nand_suspend NULL | |
1535 | #define pxa3xx_nand_resume NULL | |
1536 | #endif | |
1537 | ||
1538 | static struct platform_driver pxa3xx_nand_driver = { | |
1539 | .driver = { | |
1540 | .name = "pxa3xx-nand", | |
5576bc7b | 1541 | .of_match_table = pxa3xx_nand_dt_ids, |
fe69af00 | 1542 | }, |
1543 | .probe = pxa3xx_nand_probe, | |
1544 | .remove = pxa3xx_nand_remove, | |
1545 | .suspend = pxa3xx_nand_suspend, | |
1546 | .resume = pxa3xx_nand_resume, | |
1547 | }; | |
1548 | ||
f99640de | 1549 | module_platform_driver(pxa3xx_nand_driver); |
fe69af00 | 1550 | |
1551 | MODULE_LICENSE("GPL"); | |
1552 | MODULE_DESCRIPTION("PXA3xx NAND controller driver"); |