[linux-block.git] / drivers / mtd / nand / onenand / omap2.c

/*
 *  OneNAND driver for OMAP2 / OMAP3
 *
 *  Copyright © 2005-2006 Nokia Corporation
 *
 *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
 *  IRQ and DMA support written by Timo Teras
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; see the file COPYING. If not, write to the Free Software
 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/partitions.h>
#include <linux/of_device.h>
#include <linux/omap-gpmc.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>

#include <asm/mach/flash.h>

#define DRIVER_NAME "omap2-onenand"

#define ONENAND_BUFRAM_SIZE	(1024 * 5)

struct omap2_onenand {
	struct platform_device *pdev;
	int gpmc_cs;
	unsigned long phys_base;
	struct gpio_desc *int_gpiod;
	struct mtd_info mtd;
	struct onenand_chip onenand;
	struct completion irq_done;
	struct completion dma_done;
	struct dma_chan *dma_chan;
};

static void omap2_onenand_dma_complete_func(void *completion)
{
	complete(completion);
}

static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
{
	struct omap2_onenand *c = dev_id;

	complete(&c->irq_done);

	return IRQ_HANDLED;
}

static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
{
	return readw(c->onenand.base + reg);
}

static inline void write_reg(struct omap2_onenand *c, unsigned short value,
			     int reg)
{
	writew(value, c->onenand.base + reg);
}

static int omap2_onenand_set_cfg(struct omap2_onenand *c,
				 bool sr, bool sw,
				 int latency, int burst_len)
{
	unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;

	reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;

	switch (burst_len) {
	case 0:		/* continuous */
		break;
	case 4:
		reg |= ONENAND_SYS_CFG1_BL_4;
		break;
	case 8:
		reg |= ONENAND_SYS_CFG1_BL_8;
		break;
	case 16:
		reg |= ONENAND_SYS_CFG1_BL_16;
		break;
	case 32:
		reg |= ONENAND_SYS_CFG1_BL_32;
		break;
	default:
		return -EINVAL;
	}

	if (latency > 5)
		reg |= ONENAND_SYS_CFG1_HF;
	if (latency > 7)
		reg |= ONENAND_SYS_CFG1_VHF;
	if (sr)
		reg |= ONENAND_SYS_CFG1_SYNC_READ;
	if (sw)
		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;

	write_reg(c, reg, ONENAND_REG_SYS_CFG1);

	return 0;
}

static int omap2_onenand_get_freq(int ver)
{
	switch ((ver >> 4) & 0xf) {
	case 0:
		return 40;
	case 1:
		return 54;
	case 2:
		return 66;
	case 3:
		return 83;
	case 4:
		return 104;
	}

	return -EINVAL;
}

static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
{
	printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
	       msg, state, ctrl, intr);
}

static void wait_warn(char *msg, int state, unsigned int ctrl,
		      unsigned int intr)
{
	printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
	       "intr 0x%04x\n", msg, state, ctrl, intr);
}

static int omap2_onenand_wait(struct mtd_info *mtd, int state)
{
	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	struct onenand_chip *this = mtd->priv;
	unsigned int intr = 0;
	unsigned int ctrl, ctrl_mask;
	unsigned long timeout;
	u32 syscfg;

	if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
	    state == FL_VERIFYING_ERASE) {
		int i = 21;
		unsigned int intr_flags = ONENAND_INT_MASTER;

		switch (state) {
		case FL_RESETING:
			intr_flags |= ONENAND_INT_RESET;
			break;
		case FL_PREPARING_ERASE:
			intr_flags |= ONENAND_INT_ERASE;
			break;
		case FL_VERIFYING_ERASE:
			i = 101;
			break;
		}

		while (--i) {
			udelay(1);
			intr = read_reg(c, ONENAND_REG_INTERRUPT);
			if (intr & ONENAND_INT_MASTER)
				break;
		}
		ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
		if (ctrl & ONENAND_CTRL_ERROR) {
			wait_err("controller error", state, ctrl, intr);
			return -EIO;
		}
		if ((intr & intr_flags) == intr_flags)
			return 0;
		/* Continue in wait for interrupt branch */
	}

	if (state != FL_READING) {
		int result;

		/* Turn interrupts on */
		syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
		if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
			syscfg |= ONENAND_SYS_CFG1_IOBE;
			write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
			/* Add a delay to let GPIO settle */
			syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
		}

		reinit_completion(&c->irq_done);
		result = gpiod_get_value(c->int_gpiod);
		if (result < 0) {
			ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
			intr = read_reg(c, ONENAND_REG_INTERRUPT);
			wait_err("gpio error", state, ctrl, intr);
			return result;
		} else if (result == 0) {
			int retry_cnt = 0;
retry:
			if (!wait_for_completion_io_timeout(&c->irq_done,
						msecs_to_jiffies(20))) {
				/* Timeout after 20ms */
				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
				if (ctrl & ONENAND_CTRL_ONGO &&
				    !this->ongoing) {
					/*
					 * The operation seems to be still going
					 * so give it some more time.
					 */
					retry_cnt += 1;
					if (retry_cnt < 3)
						goto retry;
					intr = read_reg(c,
							ONENAND_REG_INTERRUPT);
					wait_err("timeout", state, ctrl, intr);
					return -EIO;
				}
				intr = read_reg(c, ONENAND_REG_INTERRUPT);
				if ((intr & ONENAND_INT_MASTER) == 0)
					wait_warn("timeout", state, ctrl, intr);
			}
		}
	} else {
		int retry_cnt = 0;

		/* Turn interrupts off */
		syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
		syscfg &= ~ONENAND_SYS_CFG1_IOBE;
		write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);

		timeout = jiffies + msecs_to_jiffies(20);
		while (1) {
			if (time_before(jiffies, timeout)) {
				intr = read_reg(c, ONENAND_REG_INTERRUPT);
				if (intr & ONENAND_INT_MASTER)
					break;
			} else {
				/* Timeout after 20ms */
				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
				if (ctrl & ONENAND_CTRL_ONGO) {
					/*
					 * The operation seems to be still going
					 * so give it some more time.
					 */
					retry_cnt += 1;
					if (retry_cnt < 3) {
						timeout = jiffies +
							  msecs_to_jiffies(20);
						continue;
					}
				}
				break;
			}
		}
	}

	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);

	if (intr & ONENAND_INT_READ) {
		int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);

		if (ecc) {
			unsigned int addr1, addr8;

			addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
			addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
			if (ecc & ONENAND_ECC_2BIT_ALL) {
				printk(KERN_ERR "onenand_wait: ECC error = "
				       "0x%04x, addr1 %#x, addr8 %#x\n",
				       ecc, addr1, addr8);
				mtd->ecc_stats.failed++;
				return -EBADMSG;
			} else if (ecc & ONENAND_ECC_1BIT_ALL) {
				printk(KERN_NOTICE "onenand_wait: correctable "
				       "ECC error = 0x%04x, addr1 %#x, "
				       "addr8 %#x\n", ecc, addr1, addr8);
				mtd->ecc_stats.corrected++;
			}
		}
	} else if (state == FL_READING) {
		wait_err("timeout", state, ctrl, intr);
		return -EIO;
	}

	if (ctrl & ONENAND_CTRL_ERROR) {
		wait_err("controller error", state, ctrl, intr);
		if (ctrl & ONENAND_CTRL_LOCK)
			printk(KERN_ERR "onenand_wait: "
					"Device is write protected!!!\n");
		return -EIO;
	}

	ctrl_mask = 0xFE9F;
	if (this->ongoing)
		ctrl_mask &= ~0x8000;

	if (ctrl & ctrl_mask)
		wait_warn("unexpected controller status", state, ctrl, intr);

	return 0;
}

static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
{
	struct onenand_chip *this = mtd->priv;

	if (ONENAND_CURRENT_BUFFERRAM(this)) {
		if (area == ONENAND_DATARAM)
			return this->writesize;
		if (area == ONENAND_SPARERAM)
			return mtd->oobsize;
	}

	return 0;
}

static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
					     dma_addr_t src, dma_addr_t dst,
					     size_t count)
{
	struct dma_async_tx_descriptor *tx;
	dma_cookie_t cookie;

	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
	if (!tx) {
		dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
		return -EIO;
	}

	reinit_completion(&c->dma_done);

	tx->callback = omap2_onenand_dma_complete_func;
	tx->callback_param = &c->dma_done;

	cookie = tx->tx_submit(tx);
	if (dma_submit_error(cookie)) {
		dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
		return -EIO;
	}

	dma_async_issue_pending(c->dma_chan);

	if (!wait_for_completion_io_timeout(&c->dma_done,
					    msecs_to_jiffies(20))) {
		dmaengine_terminate_sync(c->dma_chan);
		return -ETIMEDOUT;
	}

	return 0;
}

static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
					unsigned char *buffer, int offset,
					size_t count)
{
	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	struct onenand_chip *this = mtd->priv;
	struct device *dev = &c->pdev->dev;
	void *buf = (void *)buffer;
	dma_addr_t dma_src, dma_dst;
	int bram_offset, err;
	size_t xtra;

	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
	/*
	 * If the buffer address is not DMA-able, len is not long enough to make
	 * DMA transfers profitable or panic_write() may be in an interrupt
	 * context fallback to PIO mode.
	 */
	if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
	    count < 384 || in_interrupt() || oops_in_progress )
		goto out_copy;

	xtra = count & 3;
	if (xtra) {
		count -= xtra;
		memcpy(buf + count, this->base + bram_offset + count, xtra);
	}

	dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
	dma_src = c->phys_base + bram_offset;

	if (dma_mapping_error(dev, dma_dst)) {
		dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
		goto out_copy;
	}

	err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
	dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
	if (!err)
		return 0;

	dev_err(dev, "timeout waiting for DMA\n");

out_copy:
	memcpy(buf, this->base + bram_offset, count);
	return 0;
}

static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
					 const unsigned char *buffer,
					 int offset, size_t count)
{
	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	struct onenand_chip *this = mtd->priv;
	struct device *dev = &c->pdev->dev;
	void *buf = (void *)buffer;
	dma_addr_t dma_src, dma_dst;
	int bram_offset, err;

	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
	/*
	 * If the buffer address is not DMA-able, len is not long enough to make
	 * DMA transfers profitable or panic_write() may be in an interrupt
	 * context fallback to PIO mode.
	 */
	if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 ||
	    count < 384 || in_interrupt() || oops_in_progress )
		goto out_copy;

	dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
	dma_dst = c->phys_base + bram_offset;
	if (dma_mapping_error(dev, dma_src)) {
		dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
		goto out_copy;
	}

	err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
	dma_unmap_page(dev, dma_src, count, DMA_TO_DEVICE);
	if (!err)
		return 0;

	dev_err(dev, "timeout waiting for DMA\n");

out_copy:
	memcpy(this->base + bram_offset, buf, count);
	return 0;
}

static void omap2_onenand_shutdown(struct platform_device *pdev)
{
	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);

	/* With certain content in the buffer RAM, the OMAP boot ROM code
	 * can recognize the flash chip incorrectly. Zero it out before
	 * soft reset.
	 */
	memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
}

static int omap2_onenand_probe(struct platform_device *pdev)
{
	u32 val;
	dma_cap_mask_t mask;
	int freq, latency, r;
	struct resource *res;
	struct omap2_onenand *c;
	struct gpmc_onenand_info info;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "error getting memory resource\n");
		return -EINVAL;
	}

	r = of_property_read_u32(np, "reg", &val);
	if (r) {
		dev_err(dev, "reg not found in DT\n");
		return r;
	}

	c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
	if (!c)
		return -ENOMEM;

	init_completion(&c->irq_done);
	init_completion(&c->dma_done);
	c->gpmc_cs = val;
	c->phys_base = res->start;

	c->onenand.base = devm_ioremap_resource(dev, res);
	if (IS_ERR(c->onenand.base))
		return PTR_ERR(c->onenand.base);

	c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
	if (IS_ERR(c->int_gpiod)) {
		r = PTR_ERR(c->int_gpiod);
		/* Just try again if this happens */
		if (r != -EPROBE_DEFER)
			dev_err(dev, "error getting gpio: %d\n", r);
		return r;
	}

	if (c->int_gpiod) {
		r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
				     omap2_onenand_interrupt,
				     IRQF_TRIGGER_RISING, "onenand", c);
		if (r)
			return r;

		c->onenand.wait = omap2_onenand_wait;
	}

	dma_cap_zero(mask);
	dma_cap_set(DMA_MEMCPY, mask);

	c->dma_chan = dma_request_channel(mask, NULL, NULL);
	if (c->dma_chan) {
		c->onenand.read_bufferram = omap2_onenand_read_bufferram;
		c->onenand.write_bufferram = omap2_onenand_write_bufferram;
	}

	c->pdev = pdev;
	c->mtd.priv = &c->onenand;
	c->mtd.dev.parent = dev;
	mtd_set_of_node(&c->mtd, dev->of_node);

	dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
		 c->gpmc_cs, c->phys_base, c->onenand.base,
		 c->dma_chan ? "DMA" : "PIO");

	if ((r = onenand_scan(&c->mtd, 1)) < 0)
		goto err_release_dma;

	freq = omap2_onenand_get_freq(c->onenand.version_id);
	if (freq > 0) {
		switch (freq) {
		case 104:
			latency = 7;
			break;
		case 83:
			latency = 6;
			break;
		case 66:
			latency = 5;
			break;
		case 56:
			latency = 4;
			break;
		default:	/* 40 MHz or lower */
			latency = 3;
			break;
		}

		r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
						  freq, latency, &info);
		if (r)
			goto err_release_onenand;

		r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
					  latency, info.burst_len);
		if (r)
			goto err_release_onenand;

		if (info.sync_read || info.sync_write)
			dev_info(dev, "optimized timings for %d MHz\n", freq);
	}

	r = mtd_device_register(&c->mtd, NULL, 0);
	if (r)
		goto err_release_onenand;

	platform_set_drvdata(pdev, c);

	return 0;

err_release_onenand:
	onenand_release(&c->mtd);
err_release_dma:
	if (c->dma_chan)
		dma_release_channel(c->dma_chan);

	return r;
}

static int omap2_onenand_remove(struct platform_device *pdev)
{
	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);

	onenand_release(&c->mtd);
	if (c->dma_chan)
		dma_release_channel(c->dma_chan);
	omap2_onenand_shutdown(pdev);

	return 0;
}

static const struct of_device_id omap2_onenand_id_table[] = {
	{ .compatible = "ti,omap2-onenand", },
	{},
};
MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);

static struct platform_driver omap2_onenand_driver = {
	.probe		= omap2_onenand_probe,
	.remove		= omap2_onenand_remove,
	.shutdown	= omap2_onenand_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.of_match_table = omap2_onenand_id_table,
	},
};

module_platform_driver(omap2_onenand_driver);

MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");
Commit	Line	Data
36cd4fb5	1	/*
36cd4fb5 AH	2	* OneNAND driver for OMAP2 / OMAP3
	3	*
	4	* Copyright © 2005-2006 Nokia Corporation
	5	*
	6	* Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
	7	* IRQ and DMA support written by Timo Teras
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License version 2 as published by
	11	* the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	16	* more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along with
	19	* this program; see the file COPYING. If not, write to the Free Software
	20	* Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	21	*
	22	*/
	23
	24	#include <linux/device.h>
	25	#include <linux/module.h>
36cd4fb5 AH	26	#include <linux/mtd/mtd.h>
	27	#include <linux/mtd/onenand.h>
	28	#include <linux/mtd/partitions.h>
a758f50f LM	29	#include <linux/of_device.h>
a758f50f LM	30	#include <linux/omap-gpmc.h>
36cd4fb5 AH	31	#include <linux/platform_device.h>
	32	#include <linux/interrupt.h>
	33	#include <linux/delay.h>
cbbd6956	34	#include <linux/dma-mapping.h>
3ed6a4d1	35	#include <linux/dmaengine.h>
cbbd6956	36	#include <linux/io.h>
5a0e3ad6	37	#include <linux/slab.h>
a758f50f	38	#include <linux/gpio/consumer.h>
36cd4fb5	39
36cd4fb5	40	#include <asm/mach/flash.h>
36cd4fb5	41
36cd4fb5 AH	42	#define DRIVER_NAME "omap2-onenand"
36cd4fb5 AH	43
36cd4fb5 AH	44	#define ONENAND_BUFRAM_SIZE (1024 * 5)
	45
	46	struct omap2_onenand {
	47	struct platform_device *pdev;
	48	int gpmc_cs;
	49	unsigned long phys_base;
a758f50f	50	struct gpio_desc *int_gpiod;
36cd4fb5	51	struct mtd_info mtd;
36cd4fb5 AH	52	struct onenand_chip onenand;
	53	struct completion irq_done;
	54	struct completion dma_done;
3ed6a4d1	55	struct dma_chan *dma_chan;
36cd4fb5 AH	56	};
36cd4fb5 AH	57
3ed6a4d1	58	static void omap2_onenand_dma_complete_func(void *completion)
36cd4fb5	59	{
3ed6a4d1	60	complete(completion);
36cd4fb5 AH	61	}
	62
	63	static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
	64	{
	65	struct omap2_onenand *c = dev_id;
	66
	67	complete(&c->irq_done);
	68
	69	return IRQ_HANDLED;
	70	}
	71
	72	static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
	73	{
	74	return readw(c->onenand.base + reg);
	75	}
	76
	77	static inline void write_reg(struct omap2_onenand *c, unsigned short value,
	78	int reg)
	79	{
	80	writew(value, c->onenand.base + reg);
	81	}
	82
a758f50f LM	83	static int omap2_onenand_set_cfg(struct omap2_onenand *c,
	84	bool sr, bool sw,
	85	int latency, int burst_len)
	86	{
	87	unsigned short reg = ONENAND_SYS_CFG1_RDY \| ONENAND_SYS_CFG1_INT;
	88
	89	reg \|= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
	90
	91	switch (burst_len) {
	92	case 0: /* continuous */
	93	break;
	94	case 4:
	95	reg \|= ONENAND_SYS_CFG1_BL_4;
	96	break;
	97	case 8:
	98	reg \|= ONENAND_SYS_CFG1_BL_8;
	99	break;
	100	case 16:
	101	reg \|= ONENAND_SYS_CFG1_BL_16;
	102	break;
	103	case 32:
	104	reg \|= ONENAND_SYS_CFG1_BL_32;
	105	break;
	106	default:
	107	return -EINVAL;
	108	}
	109
	110	if (latency > 5)
	111	reg \|= ONENAND_SYS_CFG1_HF;
	112	if (latency > 7)
	113	reg \|= ONENAND_SYS_CFG1_VHF;
	114	if (sr)
	115	reg \|= ONENAND_SYS_CFG1_SYNC_READ;
	116	if (sw)
	117	reg \|= ONENAND_SYS_CFG1_SYNC_WRITE;
	118
	119	write_reg(c, reg, ONENAND_REG_SYS_CFG1);
	120
	121	return 0;
	122	}
	123
	124	static int omap2_onenand_get_freq(int ver)
	125	{
	126	switch ((ver >> 4) & 0xf) {
	127	case 0:
	128	return 40;
	129	case 1:
	130	return 54;
	131	case 2:
	132	return 66;
	133	case 3:
	134	return 83;
	135	case 4:
	136	return 104;
	137	}
	138
	139	return -EINVAL;
	140	}
	141
36cd4fb5 AH	142	static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
	143	{
	144	printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
	145	msg, state, ctrl, intr);
	146	}
	147
	148	static void wait_warn(char *msg, int state, unsigned int ctrl,
	149	unsigned int intr)
	150	{
	151	printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
	152	"intr 0x%04x\n", msg, state, ctrl, intr);
	153	}
	154
	155	static int omap2_onenand_wait(struct mtd_info *mtd, int state)
	156	{
	157	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
d19d7b46	158	struct onenand_chip *this = mtd->priv;
36cd4fb5	159	unsigned int intr = 0;
d19d7b46	160	unsigned int ctrl, ctrl_mask;
36cd4fb5 AH	161	unsigned long timeout;
	162	u32 syscfg;
	163
72073027 MK	164	if (state == FL_RESETING \|\| state == FL_PREPARING_ERASE \|\|
	165	state == FL_VERIFYING_ERASE) {
	166	int i = 21;
	167	unsigned int intr_flags = ONENAND_INT_MASTER;
	168
	169	switch (state) {
	170	case FL_RESETING:
	171	intr_flags \|= ONENAND_INT_RESET;
	172	break;
	173	case FL_PREPARING_ERASE:
	174	intr_flags \|= ONENAND_INT_ERASE;
	175	break;
	176	case FL_VERIFYING_ERASE:
	177	i = 101;
	178	break;
	179	}
36cd4fb5	180
72073027	181	while (--i) {
36cd4fb5 AH	182	udelay(1);
	183	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	184	if (intr & ONENAND_INT_MASTER)
	185	break;
	186	}
	187	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	188	if (ctrl & ONENAND_CTRL_ERROR) {
	189	wait_err("controller error", state, ctrl, intr);
	190	return -EIO;
	191	}
c497dd55 RT	192	if ((intr & intr_flags) == intr_flags)
	193	return 0;
	194	/* Continue in wait for interrupt branch */
36cd4fb5 AH	195	}
	196
	197	if (state != FL_READING) {
	198	int result;
	199
	200	/* Turn interrupts on */
	201	syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
782b7a36 AH	202	if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
	203	syscfg \|= ONENAND_SYS_CFG1_IOBE;
	204	write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
f5229331 LM	205	/* Add a delay to let GPIO settle */
f5229331 LM	206	syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
782b7a36	207	}
36cd4fb5	208
16735d02	209	reinit_completion(&c->irq_done);
a758f50f	210	result = gpiod_get_value(c->int_gpiod);
bdaca934 LM	211	if (result < 0) {
	212	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	213	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	214	wait_err("gpio error", state, ctrl, intr);
a758f50f	215	return result;
bdaca934	216	} else if (result == 0) {
36cd4fb5 AH	217	int retry_cnt = 0;
36cd4fb5 AH	218	retry:
d1205688 LM	219	if (!wait_for_completion_io_timeout(&c->irq_done,
d1205688 LM	220	msecs_to_jiffies(20))) {
36cd4fb5 AH	221	/* Timeout after 20ms */
36cd4fb5 AH	222	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
d19d7b46 RT	223	if (ctrl & ONENAND_CTRL_ONGO &&
d19d7b46 RT	224	!this->ongoing) {
36cd4fb5 AH	225	/*
	226	* The operation seems to be still going
	227	* so give it some more time.
	228	*/
	229	retry_cnt += 1;
	230	if (retry_cnt < 3)
	231	goto retry;
	232	intr = read_reg(c,
	233	ONENAND_REG_INTERRUPT);
	234	wait_err("timeout", state, ctrl, intr);
	235	return -EIO;
	236	}
	237	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	238	if ((intr & ONENAND_INT_MASTER) == 0)
	239	wait_warn("timeout", state, ctrl, intr);
	240	}
	241	}
	242	} else {
8afbc114 AH	243	int retry_cnt = 0;
8afbc114 AH	244
36cd4fb5 AH	245	/* Turn interrupts off */
	246	syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
	247	syscfg &= ~ONENAND_SYS_CFG1_IOBE;
	248	write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
	249
	250	timeout = jiffies + msecs_to_jiffies(20);
8afbc114 AH	251	while (1) {
	252	if (time_before(jiffies, timeout)) {
	253	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	254	if (intr & ONENAND_INT_MASTER)
	255	break;
	256	} else {
	257	/* Timeout after 20ms */
	258	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	259	if (ctrl & ONENAND_CTRL_ONGO) {
	260	/*
	261	* The operation seems to be still going
	262	* so give it some more time.
	263	*/
	264	retry_cnt += 1;
	265	if (retry_cnt < 3) {
	266	timeout = jiffies +
	267	msecs_to_jiffies(20);
	268	continue;
	269	}
	270	}
36cd4fb5	271	break;
8afbc114	272	}
36cd4fb5 AH	273	}
	274	}
	275
	276	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	277	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	278
	279	if (intr & ONENAND_INT_READ) {
	280	int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
	281
	282	if (ecc) {
	283	unsigned int addr1, addr8;
	284
	285	addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
	286	addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
	287	if (ecc & ONENAND_ECC_2BIT_ALL) {
	288	printk(KERN_ERR "onenand_wait: ECC error = "
	289	"0x%04x, addr1 %#x, addr8 %#x\n",
	290	ecc, addr1, addr8);
	291	mtd->ecc_stats.failed++;
	292	return -EBADMSG;
	293	} else if (ecc & ONENAND_ECC_1BIT_ALL) {
	294	printk(KERN_NOTICE "onenand_wait: correctable "
	295	"ECC error = 0x%04x, addr1 %#x, "
	296	"addr8 %#x\n", ecc, addr1, addr8);
	297	mtd->ecc_stats.corrected++;
	298	}
	299	}
	300	} else if (state == FL_READING) {
	301	wait_err("timeout", state, ctrl, intr);
	302	return -EIO;
	303	}
	304
	305	if (ctrl & ONENAND_CTRL_ERROR) {
	306	wait_err("controller error", state, ctrl, intr);
	307	if (ctrl & ONENAND_CTRL_LOCK)
	308	printk(KERN_ERR "onenand_wait: "
	309	"Device is write protected!!!\n");
	310	return -EIO;
	311	}
	312
d19d7b46 RT	313	ctrl_mask = 0xFE9F;
	314	if (this->ongoing)
	315	ctrl_mask &= ~0x8000;
	316
	317	if (ctrl & ctrl_mask)
36cd4fb5 AH	318	wait_warn("unexpected controller status", state, ctrl, intr);
	319
	320	return 0;
	321	}
	322
	323	static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
	324	{
	325	struct onenand_chip *this = mtd->priv;
	326
	327	if (ONENAND_CURRENT_BUFFERRAM(this)) {
	328	if (area == ONENAND_DATARAM)
00acf4a8	329	return this->writesize;
36cd4fb5 AH	330	if (area == ONENAND_SPARERAM)
	331	return mtd->oobsize;
	332	}
	333
	334	return 0;
	335	}
	336
36213116 PU	337	static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
	338	dma_addr_t src, dma_addr_t dst,
	339	size_t count)
	340	{
3ed6a4d1 PU	341	struct dma_async_tx_descriptor *tx;
3ed6a4d1 PU	342	dma_cookie_t cookie;
36213116	343
3ed6a4d1 PU	344	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
	345	if (!tx) {
	346	dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
	347	return -EIO;
	348	}
36213116 PU	349
36213116 PU	350	reinit_completion(&c->dma_done);
3ed6a4d1 PU	351
	352	tx->callback = omap2_onenand_dma_complete_func;
	353	tx->callback_param = &c->dma_done;
	354
	355	cookie = tx->tx_submit(tx);
	356	if (dma_submit_error(cookie)) {
	357	dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
	358	return -EIO;
	359	}
	360
	361	dma_async_issue_pending(c->dma_chan);
	362
36213116 PU	363	if (!wait_for_completion_io_timeout(&c->dma_done,
36213116 PU	364	msecs_to_jiffies(20))) {
3ed6a4d1	365	dmaengine_terminate_sync(c->dma_chan);
36213116 PU	366	return -ETIMEDOUT;
	367	}
	368
	369	return 0;
	370	}
	371
fb25070a	372	static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
36cd4fb5 AH	373	unsigned char *buffer, int offset,
	374	size_t count)
	375	{
	376	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	377	struct onenand_chip *this = mtd->priv;
6732cfd4	378	struct device *dev = &c->pdev->dev;
36cd4fb5	379	void buf = (void )buffer;
6732cfd4 LM	380	dma_addr_t dma_src, dma_dst;
6732cfd4 LM	381	int bram_offset, err;
36cd4fb5	382	size_t xtra;
36cd4fb5 AH	383
36cd4fb5 AH	384	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
6732cfd4 LM	385	/*
	386	* If the buffer address is not DMA-able, len is not long enough to make
	387	* DMA transfers profitable or panic_write() may be in an interrupt
	388	* context fallback to PIO mode.
	389	*/
	390	if (!virt_addr_valid(buf) \|\| bram_offset & 3 \|\| (size_t)buf & 3 \|\|
	391	count < 384 \|\| in_interrupt() \|\| oops_in_progress )
a29f280b AH	392	goto out_copy;
a29f280b AH	393
36cd4fb5 AH	394	xtra = count & 3;
	395	if (xtra) {
	396	count -= xtra;
	397	memcpy(buf + count, this->base + bram_offset + count, xtra);
	398	}
	399
6732cfd4	400	dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE);
36cd4fb5	401	dma_src = c->phys_base + bram_offset;
36cd4fb5	402
6732cfd4 LM	403	if (dma_mapping_error(dev, dma_dst)) {
6732cfd4 LM	404	dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
36cd4fb5 AH	405	goto out_copy;
	406	}
	407
6732cfd4 LM	408	err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
	409	dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
	410	if (!err)
	411	return 0;
	412
	413	dev_err(dev, "timeout waiting for DMA\n");
36cd4fb5 AH	414
	415	out_copy:
	416	memcpy(buf, this->base + bram_offset, count);
	417	return 0;
	418	}
	419
fb25070a	420	static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
36cd4fb5 AH	421	const unsigned char *buffer,
	422	int offset, size_t count)
	423	{
	424	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	425	struct onenand_chip *this = mtd->priv;
6732cfd4	426	struct device *dev = &c->pdev->dev;
36cd4fb5	427	void buf = (void )buffer;
6732cfd4 LM	428	dma_addr_t dma_src, dma_dst;
6732cfd4 LM	429	int bram_offset, err;
36cd4fb5 AH	430
36cd4fb5 AH	431	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
6732cfd4 LM	432	/*
	433	* If the buffer address is not DMA-able, len is not long enough to make
	434	* DMA transfers profitable or panic_write() may be in an interrupt
	435	* context fallback to PIO mode.
	436	*/
	437	if (!virt_addr_valid(buf) \|\| bram_offset & 3 \|\| (size_t)buf & 3 \|\|
	438	count < 384 \|\| in_interrupt() \|\| oops_in_progress )
36cd4fb5 AH	439	goto out_copy;
36cd4fb5 AH	440
6732cfd4	441	dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE);
36cd4fb5	442	dma_dst = c->phys_base + bram_offset;
6732cfd4 LM	443	if (dma_mapping_error(dev, dma_src)) {
6732cfd4 LM	444	dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
36cd4fb5 AH	445	goto out_copy;
	446	}
	447
6732cfd4 LM	448	err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
	449	dma_unmap_page(dev, dma_src, count, DMA_TO_DEVICE);
	450	if (!err)
	451	return 0;
	452
	453	dev_err(dev, "timeout waiting for DMA\n");
36cd4fb5 AH	454
	455	out_copy:
	456	memcpy(this->base + bram_offset, buf, count);
	457	return 0;
	458	}
	459
d3412dbd	460	static void omap2_onenand_shutdown(struct platform_device *pdev)
36cd4fb5 AH	461	{
	462	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
	463
	464	/* With certain content in the buffer RAM, the OMAP boot ROM code
	465	* can recognize the flash chip incorrectly. Zero it out before
	466	* soft reset.
	467	*/
	468	memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
	469	}
	470
06f25510	471	static int omap2_onenand_probe(struct platform_device *pdev)
36cd4fb5	472	{
a758f50f	473	u32 val;
bdaca934	474	dma_cap_mask_t mask;
a758f50f	475	int freq, latency, r;
d65ccb6d	476	struct resource *res;
a758f50f LM	477	struct omap2_onenand *c;
	478	struct gpmc_onenand_info info;
	479	struct device *dev = &pdev->dev;
	480	struct device_node *np = dev->of_node;
	481
	482	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	483	if (!res) {
	484	dev_err(dev, "error getting memory resource\n");
	485	return -EINVAL;
	486	}
36cd4fb5	487
a758f50f LM	488	r = of_property_read_u32(np, "reg", &val);
	489	if (r) {
	490	dev_err(dev, "reg not found in DT\n");
	491	return r;
36cd4fb5 AH	492	}
36cd4fb5 AH	493
a758f50f	494	c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
36cd4fb5 AH	495	if (!c)
	496	return -ENOMEM;
	497
	498	init_completion(&c->irq_done);
	499	init_completion(&c->dma_done);
a758f50f	500	c->gpmc_cs = val;
d65ccb6d	501	c->phys_base = res->start;
36cd4fb5	502
a758f50f	503	c->onenand.base = devm_ioremap_resource(dev, res);
e6b90db8	504	if (IS_ERR(c->onenand.base))
a758f50f	505	return PTR_ERR(c->onenand.base);
36cd4fb5	506
a758f50f LM	507	c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
	508	if (IS_ERR(c->int_gpiod)) {
	509	r = PTR_ERR(c->int_gpiod);
	510	/* Just try again if this happens */
	511	if (r != -EPROBE_DEFER)
	512	dev_err(dev, "error getting gpio: %d\n", r);
	513	return r;
	514	}
36cd4fb5	515
a758f50f LM	516	if (c->int_gpiod) {
	517	r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
	518	omap2_onenand_interrupt,
	519	IRQF_TRIGGER_RISING, "onenand", c);
	520	if (r)
	521	return r;
36cd4fb5	522
a758f50f	523	c->onenand.wait = omap2_onenand_wait;
bdaca934	524	}
3ed6a4d1	525
bdaca934 LM	526	dma_cap_zero(mask);
bdaca934 LM	527	dma_cap_set(DMA_MEMCPY, mask);
3ed6a4d1	528
bdaca934	529	c->dma_chan = dma_request_channel(mask, NULL, NULL);
a758f50f LM	530	if (c->dma_chan) {
	531	c->onenand.read_bufferram = omap2_onenand_read_bufferram;
	532	c->onenand.write_bufferram = omap2_onenand_write_bufferram;
	533	}
36cd4fb5 AH	534
36cd4fb5 AH	535	c->pdev = pdev;
36cd4fb5	536	c->mtd.priv = &c->onenand;
a758f50f LM	537	c->mtd.dev.parent = dev;
a758f50f LM	538	mtd_set_of_node(&c->mtd, dev->of_node);
36cd4fb5	539
a758f50f LM	540	dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
	541	c->gpmc_cs, c->phys_base, c->onenand.base,
	542	c->dma_chan ? "DMA" : "PIO");
36cd4fb5 AH	543
36cd4fb5 AH	544	if ((r = onenand_scan(&c->mtd, 1)) < 0)
e6854e02	545	goto err_release_dma;
36cd4fb5	546
a758f50f LM	547	freq = omap2_onenand_get_freq(c->onenand.version_id);
	548	if (freq > 0) {
	549	switch (freq) {
	550	case 104:
	551	latency = 7;
	552	break;
	553	case 83:
	554	latency = 6;
	555	break;
	556	case 66:
	557	latency = 5;
	558	break;
	559	case 56:
	560	latency = 4;
	561	break;
	562	default: /* 40 MHz or lower */
	563	latency = 3;
	564	break;
	565	}
	566
	567	r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
	568	freq, latency, &info);
	569	if (r)
	570	goto err_release_onenand;
	571
	572	r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
	573	latency, info.burst_len);
	574	if (r)
	575	goto err_release_onenand;
	576
	577	if (info.sync_read \|\| info.sync_write)
	578	dev_info(dev, "optimized timings for %d MHz\n", freq);
	579	}
	580
fafc0b3a	581	r = mtd_device_register(&c->mtd, NULL, 0);
263a8c86	582	if (r)
36cd4fb5 AH	583	goto err_release_onenand;
	584
	585	platform_set_drvdata(pdev, c);
	586
	587	return 0;
	588
	589	err_release_onenand:
	590	onenand_release(&c->mtd);
	591	err_release_dma:
3ed6a4d1 PU	592	if (c->dma_chan)
3ed6a4d1 PU	593	dma_release_channel(c->dma_chan);
36cd4fb5 AH	594
	595	return r;
	596	}
	597
810b7e06	598	static int omap2_onenand_remove(struct platform_device *pdev)
36cd4fb5 AH	599	{
	600	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
	601
36cd4fb5	602	onenand_release(&c->mtd);
3ed6a4d1 PU	603	if (c->dma_chan)
3ed6a4d1 PU	604	dma_release_channel(c->dma_chan);
36cd4fb5	605	omap2_onenand_shutdown(pdev);
36cd4fb5 AH	606
	607	return 0;
	608	}
	609
a758f50f LM	610	static const struct of_device_id omap2_onenand_id_table[] = {
	611	{ .compatible = "ti,omap2-onenand", },
	612	{},
	613	};
	614	MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
	615
36cd4fb5 AH	616	static struct platform_driver omap2_onenand_driver = {
36cd4fb5 AH	617	.probe = omap2_onenand_probe,
5153b88c	618	.remove = omap2_onenand_remove,
36cd4fb5 AH	619	.shutdown = omap2_onenand_shutdown,
	620	.driver = {
	621	.name = DRIVER_NAME,
a758f50f	622	.of_match_table = omap2_onenand_id_table,
36cd4fb5 AH	623	},
	624	};
	625
cdb6404c	626	module_platform_driver(omap2_onenand_driver);
36cd4fb5	627
c804c733	628	MODULE_ALIAS("platform:" DRIVER_NAME);
36cd4fb5 AH	629	MODULE_LICENSE("GPL");
	630	MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
	631	MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");