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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
10f22ee3 | 15 | #include <linux/gpio/consumer.h> |
a0e5cc58 | 16 | #include <linux/module.h> |
4e070376 | 17 | #include <linux/interrupt.h> |
c276aca4 | 18 | #include <linux/jiffies.h> |
19 | #include <linux/sched.h> | |
67ce04bf VS |
20 | #include <linux/mtd/mtd.h> |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/mtd/partitions.h> | |
763e7359 | 23 | #include <linux/omap-dma.h> |
67ce04bf | 24 | #include <linux/io.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
62116e51 PA |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
67ce04bf | 28 | |
32d42a85 | 29 | #include <linux/mtd/nand_bch.h> |
62116e51 | 30 | #include <linux/platform_data/elm.h> |
0e618ef0 | 31 | |
c509aefd | 32 | #include <linux/omap-gpmc.h> |
2203747c | 33 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 34 | |
67ce04bf | 35 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 36 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 37 | |
67ce04bf VS |
38 | #define NAND_Ecc_P1e (1 << 0) |
39 | #define NAND_Ecc_P2e (1 << 1) | |
40 | #define NAND_Ecc_P4e (1 << 2) | |
41 | #define NAND_Ecc_P8e (1 << 3) | |
42 | #define NAND_Ecc_P16e (1 << 4) | |
43 | #define NAND_Ecc_P32e (1 << 5) | |
44 | #define NAND_Ecc_P64e (1 << 6) | |
45 | #define NAND_Ecc_P128e (1 << 7) | |
46 | #define NAND_Ecc_P256e (1 << 8) | |
47 | #define NAND_Ecc_P512e (1 << 9) | |
48 | #define NAND_Ecc_P1024e (1 << 10) | |
49 | #define NAND_Ecc_P2048e (1 << 11) | |
50 | ||
51 | #define NAND_Ecc_P1o (1 << 16) | |
52 | #define NAND_Ecc_P2o (1 << 17) | |
53 | #define NAND_Ecc_P4o (1 << 18) | |
54 | #define NAND_Ecc_P8o (1 << 19) | |
55 | #define NAND_Ecc_P16o (1 << 20) | |
56 | #define NAND_Ecc_P32o (1 << 21) | |
57 | #define NAND_Ecc_P64o (1 << 22) | |
58 | #define NAND_Ecc_P128o (1 << 23) | |
59 | #define NAND_Ecc_P256o (1 << 24) | |
60 | #define NAND_Ecc_P512o (1 << 25) | |
61 | #define NAND_Ecc_P1024o (1 << 26) | |
62 | #define NAND_Ecc_P2048o (1 << 27) | |
63 | ||
64 | #define TF(value) (value ? 1 : 0) | |
65 | ||
66 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
67 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
68 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
69 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
70 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
71 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
72 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
73 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
74 | ||
75 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
76 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
77 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
78 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
79 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
80 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
81 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
82 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
83 | ||
84 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
85 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
86 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
87 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
88 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
89 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
90 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
91 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
92 | ||
93 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
94 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
95 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
96 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
97 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
98 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
99 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
100 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
101 | ||
102 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
103 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
104 | ||
65b97cf6 AM |
105 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
106 | #define ECC_CONFIG_CS_SHIFT 1 | |
107 | #define CS_MASK 0x7 | |
108 | #define ENABLE_PREFETCH (0x1 << 7) | |
109 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 110 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
111 | #define ECCSIZE1_SHIFT 22 |
112 | #define ECC1RESULTSIZE 0x1 | |
113 | #define ECCCLEAR 0x100 | |
114 | #define ECC1 0x1 | |
47f88af4 AM |
115 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
116 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
117 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
118 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
119 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 120 | |
d5e7c864 LV |
121 | #define OMAP24XX_DMA_GPMC 4 |
122 | ||
62116e51 PA |
123 | #define SECTOR_BYTES 512 |
124 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ | |
125 | #define BCH4_BIT_PAD 4 | |
62116e51 PA |
126 | |
127 | /* GPMC ecc engine settings for read */ | |
128 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
129 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
130 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
131 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
132 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
133 | ||
134 | /* GPMC ecc engine settings for write */ | |
135 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
136 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
137 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
138 | ||
b491da72 | 139 | #define BADBLOCK_MARKER_LENGTH 2 |
a919e511 | 140 | |
9748fff9 | 141 | static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, |
142 | 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78, | |
143 | 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93, | |
144 | 0x07, 0x0e}; | |
62116e51 PA |
145 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, |
146 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | |
147 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | |
62116e51 | 148 | |
1dc338e8 RL |
149 | /* Shared among all NAND instances to synchronize access to the ECC Engine */ |
150 | static struct nand_hw_control omap_gpmc_controller = { | |
151 | .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock), | |
152 | .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq), | |
153 | }; | |
59e9c5ae | 154 | |
67ce04bf | 155 | struct omap_nand_info { |
67ce04bf VS |
156 | struct nand_chip nand; |
157 | struct platform_device *pdev; | |
158 | ||
159 | int gpmc_cs; | |
01b95fc6 RQ |
160 | bool dev_ready; |
161 | enum nand_io xfer_type; | |
162 | int devsize; | |
4e558072 | 163 | enum omap_ecc ecc_opt; |
01b95fc6 RQ |
164 | struct device_node *elm_of_node; |
165 | ||
166 | unsigned long phys_base; | |
dfe32893 | 167 | struct completion comp; |
763e7359 | 168 | struct dma_chan *dma; |
5c468455 AM |
169 | int gpmc_irq_fifo; |
170 | int gpmc_irq_count; | |
4e070376 SG |
171 | enum { |
172 | OMAP_NAND_IO_READ = 0, /* read */ | |
173 | OMAP_NAND_IO_WRITE, /* write */ | |
174 | } iomode; | |
175 | u_char *buf; | |
176 | int buf_len; | |
c509aefd | 177 | /* Interface to GPMC */ |
65b97cf6 | 178 | struct gpmc_nand_regs reg; |
c509aefd | 179 | struct gpmc_nand_ops *ops; |
c9711ec5 | 180 | bool flash_bbt; |
a919e511 | 181 | /* fields specific for BCHx_HW ECC scheme */ |
62116e51 | 182 | struct device *elm_dev; |
10f22ee3 RQ |
183 | /* NAND ready gpio */ |
184 | struct gpio_desc *ready_gpiod; | |
67ce04bf VS |
185 | }; |
186 | ||
4578ea9a BB |
187 | static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd) |
188 | { | |
432420c0 | 189 | return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand); |
4578ea9a | 190 | } |
432420c0 | 191 | |
65b97cf6 AM |
192 | /** |
193 | * omap_prefetch_enable - configures and starts prefetch transfer | |
194 | * @cs: cs (chip select) number | |
195 | * @fifo_th: fifo threshold to be used for read/ write | |
196 | * @dma_mode: dma mode enable (1) or disable (0) | |
197 | * @u32_count: number of bytes to be transferred | |
198 | * @is_write: prefetch read(0) or write post(1) mode | |
199 | */ | |
200 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
201 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
202 | { | |
203 | u32 val; | |
204 | ||
205 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
206 | return -1; | |
207 | ||
208 | if (readl(info->reg.gpmc_prefetch_control)) | |
209 | return -EBUSY; | |
210 | ||
211 | /* Set the amount of bytes to be prefetched */ | |
212 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
213 | ||
214 | /* Set dma/mpu mode, the prefetch read / post write and | |
215 | * enable the engine. Set which cs is has requested for. | |
216 | */ | |
217 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
218 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
57a605b1 | 219 | (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1)); |
65b97cf6 AM |
220 | writel(val, info->reg.gpmc_prefetch_config1); |
221 | ||
222 | /* Start the prefetch engine */ | |
223 | writel(0x1, info->reg.gpmc_prefetch_control); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | /** | |
229 | * omap_prefetch_reset - disables and stops the prefetch engine | |
230 | */ | |
231 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
232 | { | |
233 | u32 config1; | |
234 | ||
235 | /* check if the same module/cs is trying to reset */ | |
236 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
237 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
238 | return -EINVAL; | |
239 | ||
240 | /* Stop the PFPW engine */ | |
241 | writel(0x0, info->reg.gpmc_prefetch_control); | |
242 | ||
243 | /* Reset/disable the PFPW engine */ | |
244 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
67ce04bf VS |
249 | /** |
250 | * omap_hwcontrol - hardware specific access to control-lines | |
251 | * @mtd: MTD device structure | |
252 | * @cmd: command to device | |
253 | * @ctrl: | |
254 | * NAND_NCE: bit 0 -> don't care | |
255 | * NAND_CLE: bit 1 -> Command Latch | |
256 | * NAND_ALE: bit 2 -> Address Latch | |
257 | * | |
258 | * NOTE: boards may use different bits for these!! | |
259 | */ | |
260 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
261 | { | |
4578ea9a | 262 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 263 | |
2c01946c SG |
264 | if (cmd != NAND_CMD_NONE) { |
265 | if (ctrl & NAND_CLE) | |
65b97cf6 | 266 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
267 | |
268 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 269 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
270 | |
271 | else /* NAND_NCE */ | |
65b97cf6 | 272 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 273 | } |
67ce04bf VS |
274 | } |
275 | ||
59e9c5ae | 276 | /** |
277 | * omap_read_buf8 - read data from NAND controller into buffer | |
278 | * @mtd: MTD device structure | |
279 | * @buf: buffer to store date | |
280 | * @len: number of bytes to read | |
281 | */ | |
282 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
283 | { | |
4bd4ebcc | 284 | struct nand_chip *nand = mtd_to_nand(mtd); |
59e9c5ae | 285 | |
286 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
287 | } | |
288 | ||
289 | /** | |
290 | * omap_write_buf8 - write buffer to NAND controller | |
291 | * @mtd: MTD device structure | |
292 | * @buf: data buffer | |
293 | * @len: number of bytes to write | |
294 | */ | |
295 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
296 | { | |
4578ea9a | 297 | struct omap_nand_info *info = mtd_to_omap(mtd); |
59e9c5ae | 298 | u_char *p = (u_char *)buf; |
d6e55216 | 299 | bool status; |
59e9c5ae | 300 | |
301 | while (len--) { | |
302 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
303 | /* wait until buffer is available for write */ |
304 | do { | |
d6e55216 | 305 | status = info->ops->nand_writebuffer_empty(); |
2c01946c | 306 | } while (!status); |
59e9c5ae | 307 | } |
308 | } | |
309 | ||
67ce04bf VS |
310 | /** |
311 | * omap_read_buf16 - read data from NAND controller into buffer | |
312 | * @mtd: MTD device structure | |
313 | * @buf: buffer to store date | |
314 | * @len: number of bytes to read | |
315 | */ | |
316 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
317 | { | |
4bd4ebcc | 318 | struct nand_chip *nand = mtd_to_nand(mtd); |
67ce04bf | 319 | |
59e9c5ae | 320 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
321 | } |
322 | ||
323 | /** | |
324 | * omap_write_buf16 - write buffer to NAND controller | |
325 | * @mtd: MTD device structure | |
326 | * @buf: data buffer | |
327 | * @len: number of bytes to write | |
328 | */ | |
329 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
330 | { | |
4578ea9a | 331 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 332 | u16 *p = (u16 *) buf; |
d6e55216 | 333 | bool status; |
67ce04bf VS |
334 | /* FIXME try bursts of writesw() or DMA ... */ |
335 | len >>= 1; | |
336 | ||
337 | while (len--) { | |
59e9c5ae | 338 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
339 | /* wait until buffer is available for write */ |
340 | do { | |
d6e55216 | 341 | status = info->ops->nand_writebuffer_empty(); |
2c01946c | 342 | } while (!status); |
67ce04bf VS |
343 | } |
344 | } | |
59e9c5ae | 345 | |
346 | /** | |
347 | * omap_read_buf_pref - read data from NAND controller into buffer | |
348 | * @mtd: MTD device structure | |
349 | * @buf: buffer to store date | |
350 | * @len: number of bytes to read | |
351 | */ | |
352 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
353 | { | |
4578ea9a | 354 | struct omap_nand_info *info = mtd_to_omap(mtd); |
2c01946c | 355 | uint32_t r_count = 0; |
59e9c5ae | 356 | int ret = 0; |
357 | u32 *p = (u32 *)buf; | |
358 | ||
359 | /* take care of subpage reads */ | |
c3341d0c VS |
360 | if (len % 4) { |
361 | if (info->nand.options & NAND_BUSWIDTH_16) | |
362 | omap_read_buf16(mtd, buf, len % 4); | |
363 | else | |
364 | omap_read_buf8(mtd, buf, len % 4); | |
365 | p = (u32 *) (buf + len % 4); | |
366 | len -= len % 4; | |
59e9c5ae | 367 | } |
59e9c5ae | 368 | |
369 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
370 | ret = omap_prefetch_enable(info->gpmc_cs, |
371 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 372 | if (ret) { |
373 | /* PFPW engine is busy, use cpu copy method */ | |
374 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 375 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 376 | else |
c5d8c0ca | 377 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 378 | } else { |
379 | do { | |
65b97cf6 | 380 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 381 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
382 | r_count = r_count >> 2; |
383 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 384 | p += r_count; |
385 | len -= r_count << 2; | |
386 | } while (len); | |
59e9c5ae | 387 | /* disable and stop the PFPW engine */ |
65b97cf6 | 388 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 389 | } |
390 | } | |
391 | ||
392 | /** | |
393 | * omap_write_buf_pref - write buffer to NAND controller | |
394 | * @mtd: MTD device structure | |
395 | * @buf: data buffer | |
396 | * @len: number of bytes to write | |
397 | */ | |
398 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
399 | const u_char *buf, int len) | |
400 | { | |
4578ea9a | 401 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4e070376 | 402 | uint32_t w_count = 0; |
59e9c5ae | 403 | int i = 0, ret = 0; |
c5d8c0ca | 404 | u16 *p = (u16 *)buf; |
4e070376 | 405 | unsigned long tim, limit; |
65b97cf6 | 406 | u32 val; |
59e9c5ae | 407 | |
408 | /* take care of subpage writes */ | |
409 | if (len % 2 != 0) { | |
2c01946c | 410 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 411 | p = (u16 *)(buf + 1); |
412 | len--; | |
413 | } | |
414 | ||
415 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
416 | ret = omap_prefetch_enable(info->gpmc_cs, |
417 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 418 | if (ret) { |
419 | /* PFPW engine is busy, use cpu copy method */ | |
420 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 421 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 422 | else |
c5d8c0ca | 423 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 424 | } else { |
2c01946c | 425 | while (len) { |
65b97cf6 | 426 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 427 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 428 | w_count = w_count >> 1; |
59e9c5ae | 429 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 430 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 431 | } |
2c01946c | 432 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
433 | tim = 0; |
434 | limit = (loops_per_jiffy * | |
435 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 436 | do { |
4e070376 | 437 | cpu_relax(); |
65b97cf6 | 438 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 439 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 440 | } while (val && (tim++ < limit)); |
4e070376 | 441 | |
59e9c5ae | 442 | /* disable and stop the PFPW engine */ |
65b97cf6 | 443 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 444 | } |
445 | } | |
446 | ||
dfe32893 | 447 | /* |
2df41d05 | 448 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 449 | * @data: pointer to completion data structure |
450 | */ | |
763e7359 RK |
451 | static void omap_nand_dma_callback(void *data) |
452 | { | |
453 | complete((struct completion *) data); | |
454 | } | |
dfe32893 | 455 | |
456 | /* | |
4cacbe22 | 457 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 458 | * @mtd: MTD device structure |
459 | * @addr: virtual address in RAM of source/destination | |
460 | * @len: number of data bytes to be transferred | |
461 | * @is_write: flag for read/write operation | |
462 | */ | |
463 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
464 | unsigned int len, int is_write) | |
465 | { | |
4578ea9a | 466 | struct omap_nand_info *info = mtd_to_omap(mtd); |
2df41d05 | 467 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 468 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
469 | DMA_FROM_DEVICE; | |
2df41d05 | 470 | struct scatterlist sg; |
4e070376 | 471 | unsigned long tim, limit; |
2df41d05 RK |
472 | unsigned n; |
473 | int ret; | |
65b97cf6 | 474 | u32 val; |
dfe32893 | 475 | |
476 | if (addr >= high_memory) { | |
477 | struct page *p1; | |
478 | ||
479 | if (((size_t)addr & PAGE_MASK) != | |
480 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
481 | goto out_copy; | |
482 | p1 = vmalloc_to_page(addr); | |
483 | if (!p1) | |
484 | goto out_copy; | |
485 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
486 | } | |
487 | ||
2df41d05 RK |
488 | sg_init_one(&sg, addr, len); |
489 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
490 | if (n == 0) { | |
dfe32893 | 491 | dev_err(&info->pdev->dev, |
492 | "Couldn't DMA map a %d byte buffer\n", len); | |
493 | goto out_copy; | |
494 | } | |
495 | ||
2df41d05 RK |
496 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
497 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
498 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
499 | if (!tx) | |
500 | goto out_copy_unmap; | |
501 | ||
502 | tx->callback = omap_nand_dma_callback; | |
503 | tx->callback_param = &info->comp; | |
504 | dmaengine_submit(tx); | |
505 | ||
03d3a1df CJF |
506 | init_completion(&info->comp); |
507 | ||
508 | /* setup and start DMA using dma_addr */ | |
509 | dma_async_issue_pending(info->dma); | |
510 | ||
65b97cf6 AM |
511 | /* configure and start prefetch transfer */ |
512 | ret = omap_prefetch_enable(info->gpmc_cs, | |
513 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 514 | if (ret) |
4e070376 | 515 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 516 | goto out_copy_unmap; |
dfe32893 | 517 | |
dfe32893 | 518 | wait_for_completion(&info->comp); |
4e070376 SG |
519 | tim = 0; |
520 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
521 | |
522 | do { | |
4e070376 | 523 | cpu_relax(); |
65b97cf6 | 524 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 525 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 526 | } while (val && (tim++ < limit)); |
dfe32893 | 527 | |
dfe32893 | 528 | /* disable and stop the PFPW engine */ |
65b97cf6 | 529 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 530 | |
2df41d05 | 531 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 532 | return 0; |
533 | ||
d7efe228 | 534 | out_copy_unmap: |
2df41d05 | 535 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 536 | out_copy: |
537 | if (info->nand.options & NAND_BUSWIDTH_16) | |
538 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
539 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
540 | else | |
541 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
542 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
543 | return 0; | |
544 | } | |
dfe32893 | 545 | |
546 | /** | |
547 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
548 | * @mtd: MTD device structure | |
549 | * @buf: buffer to store date | |
550 | * @len: number of bytes to read | |
551 | */ | |
552 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
553 | { | |
554 | if (len <= mtd->oobsize) | |
555 | omap_read_buf_pref(mtd, buf, len); | |
556 | else | |
557 | /* start transfer in DMA mode */ | |
558 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
559 | } | |
560 | ||
561 | /** | |
562 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
563 | * @mtd: MTD device structure | |
564 | * @buf: data buffer | |
565 | * @len: number of bytes to write | |
566 | */ | |
567 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
568 | const u_char *buf, int len) | |
569 | { | |
570 | if (len <= mtd->oobsize) | |
571 | omap_write_buf_pref(mtd, buf, len); | |
572 | else | |
573 | /* start transfer in DMA mode */ | |
bdaefc41 | 574 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 575 | } |
576 | ||
4e070376 | 577 | /* |
4cacbe22 | 578 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
579 | * @this_irq: gpmc irq number |
580 | * @dev: omap_nand_info structure pointer is passed here | |
581 | */ | |
582 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
583 | { | |
584 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
585 | u32 bytes; | |
4e070376 | 586 | |
65b97cf6 | 587 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 588 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
589 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
590 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 591 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
592 | goto done; |
593 | ||
594 | if (info->buf_len && (info->buf_len < bytes)) | |
595 | bytes = info->buf_len; | |
596 | else if (!info->buf_len) | |
597 | bytes = 0; | |
598 | iowrite32_rep(info->nand.IO_ADDR_W, | |
599 | (u32 *)info->buf, bytes >> 2); | |
600 | info->buf = info->buf + bytes; | |
601 | info->buf_len -= bytes; | |
602 | ||
603 | } else { | |
604 | ioread32_rep(info->nand.IO_ADDR_R, | |
605 | (u32 *)info->buf, bytes >> 2); | |
606 | info->buf = info->buf + bytes; | |
607 | ||
5c468455 | 608 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
609 | goto done; |
610 | } | |
4e070376 SG |
611 | |
612 | return IRQ_HANDLED; | |
613 | ||
614 | done: | |
615 | complete(&info->comp); | |
4e070376 | 616 | |
5c468455 AM |
617 | disable_irq_nosync(info->gpmc_irq_fifo); |
618 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
619 | |
620 | return IRQ_HANDLED; | |
621 | } | |
622 | ||
623 | /* | |
624 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
625 | * @mtd: MTD device structure | |
626 | * @buf: buffer to store date | |
627 | * @len: number of bytes to read | |
628 | */ | |
629 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
630 | { | |
4578ea9a | 631 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4e070376 SG |
632 | int ret = 0; |
633 | ||
634 | if (len <= mtd->oobsize) { | |
635 | omap_read_buf_pref(mtd, buf, len); | |
636 | return; | |
637 | } | |
638 | ||
639 | info->iomode = OMAP_NAND_IO_READ; | |
640 | info->buf = buf; | |
641 | init_completion(&info->comp); | |
642 | ||
643 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
644 | ret = omap_prefetch_enable(info->gpmc_cs, |
645 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
646 | if (ret) |
647 | /* PFPW engine is busy, use cpu copy method */ | |
648 | goto out_copy; | |
649 | ||
650 | info->buf_len = len; | |
5c468455 AM |
651 | |
652 | enable_irq(info->gpmc_irq_count); | |
653 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
654 | |
655 | /* waiting for read to complete */ | |
656 | wait_for_completion(&info->comp); | |
657 | ||
658 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 659 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
660 | return; |
661 | ||
662 | out_copy: | |
663 | if (info->nand.options & NAND_BUSWIDTH_16) | |
664 | omap_read_buf16(mtd, buf, len); | |
665 | else | |
666 | omap_read_buf8(mtd, buf, len); | |
667 | } | |
668 | ||
669 | /* | |
670 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
671 | * @mtd: MTD device structure | |
672 | * @buf: data buffer | |
673 | * @len: number of bytes to write | |
674 | */ | |
675 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
676 | const u_char *buf, int len) | |
677 | { | |
4578ea9a | 678 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4e070376 SG |
679 | int ret = 0; |
680 | unsigned long tim, limit; | |
65b97cf6 | 681 | u32 val; |
4e070376 SG |
682 | |
683 | if (len <= mtd->oobsize) { | |
684 | omap_write_buf_pref(mtd, buf, len); | |
685 | return; | |
686 | } | |
687 | ||
688 | info->iomode = OMAP_NAND_IO_WRITE; | |
689 | info->buf = (u_char *) buf; | |
690 | init_completion(&info->comp); | |
691 | ||
317379a9 | 692 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
693 | ret = omap_prefetch_enable(info->gpmc_cs, |
694 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
695 | if (ret) |
696 | /* PFPW engine is busy, use cpu copy method */ | |
697 | goto out_copy; | |
698 | ||
699 | info->buf_len = len; | |
5c468455 AM |
700 | |
701 | enable_irq(info->gpmc_irq_count); | |
702 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
703 | |
704 | /* waiting for write to complete */ | |
705 | wait_for_completion(&info->comp); | |
5c468455 | 706 | |
4e070376 SG |
707 | /* wait for data to flushed-out before reset the prefetch */ |
708 | tim = 0; | |
709 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
710 | do { |
711 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 712 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 713 | cpu_relax(); |
65b97cf6 | 714 | } while (val && (tim++ < limit)); |
4e070376 SG |
715 | |
716 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 717 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
718 | return; |
719 | ||
720 | out_copy: | |
721 | if (info->nand.options & NAND_BUSWIDTH_16) | |
722 | omap_write_buf16(mtd, buf, len); | |
723 | else | |
724 | omap_write_buf8(mtd, buf, len); | |
725 | } | |
726 | ||
67ce04bf VS |
727 | /** |
728 | * gen_true_ecc - This function will generate true ECC value | |
729 | * @ecc_buf: buffer to store ecc code | |
730 | * | |
731 | * This generated true ECC value can be used when correcting | |
732 | * data read from NAND flash memory core | |
733 | */ | |
734 | static void gen_true_ecc(u8 *ecc_buf) | |
735 | { | |
736 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
737 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
738 | ||
739 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
740 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
741 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
742 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
743 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
744 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
745 | } | |
746 | ||
747 | /** | |
748 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
749 | * @ecc_data1: ecc code from nand spare area | |
750 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
751 | * @page_data: page data | |
752 | * | |
753 | * This function compares two ECC's and indicates if there is an error. | |
754 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
755 | * If there is no error, %0 is returned. If there is an error but it |
756 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
757 | */ |
758 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
759 | u8 *ecc_data2, /* read from register */ | |
760 | u8 *page_data) | |
761 | { | |
762 | uint i; | |
763 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
764 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
765 | u8 ecc_bit[24]; | |
766 | u8 ecc_sum = 0; | |
767 | u8 find_bit = 0; | |
768 | uint find_byte = 0; | |
769 | int isEccFF; | |
770 | ||
771 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
772 | ||
773 | gen_true_ecc(ecc_data1); | |
774 | gen_true_ecc(ecc_data2); | |
775 | ||
776 | for (i = 0; i <= 2; i++) { | |
777 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
778 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
779 | } | |
780 | ||
781 | for (i = 0; i < 8; i++) { | |
782 | tmp0_bit[i] = *ecc_data1 % 2; | |
783 | *ecc_data1 = *ecc_data1 / 2; | |
784 | } | |
785 | ||
786 | for (i = 0; i < 8; i++) { | |
787 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
788 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
789 | } | |
790 | ||
791 | for (i = 0; i < 8; i++) { | |
792 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
793 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
794 | } | |
795 | ||
796 | for (i = 0; i < 8; i++) { | |
797 | comp0_bit[i] = *ecc_data2 % 2; | |
798 | *ecc_data2 = *ecc_data2 / 2; | |
799 | } | |
800 | ||
801 | for (i = 0; i < 8; i++) { | |
802 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
803 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
804 | } | |
805 | ||
806 | for (i = 0; i < 8; i++) { | |
807 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
808 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
809 | } | |
810 | ||
811 | for (i = 0; i < 6; i++) | |
812 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
813 | ||
814 | for (i = 0; i < 8; i++) | |
815 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
816 | ||
817 | for (i = 0; i < 8; i++) | |
818 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
819 | ||
820 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
821 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
822 | ||
823 | for (i = 0; i < 24; i++) | |
824 | ecc_sum += ecc_bit[i]; | |
825 | ||
826 | switch (ecc_sum) { | |
827 | case 0: | |
828 | /* Not reached because this function is not called if | |
829 | * ECC values are equal | |
830 | */ | |
831 | return 0; | |
832 | ||
833 | case 1: | |
834 | /* Uncorrectable error */ | |
289c0522 | 835 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
6e941192 | 836 | return -EBADMSG; |
67ce04bf VS |
837 | |
838 | case 11: | |
839 | /* UN-Correctable error */ | |
289c0522 | 840 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
6e941192 | 841 | return -EBADMSG; |
67ce04bf VS |
842 | |
843 | case 12: | |
844 | /* Correctable error */ | |
845 | find_byte = (ecc_bit[23] << 8) + | |
846 | (ecc_bit[21] << 7) + | |
847 | (ecc_bit[19] << 6) + | |
848 | (ecc_bit[17] << 5) + | |
849 | (ecc_bit[15] << 4) + | |
850 | (ecc_bit[13] << 3) + | |
851 | (ecc_bit[11] << 2) + | |
852 | (ecc_bit[9] << 1) + | |
853 | ecc_bit[7]; | |
854 | ||
855 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
856 | ||
0a32a102 BN |
857 | pr_debug("Correcting single bit ECC error at offset: " |
858 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
859 | |
860 | page_data[find_byte] ^= (1 << find_bit); | |
861 | ||
74f1b724 | 862 | return 1; |
67ce04bf VS |
863 | default: |
864 | if (isEccFF) { | |
865 | if (ecc_data2[0] == 0 && | |
866 | ecc_data2[1] == 0 && | |
867 | ecc_data2[2] == 0) | |
868 | return 0; | |
869 | } | |
289c0522 | 870 | pr_debug("UNCORRECTED_ERROR default\n"); |
6e941192 | 871 | return -EBADMSG; |
67ce04bf VS |
872 | } |
873 | } | |
874 | ||
875 | /** | |
876 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
877 | * @mtd: MTD device structure | |
878 | * @dat: page data | |
879 | * @read_ecc: ecc read from nand flash | |
880 | * @calc_ecc: ecc read from HW ECC registers | |
881 | * | |
882 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
883 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
884 | * detection and correction. If there are no errors, %0 is returned. If | |
885 | * there were errors and all of the errors were corrected, the number of | |
886 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
887 | * returned. | |
67ce04bf VS |
888 | */ |
889 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
890 | u_char *read_ecc, u_char *calc_ecc) | |
891 | { | |
4578ea9a | 892 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 893 | int blockCnt = 0, i = 0, ret = 0; |
74f1b724 | 894 | int stat = 0; |
67ce04bf VS |
895 | |
896 | /* Ex NAND_ECC_HW12_2048 */ | |
897 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
898 | (info->nand.ecc.size == 2048)) | |
899 | blockCnt = 4; | |
900 | else | |
901 | blockCnt = 1; | |
902 | ||
903 | for (i = 0; i < blockCnt; i++) { | |
904 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
905 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
906 | if (ret < 0) | |
907 | return ret; | |
74f1b724 JO |
908 | /* keep track of the number of corrected errors */ |
909 | stat += ret; | |
67ce04bf VS |
910 | } |
911 | read_ecc += 3; | |
912 | calc_ecc += 3; | |
913 | dat += 512; | |
914 | } | |
74f1b724 | 915 | return stat; |
67ce04bf VS |
916 | } |
917 | ||
918 | /** | |
919 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
920 | * @mtd: MTD device structure | |
921 | * @dat: The pointer to data on which ecc is computed | |
922 | * @ecc_code: The ecc_code buffer | |
923 | * | |
924 | * Using noninverted ECC can be considered ugly since writing a blank | |
925 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
926 | * nobody is trying to write data on the seemingly unused page. Reading | |
927 | * an erased page will produce an ECC mismatch between generated and read | |
928 | * ECC bytes that has to be dealt with separately. | |
929 | */ | |
930 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
931 | u_char *ecc_code) | |
932 | { | |
4578ea9a | 933 | struct omap_nand_info *info = mtd_to_omap(mtd); |
65b97cf6 AM |
934 | u32 val; |
935 | ||
936 | val = readl(info->reg.gpmc_ecc_config); | |
40ddbf50 | 937 | if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) |
65b97cf6 AM |
938 | return -EINVAL; |
939 | ||
940 | /* read ecc result */ | |
941 | val = readl(info->reg.gpmc_ecc1_result); | |
942 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
943 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
944 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
945 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
946 | ||
947 | return 0; | |
67ce04bf VS |
948 | } |
949 | ||
950 | /** | |
951 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
952 | * @mtd: MTD device structure | |
953 | * @mode: Read/Write mode | |
954 | */ | |
955 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
956 | { | |
4578ea9a | 957 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4bd4ebcc | 958 | struct nand_chip *chip = mtd_to_nand(mtd); |
67ce04bf | 959 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
65b97cf6 AM |
960 | u32 val; |
961 | ||
962 | /* clear ecc and enable bits */ | |
963 | val = ECCCLEAR | ECC1; | |
964 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 965 | |
65b97cf6 AM |
966 | /* program ecc and result sizes */ |
967 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
968 | ECC1RESULTSIZE); | |
969 | writel(val, info->reg.gpmc_ecc_size_config); | |
970 | ||
971 | switch (mode) { | |
972 | case NAND_ECC_READ: | |
973 | case NAND_ECC_WRITE: | |
974 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
975 | break; | |
976 | case NAND_ECC_READSYN: | |
977 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
978 | break; | |
979 | default: | |
980 | dev_info(&info->pdev->dev, | |
981 | "error: unrecognized Mode[%d]!\n", mode); | |
982 | break; | |
983 | } | |
67ce04bf | 984 | |
65b97cf6 AM |
985 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
986 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
987 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 988 | } |
2c01946c | 989 | |
67ce04bf VS |
990 | /** |
991 | * omap_wait - wait until the command is done | |
992 | * @mtd: MTD device structure | |
993 | * @chip: NAND Chip structure | |
994 | * | |
995 | * Wait function is called during Program and erase operations and | |
996 | * the way it is called from MTD layer, we should wait till the NAND | |
997 | * chip is ready after the programming/erase operation has completed. | |
998 | * | |
999 | * Erase can take up to 400ms and program up to 20ms according to | |
1000 | * general NAND and SmartMedia specs | |
1001 | */ | |
1002 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
1003 | { | |
4bd4ebcc | 1004 | struct nand_chip *this = mtd_to_nand(mtd); |
4578ea9a | 1005 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 1006 | unsigned long timeo = jiffies; |
a9c465f0 | 1007 | int status, state = this->state; |
67ce04bf VS |
1008 | |
1009 | if (state == FL_ERASING) | |
4ff6772b | 1010 | timeo += msecs_to_jiffies(400); |
67ce04bf | 1011 | else |
4ff6772b | 1012 | timeo += msecs_to_jiffies(20); |
67ce04bf | 1013 | |
65b97cf6 | 1014 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1015 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1016 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1017 | if (status & NAND_STATUS_READY) |
67ce04bf | 1018 | break; |
c276aca4 | 1019 | cond_resched(); |
67ce04bf | 1020 | } |
a9c465f0 | 1021 | |
4ea1e4ba | 1022 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1023 | return status; |
1024 | } | |
1025 | ||
1026 | /** | |
10f22ee3 | 1027 | * omap_dev_ready - checks the NAND Ready GPIO line |
67ce04bf | 1028 | * @mtd: MTD device structure |
10f22ee3 RQ |
1029 | * |
1030 | * Returns true if ready and false if busy. | |
67ce04bf VS |
1031 | */ |
1032 | static int omap_dev_ready(struct mtd_info *mtd) | |
1033 | { | |
4578ea9a | 1034 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 1035 | |
10f22ee3 | 1036 | return gpiod_get_value(info->ready_gpiod); |
67ce04bf VS |
1037 | } |
1038 | ||
0e618ef0 | 1039 | /** |
7c977c3e | 1040 | * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation |
0e618ef0 ID |
1041 | * @mtd: MTD device structure |
1042 | * @mode: Read/Write mode | |
62116e51 | 1043 | * |
0760e818 NMG |
1044 | * When using BCH with SW correction (i.e. no ELM), sector size is set |
1045 | * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode | |
1046 | * for both reading and writing with: | |
62116e51 PA |
1047 | * eccsize0 = 0 (no additional protected byte in spare area) |
1048 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
0e618ef0 | 1049 | */ |
7c977c3e | 1050 | static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) |
0e618ef0 | 1051 | { |
16e69322 | 1052 | unsigned int bch_type; |
2ef9f3dd | 1053 | unsigned int dev_width, nsectors; |
4578ea9a | 1054 | struct omap_nand_info *info = mtd_to_omap(mtd); |
c5957a32 | 1055 | enum omap_ecc ecc_opt = info->ecc_opt; |
4bd4ebcc | 1056 | struct nand_chip *chip = mtd_to_nand(mtd); |
62116e51 PA |
1057 | u32 val, wr_mode; |
1058 | unsigned int ecc_size1, ecc_size0; | |
1059 | ||
c5957a32 PG |
1060 | /* GPMC configurations for calculating ECC */ |
1061 | switch (ecc_opt) { | |
1062 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1063 | bch_type = 0; |
1064 | nsectors = 1; | |
0760e818 NMG |
1065 | wr_mode = BCH_WRAPMODE_6; |
1066 | ecc_size0 = BCH_ECC_SIZE0; | |
1067 | ecc_size1 = BCH_ECC_SIZE1; | |
c5957a32 PG |
1068 | break; |
1069 | case OMAP_ECC_BCH4_CODE_HW: | |
16e69322 PG |
1070 | bch_type = 0; |
1071 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1072 | if (mode == NAND_ECC_READ) { |
1073 | wr_mode = BCH_WRAPMODE_1; | |
1074 | ecc_size0 = BCH4R_ECC_SIZE0; | |
1075 | ecc_size1 = BCH4R_ECC_SIZE1; | |
1076 | } else { | |
1077 | wr_mode = BCH_WRAPMODE_6; | |
1078 | ecc_size0 = BCH_ECC_SIZE0; | |
1079 | ecc_size1 = BCH_ECC_SIZE1; | |
1080 | } | |
1081 | break; | |
1082 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1083 | bch_type = 1; |
1084 | nsectors = 1; | |
0760e818 NMG |
1085 | wr_mode = BCH_WRAPMODE_6; |
1086 | ecc_size0 = BCH_ECC_SIZE0; | |
1087 | ecc_size1 = BCH_ECC_SIZE1; | |
c5957a32 PG |
1088 | break; |
1089 | case OMAP_ECC_BCH8_CODE_HW: | |
16e69322 PG |
1090 | bch_type = 1; |
1091 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1092 | if (mode == NAND_ECC_READ) { |
1093 | wr_mode = BCH_WRAPMODE_1; | |
1094 | ecc_size0 = BCH8R_ECC_SIZE0; | |
1095 | ecc_size1 = BCH8R_ECC_SIZE1; | |
1096 | } else { | |
1097 | wr_mode = BCH_WRAPMODE_6; | |
1098 | ecc_size0 = BCH_ECC_SIZE0; | |
1099 | ecc_size1 = BCH_ECC_SIZE1; | |
1100 | } | |
1101 | break; | |
9748fff9 | 1102 | case OMAP_ECC_BCH16_CODE_HW: |
1103 | bch_type = 0x2; | |
1104 | nsectors = chip->ecc.steps; | |
1105 | if (mode == NAND_ECC_READ) { | |
1106 | wr_mode = 0x01; | |
1107 | ecc_size0 = 52; /* ECC bits in nibbles per sector */ | |
1108 | ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ | |
1109 | } else { | |
1110 | wr_mode = 0x01; | |
1111 | ecc_size0 = 0; /* extra bits in nibbles per sector */ | |
1112 | ecc_size1 = 52; /* OOB bits in nibbles per sector */ | |
1113 | } | |
1114 | break; | |
c5957a32 PG |
1115 | default: |
1116 | return; | |
1117 | } | |
2ef9f3dd AM |
1118 | |
1119 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1120 | ||
62116e51 PA |
1121 | /* Configure ecc size for BCH */ |
1122 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
2ef9f3dd AM |
1123 | writel(val, info->reg.gpmc_ecc_size_config); |
1124 | ||
62116e51 PA |
1125 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
1126 | ||
2ef9f3dd AM |
1127 | /* BCH configuration */ |
1128 | val = ((1 << 16) | /* enable BCH */ | |
16e69322 | 1129 | (bch_type << 12) | /* BCH4/BCH8/BCH16 */ |
62116e51 | 1130 | (wr_mode << 8) | /* wrap mode */ |
2ef9f3dd AM |
1131 | (dev_width << 7) | /* bus width */ |
1132 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1133 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1134 | (0x1)); /* enable ECC */ | |
1135 | ||
1136 | writel(val, info->reg.gpmc_ecc_config); | |
1137 | ||
62116e51 | 1138 | /* Clear ecc and enable bits */ |
2ef9f3dd | 1139 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
0e618ef0 | 1140 | } |
7c977c3e | 1141 | |
2c9f2365 | 1142 | static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f}; |
7bcd1dca PG |
1143 | static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, |
1144 | 0x97, 0x79, 0xe5, 0x24, 0xb5}; | |
0e618ef0 | 1145 | |
62116e51 | 1146 | /** |
a4c7ca00 | 1147 | * omap_calculate_ecc_bch - Generate bytes of ECC bytes |
62116e51 PA |
1148 | * @mtd: MTD device structure |
1149 | * @dat: The pointer to data on which ecc is computed | |
1150 | * @ecc_code: The ecc_code buffer | |
1151 | * | |
1152 | * Support calculating of BCH4/8 ecc vectors for the page | |
1153 | */ | |
a4c7ca00 | 1154 | static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, |
f5dc06fb | 1155 | const u_char *dat, u_char *ecc_calc) |
62116e51 | 1156 | { |
4578ea9a | 1157 | struct omap_nand_info *info = mtd_to_omap(mtd); |
f5dc06fb PG |
1158 | int eccbytes = info->nand.ecc.bytes; |
1159 | struct gpmc_nand_regs *gpmc_regs = &info->reg; | |
1160 | u8 *ecc_code; | |
62116e51 | 1161 | unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4; |
9748fff9 | 1162 | u32 val; |
2913aae5 | 1163 | int i, j; |
62116e51 PA |
1164 | |
1165 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
62116e51 | 1166 | for (i = 0; i < nsectors; i++) { |
f5dc06fb PG |
1167 | ecc_code = ecc_calc; |
1168 | switch (info->ecc_opt) { | |
7bcd1dca | 1169 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1170 | case OMAP_ECC_BCH8_CODE_HW: |
1171 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1172 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1173 | bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1174 | bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); | |
62116e51 PA |
1175 | *ecc_code++ = (bch_val4 & 0xFF); |
1176 | *ecc_code++ = ((bch_val3 >> 24) & 0xFF); | |
1177 | *ecc_code++ = ((bch_val3 >> 16) & 0xFF); | |
1178 | *ecc_code++ = ((bch_val3 >> 8) & 0xFF); | |
1179 | *ecc_code++ = (bch_val3 & 0xFF); | |
1180 | *ecc_code++ = ((bch_val2 >> 24) & 0xFF); | |
1181 | *ecc_code++ = ((bch_val2 >> 16) & 0xFF); | |
1182 | *ecc_code++ = ((bch_val2 >> 8) & 0xFF); | |
1183 | *ecc_code++ = (bch_val2 & 0xFF); | |
1184 | *ecc_code++ = ((bch_val1 >> 24) & 0xFF); | |
1185 | *ecc_code++ = ((bch_val1 >> 16) & 0xFF); | |
1186 | *ecc_code++ = ((bch_val1 >> 8) & 0xFF); | |
1187 | *ecc_code++ = (bch_val1 & 0xFF); | |
f5dc06fb | 1188 | break; |
2c9f2365 | 1189 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1190 | case OMAP_ECC_BCH4_CODE_HW: |
1191 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1192 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
62116e51 PA |
1193 | *ecc_code++ = ((bch_val2 >> 12) & 0xFF); |
1194 | *ecc_code++ = ((bch_val2 >> 4) & 0xFF); | |
1195 | *ecc_code++ = ((bch_val2 & 0xF) << 4) | | |
1196 | ((bch_val1 >> 28) & 0xF); | |
1197 | *ecc_code++ = ((bch_val1 >> 20) & 0xFF); | |
1198 | *ecc_code++ = ((bch_val1 >> 12) & 0xFF); | |
1199 | *ecc_code++ = ((bch_val1 >> 4) & 0xFF); | |
1200 | *ecc_code++ = ((bch_val1 & 0xF) << 4); | |
f5dc06fb | 1201 | break; |
9748fff9 | 1202 | case OMAP_ECC_BCH16_CODE_HW: |
1203 | val = readl(gpmc_regs->gpmc_bch_result6[i]); | |
1204 | ecc_code[0] = ((val >> 8) & 0xFF); | |
1205 | ecc_code[1] = ((val >> 0) & 0xFF); | |
1206 | val = readl(gpmc_regs->gpmc_bch_result5[i]); | |
1207 | ecc_code[2] = ((val >> 24) & 0xFF); | |
1208 | ecc_code[3] = ((val >> 16) & 0xFF); | |
1209 | ecc_code[4] = ((val >> 8) & 0xFF); | |
1210 | ecc_code[5] = ((val >> 0) & 0xFF); | |
1211 | val = readl(gpmc_regs->gpmc_bch_result4[i]); | |
1212 | ecc_code[6] = ((val >> 24) & 0xFF); | |
1213 | ecc_code[7] = ((val >> 16) & 0xFF); | |
1214 | ecc_code[8] = ((val >> 8) & 0xFF); | |
1215 | ecc_code[9] = ((val >> 0) & 0xFF); | |
1216 | val = readl(gpmc_regs->gpmc_bch_result3[i]); | |
1217 | ecc_code[10] = ((val >> 24) & 0xFF); | |
1218 | ecc_code[11] = ((val >> 16) & 0xFF); | |
1219 | ecc_code[12] = ((val >> 8) & 0xFF); | |
1220 | ecc_code[13] = ((val >> 0) & 0xFF); | |
1221 | val = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1222 | ecc_code[14] = ((val >> 24) & 0xFF); | |
1223 | ecc_code[15] = ((val >> 16) & 0xFF); | |
1224 | ecc_code[16] = ((val >> 8) & 0xFF); | |
1225 | ecc_code[17] = ((val >> 0) & 0xFF); | |
1226 | val = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1227 | ecc_code[18] = ((val >> 24) & 0xFF); | |
1228 | ecc_code[19] = ((val >> 16) & 0xFF); | |
1229 | ecc_code[20] = ((val >> 8) & 0xFF); | |
1230 | ecc_code[21] = ((val >> 0) & 0xFF); | |
1231 | val = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1232 | ecc_code[22] = ((val >> 24) & 0xFF); | |
1233 | ecc_code[23] = ((val >> 16) & 0xFF); | |
1234 | ecc_code[24] = ((val >> 8) & 0xFF); | |
1235 | ecc_code[25] = ((val >> 0) & 0xFF); | |
1236 | break; | |
f5dc06fb PG |
1237 | default: |
1238 | return -EINVAL; | |
62116e51 | 1239 | } |
f5dc06fb PG |
1240 | |
1241 | /* ECC scheme specific syndrome customizations */ | |
1242 | switch (info->ecc_opt) { | |
2c9f2365 PG |
1243 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
1244 | /* Add constant polynomial to remainder, so that | |
1245 | * ECC of blank pages results in 0x0 on reading back */ | |
2913aae5 TJ |
1246 | for (j = 0; j < eccbytes; j++) |
1247 | ecc_calc[j] ^= bch4_polynomial[j]; | |
2c9f2365 | 1248 | break; |
f5dc06fb PG |
1249 | case OMAP_ECC_BCH4_CODE_HW: |
1250 | /* Set 8th ECC byte as 0x0 for ROM compatibility */ | |
1251 | ecc_calc[eccbytes - 1] = 0x0; | |
1252 | break; | |
7bcd1dca PG |
1253 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
1254 | /* Add constant polynomial to remainder, so that | |
1255 | * ECC of blank pages results in 0x0 on reading back */ | |
2913aae5 TJ |
1256 | for (j = 0; j < eccbytes; j++) |
1257 | ecc_calc[j] ^= bch8_polynomial[j]; | |
7bcd1dca | 1258 | break; |
f5dc06fb PG |
1259 | case OMAP_ECC_BCH8_CODE_HW: |
1260 | /* Set 14th ECC byte as 0x0 for ROM compatibility */ | |
1261 | ecc_calc[eccbytes - 1] = 0x0; | |
1262 | break; | |
9748fff9 | 1263 | case OMAP_ECC_BCH16_CODE_HW: |
1264 | break; | |
f5dc06fb PG |
1265 | default: |
1266 | return -EINVAL; | |
1267 | } | |
1268 | ||
1269 | ecc_calc += eccbytes; | |
62116e51 PA |
1270 | } |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | /** | |
1276 | * erased_sector_bitflips - count bit flips | |
1277 | * @data: data sector buffer | |
1278 | * @oob: oob buffer | |
1279 | * @info: omap_nand_info | |
1280 | * | |
1281 | * Check the bit flips in erased page falls below correctable level. | |
1282 | * If falls below, report the page as erased with correctable bit | |
1283 | * flip, else report as uncorrectable page. | |
1284 | */ | |
1285 | static int erased_sector_bitflips(u_char *data, u_char *oob, | |
1286 | struct omap_nand_info *info) | |
1287 | { | |
1288 | int flip_bits = 0, i; | |
1289 | ||
1290 | for (i = 0; i < info->nand.ecc.size; i++) { | |
1291 | flip_bits += hweight8(~data[i]); | |
1292 | if (flip_bits > info->nand.ecc.strength) | |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | for (i = 0; i < info->nand.ecc.bytes - 1; i++) { | |
1297 | flip_bits += hweight8(~oob[i]); | |
1298 | if (flip_bits > info->nand.ecc.strength) | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | /* | |
1303 | * Bit flips falls in correctable level. | |
1304 | * Fill data area with 0xFF | |
1305 | */ | |
1306 | if (flip_bits) { | |
1307 | memset(data, 0xFF, info->nand.ecc.size); | |
1308 | memset(oob, 0xFF, info->nand.ecc.bytes); | |
1309 | } | |
1310 | ||
1311 | return flip_bits; | |
1312 | } | |
1313 | ||
1314 | /** | |
1315 | * omap_elm_correct_data - corrects page data area in case error reported | |
1316 | * @mtd: MTD device structure | |
1317 | * @data: page data | |
1318 | * @read_ecc: ecc read from nand flash | |
1319 | * @calc_ecc: ecc read from HW ECC registers | |
1320 | * | |
1321 | * Calculated ecc vector reported as zero in case of non-error pages. | |
78f43c53 PG |
1322 | * In case of non-zero ecc vector, first filter out erased-pages, and |
1323 | * then process data via ELM to detect bit-flips. | |
62116e51 PA |
1324 | */ |
1325 | static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |
1326 | u_char *read_ecc, u_char *calc_ecc) | |
1327 | { | |
4578ea9a | 1328 | struct omap_nand_info *info = mtd_to_omap(mtd); |
de0a4d69 | 1329 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; |
62116e51 PA |
1330 | int eccsteps = info->nand.ecc.steps; |
1331 | int i , j, stat = 0; | |
de0a4d69 | 1332 | int eccflag, actual_eccbytes; |
62116e51 PA |
1333 | struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; |
1334 | u_char *ecc_vec = calc_ecc; | |
1335 | u_char *spare_ecc = read_ecc; | |
1336 | u_char *erased_ecc_vec; | |
78f43c53 PG |
1337 | u_char *buf; |
1338 | int bitflip_count; | |
62116e51 | 1339 | bool is_error_reported = false; |
b08e1f63 | 1340 | u32 bit_pos, byte_pos, error_max, pos; |
13fbe064 | 1341 | int err; |
62116e51 | 1342 | |
de0a4d69 PG |
1343 | switch (info->ecc_opt) { |
1344 | case OMAP_ECC_BCH4_CODE_HW: | |
1345 | /* omit 7th ECC byte reserved for ROM code compatibility */ | |
1346 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1347 | erased_ecc_vec = bch4_vector; |
de0a4d69 PG |
1348 | break; |
1349 | case OMAP_ECC_BCH8_CODE_HW: | |
1350 | /* omit 14th ECC byte reserved for ROM code compatibility */ | |
1351 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1352 | erased_ecc_vec = bch8_vector; |
de0a4d69 | 1353 | break; |
9748fff9 | 1354 | case OMAP_ECC_BCH16_CODE_HW: |
1355 | actual_eccbytes = ecc->bytes; | |
1356 | erased_ecc_vec = bch16_vector; | |
1357 | break; | |
de0a4d69 | 1358 | default: |
d2f08c75 | 1359 | dev_err(&info->pdev->dev, "invalid driver configuration\n"); |
de0a4d69 PG |
1360 | return -EINVAL; |
1361 | } | |
1362 | ||
62116e51 PA |
1363 | /* Initialize elm error vector to zero */ |
1364 | memset(err_vec, 0, sizeof(err_vec)); | |
1365 | ||
62116e51 PA |
1366 | for (i = 0; i < eccsteps ; i++) { |
1367 | eccflag = 0; /* initialize eccflag */ | |
1368 | ||
1369 | /* | |
1370 | * Check any error reported, | |
1371 | * In case of error, non zero ecc reported. | |
1372 | */ | |
de0a4d69 | 1373 | for (j = 0; j < actual_eccbytes; j++) { |
62116e51 PA |
1374 | if (calc_ecc[j] != 0) { |
1375 | eccflag = 1; /* non zero ecc, error present */ | |
1376 | break; | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | if (eccflag == 1) { | |
78f43c53 PG |
1381 | if (memcmp(calc_ecc, erased_ecc_vec, |
1382 | actual_eccbytes) == 0) { | |
62116e51 | 1383 | /* |
78f43c53 PG |
1384 | * calc_ecc[] matches pattern for ECC(all 0xff) |
1385 | * so this is definitely an erased-page | |
62116e51 | 1386 | */ |
62116e51 | 1387 | } else { |
78f43c53 PG |
1388 | buf = &data[info->nand.ecc.size * i]; |
1389 | /* | |
1390 | * count number of 0-bits in read_buf. | |
1391 | * This check can be removed once a similar | |
1392 | * check is introduced in generic NAND driver | |
1393 | */ | |
1394 | bitflip_count = erased_sector_bitflips( | |
1395 | buf, read_ecc, info); | |
1396 | if (bitflip_count) { | |
1397 | /* | |
1398 | * number of 0-bits within ECC limits | |
1399 | * So this may be an erased-page | |
1400 | */ | |
1401 | stat += bitflip_count; | |
1402 | } else { | |
1403 | /* | |
1404 | * Too many 0-bits. It may be a | |
1405 | * - programmed-page, OR | |
1406 | * - erased-page with many bit-flips | |
1407 | * So this page requires check by ELM | |
1408 | */ | |
1409 | err_vec[i].error_reported = true; | |
1410 | is_error_reported = true; | |
62116e51 PA |
1411 | } |
1412 | } | |
1413 | } | |
1414 | ||
1415 | /* Update the ecc vector */ | |
de0a4d69 PG |
1416 | calc_ecc += ecc->bytes; |
1417 | read_ecc += ecc->bytes; | |
62116e51 PA |
1418 | } |
1419 | ||
1420 | /* Check if any error reported */ | |
1421 | if (!is_error_reported) | |
f306e8c3 | 1422 | return stat; |
62116e51 PA |
1423 | |
1424 | /* Decode BCH error using ELM module */ | |
1425 | elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); | |
1426 | ||
13fbe064 | 1427 | err = 0; |
62116e51 | 1428 | for (i = 0; i < eccsteps; i++) { |
13fbe064 | 1429 | if (err_vec[i].error_uncorrectable) { |
d2f08c75 EG |
1430 | dev_err(&info->pdev->dev, |
1431 | "uncorrectable bit-flips found\n"); | |
13fbe064 PG |
1432 | err = -EBADMSG; |
1433 | } else if (err_vec[i].error_reported) { | |
62116e51 | 1434 | for (j = 0; j < err_vec[i].error_count; j++) { |
b08e1f63 PG |
1435 | switch (info->ecc_opt) { |
1436 | case OMAP_ECC_BCH4_CODE_HW: | |
1437 | /* Add 4 bits to take care of padding */ | |
62116e51 PA |
1438 | pos = err_vec[i].error_loc[j] + |
1439 | BCH4_BIT_PAD; | |
b08e1f63 PG |
1440 | break; |
1441 | case OMAP_ECC_BCH8_CODE_HW: | |
9748fff9 | 1442 | case OMAP_ECC_BCH16_CODE_HW: |
b08e1f63 PG |
1443 | pos = err_vec[i].error_loc[j]; |
1444 | break; | |
1445 | default: | |
1446 | return -EINVAL; | |
1447 | } | |
1448 | error_max = (ecc->size + actual_eccbytes) * 8; | |
62116e51 PA |
1449 | /* Calculate bit position of error */ |
1450 | bit_pos = pos % 8; | |
1451 | ||
1452 | /* Calculate byte position of error */ | |
1453 | byte_pos = (error_max - pos - 1) / 8; | |
1454 | ||
1455 | if (pos < error_max) { | |
13fbe064 PG |
1456 | if (byte_pos < 512) { |
1457 | pr_debug("bitflip@dat[%d]=%x\n", | |
1458 | byte_pos, data[byte_pos]); | |
62116e51 | 1459 | data[byte_pos] ^= 1 << bit_pos; |
13fbe064 PG |
1460 | } else { |
1461 | pr_debug("bitflip@oob[%d]=%x\n", | |
1462 | (byte_pos - 512), | |
1463 | spare_ecc[byte_pos - 512]); | |
62116e51 PA |
1464 | spare_ecc[byte_pos - 512] ^= |
1465 | 1 << bit_pos; | |
13fbe064 PG |
1466 | } |
1467 | } else { | |
d2f08c75 EG |
1468 | dev_err(&info->pdev->dev, |
1469 | "invalid bit-flip @ %d:%d\n", | |
1470 | byte_pos, bit_pos); | |
13fbe064 | 1471 | err = -EBADMSG; |
62116e51 | 1472 | } |
62116e51 PA |
1473 | } |
1474 | } | |
1475 | ||
1476 | /* Update number of correctable errors */ | |
1477 | stat += err_vec[i].error_count; | |
1478 | ||
1479 | /* Update page data with sector size */ | |
b08e1f63 | 1480 | data += ecc->size; |
de0a4d69 | 1481 | spare_ecc += ecc->bytes; |
62116e51 PA |
1482 | } |
1483 | ||
13fbe064 | 1484 | return (err) ? err : stat; |
62116e51 PA |
1485 | } |
1486 | ||
62116e51 PA |
1487 | /** |
1488 | * omap_write_page_bch - BCH ecc based write page function for entire page | |
1489 | * @mtd: mtd info structure | |
1490 | * @chip: nand chip info structure | |
1491 | * @buf: data buffer | |
1492 | * @oob_required: must write chip->oob_poi to OOB | |
45aaeff9 | 1493 | * @page: page |
62116e51 PA |
1494 | * |
1495 | * Custom write page method evolved to support multi sector writing in one shot | |
1496 | */ | |
1497 | static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
45aaeff9 | 1498 | const uint8_t *buf, int oob_required, int page) |
62116e51 | 1499 | { |
8cfc1e8b | 1500 | int ret; |
62116e51 | 1501 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
62116e51 PA |
1502 | |
1503 | /* Enable GPMC ecc engine */ | |
1504 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1505 | ||
1506 | /* Write data */ | |
1507 | chip->write_buf(mtd, buf, mtd->writesize); | |
1508 | ||
1509 | /* Update ecc vector from GPMC result registers */ | |
1510 | chip->ecc.calculate(mtd, buf, &ecc_calc[0]); | |
1511 | ||
8cfc1e8b BB |
1512 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
1513 | chip->ecc.total); | |
1514 | if (ret) | |
1515 | return ret; | |
62116e51 PA |
1516 | |
1517 | /* Write ecc vector to OOB area */ | |
1518 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | /** | |
1523 | * omap_read_page_bch - BCH ecc based page read function for entire page | |
1524 | * @mtd: mtd info structure | |
1525 | * @chip: nand chip info structure | |
1526 | * @buf: buffer to store read data | |
1527 | * @oob_required: caller requires OOB data read to chip->oob_poi | |
1528 | * @page: page number to read | |
1529 | * | |
1530 | * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module | |
1531 | * used for error correction. | |
1532 | * Custom method evolved to support ELM error correction & multi sector | |
1533 | * reading. On reading page data area is read along with OOB data with | |
1534 | * ecc engine enabled. ecc vector updated after read of OOB data. | |
1535 | * For non error pages ecc vector reported as zero. | |
1536 | */ | |
1537 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1538 | uint8_t *buf, int oob_required, int page) | |
1539 | { | |
1540 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1541 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8cfc1e8b | 1542 | int stat, ret; |
62116e51 PA |
1543 | unsigned int max_bitflips = 0; |
1544 | ||
1545 | /* Enable GPMC ecc engine */ | |
1546 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1547 | ||
1548 | /* Read data */ | |
1549 | chip->read_buf(mtd, buf, mtd->writesize); | |
1550 | ||
1551 | /* Read oob bytes */ | |
8cfc1e8b BB |
1552 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1553 | mtd->writesize + BADBLOCK_MARKER_LENGTH, -1); | |
1554 | chip->read_buf(mtd, chip->oob_poi + BADBLOCK_MARKER_LENGTH, | |
1555 | chip->ecc.total); | |
62116e51 PA |
1556 | |
1557 | /* Calculate ecc bytes */ | |
1558 | chip->ecc.calculate(mtd, buf, ecc_calc); | |
1559 | ||
8cfc1e8b BB |
1560 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1561 | chip->ecc.total); | |
1562 | if (ret) | |
1563 | return ret; | |
62116e51 PA |
1564 | |
1565 | stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); | |
1566 | ||
1567 | if (stat < 0) { | |
1568 | mtd->ecc_stats.failed++; | |
1569 | } else { | |
1570 | mtd->ecc_stats.corrected += stat; | |
1571 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1572 | } | |
1573 | ||
1574 | return max_bitflips; | |
1575 | } | |
1576 | ||
0e618ef0 | 1577 | /** |
a919e511 PG |
1578 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1579 | * @omap_nand_info: NAND device structure containing platform data | |
0e618ef0 | 1580 | */ |
93af53b8 EG |
1581 | static bool is_elm_present(struct omap_nand_info *info, |
1582 | struct device_node *elm_node) | |
0e618ef0 | 1583 | { |
a919e511 | 1584 | struct platform_device *pdev; |
93af53b8 | 1585 | |
a919e511 PG |
1586 | /* check whether elm-id is passed via DT */ |
1587 | if (!elm_node) { | |
d2f08c75 | 1588 | dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); |
93af53b8 | 1589 | return false; |
a919e511 PG |
1590 | } |
1591 | pdev = of_find_device_by_node(elm_node); | |
1592 | /* check whether ELM device is registered */ | |
1593 | if (!pdev) { | |
d2f08c75 | 1594 | dev_err(&info->pdev->dev, "ELM device not found\n"); |
93af53b8 | 1595 | return false; |
0e618ef0 | 1596 | } |
a919e511 PG |
1597 | /* ELM module available, now configure it */ |
1598 | info->elm_dev = &pdev->dev; | |
93af53b8 EG |
1599 | return true; |
1600 | } | |
3f4eb14b | 1601 | |
93af53b8 EG |
1602 | static bool omap2_nand_ecc_check(struct omap_nand_info *info, |
1603 | struct omap_nand_platform_data *pdata) | |
1604 | { | |
1605 | bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm; | |
1606 | ||
1607 | switch (info->ecc_opt) { | |
1608 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
1609 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
1610 | ecc_needs_omap_bch = false; | |
1611 | ecc_needs_bch = true; | |
1612 | ecc_needs_elm = false; | |
1613 | break; | |
1614 | case OMAP_ECC_BCH4_CODE_HW: | |
1615 | case OMAP_ECC_BCH8_CODE_HW: | |
1616 | case OMAP_ECC_BCH16_CODE_HW: | |
1617 | ecc_needs_omap_bch = true; | |
1618 | ecc_needs_bch = false; | |
1619 | ecc_needs_elm = true; | |
1620 | break; | |
1621 | default: | |
1622 | ecc_needs_omap_bch = false; | |
1623 | ecc_needs_bch = false; | |
1624 | ecc_needs_elm = false; | |
1625 | break; | |
1626 | } | |
1627 | ||
1628 | if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) { | |
1629 | dev_err(&info->pdev->dev, | |
1630 | "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1631 | return false; | |
1632 | } | |
1633 | if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) { | |
1634 | dev_err(&info->pdev->dev, | |
1635 | "CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1636 | return false; | |
1637 | } | |
01b95fc6 | 1638 | if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) { |
93af53b8 EG |
1639 | dev_err(&info->pdev->dev, "ELM not available\n"); |
1640 | return false; | |
1641 | } | |
1642 | ||
1643 | return true; | |
0e618ef0 ID |
1644 | } |
1645 | ||
c9711ec5 RQ |
1646 | static const char * const nand_xfer_types[] = { |
1647 | [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", | |
1648 | [NAND_OMAP_POLLED] = "polled", | |
1649 | [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", | |
1650 | [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", | |
1651 | }; | |
1652 | ||
1653 | static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info) | |
1654 | { | |
1655 | struct device_node *child = dev->of_node; | |
1656 | int i; | |
1657 | const char *s; | |
1658 | u32 cs; | |
1659 | ||
1660 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1661 | dev_err(dev, "reg not found in DT\n"); | |
1662 | return -EINVAL; | |
1663 | } | |
1664 | ||
1665 | info->gpmc_cs = cs; | |
1666 | ||
1667 | /* detect availability of ELM module. Won't be present pre-OMAP4 */ | |
1668 | info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); | |
1669 | if (!info->elm_of_node) | |
1670 | dev_dbg(dev, "ti,elm-id not in DT\n"); | |
1671 | ||
1672 | /* select ecc-scheme for NAND */ | |
1673 | if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { | |
1674 | dev_err(dev, "ti,nand-ecc-opt not found\n"); | |
1675 | return -EINVAL; | |
1676 | } | |
1677 | ||
1678 | if (!strcmp(s, "sw")) { | |
1679 | info->ecc_opt = OMAP_ECC_HAM1_CODE_SW; | |
1680 | } else if (!strcmp(s, "ham1") || | |
1681 | !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) { | |
1682 | info->ecc_opt = OMAP_ECC_HAM1_CODE_HW; | |
1683 | } else if (!strcmp(s, "bch4")) { | |
1684 | if (info->elm_of_node) | |
1685 | info->ecc_opt = OMAP_ECC_BCH4_CODE_HW; | |
1686 | else | |
1687 | info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; | |
1688 | } else if (!strcmp(s, "bch8")) { | |
1689 | if (info->elm_of_node) | |
1690 | info->ecc_opt = OMAP_ECC_BCH8_CODE_HW; | |
1691 | else | |
1692 | info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; | |
1693 | } else if (!strcmp(s, "bch16")) { | |
1694 | info->ecc_opt = OMAP_ECC_BCH16_CODE_HW; | |
1695 | } else { | |
1696 | dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n"); | |
1697 | return -EINVAL; | |
1698 | } | |
1699 | ||
1700 | /* select data transfer mode */ | |
1701 | if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) { | |
1702 | for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) { | |
1703 | if (!strcasecmp(s, nand_xfer_types[i])) { | |
1704 | info->xfer_type = i; | |
f679888f | 1705 | return 0; |
c9711ec5 RQ |
1706 | } |
1707 | } | |
1708 | ||
1709 | dev_err(dev, "unrecognized value for ti,nand-xfer-type\n"); | |
1710 | return -EINVAL; | |
1711 | } | |
1712 | ||
c9711ec5 RQ |
1713 | return 0; |
1714 | } | |
1715 | ||
e04dbf35 BB |
1716 | static int omap_ooblayout_ecc(struct mtd_info *mtd, int section, |
1717 | struct mtd_oob_region *oobregion) | |
1718 | { | |
1719 | struct omap_nand_info *info = mtd_to_omap(mtd); | |
1720 | struct nand_chip *chip = &info->nand; | |
1721 | int off = BADBLOCK_MARKER_LENGTH; | |
1722 | ||
1723 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && | |
1724 | !(chip->options & NAND_BUSWIDTH_16)) | |
1725 | off = 1; | |
1726 | ||
1727 | if (section) | |
1728 | return -ERANGE; | |
1729 | ||
1730 | oobregion->offset = off; | |
1731 | oobregion->length = chip->ecc.total; | |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | static int omap_ooblayout_free(struct mtd_info *mtd, int section, | |
1737 | struct mtd_oob_region *oobregion) | |
1738 | { | |
1739 | struct omap_nand_info *info = mtd_to_omap(mtd); | |
1740 | struct nand_chip *chip = &info->nand; | |
1741 | int off = BADBLOCK_MARKER_LENGTH; | |
1742 | ||
1743 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && | |
1744 | !(chip->options & NAND_BUSWIDTH_16)) | |
1745 | off = 1; | |
1746 | ||
1747 | if (section) | |
1748 | return -ERANGE; | |
1749 | ||
1750 | off += chip->ecc.total; | |
1751 | if (off >= mtd->oobsize) | |
1752 | return -ERANGE; | |
1753 | ||
1754 | oobregion->offset = off; | |
1755 | oobregion->length = mtd->oobsize - off; | |
1756 | ||
1757 | return 0; | |
1758 | } | |
1759 | ||
1760 | static const struct mtd_ooblayout_ops omap_ooblayout_ops = { | |
1761 | .ecc = omap_ooblayout_ecc, | |
1762 | .free = omap_ooblayout_free, | |
1763 | }; | |
1764 | ||
1765 | static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1766 | struct mtd_oob_region *oobregion) | |
1767 | { | |
1768 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1769 | int off = BADBLOCK_MARKER_LENGTH; | |
1770 | ||
1771 | if (section >= chip->ecc.steps) | |
1772 | return -ERANGE; | |
1773 | ||
1774 | /* | |
1775 | * When SW correction is employed, one OMAP specific marker byte is | |
1776 | * reserved after each ECC step. | |
1777 | */ | |
1778 | oobregion->offset = off + (section * (chip->ecc.bytes + 1)); | |
1779 | oobregion->length = chip->ecc.bytes; | |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
1784 | static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section, | |
1785 | struct mtd_oob_region *oobregion) | |
1786 | { | |
1787 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1788 | int off = BADBLOCK_MARKER_LENGTH; | |
1789 | ||
1790 | if (section) | |
1791 | return -ERANGE; | |
1792 | ||
1793 | /* | |
1794 | * When SW correction is employed, one OMAP specific marker byte is | |
1795 | * reserved after each ECC step. | |
1796 | */ | |
1797 | off += ((chip->ecc.bytes + 1) * chip->ecc.steps); | |
1798 | if (off >= mtd->oobsize) | |
1799 | return -ERANGE; | |
1800 | ||
1801 | oobregion->offset = off; | |
1802 | oobregion->length = mtd->oobsize - off; | |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
1807 | static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = { | |
1808 | .ecc = omap_sw_ooblayout_ecc, | |
1809 | .free = omap_sw_ooblayout_free, | |
1810 | }; | |
1811 | ||
06f25510 | 1812 | static int omap_nand_probe(struct platform_device *pdev) |
67ce04bf VS |
1813 | { |
1814 | struct omap_nand_info *info; | |
c9711ec5 | 1815 | struct omap_nand_platform_data *pdata = NULL; |
633deb58 PG |
1816 | struct mtd_info *mtd; |
1817 | struct nand_chip *nand_chip; | |
67ce04bf | 1818 | int err; |
633deb58 PG |
1819 | dma_cap_mask_t mask; |
1820 | unsigned sig; | |
9c4c2f8b | 1821 | struct resource *res; |
c9711ec5 | 1822 | struct device *dev = &pdev->dev; |
e04dbf35 BB |
1823 | int min_oobbytes = BADBLOCK_MARKER_LENGTH; |
1824 | int oobbytes_per_step; | |
67ce04bf | 1825 | |
70ba6d71 PG |
1826 | info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), |
1827 | GFP_KERNEL); | |
67ce04bf VS |
1828 | if (!info) |
1829 | return -ENOMEM; | |
1830 | ||
c9711ec5 | 1831 | info->pdev = pdev; |
67ce04bf | 1832 | |
c9711ec5 RQ |
1833 | if (dev->of_node) { |
1834 | if (omap_get_dt_info(dev, info)) | |
1835 | return -EINVAL; | |
1836 | } else { | |
1837 | pdata = dev_get_platdata(&pdev->dev); | |
1838 | if (!pdata) { | |
1839 | dev_err(&pdev->dev, "platform data missing\n"); | |
1840 | return -EINVAL; | |
1841 | } | |
1842 | ||
1843 | info->gpmc_cs = pdata->cs; | |
1844 | info->reg = pdata->reg; | |
1845 | info->ecc_opt = pdata->ecc_opt; | |
10f22ee3 RQ |
1846 | if (pdata->dev_ready) |
1847 | dev_info(&pdev->dev, "pdata->dev_ready is deprecated\n"); | |
1848 | ||
c9711ec5 RQ |
1849 | info->xfer_type = pdata->xfer_type; |
1850 | info->devsize = pdata->devsize; | |
1851 | info->elm_of_node = pdata->elm_of_node; | |
1852 | info->flash_bbt = pdata->flash_bbt; | |
1853 | } | |
1854 | ||
1855 | platform_set_drvdata(pdev, info); | |
c509aefd RQ |
1856 | info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs); |
1857 | if (!info->ops) { | |
1858 | dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n"); | |
1859 | return -ENODEV; | |
1860 | } | |
01b95fc6 | 1861 | |
432420c0 BB |
1862 | nand_chip = &info->nand; |
1863 | mtd = nand_to_mtd(nand_chip); | |
853f1c58 | 1864 | mtd->dev.parent = &pdev->dev; |
32d42a85 | 1865 | nand_chip->ecc.priv = NULL; |
c9711ec5 | 1866 | nand_set_flash_node(nand_chip, dev->of_node); |
67ce04bf | 1867 | |
9c4c2f8b | 1868 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
00d09891 JH |
1869 | nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); |
1870 | if (IS_ERR(nand_chip->IO_ADDR_R)) | |
1871 | return PTR_ERR(nand_chip->IO_ADDR_R); | |
67ce04bf | 1872 | |
9c4c2f8b | 1873 | info->phys_base = res->start; |
59e9c5ae | 1874 | |
1dc338e8 | 1875 | nand_chip->controller = &omap_gpmc_controller; |
67ce04bf | 1876 | |
633deb58 PG |
1877 | nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; |
1878 | nand_chip->cmd_ctrl = omap_hwcontrol; | |
67ce04bf | 1879 | |
10f22ee3 RQ |
1880 | info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", |
1881 | GPIOD_IN); | |
1882 | if (IS_ERR(info->ready_gpiod)) { | |
1883 | dev_err(dev, "failed to get ready gpio\n"); | |
1884 | return PTR_ERR(info->ready_gpiod); | |
1885 | } | |
1886 | ||
67ce04bf VS |
1887 | /* |
1888 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1889 | * function and the generic nand_wait function which reads the status |
1890 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1891 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1892 | * device and read status register until you get a failure or success | |
1893 | */ | |
10f22ee3 | 1894 | if (info->ready_gpiod) { |
633deb58 PG |
1895 | nand_chip->dev_ready = omap_dev_ready; |
1896 | nand_chip->chip_delay = 0; | |
67ce04bf | 1897 | } else { |
633deb58 PG |
1898 | nand_chip->waitfunc = omap_wait; |
1899 | nand_chip->chip_delay = 50; | |
67ce04bf VS |
1900 | } |
1901 | ||
c9711ec5 | 1902 | if (info->flash_bbt) |
f679888f | 1903 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH; |
fef775ca | 1904 | |
f18befb5 | 1905 | /* scan NAND device connected to chip controller */ |
01b95fc6 | 1906 | nand_chip->options |= info->devsize & NAND_BUSWIDTH_16; |
f18befb5 | 1907 | if (nand_scan_ident(mtd, 1, NULL)) { |
01b95fc6 RQ |
1908 | dev_err(&info->pdev->dev, |
1909 | "scan failed, may be bus-width mismatch\n"); | |
f18befb5 | 1910 | err = -ENXIO; |
70ba6d71 | 1911 | goto return_error; |
f18befb5 PG |
1912 | } |
1913 | ||
f679888f BB |
1914 | if (nand_chip->bbt_options & NAND_BBT_USE_FLASH) |
1915 | nand_chip->bbt_options |= NAND_BBT_NO_OOB; | |
1916 | else | |
1917 | nand_chip->options |= NAND_SKIP_BBTSCAN; | |
1918 | ||
f18befb5 | 1919 | /* re-populate low-level callbacks based on xfer modes */ |
01b95fc6 | 1920 | switch (info->xfer_type) { |
1b0b323c | 1921 | case NAND_OMAP_PREFETCH_POLLED: |
633deb58 PG |
1922 | nand_chip->read_buf = omap_read_buf_pref; |
1923 | nand_chip->write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1924 | break; |
1925 | ||
1926 | case NAND_OMAP_POLLED: | |
cf0e4d2b | 1927 | /* Use nand_base defaults for {read,write}_buf */ |
1b0b323c SG |
1928 | break; |
1929 | ||
1930 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1931 | dma_cap_zero(mask); |
1932 | dma_cap_set(DMA_SLAVE, mask); | |
1933 | sig = OMAP24XX_DMA_GPMC; | |
1934 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1935 | if (!info->dma) { | |
2df41d05 RK |
1936 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1937 | err = -ENXIO; | |
70ba6d71 | 1938 | goto return_error; |
763e7359 RK |
1939 | } else { |
1940 | struct dma_slave_config cfg; | |
763e7359 RK |
1941 | |
1942 | memset(&cfg, 0, sizeof(cfg)); | |
1943 | cfg.src_addr = info->phys_base; | |
1944 | cfg.dst_addr = info->phys_base; | |
1945 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1946 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1947 | cfg.src_maxburst = 16; | |
1948 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1949 | err = dmaengine_slave_config(info->dma, &cfg); |
1950 | if (err) { | |
763e7359 | 1951 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1952 | err); |
70ba6d71 | 1953 | goto return_error; |
763e7359 | 1954 | } |
633deb58 PG |
1955 | nand_chip->read_buf = omap_read_buf_dma_pref; |
1956 | nand_chip->write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1957 | } |
1958 | break; | |
1959 | ||
4e070376 | 1960 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1961 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1962 | if (info->gpmc_irq_fifo <= 0) { | |
1963 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1964 | err = -ENODEV; | |
70ba6d71 | 1965 | goto return_error; |
5c468455 | 1966 | } |
70ba6d71 PG |
1967 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo, |
1968 | omap_nand_irq, IRQF_SHARED, | |
1969 | "gpmc-nand-fifo", info); | |
4e070376 SG |
1970 | if (err) { |
1971 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1972 | info->gpmc_irq_fifo, err); |
1973 | info->gpmc_irq_fifo = 0; | |
70ba6d71 | 1974 | goto return_error; |
5c468455 AM |
1975 | } |
1976 | ||
1977 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1978 | if (info->gpmc_irq_count <= 0) { | |
1979 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1980 | err = -ENODEV; | |
70ba6d71 | 1981 | goto return_error; |
5c468455 | 1982 | } |
70ba6d71 PG |
1983 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_count, |
1984 | omap_nand_irq, IRQF_SHARED, | |
1985 | "gpmc-nand-count", info); | |
5c468455 AM |
1986 | if (err) { |
1987 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1988 | info->gpmc_irq_count, err); | |
1989 | info->gpmc_irq_count = 0; | |
70ba6d71 | 1990 | goto return_error; |
4e070376 | 1991 | } |
5c468455 | 1992 | |
633deb58 PG |
1993 | nand_chip->read_buf = omap_read_buf_irq_pref; |
1994 | nand_chip->write_buf = omap_write_buf_irq_pref; | |
5c468455 | 1995 | |
4e070376 SG |
1996 | break; |
1997 | ||
1b0b323c SG |
1998 | default: |
1999 | dev_err(&pdev->dev, | |
01b95fc6 | 2000 | "xfer_type(%d) not supported!\n", info->xfer_type); |
1b0b323c | 2001 | err = -EINVAL; |
70ba6d71 | 2002 | goto return_error; |
59e9c5ae | 2003 | } |
59e9c5ae | 2004 | |
93af53b8 EG |
2005 | if (!omap2_nand_ecc_check(info, pdata)) { |
2006 | err = -EINVAL; | |
2007 | goto return_error; | |
2008 | } | |
2009 | ||
a8c65d50 BB |
2010 | /* |
2011 | * Bail out earlier to let NAND_ECC_SOFT code create its own | |
e04dbf35 | 2012 | * ooblayout instead of using ours. |
a8c65d50 BB |
2013 | */ |
2014 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) { | |
2015 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
d7b83b8a | 2016 | nand_chip->ecc.algo = NAND_ECC_HAMMING; |
a8c65d50 BB |
2017 | goto scan_tail; |
2018 | } | |
2019 | ||
a919e511 | 2020 | /* populate MTD interface based on ECC scheme */ |
4e558072 | 2021 | switch (info->ecc_opt) { |
a919e511 PG |
2022 | case OMAP_ECC_HAM1_CODE_HW: |
2023 | pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); | |
2024 | nand_chip->ecc.mode = NAND_ECC_HW; | |
633deb58 PG |
2025 | nand_chip->ecc.bytes = 3; |
2026 | nand_chip->ecc.size = 512; | |
2027 | nand_chip->ecc.strength = 1; | |
2028 | nand_chip->ecc.calculate = omap_calculate_ecc; | |
2029 | nand_chip->ecc.hwctl = omap_enable_hwecc; | |
2030 | nand_chip->ecc.correct = omap_correct_data; | |
e04dbf35 BB |
2031 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2032 | oobbytes_per_step = nand_chip->ecc.bytes; | |
2033 | ||
2034 | if (!(nand_chip->options & NAND_BUSWIDTH_16)) | |
2035 | min_oobbytes = 1; | |
2036 | ||
a919e511 PG |
2037 | break; |
2038 | ||
2039 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
a919e511 PG |
2040 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); |
2041 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2042 | nand_chip->ecc.size = 512; | |
2043 | nand_chip->ecc.bytes = 7; | |
2044 | nand_chip->ecc.strength = 4; | |
7c977c3e | 2045 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 2046 | nand_chip->ecc.correct = nand_bch_correct_data; |
2c9f2365 | 2047 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
e04dbf35 BB |
2048 | mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops); |
2049 | /* Reserve one byte for the OMAP marker */ | |
2050 | oobbytes_per_step = nand_chip->ecc.bytes + 1; | |
a919e511 | 2051 | /* software bch library is used for locating errors */ |
a8c65d50 | 2052 | nand_chip->ecc.priv = nand_bch_init(mtd); |
32d42a85 | 2053 | if (!nand_chip->ecc.priv) { |
d2f08c75 | 2054 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
0e618ef0 | 2055 | err = -EINVAL; |
d2f08c75 | 2056 | goto return_error; |
a919e511 PG |
2057 | } |
2058 | break; | |
a919e511 PG |
2059 | |
2060 | case OMAP_ECC_BCH4_CODE_HW: | |
a919e511 PG |
2061 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); |
2062 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2063 | nand_chip->ecc.size = 512; | |
2064 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
2065 | nand_chip->ecc.bytes = 7 + 1; | |
2066 | nand_chip->ecc.strength = 4; | |
7c977c3e | 2067 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 2068 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 2069 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
2070 | nand_chip->ecc.read_page = omap_read_page_bch; |
2071 | nand_chip->ecc.write_page = omap_write_page_bch; | |
e04dbf35 BB |
2072 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2073 | oobbytes_per_step = nand_chip->ecc.bytes; | |
93af53b8 EG |
2074 | |
2075 | err = elm_config(info->elm_dev, BCH4_ECC, | |
432420c0 | 2076 | mtd->writesize / nand_chip->ecc.size, |
93af53b8 EG |
2077 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2078 | if (err < 0) | |
70ba6d71 | 2079 | goto return_error; |
a919e511 | 2080 | break; |
a919e511 PG |
2081 | |
2082 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
a919e511 PG |
2083 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); |
2084 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2085 | nand_chip->ecc.size = 512; | |
2086 | nand_chip->ecc.bytes = 13; | |
2087 | nand_chip->ecc.strength = 8; | |
7c977c3e | 2088 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 2089 | nand_chip->ecc.correct = nand_bch_correct_data; |
7bcd1dca | 2090 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
e04dbf35 BB |
2091 | mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops); |
2092 | /* Reserve one byte for the OMAP marker */ | |
2093 | oobbytes_per_step = nand_chip->ecc.bytes + 1; | |
a919e511 | 2094 | /* software bch library is used for locating errors */ |
a8c65d50 | 2095 | nand_chip->ecc.priv = nand_bch_init(mtd); |
32d42a85 | 2096 | if (!nand_chip->ecc.priv) { |
d2f08c75 | 2097 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
a919e511 | 2098 | err = -EINVAL; |
70ba6d71 | 2099 | goto return_error; |
a919e511 PG |
2100 | } |
2101 | break; | |
a919e511 PG |
2102 | |
2103 | case OMAP_ECC_BCH8_CODE_HW: | |
a919e511 PG |
2104 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); |
2105 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2106 | nand_chip->ecc.size = 512; | |
2107 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
2108 | nand_chip->ecc.bytes = 13 + 1; | |
2109 | nand_chip->ecc.strength = 8; | |
7c977c3e | 2110 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 2111 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 2112 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
2113 | nand_chip->ecc.read_page = omap_read_page_bch; |
2114 | nand_chip->ecc.write_page = omap_write_page_bch; | |
e04dbf35 BB |
2115 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2116 | oobbytes_per_step = nand_chip->ecc.bytes; | |
93af53b8 EG |
2117 | |
2118 | err = elm_config(info->elm_dev, BCH8_ECC, | |
432420c0 | 2119 | mtd->writesize / nand_chip->ecc.size, |
93af53b8 EG |
2120 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2121 | if (err < 0) | |
70ba6d71 | 2122 | goto return_error; |
93af53b8 | 2123 | |
a919e511 | 2124 | break; |
a919e511 | 2125 | |
9748fff9 | 2126 | case OMAP_ECC_BCH16_CODE_HW: |
9748fff9 | 2127 | pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); |
2128 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2129 | nand_chip->ecc.size = 512; | |
2130 | nand_chip->ecc.bytes = 26; | |
2131 | nand_chip->ecc.strength = 16; | |
2132 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; | |
2133 | nand_chip->ecc.correct = omap_elm_correct_data; | |
2134 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; | |
2135 | nand_chip->ecc.read_page = omap_read_page_bch; | |
2136 | nand_chip->ecc.write_page = omap_write_page_bch; | |
e04dbf35 BB |
2137 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2138 | oobbytes_per_step = nand_chip->ecc.bytes; | |
93af53b8 EG |
2139 | |
2140 | err = elm_config(info->elm_dev, BCH16_ECC, | |
432420c0 | 2141 | mtd->writesize / nand_chip->ecc.size, |
93af53b8 EG |
2142 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2143 | if (err < 0) | |
9748fff9 | 2144 | goto return_error; |
93af53b8 | 2145 | |
9748fff9 | 2146 | break; |
a919e511 | 2147 | default: |
d2f08c75 | 2148 | dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n"); |
a919e511 | 2149 | err = -EINVAL; |
70ba6d71 | 2150 | goto return_error; |
f3d73f36 | 2151 | } |
67ce04bf | 2152 | |
b491da72 | 2153 | /* check if NAND device's OOB is enough to store ECC signatures */ |
e04dbf35 BB |
2154 | min_oobbytes += (oobbytes_per_step * |
2155 | (mtd->writesize / nand_chip->ecc.size)); | |
2156 | if (mtd->oobsize < min_oobbytes) { | |
d2f08c75 EG |
2157 | dev_err(&info->pdev->dev, |
2158 | "not enough OOB bytes required = %d, available=%d\n", | |
e04dbf35 | 2159 | min_oobbytes, mtd->oobsize); |
b491da72 | 2160 | err = -EINVAL; |
70ba6d71 | 2161 | goto return_error; |
f040d332 | 2162 | } |
1b0b323c | 2163 | |
7d5929c1 | 2164 | scan_tail: |
a80f1c1f | 2165 | /* second phase scan */ |
633deb58 | 2166 | if (nand_scan_tail(mtd)) { |
a80f1c1f | 2167 | err = -ENXIO; |
70ba6d71 | 2168 | goto return_error; |
a80f1c1f JW |
2169 | } |
2170 | ||
c9711ec5 RQ |
2171 | if (dev->of_node) |
2172 | mtd_device_register(mtd, NULL, 0); | |
2173 | else | |
2174 | mtd_device_register(mtd, pdata->parts, pdata->nr_parts); | |
67ce04bf | 2175 | |
633deb58 | 2176 | platform_set_drvdata(pdev, mtd); |
67ce04bf VS |
2177 | |
2178 | return 0; | |
2179 | ||
70ba6d71 | 2180 | return_error: |
763e7359 RK |
2181 | if (info->dma) |
2182 | dma_release_channel(info->dma); | |
32d42a85 PG |
2183 | if (nand_chip->ecc.priv) { |
2184 | nand_bch_free(nand_chip->ecc.priv); | |
2185 | nand_chip->ecc.priv = NULL; | |
2186 | } | |
67ce04bf VS |
2187 | return err; |
2188 | } | |
2189 | ||
2190 | static int omap_nand_remove(struct platform_device *pdev) | |
2191 | { | |
2192 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
4bd4ebcc | 2193 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
4578ea9a | 2194 | struct omap_nand_info *info = mtd_to_omap(mtd); |
32d42a85 PG |
2195 | if (nand_chip->ecc.priv) { |
2196 | nand_bch_free(nand_chip->ecc.priv); | |
2197 | nand_chip->ecc.priv = NULL; | |
2198 | } | |
763e7359 RK |
2199 | if (info->dma) |
2200 | dma_release_channel(info->dma); | |
633deb58 | 2201 | nand_release(mtd); |
67ce04bf VS |
2202 | return 0; |
2203 | } | |
2204 | ||
c9711ec5 RQ |
2205 | static const struct of_device_id omap_nand_ids[] = { |
2206 | { .compatible = "ti,omap2-nand", }, | |
2207 | {}, | |
2208 | }; | |
2209 | ||
67ce04bf VS |
2210 | static struct platform_driver omap_nand_driver = { |
2211 | .probe = omap_nand_probe, | |
2212 | .remove = omap_nand_remove, | |
2213 | .driver = { | |
2214 | .name = DRIVER_NAME, | |
c9711ec5 | 2215 | .of_match_table = of_match_ptr(omap_nand_ids), |
67ce04bf VS |
2216 | }, |
2217 | }; | |
2218 | ||
f99640de | 2219 | module_platform_driver(omap_nand_driver); |
67ce04bf | 2220 | |
c804c733 | 2221 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
2222 | MODULE_LICENSE("GPL"); |
2223 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |