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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
a0e5cc58 | 15 | #include <linux/module.h> |
4e070376 | 16 | #include <linux/interrupt.h> |
c276aca4 | 17 | #include <linux/jiffies.h> |
18 | #include <linux/sched.h> | |
67ce04bf VS |
19 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
763e7359 | 22 | #include <linux/omap-dma.h> |
67ce04bf | 23 | #include <linux/io.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
62116e51 PA |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
67ce04bf | 27 | |
32d42a85 | 28 | #include <linux/mtd/nand_bch.h> |
62116e51 | 29 | #include <linux/platform_data/elm.h> |
0e618ef0 | 30 | |
2203747c | 31 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 32 | |
67ce04bf | 33 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 34 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 35 | |
67ce04bf VS |
36 | #define NAND_Ecc_P1e (1 << 0) |
37 | #define NAND_Ecc_P2e (1 << 1) | |
38 | #define NAND_Ecc_P4e (1 << 2) | |
39 | #define NAND_Ecc_P8e (1 << 3) | |
40 | #define NAND_Ecc_P16e (1 << 4) | |
41 | #define NAND_Ecc_P32e (1 << 5) | |
42 | #define NAND_Ecc_P64e (1 << 6) | |
43 | #define NAND_Ecc_P128e (1 << 7) | |
44 | #define NAND_Ecc_P256e (1 << 8) | |
45 | #define NAND_Ecc_P512e (1 << 9) | |
46 | #define NAND_Ecc_P1024e (1 << 10) | |
47 | #define NAND_Ecc_P2048e (1 << 11) | |
48 | ||
49 | #define NAND_Ecc_P1o (1 << 16) | |
50 | #define NAND_Ecc_P2o (1 << 17) | |
51 | #define NAND_Ecc_P4o (1 << 18) | |
52 | #define NAND_Ecc_P8o (1 << 19) | |
53 | #define NAND_Ecc_P16o (1 << 20) | |
54 | #define NAND_Ecc_P32o (1 << 21) | |
55 | #define NAND_Ecc_P64o (1 << 22) | |
56 | #define NAND_Ecc_P128o (1 << 23) | |
57 | #define NAND_Ecc_P256o (1 << 24) | |
58 | #define NAND_Ecc_P512o (1 << 25) | |
59 | #define NAND_Ecc_P1024o (1 << 26) | |
60 | #define NAND_Ecc_P2048o (1 << 27) | |
61 | ||
62 | #define TF(value) (value ? 1 : 0) | |
63 | ||
64 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
65 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
66 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
67 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
68 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
69 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
70 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
71 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
72 | ||
73 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
74 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
75 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
76 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
77 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
78 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
79 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
80 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
81 | ||
82 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
83 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
84 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
85 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
86 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
87 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
88 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
89 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
90 | ||
91 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
92 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
93 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
94 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
95 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
96 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
97 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
98 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
99 | ||
100 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
101 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
102 | ||
65b97cf6 AM |
103 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
104 | #define ECC_CONFIG_CS_SHIFT 1 | |
105 | #define CS_MASK 0x7 | |
106 | #define ENABLE_PREFETCH (0x1 << 7) | |
107 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 108 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
109 | #define ECCSIZE1_SHIFT 22 |
110 | #define ECC1RESULTSIZE 0x1 | |
111 | #define ECCCLEAR 0x100 | |
112 | #define ECC1 0x1 | |
47f88af4 AM |
113 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
114 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
115 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
116 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
117 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 118 | |
d5e7c864 LV |
119 | #define OMAP24XX_DMA_GPMC 4 |
120 | ||
62116e51 PA |
121 | #define SECTOR_BYTES 512 |
122 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ | |
123 | #define BCH4_BIT_PAD 4 | |
62116e51 PA |
124 | |
125 | /* GPMC ecc engine settings for read */ | |
126 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
127 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
128 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
129 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
130 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
131 | ||
132 | /* GPMC ecc engine settings for write */ | |
133 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
134 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
135 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
136 | ||
b491da72 | 137 | #define BADBLOCK_MARKER_LENGTH 2 |
a919e511 | 138 | |
9748fff9 | 139 | static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, |
140 | 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78, | |
141 | 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93, | |
142 | 0x07, 0x0e}; | |
62116e51 PA |
143 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, |
144 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | |
145 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | |
62116e51 | 146 | |
1dc338e8 RL |
147 | /* Shared among all NAND instances to synchronize access to the ECC Engine */ |
148 | static struct nand_hw_control omap_gpmc_controller = { | |
149 | .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock), | |
150 | .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq), | |
151 | }; | |
59e9c5ae | 152 | |
67ce04bf | 153 | struct omap_nand_info { |
67ce04bf VS |
154 | struct omap_nand_platform_data *pdata; |
155 | struct mtd_info mtd; | |
67ce04bf VS |
156 | struct nand_chip nand; |
157 | struct platform_device *pdev; | |
158 | ||
159 | int gpmc_cs; | |
160 | unsigned long phys_base; | |
4e558072 | 161 | enum omap_ecc ecc_opt; |
dfe32893 | 162 | struct completion comp; |
763e7359 | 163 | struct dma_chan *dma; |
5c468455 AM |
164 | int gpmc_irq_fifo; |
165 | int gpmc_irq_count; | |
4e070376 SG |
166 | enum { |
167 | OMAP_NAND_IO_READ = 0, /* read */ | |
168 | OMAP_NAND_IO_WRITE, /* write */ | |
169 | } iomode; | |
170 | u_char *buf; | |
171 | int buf_len; | |
65b97cf6 | 172 | struct gpmc_nand_regs reg; |
94cb4ee0 RL |
173 | /* generated at runtime depending on ECC algorithm and layout selected */ |
174 | struct nand_ecclayout oobinfo; | |
a919e511 | 175 | /* fields specific for BCHx_HW ECC scheme */ |
62116e51 PA |
176 | struct device *elm_dev; |
177 | struct device_node *of_node; | |
67ce04bf VS |
178 | }; |
179 | ||
65b97cf6 AM |
180 | /** |
181 | * omap_prefetch_enable - configures and starts prefetch transfer | |
182 | * @cs: cs (chip select) number | |
183 | * @fifo_th: fifo threshold to be used for read/ write | |
184 | * @dma_mode: dma mode enable (1) or disable (0) | |
185 | * @u32_count: number of bytes to be transferred | |
186 | * @is_write: prefetch read(0) or write post(1) mode | |
187 | */ | |
188 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
189 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
190 | { | |
191 | u32 val; | |
192 | ||
193 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
194 | return -1; | |
195 | ||
196 | if (readl(info->reg.gpmc_prefetch_control)) | |
197 | return -EBUSY; | |
198 | ||
199 | /* Set the amount of bytes to be prefetched */ | |
200 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
201 | ||
202 | /* Set dma/mpu mode, the prefetch read / post write and | |
203 | * enable the engine. Set which cs is has requested for. | |
204 | */ | |
205 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
206 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
207 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); | |
208 | writel(val, info->reg.gpmc_prefetch_config1); | |
209 | ||
210 | /* Start the prefetch engine */ | |
211 | writel(0x1, info->reg.gpmc_prefetch_control); | |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
216 | /** | |
217 | * omap_prefetch_reset - disables and stops the prefetch engine | |
218 | */ | |
219 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
220 | { | |
221 | u32 config1; | |
222 | ||
223 | /* check if the same module/cs is trying to reset */ | |
224 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
225 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
226 | return -EINVAL; | |
227 | ||
228 | /* Stop the PFPW engine */ | |
229 | writel(0x0, info->reg.gpmc_prefetch_control); | |
230 | ||
231 | /* Reset/disable the PFPW engine */ | |
232 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
67ce04bf VS |
237 | /** |
238 | * omap_hwcontrol - hardware specific access to control-lines | |
239 | * @mtd: MTD device structure | |
240 | * @cmd: command to device | |
241 | * @ctrl: | |
242 | * NAND_NCE: bit 0 -> don't care | |
243 | * NAND_CLE: bit 1 -> Command Latch | |
244 | * NAND_ALE: bit 2 -> Address Latch | |
245 | * | |
246 | * NOTE: boards may use different bits for these!! | |
247 | */ | |
248 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
249 | { | |
250 | struct omap_nand_info *info = container_of(mtd, | |
251 | struct omap_nand_info, mtd); | |
67ce04bf | 252 | |
2c01946c SG |
253 | if (cmd != NAND_CMD_NONE) { |
254 | if (ctrl & NAND_CLE) | |
65b97cf6 | 255 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
256 | |
257 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 258 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
259 | |
260 | else /* NAND_NCE */ | |
65b97cf6 | 261 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 262 | } |
67ce04bf VS |
263 | } |
264 | ||
59e9c5ae | 265 | /** |
266 | * omap_read_buf8 - read data from NAND controller into buffer | |
267 | * @mtd: MTD device structure | |
268 | * @buf: buffer to store date | |
269 | * @len: number of bytes to read | |
270 | */ | |
271 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
272 | { | |
273 | struct nand_chip *nand = mtd->priv; | |
274 | ||
275 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
276 | } | |
277 | ||
278 | /** | |
279 | * omap_write_buf8 - write buffer to NAND controller | |
280 | * @mtd: MTD device structure | |
281 | * @buf: data buffer | |
282 | * @len: number of bytes to write | |
283 | */ | |
284 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
285 | { | |
286 | struct omap_nand_info *info = container_of(mtd, | |
287 | struct omap_nand_info, mtd); | |
288 | u_char *p = (u_char *)buf; | |
2c01946c | 289 | u32 status = 0; |
59e9c5ae | 290 | |
291 | while (len--) { | |
292 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
293 | /* wait until buffer is available for write */ |
294 | do { | |
65b97cf6 | 295 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 296 | STATUS_BUFF_EMPTY; |
2c01946c | 297 | } while (!status); |
59e9c5ae | 298 | } |
299 | } | |
300 | ||
67ce04bf VS |
301 | /** |
302 | * omap_read_buf16 - read data from NAND controller into buffer | |
303 | * @mtd: MTD device structure | |
304 | * @buf: buffer to store date | |
305 | * @len: number of bytes to read | |
306 | */ | |
307 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
308 | { | |
309 | struct nand_chip *nand = mtd->priv; | |
310 | ||
59e9c5ae | 311 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
312 | } |
313 | ||
314 | /** | |
315 | * omap_write_buf16 - write buffer to NAND controller | |
316 | * @mtd: MTD device structure | |
317 | * @buf: data buffer | |
318 | * @len: number of bytes to write | |
319 | */ | |
320 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
321 | { | |
322 | struct omap_nand_info *info = container_of(mtd, | |
323 | struct omap_nand_info, mtd); | |
324 | u16 *p = (u16 *) buf; | |
2c01946c | 325 | u32 status = 0; |
67ce04bf VS |
326 | /* FIXME try bursts of writesw() or DMA ... */ |
327 | len >>= 1; | |
328 | ||
329 | while (len--) { | |
59e9c5ae | 330 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
331 | /* wait until buffer is available for write */ |
332 | do { | |
65b97cf6 | 333 | status = readl(info->reg.gpmc_status) & |
47f88af4 | 334 | STATUS_BUFF_EMPTY; |
2c01946c | 335 | } while (!status); |
67ce04bf VS |
336 | } |
337 | } | |
59e9c5ae | 338 | |
339 | /** | |
340 | * omap_read_buf_pref - read data from NAND controller into buffer | |
341 | * @mtd: MTD device structure | |
342 | * @buf: buffer to store date | |
343 | * @len: number of bytes to read | |
344 | */ | |
345 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
346 | { | |
347 | struct omap_nand_info *info = container_of(mtd, | |
348 | struct omap_nand_info, mtd); | |
2c01946c | 349 | uint32_t r_count = 0; |
59e9c5ae | 350 | int ret = 0; |
351 | u32 *p = (u32 *)buf; | |
352 | ||
353 | /* take care of subpage reads */ | |
c3341d0c VS |
354 | if (len % 4) { |
355 | if (info->nand.options & NAND_BUSWIDTH_16) | |
356 | omap_read_buf16(mtd, buf, len % 4); | |
357 | else | |
358 | omap_read_buf8(mtd, buf, len % 4); | |
359 | p = (u32 *) (buf + len % 4); | |
360 | len -= len % 4; | |
59e9c5ae | 361 | } |
59e9c5ae | 362 | |
363 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
364 | ret = omap_prefetch_enable(info->gpmc_cs, |
365 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 366 | if (ret) { |
367 | /* PFPW engine is busy, use cpu copy method */ | |
368 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 369 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 370 | else |
c5d8c0ca | 371 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 372 | } else { |
373 | do { | |
65b97cf6 | 374 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 375 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
376 | r_count = r_count >> 2; |
377 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 378 | p += r_count; |
379 | len -= r_count << 2; | |
380 | } while (len); | |
59e9c5ae | 381 | /* disable and stop the PFPW engine */ |
65b97cf6 | 382 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 383 | } |
384 | } | |
385 | ||
386 | /** | |
387 | * omap_write_buf_pref - write buffer to NAND controller | |
388 | * @mtd: MTD device structure | |
389 | * @buf: data buffer | |
390 | * @len: number of bytes to write | |
391 | */ | |
392 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
393 | const u_char *buf, int len) | |
394 | { | |
395 | struct omap_nand_info *info = container_of(mtd, | |
396 | struct omap_nand_info, mtd); | |
4e070376 | 397 | uint32_t w_count = 0; |
59e9c5ae | 398 | int i = 0, ret = 0; |
c5d8c0ca | 399 | u16 *p = (u16 *)buf; |
4e070376 | 400 | unsigned long tim, limit; |
65b97cf6 | 401 | u32 val; |
59e9c5ae | 402 | |
403 | /* take care of subpage writes */ | |
404 | if (len % 2 != 0) { | |
2c01946c | 405 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 406 | p = (u16 *)(buf + 1); |
407 | len--; | |
408 | } | |
409 | ||
410 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
411 | ret = omap_prefetch_enable(info->gpmc_cs, |
412 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 413 | if (ret) { |
414 | /* PFPW engine is busy, use cpu copy method */ | |
415 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 416 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 417 | else |
c5d8c0ca | 418 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 419 | } else { |
2c01946c | 420 | while (len) { |
65b97cf6 | 421 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 422 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 423 | w_count = w_count >> 1; |
59e9c5ae | 424 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 425 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 426 | } |
2c01946c | 427 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
428 | tim = 0; |
429 | limit = (loops_per_jiffy * | |
430 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 431 | do { |
4e070376 | 432 | cpu_relax(); |
65b97cf6 | 433 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 434 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 435 | } while (val && (tim++ < limit)); |
4e070376 | 436 | |
59e9c5ae | 437 | /* disable and stop the PFPW engine */ |
65b97cf6 | 438 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 439 | } |
440 | } | |
441 | ||
dfe32893 | 442 | /* |
2df41d05 | 443 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 444 | * @data: pointer to completion data structure |
445 | */ | |
763e7359 RK |
446 | static void omap_nand_dma_callback(void *data) |
447 | { | |
448 | complete((struct completion *) data); | |
449 | } | |
dfe32893 | 450 | |
451 | /* | |
4cacbe22 | 452 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 453 | * @mtd: MTD device structure |
454 | * @addr: virtual address in RAM of source/destination | |
455 | * @len: number of data bytes to be transferred | |
456 | * @is_write: flag for read/write operation | |
457 | */ | |
458 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
459 | unsigned int len, int is_write) | |
460 | { | |
461 | struct omap_nand_info *info = container_of(mtd, | |
462 | struct omap_nand_info, mtd); | |
2df41d05 | 463 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 464 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
465 | DMA_FROM_DEVICE; | |
2df41d05 | 466 | struct scatterlist sg; |
4e070376 | 467 | unsigned long tim, limit; |
2df41d05 RK |
468 | unsigned n; |
469 | int ret; | |
65b97cf6 | 470 | u32 val; |
dfe32893 | 471 | |
472 | if (addr >= high_memory) { | |
473 | struct page *p1; | |
474 | ||
475 | if (((size_t)addr & PAGE_MASK) != | |
476 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
477 | goto out_copy; | |
478 | p1 = vmalloc_to_page(addr); | |
479 | if (!p1) | |
480 | goto out_copy; | |
481 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
482 | } | |
483 | ||
2df41d05 RK |
484 | sg_init_one(&sg, addr, len); |
485 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
486 | if (n == 0) { | |
dfe32893 | 487 | dev_err(&info->pdev->dev, |
488 | "Couldn't DMA map a %d byte buffer\n", len); | |
489 | goto out_copy; | |
490 | } | |
491 | ||
2df41d05 RK |
492 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
493 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
494 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
495 | if (!tx) | |
496 | goto out_copy_unmap; | |
497 | ||
498 | tx->callback = omap_nand_dma_callback; | |
499 | tx->callback_param = &info->comp; | |
500 | dmaengine_submit(tx); | |
501 | ||
65b97cf6 AM |
502 | /* configure and start prefetch transfer */ |
503 | ret = omap_prefetch_enable(info->gpmc_cs, | |
504 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 505 | if (ret) |
4e070376 | 506 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 507 | goto out_copy_unmap; |
dfe32893 | 508 | |
509 | init_completion(&info->comp); | |
2df41d05 | 510 | dma_async_issue_pending(info->dma); |
dfe32893 | 511 | |
512 | /* setup and start DMA using dma_addr */ | |
513 | wait_for_completion(&info->comp); | |
4e070376 SG |
514 | tim = 0; |
515 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
516 | |
517 | do { | |
4e070376 | 518 | cpu_relax(); |
65b97cf6 | 519 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 520 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 521 | } while (val && (tim++ < limit)); |
dfe32893 | 522 | |
dfe32893 | 523 | /* disable and stop the PFPW engine */ |
65b97cf6 | 524 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 525 | |
2df41d05 | 526 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 527 | return 0; |
528 | ||
d7efe228 | 529 | out_copy_unmap: |
2df41d05 | 530 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 531 | out_copy: |
532 | if (info->nand.options & NAND_BUSWIDTH_16) | |
533 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
534 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
535 | else | |
536 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
537 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
538 | return 0; | |
539 | } | |
dfe32893 | 540 | |
541 | /** | |
542 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
543 | * @mtd: MTD device structure | |
544 | * @buf: buffer to store date | |
545 | * @len: number of bytes to read | |
546 | */ | |
547 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
548 | { | |
549 | if (len <= mtd->oobsize) | |
550 | omap_read_buf_pref(mtd, buf, len); | |
551 | else | |
552 | /* start transfer in DMA mode */ | |
553 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
554 | } | |
555 | ||
556 | /** | |
557 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
558 | * @mtd: MTD device structure | |
559 | * @buf: data buffer | |
560 | * @len: number of bytes to write | |
561 | */ | |
562 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
563 | const u_char *buf, int len) | |
564 | { | |
565 | if (len <= mtd->oobsize) | |
566 | omap_write_buf_pref(mtd, buf, len); | |
567 | else | |
568 | /* start transfer in DMA mode */ | |
bdaefc41 | 569 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 570 | } |
571 | ||
4e070376 | 572 | /* |
4cacbe22 | 573 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
574 | * @this_irq: gpmc irq number |
575 | * @dev: omap_nand_info structure pointer is passed here | |
576 | */ | |
577 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
578 | { | |
579 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
580 | u32 bytes; | |
4e070376 | 581 | |
65b97cf6 | 582 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 583 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
584 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
585 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 586 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
587 | goto done; |
588 | ||
589 | if (info->buf_len && (info->buf_len < bytes)) | |
590 | bytes = info->buf_len; | |
591 | else if (!info->buf_len) | |
592 | bytes = 0; | |
593 | iowrite32_rep(info->nand.IO_ADDR_W, | |
594 | (u32 *)info->buf, bytes >> 2); | |
595 | info->buf = info->buf + bytes; | |
596 | info->buf_len -= bytes; | |
597 | ||
598 | } else { | |
599 | ioread32_rep(info->nand.IO_ADDR_R, | |
600 | (u32 *)info->buf, bytes >> 2); | |
601 | info->buf = info->buf + bytes; | |
602 | ||
5c468455 | 603 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
604 | goto done; |
605 | } | |
4e070376 SG |
606 | |
607 | return IRQ_HANDLED; | |
608 | ||
609 | done: | |
610 | complete(&info->comp); | |
4e070376 | 611 | |
5c468455 AM |
612 | disable_irq_nosync(info->gpmc_irq_fifo); |
613 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
614 | |
615 | return IRQ_HANDLED; | |
616 | } | |
617 | ||
618 | /* | |
619 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
620 | * @mtd: MTD device structure | |
621 | * @buf: buffer to store date | |
622 | * @len: number of bytes to read | |
623 | */ | |
624 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
625 | { | |
626 | struct omap_nand_info *info = container_of(mtd, | |
627 | struct omap_nand_info, mtd); | |
628 | int ret = 0; | |
629 | ||
630 | if (len <= mtd->oobsize) { | |
631 | omap_read_buf_pref(mtd, buf, len); | |
632 | return; | |
633 | } | |
634 | ||
635 | info->iomode = OMAP_NAND_IO_READ; | |
636 | info->buf = buf; | |
637 | init_completion(&info->comp); | |
638 | ||
639 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
640 | ret = omap_prefetch_enable(info->gpmc_cs, |
641 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
642 | if (ret) |
643 | /* PFPW engine is busy, use cpu copy method */ | |
644 | goto out_copy; | |
645 | ||
646 | info->buf_len = len; | |
5c468455 AM |
647 | |
648 | enable_irq(info->gpmc_irq_count); | |
649 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
650 | |
651 | /* waiting for read to complete */ | |
652 | wait_for_completion(&info->comp); | |
653 | ||
654 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 655 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
656 | return; |
657 | ||
658 | out_copy: | |
659 | if (info->nand.options & NAND_BUSWIDTH_16) | |
660 | omap_read_buf16(mtd, buf, len); | |
661 | else | |
662 | omap_read_buf8(mtd, buf, len); | |
663 | } | |
664 | ||
665 | /* | |
666 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
667 | * @mtd: MTD device structure | |
668 | * @buf: data buffer | |
669 | * @len: number of bytes to write | |
670 | */ | |
671 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
672 | const u_char *buf, int len) | |
673 | { | |
674 | struct omap_nand_info *info = container_of(mtd, | |
675 | struct omap_nand_info, mtd); | |
676 | int ret = 0; | |
677 | unsigned long tim, limit; | |
65b97cf6 | 678 | u32 val; |
4e070376 SG |
679 | |
680 | if (len <= mtd->oobsize) { | |
681 | omap_write_buf_pref(mtd, buf, len); | |
682 | return; | |
683 | } | |
684 | ||
685 | info->iomode = OMAP_NAND_IO_WRITE; | |
686 | info->buf = (u_char *) buf; | |
687 | init_completion(&info->comp); | |
688 | ||
317379a9 | 689 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
690 | ret = omap_prefetch_enable(info->gpmc_cs, |
691 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
692 | if (ret) |
693 | /* PFPW engine is busy, use cpu copy method */ | |
694 | goto out_copy; | |
695 | ||
696 | info->buf_len = len; | |
5c468455 AM |
697 | |
698 | enable_irq(info->gpmc_irq_count); | |
699 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
700 | |
701 | /* waiting for write to complete */ | |
702 | wait_for_completion(&info->comp); | |
5c468455 | 703 | |
4e070376 SG |
704 | /* wait for data to flushed-out before reset the prefetch */ |
705 | tim = 0; | |
706 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
707 | do { |
708 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 709 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 710 | cpu_relax(); |
65b97cf6 | 711 | } while (val && (tim++ < limit)); |
4e070376 SG |
712 | |
713 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 714 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
715 | return; |
716 | ||
717 | out_copy: | |
718 | if (info->nand.options & NAND_BUSWIDTH_16) | |
719 | omap_write_buf16(mtd, buf, len); | |
720 | else | |
721 | omap_write_buf8(mtd, buf, len); | |
722 | } | |
723 | ||
67ce04bf VS |
724 | /** |
725 | * gen_true_ecc - This function will generate true ECC value | |
726 | * @ecc_buf: buffer to store ecc code | |
727 | * | |
728 | * This generated true ECC value can be used when correcting | |
729 | * data read from NAND flash memory core | |
730 | */ | |
731 | static void gen_true_ecc(u8 *ecc_buf) | |
732 | { | |
733 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
734 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
735 | ||
736 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
737 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
738 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
739 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
740 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
741 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
742 | } | |
743 | ||
744 | /** | |
745 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
746 | * @ecc_data1: ecc code from nand spare area | |
747 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
748 | * @page_data: page data | |
749 | * | |
750 | * This function compares two ECC's and indicates if there is an error. | |
751 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
752 | * If there is no error, %0 is returned. If there is an error but it |
753 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
754 | */ |
755 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
756 | u8 *ecc_data2, /* read from register */ | |
757 | u8 *page_data) | |
758 | { | |
759 | uint i; | |
760 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
761 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
762 | u8 ecc_bit[24]; | |
763 | u8 ecc_sum = 0; | |
764 | u8 find_bit = 0; | |
765 | uint find_byte = 0; | |
766 | int isEccFF; | |
767 | ||
768 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
769 | ||
770 | gen_true_ecc(ecc_data1); | |
771 | gen_true_ecc(ecc_data2); | |
772 | ||
773 | for (i = 0; i <= 2; i++) { | |
774 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
775 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
776 | } | |
777 | ||
778 | for (i = 0; i < 8; i++) { | |
779 | tmp0_bit[i] = *ecc_data1 % 2; | |
780 | *ecc_data1 = *ecc_data1 / 2; | |
781 | } | |
782 | ||
783 | for (i = 0; i < 8; i++) { | |
784 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
785 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
786 | } | |
787 | ||
788 | for (i = 0; i < 8; i++) { | |
789 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
790 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
791 | } | |
792 | ||
793 | for (i = 0; i < 8; i++) { | |
794 | comp0_bit[i] = *ecc_data2 % 2; | |
795 | *ecc_data2 = *ecc_data2 / 2; | |
796 | } | |
797 | ||
798 | for (i = 0; i < 8; i++) { | |
799 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
800 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
801 | } | |
802 | ||
803 | for (i = 0; i < 8; i++) { | |
804 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
805 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
806 | } | |
807 | ||
808 | for (i = 0; i < 6; i++) | |
809 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
810 | ||
811 | for (i = 0; i < 8; i++) | |
812 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
813 | ||
814 | for (i = 0; i < 8; i++) | |
815 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
816 | ||
817 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
818 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
819 | ||
820 | for (i = 0; i < 24; i++) | |
821 | ecc_sum += ecc_bit[i]; | |
822 | ||
823 | switch (ecc_sum) { | |
824 | case 0: | |
825 | /* Not reached because this function is not called if | |
826 | * ECC values are equal | |
827 | */ | |
828 | return 0; | |
829 | ||
830 | case 1: | |
831 | /* Uncorrectable error */ | |
289c0522 | 832 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
67ce04bf VS |
833 | return -1; |
834 | ||
835 | case 11: | |
836 | /* UN-Correctable error */ | |
289c0522 | 837 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
67ce04bf VS |
838 | return -1; |
839 | ||
840 | case 12: | |
841 | /* Correctable error */ | |
842 | find_byte = (ecc_bit[23] << 8) + | |
843 | (ecc_bit[21] << 7) + | |
844 | (ecc_bit[19] << 6) + | |
845 | (ecc_bit[17] << 5) + | |
846 | (ecc_bit[15] << 4) + | |
847 | (ecc_bit[13] << 3) + | |
848 | (ecc_bit[11] << 2) + | |
849 | (ecc_bit[9] << 1) + | |
850 | ecc_bit[7]; | |
851 | ||
852 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
853 | ||
0a32a102 BN |
854 | pr_debug("Correcting single bit ECC error at offset: " |
855 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
856 | |
857 | page_data[find_byte] ^= (1 << find_bit); | |
858 | ||
74f1b724 | 859 | return 1; |
67ce04bf VS |
860 | default: |
861 | if (isEccFF) { | |
862 | if (ecc_data2[0] == 0 && | |
863 | ecc_data2[1] == 0 && | |
864 | ecc_data2[2] == 0) | |
865 | return 0; | |
866 | } | |
289c0522 | 867 | pr_debug("UNCORRECTED_ERROR default\n"); |
67ce04bf VS |
868 | return -1; |
869 | } | |
870 | } | |
871 | ||
872 | /** | |
873 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
874 | * @mtd: MTD device structure | |
875 | * @dat: page data | |
876 | * @read_ecc: ecc read from nand flash | |
877 | * @calc_ecc: ecc read from HW ECC registers | |
878 | * | |
879 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
880 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
881 | * detection and correction. If there are no errors, %0 is returned. If | |
882 | * there were errors and all of the errors were corrected, the number of | |
883 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
884 | * returned. | |
67ce04bf VS |
885 | */ |
886 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
887 | u_char *read_ecc, u_char *calc_ecc) | |
888 | { | |
889 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
890 | mtd); | |
891 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 892 | int stat = 0; |
67ce04bf VS |
893 | |
894 | /* Ex NAND_ECC_HW12_2048 */ | |
895 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
896 | (info->nand.ecc.size == 2048)) | |
897 | blockCnt = 4; | |
898 | else | |
899 | blockCnt = 1; | |
900 | ||
901 | for (i = 0; i < blockCnt; i++) { | |
902 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
903 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
904 | if (ret < 0) | |
905 | return ret; | |
74f1b724 JO |
906 | /* keep track of the number of corrected errors */ |
907 | stat += ret; | |
67ce04bf VS |
908 | } |
909 | read_ecc += 3; | |
910 | calc_ecc += 3; | |
911 | dat += 512; | |
912 | } | |
74f1b724 | 913 | return stat; |
67ce04bf VS |
914 | } |
915 | ||
916 | /** | |
917 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
918 | * @mtd: MTD device structure | |
919 | * @dat: The pointer to data on which ecc is computed | |
920 | * @ecc_code: The ecc_code buffer | |
921 | * | |
922 | * Using noninverted ECC can be considered ugly since writing a blank | |
923 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
924 | * nobody is trying to write data on the seemingly unused page. Reading | |
925 | * an erased page will produce an ECC mismatch between generated and read | |
926 | * ECC bytes that has to be dealt with separately. | |
927 | */ | |
928 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
929 | u_char *ecc_code) | |
930 | { | |
931 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
932 | mtd); | |
65b97cf6 AM |
933 | u32 val; |
934 | ||
935 | val = readl(info->reg.gpmc_ecc_config); | |
40ddbf50 | 936 | if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) |
65b97cf6 AM |
937 | return -EINVAL; |
938 | ||
939 | /* read ecc result */ | |
940 | val = readl(info->reg.gpmc_ecc1_result); | |
941 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
942 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
943 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
944 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
945 | ||
946 | return 0; | |
67ce04bf VS |
947 | } |
948 | ||
949 | /** | |
950 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
951 | * @mtd: MTD device structure | |
952 | * @mode: Read/Write mode | |
953 | */ | |
954 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
955 | { | |
956 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
957 | mtd); | |
958 | struct nand_chip *chip = mtd->priv; | |
959 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
65b97cf6 AM |
960 | u32 val; |
961 | ||
962 | /* clear ecc and enable bits */ | |
963 | val = ECCCLEAR | ECC1; | |
964 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 965 | |
65b97cf6 AM |
966 | /* program ecc and result sizes */ |
967 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
968 | ECC1RESULTSIZE); | |
969 | writel(val, info->reg.gpmc_ecc_size_config); | |
970 | ||
971 | switch (mode) { | |
972 | case NAND_ECC_READ: | |
973 | case NAND_ECC_WRITE: | |
974 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
975 | break; | |
976 | case NAND_ECC_READSYN: | |
977 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
978 | break; | |
979 | default: | |
980 | dev_info(&info->pdev->dev, | |
981 | "error: unrecognized Mode[%d]!\n", mode); | |
982 | break; | |
983 | } | |
67ce04bf | 984 | |
65b97cf6 AM |
985 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
986 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
987 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 988 | } |
2c01946c | 989 | |
67ce04bf VS |
990 | /** |
991 | * omap_wait - wait until the command is done | |
992 | * @mtd: MTD device structure | |
993 | * @chip: NAND Chip structure | |
994 | * | |
995 | * Wait function is called during Program and erase operations and | |
996 | * the way it is called from MTD layer, we should wait till the NAND | |
997 | * chip is ready after the programming/erase operation has completed. | |
998 | * | |
999 | * Erase can take up to 400ms and program up to 20ms according to | |
1000 | * general NAND and SmartMedia specs | |
1001 | */ | |
1002 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
1003 | { | |
1004 | struct nand_chip *this = mtd->priv; | |
1005 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1006 | mtd); | |
1007 | unsigned long timeo = jiffies; | |
a9c465f0 | 1008 | int status, state = this->state; |
67ce04bf VS |
1009 | |
1010 | if (state == FL_ERASING) | |
4ff6772b | 1011 | timeo += msecs_to_jiffies(400); |
67ce04bf | 1012 | else |
4ff6772b | 1013 | timeo += msecs_to_jiffies(20); |
67ce04bf | 1014 | |
65b97cf6 | 1015 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1016 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1017 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1018 | if (status & NAND_STATUS_READY) |
67ce04bf | 1019 | break; |
c276aca4 | 1020 | cond_resched(); |
67ce04bf | 1021 | } |
a9c465f0 | 1022 | |
4ea1e4ba | 1023 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1024 | return status; |
1025 | } | |
1026 | ||
1027 | /** | |
1028 | * omap_dev_ready - calls the platform specific dev_ready function | |
1029 | * @mtd: MTD device structure | |
1030 | */ | |
1031 | static int omap_dev_ready(struct mtd_info *mtd) | |
1032 | { | |
2c01946c | 1033 | unsigned int val = 0; |
67ce04bf VS |
1034 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1035 | mtd); | |
67ce04bf | 1036 | |
65b97cf6 AM |
1037 | val = readl(info->reg.gpmc_status); |
1038 | ||
67ce04bf | 1039 | if ((val & 0x100) == 0x100) { |
65b97cf6 | 1040 | return 1; |
67ce04bf | 1041 | } else { |
65b97cf6 | 1042 | return 0; |
67ce04bf | 1043 | } |
67ce04bf VS |
1044 | } |
1045 | ||
0e618ef0 | 1046 | /** |
7c977c3e | 1047 | * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation |
0e618ef0 ID |
1048 | * @mtd: MTD device structure |
1049 | * @mode: Read/Write mode | |
62116e51 | 1050 | * |
0760e818 NMG |
1051 | * When using BCH with SW correction (i.e. no ELM), sector size is set |
1052 | * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode | |
1053 | * for both reading and writing with: | |
62116e51 PA |
1054 | * eccsize0 = 0 (no additional protected byte in spare area) |
1055 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
0e618ef0 | 1056 | */ |
7c977c3e | 1057 | static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) |
0e618ef0 | 1058 | { |
16e69322 | 1059 | unsigned int bch_type; |
2ef9f3dd | 1060 | unsigned int dev_width, nsectors; |
0e618ef0 ID |
1061 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1062 | mtd); | |
c5957a32 | 1063 | enum omap_ecc ecc_opt = info->ecc_opt; |
0e618ef0 | 1064 | struct nand_chip *chip = mtd->priv; |
62116e51 PA |
1065 | u32 val, wr_mode; |
1066 | unsigned int ecc_size1, ecc_size0; | |
1067 | ||
c5957a32 PG |
1068 | /* GPMC configurations for calculating ECC */ |
1069 | switch (ecc_opt) { | |
1070 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1071 | bch_type = 0; |
1072 | nsectors = 1; | |
0760e818 NMG |
1073 | wr_mode = BCH_WRAPMODE_6; |
1074 | ecc_size0 = BCH_ECC_SIZE0; | |
1075 | ecc_size1 = BCH_ECC_SIZE1; | |
c5957a32 PG |
1076 | break; |
1077 | case OMAP_ECC_BCH4_CODE_HW: | |
16e69322 PG |
1078 | bch_type = 0; |
1079 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1080 | if (mode == NAND_ECC_READ) { |
1081 | wr_mode = BCH_WRAPMODE_1; | |
1082 | ecc_size0 = BCH4R_ECC_SIZE0; | |
1083 | ecc_size1 = BCH4R_ECC_SIZE1; | |
1084 | } else { | |
1085 | wr_mode = BCH_WRAPMODE_6; | |
1086 | ecc_size0 = BCH_ECC_SIZE0; | |
1087 | ecc_size1 = BCH_ECC_SIZE1; | |
1088 | } | |
1089 | break; | |
1090 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1091 | bch_type = 1; |
1092 | nsectors = 1; | |
0760e818 NMG |
1093 | wr_mode = BCH_WRAPMODE_6; |
1094 | ecc_size0 = BCH_ECC_SIZE0; | |
1095 | ecc_size1 = BCH_ECC_SIZE1; | |
c5957a32 PG |
1096 | break; |
1097 | case OMAP_ECC_BCH8_CODE_HW: | |
16e69322 PG |
1098 | bch_type = 1; |
1099 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1100 | if (mode == NAND_ECC_READ) { |
1101 | wr_mode = BCH_WRAPMODE_1; | |
1102 | ecc_size0 = BCH8R_ECC_SIZE0; | |
1103 | ecc_size1 = BCH8R_ECC_SIZE1; | |
1104 | } else { | |
1105 | wr_mode = BCH_WRAPMODE_6; | |
1106 | ecc_size0 = BCH_ECC_SIZE0; | |
1107 | ecc_size1 = BCH_ECC_SIZE1; | |
1108 | } | |
1109 | break; | |
9748fff9 | 1110 | case OMAP_ECC_BCH16_CODE_HW: |
1111 | bch_type = 0x2; | |
1112 | nsectors = chip->ecc.steps; | |
1113 | if (mode == NAND_ECC_READ) { | |
1114 | wr_mode = 0x01; | |
1115 | ecc_size0 = 52; /* ECC bits in nibbles per sector */ | |
1116 | ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ | |
1117 | } else { | |
1118 | wr_mode = 0x01; | |
1119 | ecc_size0 = 0; /* extra bits in nibbles per sector */ | |
1120 | ecc_size1 = 52; /* OOB bits in nibbles per sector */ | |
1121 | } | |
1122 | break; | |
c5957a32 PG |
1123 | default: |
1124 | return; | |
1125 | } | |
2ef9f3dd AM |
1126 | |
1127 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1128 | ||
62116e51 PA |
1129 | /* Configure ecc size for BCH */ |
1130 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
2ef9f3dd AM |
1131 | writel(val, info->reg.gpmc_ecc_size_config); |
1132 | ||
62116e51 PA |
1133 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
1134 | ||
2ef9f3dd AM |
1135 | /* BCH configuration */ |
1136 | val = ((1 << 16) | /* enable BCH */ | |
16e69322 | 1137 | (bch_type << 12) | /* BCH4/BCH8/BCH16 */ |
62116e51 | 1138 | (wr_mode << 8) | /* wrap mode */ |
2ef9f3dd AM |
1139 | (dev_width << 7) | /* bus width */ |
1140 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1141 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1142 | (0x1)); /* enable ECC */ | |
1143 | ||
1144 | writel(val, info->reg.gpmc_ecc_config); | |
1145 | ||
62116e51 | 1146 | /* Clear ecc and enable bits */ |
2ef9f3dd | 1147 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
0e618ef0 | 1148 | } |
7c977c3e | 1149 | |
2c9f2365 | 1150 | static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f}; |
7bcd1dca PG |
1151 | static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, |
1152 | 0x97, 0x79, 0xe5, 0x24, 0xb5}; | |
0e618ef0 | 1153 | |
62116e51 | 1154 | /** |
a4c7ca00 | 1155 | * omap_calculate_ecc_bch - Generate bytes of ECC bytes |
62116e51 PA |
1156 | * @mtd: MTD device structure |
1157 | * @dat: The pointer to data on which ecc is computed | |
1158 | * @ecc_code: The ecc_code buffer | |
1159 | * | |
1160 | * Support calculating of BCH4/8 ecc vectors for the page | |
1161 | */ | |
a4c7ca00 | 1162 | static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, |
f5dc06fb | 1163 | const u_char *dat, u_char *ecc_calc) |
62116e51 PA |
1164 | { |
1165 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1166 | mtd); | |
f5dc06fb PG |
1167 | int eccbytes = info->nand.ecc.bytes; |
1168 | struct gpmc_nand_regs *gpmc_regs = &info->reg; | |
1169 | u8 *ecc_code; | |
62116e51 | 1170 | unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4; |
9748fff9 | 1171 | u32 val; |
2913aae5 | 1172 | int i, j; |
62116e51 PA |
1173 | |
1174 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
62116e51 | 1175 | for (i = 0; i < nsectors; i++) { |
f5dc06fb PG |
1176 | ecc_code = ecc_calc; |
1177 | switch (info->ecc_opt) { | |
7bcd1dca | 1178 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1179 | case OMAP_ECC_BCH8_CODE_HW: |
1180 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1181 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1182 | bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1183 | bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); | |
62116e51 PA |
1184 | *ecc_code++ = (bch_val4 & 0xFF); |
1185 | *ecc_code++ = ((bch_val3 >> 24) & 0xFF); | |
1186 | *ecc_code++ = ((bch_val3 >> 16) & 0xFF); | |
1187 | *ecc_code++ = ((bch_val3 >> 8) & 0xFF); | |
1188 | *ecc_code++ = (bch_val3 & 0xFF); | |
1189 | *ecc_code++ = ((bch_val2 >> 24) & 0xFF); | |
1190 | *ecc_code++ = ((bch_val2 >> 16) & 0xFF); | |
1191 | *ecc_code++ = ((bch_val2 >> 8) & 0xFF); | |
1192 | *ecc_code++ = (bch_val2 & 0xFF); | |
1193 | *ecc_code++ = ((bch_val1 >> 24) & 0xFF); | |
1194 | *ecc_code++ = ((bch_val1 >> 16) & 0xFF); | |
1195 | *ecc_code++ = ((bch_val1 >> 8) & 0xFF); | |
1196 | *ecc_code++ = (bch_val1 & 0xFF); | |
f5dc06fb | 1197 | break; |
2c9f2365 | 1198 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1199 | case OMAP_ECC_BCH4_CODE_HW: |
1200 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1201 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
62116e51 PA |
1202 | *ecc_code++ = ((bch_val2 >> 12) & 0xFF); |
1203 | *ecc_code++ = ((bch_val2 >> 4) & 0xFF); | |
1204 | *ecc_code++ = ((bch_val2 & 0xF) << 4) | | |
1205 | ((bch_val1 >> 28) & 0xF); | |
1206 | *ecc_code++ = ((bch_val1 >> 20) & 0xFF); | |
1207 | *ecc_code++ = ((bch_val1 >> 12) & 0xFF); | |
1208 | *ecc_code++ = ((bch_val1 >> 4) & 0xFF); | |
1209 | *ecc_code++ = ((bch_val1 & 0xF) << 4); | |
f5dc06fb | 1210 | break; |
9748fff9 | 1211 | case OMAP_ECC_BCH16_CODE_HW: |
1212 | val = readl(gpmc_regs->gpmc_bch_result6[i]); | |
1213 | ecc_code[0] = ((val >> 8) & 0xFF); | |
1214 | ecc_code[1] = ((val >> 0) & 0xFF); | |
1215 | val = readl(gpmc_regs->gpmc_bch_result5[i]); | |
1216 | ecc_code[2] = ((val >> 24) & 0xFF); | |
1217 | ecc_code[3] = ((val >> 16) & 0xFF); | |
1218 | ecc_code[4] = ((val >> 8) & 0xFF); | |
1219 | ecc_code[5] = ((val >> 0) & 0xFF); | |
1220 | val = readl(gpmc_regs->gpmc_bch_result4[i]); | |
1221 | ecc_code[6] = ((val >> 24) & 0xFF); | |
1222 | ecc_code[7] = ((val >> 16) & 0xFF); | |
1223 | ecc_code[8] = ((val >> 8) & 0xFF); | |
1224 | ecc_code[9] = ((val >> 0) & 0xFF); | |
1225 | val = readl(gpmc_regs->gpmc_bch_result3[i]); | |
1226 | ecc_code[10] = ((val >> 24) & 0xFF); | |
1227 | ecc_code[11] = ((val >> 16) & 0xFF); | |
1228 | ecc_code[12] = ((val >> 8) & 0xFF); | |
1229 | ecc_code[13] = ((val >> 0) & 0xFF); | |
1230 | val = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1231 | ecc_code[14] = ((val >> 24) & 0xFF); | |
1232 | ecc_code[15] = ((val >> 16) & 0xFF); | |
1233 | ecc_code[16] = ((val >> 8) & 0xFF); | |
1234 | ecc_code[17] = ((val >> 0) & 0xFF); | |
1235 | val = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1236 | ecc_code[18] = ((val >> 24) & 0xFF); | |
1237 | ecc_code[19] = ((val >> 16) & 0xFF); | |
1238 | ecc_code[20] = ((val >> 8) & 0xFF); | |
1239 | ecc_code[21] = ((val >> 0) & 0xFF); | |
1240 | val = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1241 | ecc_code[22] = ((val >> 24) & 0xFF); | |
1242 | ecc_code[23] = ((val >> 16) & 0xFF); | |
1243 | ecc_code[24] = ((val >> 8) & 0xFF); | |
1244 | ecc_code[25] = ((val >> 0) & 0xFF); | |
1245 | break; | |
f5dc06fb PG |
1246 | default: |
1247 | return -EINVAL; | |
62116e51 | 1248 | } |
f5dc06fb PG |
1249 | |
1250 | /* ECC scheme specific syndrome customizations */ | |
1251 | switch (info->ecc_opt) { | |
2c9f2365 PG |
1252 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
1253 | /* Add constant polynomial to remainder, so that | |
1254 | * ECC of blank pages results in 0x0 on reading back */ | |
2913aae5 TJ |
1255 | for (j = 0; j < eccbytes; j++) |
1256 | ecc_calc[j] ^= bch4_polynomial[j]; | |
2c9f2365 | 1257 | break; |
f5dc06fb PG |
1258 | case OMAP_ECC_BCH4_CODE_HW: |
1259 | /* Set 8th ECC byte as 0x0 for ROM compatibility */ | |
1260 | ecc_calc[eccbytes - 1] = 0x0; | |
1261 | break; | |
7bcd1dca PG |
1262 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
1263 | /* Add constant polynomial to remainder, so that | |
1264 | * ECC of blank pages results in 0x0 on reading back */ | |
2913aae5 TJ |
1265 | for (j = 0; j < eccbytes; j++) |
1266 | ecc_calc[j] ^= bch8_polynomial[j]; | |
7bcd1dca | 1267 | break; |
f5dc06fb PG |
1268 | case OMAP_ECC_BCH8_CODE_HW: |
1269 | /* Set 14th ECC byte as 0x0 for ROM compatibility */ | |
1270 | ecc_calc[eccbytes - 1] = 0x0; | |
1271 | break; | |
9748fff9 | 1272 | case OMAP_ECC_BCH16_CODE_HW: |
1273 | break; | |
f5dc06fb PG |
1274 | default: |
1275 | return -EINVAL; | |
1276 | } | |
1277 | ||
1278 | ecc_calc += eccbytes; | |
62116e51 PA |
1279 | } |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | /** | |
1285 | * erased_sector_bitflips - count bit flips | |
1286 | * @data: data sector buffer | |
1287 | * @oob: oob buffer | |
1288 | * @info: omap_nand_info | |
1289 | * | |
1290 | * Check the bit flips in erased page falls below correctable level. | |
1291 | * If falls below, report the page as erased with correctable bit | |
1292 | * flip, else report as uncorrectable page. | |
1293 | */ | |
1294 | static int erased_sector_bitflips(u_char *data, u_char *oob, | |
1295 | struct omap_nand_info *info) | |
1296 | { | |
1297 | int flip_bits = 0, i; | |
1298 | ||
1299 | for (i = 0; i < info->nand.ecc.size; i++) { | |
1300 | flip_bits += hweight8(~data[i]); | |
1301 | if (flip_bits > info->nand.ecc.strength) | |
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | for (i = 0; i < info->nand.ecc.bytes - 1; i++) { | |
1306 | flip_bits += hweight8(~oob[i]); | |
1307 | if (flip_bits > info->nand.ecc.strength) | |
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | /* | |
1312 | * Bit flips falls in correctable level. | |
1313 | * Fill data area with 0xFF | |
1314 | */ | |
1315 | if (flip_bits) { | |
1316 | memset(data, 0xFF, info->nand.ecc.size); | |
1317 | memset(oob, 0xFF, info->nand.ecc.bytes); | |
1318 | } | |
1319 | ||
1320 | return flip_bits; | |
1321 | } | |
1322 | ||
1323 | /** | |
1324 | * omap_elm_correct_data - corrects page data area in case error reported | |
1325 | * @mtd: MTD device structure | |
1326 | * @data: page data | |
1327 | * @read_ecc: ecc read from nand flash | |
1328 | * @calc_ecc: ecc read from HW ECC registers | |
1329 | * | |
1330 | * Calculated ecc vector reported as zero in case of non-error pages. | |
78f43c53 PG |
1331 | * In case of non-zero ecc vector, first filter out erased-pages, and |
1332 | * then process data via ELM to detect bit-flips. | |
62116e51 PA |
1333 | */ |
1334 | static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |
1335 | u_char *read_ecc, u_char *calc_ecc) | |
1336 | { | |
1337 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
1338 | mtd); | |
de0a4d69 | 1339 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; |
62116e51 PA |
1340 | int eccsteps = info->nand.ecc.steps; |
1341 | int i , j, stat = 0; | |
de0a4d69 | 1342 | int eccflag, actual_eccbytes; |
62116e51 PA |
1343 | struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; |
1344 | u_char *ecc_vec = calc_ecc; | |
1345 | u_char *spare_ecc = read_ecc; | |
1346 | u_char *erased_ecc_vec; | |
78f43c53 PG |
1347 | u_char *buf; |
1348 | int bitflip_count; | |
62116e51 | 1349 | bool is_error_reported = false; |
b08e1f63 | 1350 | u32 bit_pos, byte_pos, error_max, pos; |
13fbe064 | 1351 | int err; |
62116e51 | 1352 | |
de0a4d69 PG |
1353 | switch (info->ecc_opt) { |
1354 | case OMAP_ECC_BCH4_CODE_HW: | |
1355 | /* omit 7th ECC byte reserved for ROM code compatibility */ | |
1356 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1357 | erased_ecc_vec = bch4_vector; |
de0a4d69 PG |
1358 | break; |
1359 | case OMAP_ECC_BCH8_CODE_HW: | |
1360 | /* omit 14th ECC byte reserved for ROM code compatibility */ | |
1361 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1362 | erased_ecc_vec = bch8_vector; |
de0a4d69 | 1363 | break; |
9748fff9 | 1364 | case OMAP_ECC_BCH16_CODE_HW: |
1365 | actual_eccbytes = ecc->bytes; | |
1366 | erased_ecc_vec = bch16_vector; | |
1367 | break; | |
de0a4d69 | 1368 | default: |
d2f08c75 | 1369 | dev_err(&info->pdev->dev, "invalid driver configuration\n"); |
de0a4d69 PG |
1370 | return -EINVAL; |
1371 | } | |
1372 | ||
62116e51 PA |
1373 | /* Initialize elm error vector to zero */ |
1374 | memset(err_vec, 0, sizeof(err_vec)); | |
1375 | ||
62116e51 PA |
1376 | for (i = 0; i < eccsteps ; i++) { |
1377 | eccflag = 0; /* initialize eccflag */ | |
1378 | ||
1379 | /* | |
1380 | * Check any error reported, | |
1381 | * In case of error, non zero ecc reported. | |
1382 | */ | |
de0a4d69 | 1383 | for (j = 0; j < actual_eccbytes; j++) { |
62116e51 PA |
1384 | if (calc_ecc[j] != 0) { |
1385 | eccflag = 1; /* non zero ecc, error present */ | |
1386 | break; | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | if (eccflag == 1) { | |
78f43c53 PG |
1391 | if (memcmp(calc_ecc, erased_ecc_vec, |
1392 | actual_eccbytes) == 0) { | |
62116e51 | 1393 | /* |
78f43c53 PG |
1394 | * calc_ecc[] matches pattern for ECC(all 0xff) |
1395 | * so this is definitely an erased-page | |
62116e51 | 1396 | */ |
62116e51 | 1397 | } else { |
78f43c53 PG |
1398 | buf = &data[info->nand.ecc.size * i]; |
1399 | /* | |
1400 | * count number of 0-bits in read_buf. | |
1401 | * This check can be removed once a similar | |
1402 | * check is introduced in generic NAND driver | |
1403 | */ | |
1404 | bitflip_count = erased_sector_bitflips( | |
1405 | buf, read_ecc, info); | |
1406 | if (bitflip_count) { | |
1407 | /* | |
1408 | * number of 0-bits within ECC limits | |
1409 | * So this may be an erased-page | |
1410 | */ | |
1411 | stat += bitflip_count; | |
1412 | } else { | |
1413 | /* | |
1414 | * Too many 0-bits. It may be a | |
1415 | * - programmed-page, OR | |
1416 | * - erased-page with many bit-flips | |
1417 | * So this page requires check by ELM | |
1418 | */ | |
1419 | err_vec[i].error_reported = true; | |
1420 | is_error_reported = true; | |
62116e51 PA |
1421 | } |
1422 | } | |
1423 | } | |
1424 | ||
1425 | /* Update the ecc vector */ | |
de0a4d69 PG |
1426 | calc_ecc += ecc->bytes; |
1427 | read_ecc += ecc->bytes; | |
62116e51 PA |
1428 | } |
1429 | ||
1430 | /* Check if any error reported */ | |
1431 | if (!is_error_reported) | |
f306e8c3 | 1432 | return stat; |
62116e51 PA |
1433 | |
1434 | /* Decode BCH error using ELM module */ | |
1435 | elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); | |
1436 | ||
13fbe064 | 1437 | err = 0; |
62116e51 | 1438 | for (i = 0; i < eccsteps; i++) { |
13fbe064 | 1439 | if (err_vec[i].error_uncorrectable) { |
d2f08c75 EG |
1440 | dev_err(&info->pdev->dev, |
1441 | "uncorrectable bit-flips found\n"); | |
13fbe064 PG |
1442 | err = -EBADMSG; |
1443 | } else if (err_vec[i].error_reported) { | |
62116e51 | 1444 | for (j = 0; j < err_vec[i].error_count; j++) { |
b08e1f63 PG |
1445 | switch (info->ecc_opt) { |
1446 | case OMAP_ECC_BCH4_CODE_HW: | |
1447 | /* Add 4 bits to take care of padding */ | |
62116e51 PA |
1448 | pos = err_vec[i].error_loc[j] + |
1449 | BCH4_BIT_PAD; | |
b08e1f63 PG |
1450 | break; |
1451 | case OMAP_ECC_BCH8_CODE_HW: | |
9748fff9 | 1452 | case OMAP_ECC_BCH16_CODE_HW: |
b08e1f63 PG |
1453 | pos = err_vec[i].error_loc[j]; |
1454 | break; | |
1455 | default: | |
1456 | return -EINVAL; | |
1457 | } | |
1458 | error_max = (ecc->size + actual_eccbytes) * 8; | |
62116e51 PA |
1459 | /* Calculate bit position of error */ |
1460 | bit_pos = pos % 8; | |
1461 | ||
1462 | /* Calculate byte position of error */ | |
1463 | byte_pos = (error_max - pos - 1) / 8; | |
1464 | ||
1465 | if (pos < error_max) { | |
13fbe064 PG |
1466 | if (byte_pos < 512) { |
1467 | pr_debug("bitflip@dat[%d]=%x\n", | |
1468 | byte_pos, data[byte_pos]); | |
62116e51 | 1469 | data[byte_pos] ^= 1 << bit_pos; |
13fbe064 PG |
1470 | } else { |
1471 | pr_debug("bitflip@oob[%d]=%x\n", | |
1472 | (byte_pos - 512), | |
1473 | spare_ecc[byte_pos - 512]); | |
62116e51 PA |
1474 | spare_ecc[byte_pos - 512] ^= |
1475 | 1 << bit_pos; | |
13fbe064 PG |
1476 | } |
1477 | } else { | |
d2f08c75 EG |
1478 | dev_err(&info->pdev->dev, |
1479 | "invalid bit-flip @ %d:%d\n", | |
1480 | byte_pos, bit_pos); | |
13fbe064 | 1481 | err = -EBADMSG; |
62116e51 | 1482 | } |
62116e51 PA |
1483 | } |
1484 | } | |
1485 | ||
1486 | /* Update number of correctable errors */ | |
1487 | stat += err_vec[i].error_count; | |
1488 | ||
1489 | /* Update page data with sector size */ | |
b08e1f63 | 1490 | data += ecc->size; |
de0a4d69 | 1491 | spare_ecc += ecc->bytes; |
62116e51 PA |
1492 | } |
1493 | ||
13fbe064 | 1494 | return (err) ? err : stat; |
62116e51 PA |
1495 | } |
1496 | ||
62116e51 PA |
1497 | /** |
1498 | * omap_write_page_bch - BCH ecc based write page function for entire page | |
1499 | * @mtd: mtd info structure | |
1500 | * @chip: nand chip info structure | |
1501 | * @buf: data buffer | |
1502 | * @oob_required: must write chip->oob_poi to OOB | |
1503 | * | |
1504 | * Custom write page method evolved to support multi sector writing in one shot | |
1505 | */ | |
1506 | static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1507 | const uint8_t *buf, int oob_required) | |
1508 | { | |
1509 | int i; | |
1510 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1511 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1512 | ||
1513 | /* Enable GPMC ecc engine */ | |
1514 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1515 | ||
1516 | /* Write data */ | |
1517 | chip->write_buf(mtd, buf, mtd->writesize); | |
1518 | ||
1519 | /* Update ecc vector from GPMC result registers */ | |
1520 | chip->ecc.calculate(mtd, buf, &ecc_calc[0]); | |
1521 | ||
1522 | for (i = 0; i < chip->ecc.total; i++) | |
1523 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1524 | ||
1525 | /* Write ecc vector to OOB area */ | |
1526 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | /** | |
1531 | * omap_read_page_bch - BCH ecc based page read function for entire page | |
1532 | * @mtd: mtd info structure | |
1533 | * @chip: nand chip info structure | |
1534 | * @buf: buffer to store read data | |
1535 | * @oob_required: caller requires OOB data read to chip->oob_poi | |
1536 | * @page: page number to read | |
1537 | * | |
1538 | * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module | |
1539 | * used for error correction. | |
1540 | * Custom method evolved to support ELM error correction & multi sector | |
1541 | * reading. On reading page data area is read along with OOB data with | |
1542 | * ecc engine enabled. ecc vector updated after read of OOB data. | |
1543 | * For non error pages ecc vector reported as zero. | |
1544 | */ | |
1545 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1546 | uint8_t *buf, int oob_required, int page) | |
1547 | { | |
1548 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1549 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1550 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1551 | uint8_t *oob = &chip->oob_poi[eccpos[0]]; | |
1552 | uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0]; | |
1553 | int stat; | |
1554 | unsigned int max_bitflips = 0; | |
1555 | ||
1556 | /* Enable GPMC ecc engine */ | |
1557 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1558 | ||
1559 | /* Read data */ | |
1560 | chip->read_buf(mtd, buf, mtd->writesize); | |
1561 | ||
1562 | /* Read oob bytes */ | |
1563 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); | |
1564 | chip->read_buf(mtd, oob, chip->ecc.total); | |
1565 | ||
1566 | /* Calculate ecc bytes */ | |
1567 | chip->ecc.calculate(mtd, buf, ecc_calc); | |
1568 | ||
1569 | memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total); | |
1570 | ||
1571 | stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); | |
1572 | ||
1573 | if (stat < 0) { | |
1574 | mtd->ecc_stats.failed++; | |
1575 | } else { | |
1576 | mtd->ecc_stats.corrected += stat; | |
1577 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1578 | } | |
1579 | ||
1580 | return max_bitflips; | |
1581 | } | |
1582 | ||
0e618ef0 | 1583 | /** |
a919e511 PG |
1584 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1585 | * @omap_nand_info: NAND device structure containing platform data | |
0e618ef0 | 1586 | */ |
93af53b8 EG |
1587 | static bool is_elm_present(struct omap_nand_info *info, |
1588 | struct device_node *elm_node) | |
0e618ef0 | 1589 | { |
a919e511 | 1590 | struct platform_device *pdev; |
93af53b8 | 1591 | |
a919e511 PG |
1592 | /* check whether elm-id is passed via DT */ |
1593 | if (!elm_node) { | |
d2f08c75 | 1594 | dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); |
93af53b8 | 1595 | return false; |
a919e511 PG |
1596 | } |
1597 | pdev = of_find_device_by_node(elm_node); | |
1598 | /* check whether ELM device is registered */ | |
1599 | if (!pdev) { | |
d2f08c75 | 1600 | dev_err(&info->pdev->dev, "ELM device not found\n"); |
93af53b8 | 1601 | return false; |
0e618ef0 | 1602 | } |
a919e511 PG |
1603 | /* ELM module available, now configure it */ |
1604 | info->elm_dev = &pdev->dev; | |
93af53b8 EG |
1605 | return true; |
1606 | } | |
3f4eb14b | 1607 | |
93af53b8 EG |
1608 | static bool omap2_nand_ecc_check(struct omap_nand_info *info, |
1609 | struct omap_nand_platform_data *pdata) | |
1610 | { | |
1611 | bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm; | |
1612 | ||
1613 | switch (info->ecc_opt) { | |
1614 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
1615 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
1616 | ecc_needs_omap_bch = false; | |
1617 | ecc_needs_bch = true; | |
1618 | ecc_needs_elm = false; | |
1619 | break; | |
1620 | case OMAP_ECC_BCH4_CODE_HW: | |
1621 | case OMAP_ECC_BCH8_CODE_HW: | |
1622 | case OMAP_ECC_BCH16_CODE_HW: | |
1623 | ecc_needs_omap_bch = true; | |
1624 | ecc_needs_bch = false; | |
1625 | ecc_needs_elm = true; | |
1626 | break; | |
1627 | default: | |
1628 | ecc_needs_omap_bch = false; | |
1629 | ecc_needs_bch = false; | |
1630 | ecc_needs_elm = false; | |
1631 | break; | |
1632 | } | |
1633 | ||
1634 | if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) { | |
1635 | dev_err(&info->pdev->dev, | |
1636 | "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1637 | return false; | |
1638 | } | |
1639 | if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) { | |
1640 | dev_err(&info->pdev->dev, | |
1641 | "CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1642 | return false; | |
1643 | } | |
1644 | if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) { | |
1645 | dev_err(&info->pdev->dev, "ELM not available\n"); | |
1646 | return false; | |
1647 | } | |
1648 | ||
1649 | return true; | |
0e618ef0 ID |
1650 | } |
1651 | ||
06f25510 | 1652 | static int omap_nand_probe(struct platform_device *pdev) |
67ce04bf VS |
1653 | { |
1654 | struct omap_nand_info *info; | |
1655 | struct omap_nand_platform_data *pdata; | |
633deb58 PG |
1656 | struct mtd_info *mtd; |
1657 | struct nand_chip *nand_chip; | |
b491da72 | 1658 | struct nand_ecclayout *ecclayout; |
67ce04bf | 1659 | int err; |
b491da72 | 1660 | int i; |
633deb58 PG |
1661 | dma_cap_mask_t mask; |
1662 | unsigned sig; | |
eae39cb4 | 1663 | unsigned oob_index; |
9c4c2f8b | 1664 | struct resource *res; |
ccf04c51 | 1665 | struct mtd_part_parser_data ppdata = {}; |
67ce04bf | 1666 | |
453810b7 | 1667 | pdata = dev_get_platdata(&pdev->dev); |
67ce04bf VS |
1668 | if (pdata == NULL) { |
1669 | dev_err(&pdev->dev, "platform data missing\n"); | |
1670 | return -ENODEV; | |
1671 | } | |
1672 | ||
70ba6d71 PG |
1673 | info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), |
1674 | GFP_KERNEL); | |
67ce04bf VS |
1675 | if (!info) |
1676 | return -ENOMEM; | |
1677 | ||
1678 | platform_set_drvdata(pdev, info); | |
1679 | ||
633deb58 | 1680 | info->pdev = pdev; |
67ce04bf | 1681 | info->gpmc_cs = pdata->cs; |
65b97cf6 | 1682 | info->reg = pdata->reg; |
a919e511 | 1683 | info->of_node = pdata->of_node; |
4e558072 | 1684 | info->ecc_opt = pdata->ecc_opt; |
633deb58 PG |
1685 | mtd = &info->mtd; |
1686 | mtd->priv = &info->nand; | |
1687 | mtd->name = dev_name(&pdev->dev); | |
1688 | mtd->owner = THIS_MODULE; | |
1689 | nand_chip = &info->nand; | |
32d42a85 | 1690 | nand_chip->ecc.priv = NULL; |
67ce04bf | 1691 | |
9c4c2f8b | 1692 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
00d09891 JH |
1693 | nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); |
1694 | if (IS_ERR(nand_chip->IO_ADDR_R)) | |
1695 | return PTR_ERR(nand_chip->IO_ADDR_R); | |
67ce04bf | 1696 | |
9c4c2f8b | 1697 | info->phys_base = res->start; |
59e9c5ae | 1698 | |
1dc338e8 | 1699 | nand_chip->controller = &omap_gpmc_controller; |
67ce04bf | 1700 | |
633deb58 PG |
1701 | nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; |
1702 | nand_chip->cmd_ctrl = omap_hwcontrol; | |
67ce04bf | 1703 | |
67ce04bf VS |
1704 | /* |
1705 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1706 | * function and the generic nand_wait function which reads the status |
1707 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1708 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1709 | * device and read status register until you get a failure or success | |
1710 | */ | |
1711 | if (pdata->dev_ready) { | |
633deb58 PG |
1712 | nand_chip->dev_ready = omap_dev_ready; |
1713 | nand_chip->chip_delay = 0; | |
67ce04bf | 1714 | } else { |
633deb58 PG |
1715 | nand_chip->waitfunc = omap_wait; |
1716 | nand_chip->chip_delay = 50; | |
67ce04bf VS |
1717 | } |
1718 | ||
fef775ca EG |
1719 | if (pdata->flash_bbt) |
1720 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; | |
1721 | else | |
1722 | nand_chip->options |= NAND_SKIP_BBTSCAN; | |
1723 | ||
f18befb5 PG |
1724 | /* scan NAND device connected to chip controller */ |
1725 | nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16; | |
1726 | if (nand_scan_ident(mtd, 1, NULL)) { | |
d2f08c75 | 1727 | dev_err(&info->pdev->dev, "scan failed, may be bus-width mismatch\n"); |
f18befb5 | 1728 | err = -ENXIO; |
70ba6d71 | 1729 | goto return_error; |
f18befb5 PG |
1730 | } |
1731 | ||
1732 | /* re-populate low-level callbacks based on xfer modes */ | |
1b0b323c SG |
1733 | switch (pdata->xfer_type) { |
1734 | case NAND_OMAP_PREFETCH_POLLED: | |
633deb58 PG |
1735 | nand_chip->read_buf = omap_read_buf_pref; |
1736 | nand_chip->write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1737 | break; |
1738 | ||
1739 | case NAND_OMAP_POLLED: | |
cf0e4d2b | 1740 | /* Use nand_base defaults for {read,write}_buf */ |
1b0b323c SG |
1741 | break; |
1742 | ||
1743 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1744 | dma_cap_zero(mask); |
1745 | dma_cap_set(DMA_SLAVE, mask); | |
1746 | sig = OMAP24XX_DMA_GPMC; | |
1747 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); | |
1748 | if (!info->dma) { | |
2df41d05 RK |
1749 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
1750 | err = -ENXIO; | |
70ba6d71 | 1751 | goto return_error; |
763e7359 RK |
1752 | } else { |
1753 | struct dma_slave_config cfg; | |
763e7359 RK |
1754 | |
1755 | memset(&cfg, 0, sizeof(cfg)); | |
1756 | cfg.src_addr = info->phys_base; | |
1757 | cfg.dst_addr = info->phys_base; | |
1758 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1759 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1760 | cfg.src_maxburst = 16; | |
1761 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1762 | err = dmaengine_slave_config(info->dma, &cfg); |
1763 | if (err) { | |
763e7359 | 1764 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1765 | err); |
70ba6d71 | 1766 | goto return_error; |
763e7359 | 1767 | } |
633deb58 PG |
1768 | nand_chip->read_buf = omap_read_buf_dma_pref; |
1769 | nand_chip->write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1770 | } |
1771 | break; | |
1772 | ||
4e070376 | 1773 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1774 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1775 | if (info->gpmc_irq_fifo <= 0) { | |
1776 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1777 | err = -ENODEV; | |
70ba6d71 | 1778 | goto return_error; |
5c468455 | 1779 | } |
70ba6d71 PG |
1780 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo, |
1781 | omap_nand_irq, IRQF_SHARED, | |
1782 | "gpmc-nand-fifo", info); | |
4e070376 SG |
1783 | if (err) { |
1784 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1785 | info->gpmc_irq_fifo, err); |
1786 | info->gpmc_irq_fifo = 0; | |
70ba6d71 | 1787 | goto return_error; |
5c468455 AM |
1788 | } |
1789 | ||
1790 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1791 | if (info->gpmc_irq_count <= 0) { | |
1792 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1793 | err = -ENODEV; | |
70ba6d71 | 1794 | goto return_error; |
5c468455 | 1795 | } |
70ba6d71 PG |
1796 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_count, |
1797 | omap_nand_irq, IRQF_SHARED, | |
1798 | "gpmc-nand-count", info); | |
5c468455 AM |
1799 | if (err) { |
1800 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1801 | info->gpmc_irq_count, err); | |
1802 | info->gpmc_irq_count = 0; | |
70ba6d71 | 1803 | goto return_error; |
4e070376 | 1804 | } |
5c468455 | 1805 | |
633deb58 PG |
1806 | nand_chip->read_buf = omap_read_buf_irq_pref; |
1807 | nand_chip->write_buf = omap_write_buf_irq_pref; | |
5c468455 | 1808 | |
4e070376 SG |
1809 | break; |
1810 | ||
1b0b323c SG |
1811 | default: |
1812 | dev_err(&pdev->dev, | |
1813 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1814 | err = -EINVAL; | |
70ba6d71 | 1815 | goto return_error; |
59e9c5ae | 1816 | } |
59e9c5ae | 1817 | |
93af53b8 EG |
1818 | if (!omap2_nand_ecc_check(info, pdata)) { |
1819 | err = -EINVAL; | |
1820 | goto return_error; | |
1821 | } | |
1822 | ||
a919e511 | 1823 | /* populate MTD interface based on ECC scheme */ |
94cb4ee0 | 1824 | ecclayout = &info->oobinfo; |
4e558072 | 1825 | switch (info->ecc_opt) { |
7d5929c1 RQ |
1826 | case OMAP_ECC_HAM1_CODE_SW: |
1827 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
1828 | break; | |
1829 | ||
a919e511 PG |
1830 | case OMAP_ECC_HAM1_CODE_HW: |
1831 | pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); | |
1832 | nand_chip->ecc.mode = NAND_ECC_HW; | |
633deb58 PG |
1833 | nand_chip->ecc.bytes = 3; |
1834 | nand_chip->ecc.size = 512; | |
1835 | nand_chip->ecc.strength = 1; | |
1836 | nand_chip->ecc.calculate = omap_calculate_ecc; | |
1837 | nand_chip->ecc.hwctl = omap_enable_hwecc; | |
1838 | nand_chip->ecc.correct = omap_correct_data; | |
b491da72 PG |
1839 | /* define ECC layout */ |
1840 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1841 | (mtd->writesize / | |
1842 | nand_chip->ecc.size); | |
1843 | if (nand_chip->options & NAND_BUSWIDTH_16) | |
eae39cb4 | 1844 | oob_index = BADBLOCK_MARKER_LENGTH; |
b491da72 | 1845 | else |
eae39cb4 PG |
1846 | oob_index = 1; |
1847 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1848 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1849 | /* no reserved-marker in ecclayout for this ecc-scheme */ |
1850 | ecclayout->oobfree->offset = | |
1851 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 PG |
1852 | break; |
1853 | ||
1854 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
a919e511 PG |
1855 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); |
1856 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1857 | nand_chip->ecc.size = 512; | |
1858 | nand_chip->ecc.bytes = 7; | |
1859 | nand_chip->ecc.strength = 4; | |
7c977c3e | 1860 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 1861 | nand_chip->ecc.correct = nand_bch_correct_data; |
2c9f2365 | 1862 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
b491da72 PG |
1863 | /* define ECC layout */ |
1864 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1865 | (mtd->writesize / | |
1866 | nand_chip->ecc.size); | |
eae39cb4 PG |
1867 | oob_index = BADBLOCK_MARKER_LENGTH; |
1868 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { | |
1869 | ecclayout->eccpos[i] = oob_index; | |
1870 | if (((i + 1) % nand_chip->ecc.bytes) == 0) | |
1871 | oob_index++; | |
1872 | } | |
aa6092f9 PG |
1873 | /* include reserved-marker in ecclayout->oobfree calculation */ |
1874 | ecclayout->oobfree->offset = 1 + | |
1875 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1876 | /* software bch library is used for locating errors */ |
32d42a85 PG |
1877 | nand_chip->ecc.priv = nand_bch_init(mtd, |
1878 | nand_chip->ecc.size, | |
1879 | nand_chip->ecc.bytes, | |
7d5929c1 | 1880 | &ecclayout); |
32d42a85 | 1881 | if (!nand_chip->ecc.priv) { |
d2f08c75 | 1882 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
0e618ef0 | 1883 | err = -EINVAL; |
d2f08c75 | 1884 | goto return_error; |
a919e511 PG |
1885 | } |
1886 | break; | |
a919e511 PG |
1887 | |
1888 | case OMAP_ECC_BCH4_CODE_HW: | |
a919e511 PG |
1889 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); |
1890 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1891 | nand_chip->ecc.size = 512; | |
1892 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1893 | nand_chip->ecc.bytes = 7 + 1; | |
1894 | nand_chip->ecc.strength = 4; | |
7c977c3e | 1895 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 1896 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 1897 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
1898 | nand_chip->ecc.read_page = omap_read_page_bch; |
1899 | nand_chip->ecc.write_page = omap_write_page_bch; | |
b491da72 PG |
1900 | /* define ECC layout */ |
1901 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1902 | (mtd->writesize / | |
1903 | nand_chip->ecc.size); | |
eae39cb4 PG |
1904 | oob_index = BADBLOCK_MARKER_LENGTH; |
1905 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1906 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1907 | /* reserved marker already included in ecclayout->eccbytes */ |
1908 | ecclayout->oobfree->offset = | |
1909 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
93af53b8 EG |
1910 | |
1911 | err = elm_config(info->elm_dev, BCH4_ECC, | |
1912 | info->mtd.writesize / nand_chip->ecc.size, | |
1913 | nand_chip->ecc.size, nand_chip->ecc.bytes); | |
1914 | if (err < 0) | |
70ba6d71 | 1915 | goto return_error; |
a919e511 | 1916 | break; |
a919e511 PG |
1917 | |
1918 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
a919e511 PG |
1919 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); |
1920 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1921 | nand_chip->ecc.size = 512; | |
1922 | nand_chip->ecc.bytes = 13; | |
1923 | nand_chip->ecc.strength = 8; | |
7c977c3e | 1924 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 1925 | nand_chip->ecc.correct = nand_bch_correct_data; |
7bcd1dca | 1926 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
b491da72 PG |
1927 | /* define ECC layout */ |
1928 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1929 | (mtd->writesize / | |
1930 | nand_chip->ecc.size); | |
eae39cb4 PG |
1931 | oob_index = BADBLOCK_MARKER_LENGTH; |
1932 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) { | |
1933 | ecclayout->eccpos[i] = oob_index; | |
1934 | if (((i + 1) % nand_chip->ecc.bytes) == 0) | |
1935 | oob_index++; | |
1936 | } | |
aa6092f9 PG |
1937 | /* include reserved-marker in ecclayout->oobfree calculation */ |
1938 | ecclayout->oobfree->offset = 1 + | |
1939 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1940 | /* software bch library is used for locating errors */ |
32d42a85 PG |
1941 | nand_chip->ecc.priv = nand_bch_init(mtd, |
1942 | nand_chip->ecc.size, | |
1943 | nand_chip->ecc.bytes, | |
7d5929c1 | 1944 | &ecclayout); |
32d42a85 | 1945 | if (!nand_chip->ecc.priv) { |
d2f08c75 | 1946 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
a919e511 | 1947 | err = -EINVAL; |
70ba6d71 | 1948 | goto return_error; |
a919e511 PG |
1949 | } |
1950 | break; | |
a919e511 PG |
1951 | |
1952 | case OMAP_ECC_BCH8_CODE_HW: | |
a919e511 PG |
1953 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); |
1954 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1955 | nand_chip->ecc.size = 512; | |
1956 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
1957 | nand_chip->ecc.bytes = 13 + 1; | |
1958 | nand_chip->ecc.strength = 8; | |
7c977c3e | 1959 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 1960 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 1961 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
1962 | nand_chip->ecc.read_page = omap_read_page_bch; |
1963 | nand_chip->ecc.write_page = omap_write_page_bch; | |
93af53b8 EG |
1964 | |
1965 | err = elm_config(info->elm_dev, BCH8_ECC, | |
1966 | info->mtd.writesize / nand_chip->ecc.size, | |
1967 | nand_chip->ecc.size, nand_chip->ecc.bytes); | |
1968 | if (err < 0) | |
70ba6d71 | 1969 | goto return_error; |
93af53b8 | 1970 | |
b491da72 PG |
1971 | /* define ECC layout */ |
1972 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
1973 | (mtd->writesize / | |
1974 | nand_chip->ecc.size); | |
eae39cb4 PG |
1975 | oob_index = BADBLOCK_MARKER_LENGTH; |
1976 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
1977 | ecclayout->eccpos[i] = oob_index; | |
aa6092f9 PG |
1978 | /* reserved marker already included in ecclayout->eccbytes */ |
1979 | ecclayout->oobfree->offset = | |
1980 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
a919e511 | 1981 | break; |
a919e511 | 1982 | |
9748fff9 | 1983 | case OMAP_ECC_BCH16_CODE_HW: |
9748fff9 | 1984 | pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); |
1985 | nand_chip->ecc.mode = NAND_ECC_HW; | |
1986 | nand_chip->ecc.size = 512; | |
1987 | nand_chip->ecc.bytes = 26; | |
1988 | nand_chip->ecc.strength = 16; | |
1989 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; | |
1990 | nand_chip->ecc.correct = omap_elm_correct_data; | |
1991 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; | |
1992 | nand_chip->ecc.read_page = omap_read_page_bch; | |
1993 | nand_chip->ecc.write_page = omap_write_page_bch; | |
93af53b8 EG |
1994 | |
1995 | err = elm_config(info->elm_dev, BCH16_ECC, | |
1996 | info->mtd.writesize / nand_chip->ecc.size, | |
1997 | nand_chip->ecc.size, nand_chip->ecc.bytes); | |
1998 | if (err < 0) | |
9748fff9 | 1999 | goto return_error; |
93af53b8 | 2000 | |
9748fff9 | 2001 | /* define ECC layout */ |
2002 | ecclayout->eccbytes = nand_chip->ecc.bytes * | |
2003 | (mtd->writesize / | |
2004 | nand_chip->ecc.size); | |
2005 | oob_index = BADBLOCK_MARKER_LENGTH; | |
2006 | for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) | |
2007 | ecclayout->eccpos[i] = oob_index; | |
2008 | /* reserved marker already included in ecclayout->eccbytes */ | |
2009 | ecclayout->oobfree->offset = | |
2010 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | |
2011 | break; | |
a919e511 | 2012 | default: |
d2f08c75 | 2013 | dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n"); |
a919e511 | 2014 | err = -EINVAL; |
70ba6d71 | 2015 | goto return_error; |
f3d73f36 | 2016 | } |
67ce04bf | 2017 | |
7d5929c1 RQ |
2018 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) |
2019 | goto scan_tail; | |
2020 | ||
bb38eefb PG |
2021 | /* all OOB bytes from oobfree->offset till end off OOB are free */ |
2022 | ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; | |
b491da72 PG |
2023 | /* check if NAND device's OOB is enough to store ECC signatures */ |
2024 | if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) { | |
d2f08c75 EG |
2025 | dev_err(&info->pdev->dev, |
2026 | "not enough OOB bytes required = %d, available=%d\n", | |
2027 | ecclayout->eccbytes, mtd->oobsize); | |
b491da72 | 2028 | err = -EINVAL; |
70ba6d71 | 2029 | goto return_error; |
f040d332 | 2030 | } |
7d5929c1 | 2031 | nand_chip->ecc.layout = ecclayout; |
1b0b323c | 2032 | |
7d5929c1 | 2033 | scan_tail: |
a80f1c1f | 2034 | /* second phase scan */ |
633deb58 | 2035 | if (nand_scan_tail(mtd)) { |
a80f1c1f | 2036 | err = -ENXIO; |
70ba6d71 | 2037 | goto return_error; |
a80f1c1f JW |
2038 | } |
2039 | ||
ccf04c51 | 2040 | ppdata.of_node = pdata->of_node; |
633deb58 | 2041 | mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts, |
42d7fbe2 | 2042 | pdata->nr_parts); |
67ce04bf | 2043 | |
633deb58 | 2044 | platform_set_drvdata(pdev, mtd); |
67ce04bf VS |
2045 | |
2046 | return 0; | |
2047 | ||
70ba6d71 | 2048 | return_error: |
763e7359 RK |
2049 | if (info->dma) |
2050 | dma_release_channel(info->dma); | |
32d42a85 PG |
2051 | if (nand_chip->ecc.priv) { |
2052 | nand_bch_free(nand_chip->ecc.priv); | |
2053 | nand_chip->ecc.priv = NULL; | |
2054 | } | |
67ce04bf VS |
2055 | return err; |
2056 | } | |
2057 | ||
2058 | static int omap_nand_remove(struct platform_device *pdev) | |
2059 | { | |
2060 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
633deb58 | 2061 | struct nand_chip *nand_chip = mtd->priv; |
f35b6eda VS |
2062 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
2063 | mtd); | |
32d42a85 PG |
2064 | if (nand_chip->ecc.priv) { |
2065 | nand_bch_free(nand_chip->ecc.priv); | |
2066 | nand_chip->ecc.priv = NULL; | |
2067 | } | |
763e7359 RK |
2068 | if (info->dma) |
2069 | dma_release_channel(info->dma); | |
633deb58 | 2070 | nand_release(mtd); |
67ce04bf VS |
2071 | return 0; |
2072 | } | |
2073 | ||
2074 | static struct platform_driver omap_nand_driver = { | |
2075 | .probe = omap_nand_probe, | |
2076 | .remove = omap_nand_remove, | |
2077 | .driver = { | |
2078 | .name = DRIVER_NAME, | |
67ce04bf VS |
2079 | }, |
2080 | }; | |
2081 | ||
f99640de | 2082 | module_platform_driver(omap_nand_driver); |
67ce04bf | 2083 | |
c804c733 | 2084 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
2085 | MODULE_LICENSE("GPL"); |
2086 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |