Commit | Line | Data |
---|---|---|
ce4c61f1 TG |
1 | /* |
2 | * drivers/mtd/ndfc.c | |
3 | * | |
4 | * Overview: | |
a808ad3b | 5 | * Platform independent driver for NDFC (NanD Flash Controller) |
ce4c61f1 TG |
6 | * integrated into EP440 cores |
7 | * | |
a808ad3b SM |
8 | * Ported to an OF platform driver by Sean MacLennan |
9 | * | |
10 | * The NDFC supports multiple chips, but this driver only supports a | |
11 | * single chip since I do not have access to any boards with | |
12 | * multiple chips. | |
13 | * | |
ce4c61f1 TG |
14 | * Author: Thomas Gleixner |
15 | * | |
16 | * Copyright 2006 IBM | |
a808ad3b SM |
17 | * Copyright 2008 PIKA Technologies |
18 | * Sean MacLennan <smaclennan@pikatech.com> | |
ce4c61f1 TG |
19 | * |
20 | * This program is free software; you can redistribute it and/or modify it | |
21 | * under the terms of the GNU General Public License as published by the | |
22 | * Free Software Foundation; either version 2 of the License, or (at your | |
23 | * option) any later version. | |
24 | * | |
25 | */ | |
26 | #include <linux/module.h> | |
27 | #include <linux/mtd/nand.h> | |
28 | #include <linux/mtd/nand_ecc.h> | |
29 | #include <linux/mtd/partitions.h> | |
30 | #include <linux/mtd/ndfc.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ce4c61f1 | 32 | #include <linux/mtd/mtd.h> |
a808ad3b | 33 | #include <linux/of_platform.h> |
ce4c61f1 | 34 | #include <asm/io.h> |
ce4c61f1 | 35 | |
410fe2f0 | 36 | #define NDFC_MAX_CS 4 |
ce4c61f1 TG |
37 | |
38 | struct ndfc_controller { | |
2dc11581 | 39 | struct platform_device *ofdev; |
a808ad3b SM |
40 | void __iomem *ndfcbase; |
41 | struct mtd_info mtd; | |
42 | struct nand_chip chip; | |
43 | int chip_select; | |
44 | struct nand_hw_control ndfc_control; | |
ce4c61f1 TG |
45 | }; |
46 | ||
410fe2f0 | 47 | static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS]; |
ce4c61f1 TG |
48 | |
49 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) | |
50 | { | |
51 | uint32_t ccr; | |
410fe2f0 FR |
52 | struct nand_chip *nchip = mtd->priv; |
53 | struct ndfc_controller *ndfc = nchip->priv; | |
ce4c61f1 | 54 | |
a808ad3b | 55 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 TG |
56 | if (chip >= 0) { |
57 | ccr &= ~NDFC_CCR_BS_MASK; | |
a808ad3b | 58 | ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); |
ce4c61f1 TG |
59 | } else |
60 | ccr |= NDFC_CCR_RESET_CE; | |
a808ad3b | 61 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
62 | } |
63 | ||
7abd3ef9 | 64 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
ce4c61f1 | 65 | { |
410fe2f0 FR |
66 | struct nand_chip *chip = mtd->priv; |
67 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 68 | |
7abd3ef9 TG |
69 | if (cmd == NAND_CMD_NONE) |
70 | return; | |
71 | ||
72 | if (ctrl & NAND_CLE) | |
1794c130 | 73 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); |
7abd3ef9 | 74 | else |
1794c130 | 75 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); |
ce4c61f1 TG |
76 | } |
77 | ||
78 | static int ndfc_ready(struct mtd_info *mtd) | |
79 | { | |
410fe2f0 FR |
80 | struct nand_chip *chip = mtd->priv; |
81 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 82 | |
a808ad3b | 83 | return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; |
ce4c61f1 TG |
84 | } |
85 | ||
86 | static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode) | |
87 | { | |
88 | uint32_t ccr; | |
410fe2f0 FR |
89 | struct nand_chip *chip = mtd->priv; |
90 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 | 91 | |
a808ad3b | 92 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 | 93 | ccr |= NDFC_CCR_RESET_ECC; |
a808ad3b | 94 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
95 | wmb(); |
96 | } | |
97 | ||
98 | static int ndfc_calculate_ecc(struct mtd_info *mtd, | |
99 | const u_char *dat, u_char *ecc_code) | |
100 | { | |
410fe2f0 FR |
101 | struct nand_chip *chip = mtd->priv; |
102 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
103 | uint32_t ecc; |
104 | uint8_t *p = (uint8_t *)&ecc; | |
105 | ||
106 | wmb(); | |
a808ad3b SM |
107 | ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); |
108 | /* The NDFC uses Smart Media (SMC) bytes order */ | |
76c23c32 FK |
109 | ecc_code[0] = p[1]; |
110 | ecc_code[1] = p[2]; | |
ce4c61f1 TG |
111 | ecc_code[2] = p[3]; |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | /* | |
117 | * Speedups for buffer read/write/verify | |
118 | * | |
119 | * NDFC allows 32bit read/write of data. So we can speed up the buffer | |
120 | * functions. No further checking, as nand_base will always read/write | |
121 | * page aligned. | |
122 | */ | |
123 | static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
124 | { | |
410fe2f0 FR |
125 | struct nand_chip *chip = mtd->priv; |
126 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
127 | uint32_t *p = (uint32_t *) buf; |
128 | ||
129 | for(;len > 0; len -= 4) | |
a808ad3b | 130 | *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); |
ce4c61f1 TG |
131 | } |
132 | ||
133 | static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
134 | { | |
410fe2f0 FR |
135 | struct nand_chip *chip = mtd->priv; |
136 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
137 | uint32_t *p = (uint32_t *) buf; |
138 | ||
139 | for(;len > 0; len -= 4) | |
a808ad3b | 140 | out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); |
ce4c61f1 TG |
141 | } |
142 | ||
143 | static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
144 | { | |
410fe2f0 FR |
145 | struct nand_chip *chip = mtd->priv; |
146 | struct ndfc_controller *ndfc = chip->priv; | |
ce4c61f1 TG |
147 | uint32_t *p = (uint32_t *) buf; |
148 | ||
149 | for(;len > 0; len -= 4) | |
a808ad3b | 150 | if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA)) |
ce4c61f1 TG |
151 | return -EFAULT; |
152 | return 0; | |
153 | } | |
154 | ||
155 | /* | |
156 | * Initialize chip structure | |
157 | */ | |
a808ad3b SM |
158 | static int ndfc_chip_init(struct ndfc_controller *ndfc, |
159 | struct device_node *node) | |
ce4c61f1 | 160 | { |
a808ad3b SM |
161 | struct device_node *flash_np; |
162 | struct nand_chip *chip = &ndfc->chip; | |
9d7948c5 | 163 | struct mtd_part_parser_data ppdata; |
a808ad3b | 164 | int ret; |
ce4c61f1 TG |
165 | |
166 | chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; | |
167 | chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; | |
7abd3ef9 | 168 | chip->cmd_ctrl = ndfc_hwcontrol; |
ce4c61f1 TG |
169 | chip->dev_ready = ndfc_ready; |
170 | chip->select_chip = ndfc_select_chip; | |
171 | chip->chip_delay = 50; | |
ce4c61f1 TG |
172 | chip->controller = &ndfc->ndfc_control; |
173 | chip->read_buf = ndfc_read_buf; | |
174 | chip->write_buf = ndfc_write_buf; | |
175 | chip->verify_buf = ndfc_verify_buf; | |
6dfc6d25 TG |
176 | chip->ecc.correct = nand_correct_data; |
177 | chip->ecc.hwctl = ndfc_enable_hwecc; | |
178 | chip->ecc.calculate = ndfc_calculate_ecc; | |
179 | chip->ecc.mode = NAND_ECC_HW; | |
180 | chip->ecc.size = 256; | |
181 | chip->ecc.bytes = 3; | |
6a918bad | 182 | chip->ecc.strength = 1; |
410fe2f0 | 183 | chip->priv = ndfc; |
ce4c61f1 | 184 | |
a808ad3b SM |
185 | ndfc->mtd.priv = chip; |
186 | ndfc->mtd.owner = THIS_MODULE; | |
ce4c61f1 | 187 | |
a808ad3b SM |
188 | flash_np = of_get_next_child(node, NULL); |
189 | if (!flash_np) | |
ce4c61f1 | 190 | return -ENODEV; |
a808ad3b | 191 | |
629be5f2 | 192 | ppdata.of_node = flash_np; |
a808ad3b | 193 | ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s", |
c36f1e33 | 194 | dev_name(&ndfc->ofdev->dev), flash_np->name); |
a808ad3b SM |
195 | if (!ndfc->mtd.name) { |
196 | ret = -ENOMEM; | |
197 | goto err; | |
ce4c61f1 TG |
198 | } |
199 | ||
a808ad3b SM |
200 | ret = nand_scan(&ndfc->mtd, 1); |
201 | if (ret) | |
202 | goto err; | |
ce4c61f1 | 203 | |
a9106497 | 204 | ret = mtd_device_parse_register(&ndfc->mtd, NULL, &ppdata, NULL, 0); |
ce4c61f1 | 205 | |
a808ad3b SM |
206 | err: |
207 | of_node_put(flash_np); | |
208 | if (ret) | |
209 | kfree(ndfc->mtd.name); | |
210 | return ret; | |
ce4c61f1 TG |
211 | } |
212 | ||
1c48a5c9 | 213 | static int __devinit ndfc_probe(struct platform_device *ofdev) |
ce4c61f1 | 214 | { |
410fe2f0 | 215 | struct ndfc_controller *ndfc; |
766f271a | 216 | const __be32 *reg; |
a808ad3b | 217 | u32 ccr; |
410fe2f0 | 218 | int err, len, cs; |
a808ad3b SM |
219 | |
220 | /* Read the reg property to get the chip select */ | |
61c7a080 | 221 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
a808ad3b SM |
222 | if (reg == NULL || len != 12) { |
223 | dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); | |
224 | return -ENOENT; | |
225 | } | |
410fe2f0 FR |
226 | |
227 | cs = be32_to_cpu(reg[0]); | |
228 | if (cs >= NDFC_MAX_CS) { | |
229 | dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); | |
230 | return -EINVAL; | |
231 | } | |
232 | ||
233 | ndfc = &ndfc_ctrl[cs]; | |
234 | ndfc->chip_select = cs; | |
235 | ||
236 | spin_lock_init(&ndfc->ndfc_control.lock); | |
237 | init_waitqueue_head(&ndfc->ndfc_control.wq); | |
238 | ndfc->ofdev = ofdev; | |
239 | dev_set_drvdata(&ofdev->dev, ndfc); | |
a808ad3b | 240 | |
61c7a080 | 241 | ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); |
ce4c61f1 | 242 | if (!ndfc->ndfcbase) { |
a808ad3b | 243 | dev_err(&ofdev->dev, "failed to get memory\n"); |
ce4c61f1 TG |
244 | return -EIO; |
245 | } | |
246 | ||
a808ad3b | 247 | ccr = NDFC_CCR_BS(ndfc->chip_select); |
ce4c61f1 | 248 | |
a808ad3b | 249 | /* It is ok if ccr does not exist - just default to 0 */ |
61c7a080 | 250 | reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); |
a808ad3b | 251 | if (reg) |
766f271a | 252 | ccr |= be32_to_cpup(reg); |
ce4c61f1 | 253 | |
a808ad3b | 254 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 | 255 | |
a808ad3b | 256 | /* Set the bank settings if given */ |
61c7a080 | 257 | reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); |
a808ad3b SM |
258 | if (reg) { |
259 | int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); | |
766f271a | 260 | out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); |
a808ad3b SM |
261 | } |
262 | ||
61c7a080 | 263 | err = ndfc_chip_init(ndfc, ofdev->dev.of_node); |
a808ad3b SM |
264 | if (err) { |
265 | iounmap(ndfc->ndfcbase); | |
266 | return err; | |
267 | } | |
ce4c61f1 TG |
268 | |
269 | return 0; | |
270 | } | |
271 | ||
2dc11581 | 272 | static int __devexit ndfc_remove(struct platform_device *ofdev) |
ce4c61f1 | 273 | { |
a808ad3b | 274 | struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); |
ce4c61f1 | 275 | |
a808ad3b | 276 | nand_release(&ndfc->mtd); |
96166056 | 277 | kfree(ndfc->mtd.name); |
ce4c61f1 | 278 | |
ce4c61f1 TG |
279 | return 0; |
280 | } | |
281 | ||
a808ad3b SM |
282 | static const struct of_device_id ndfc_match[] = { |
283 | { .compatible = "ibm,ndfc", }, | |
284 | {} | |
ce4c61f1 | 285 | }; |
a808ad3b | 286 | MODULE_DEVICE_TABLE(of, ndfc_match); |
ce4c61f1 | 287 | |
1c48a5c9 | 288 | static struct platform_driver ndfc_driver = { |
a808ad3b | 289 | .driver = { |
4018294b GL |
290 | .name = "ndfc", |
291 | .owner = THIS_MODULE, | |
292 | .of_match_table = ndfc_match, | |
ce4c61f1 | 293 | }, |
a808ad3b SM |
294 | .probe = ndfc_probe, |
295 | .remove = __devexit_p(ndfc_remove), | |
ce4c61f1 TG |
296 | }; |
297 | ||
f99640de | 298 | module_platform_driver(ndfc_driver); |
ce4c61f1 TG |
299 | |
300 | MODULE_LICENSE("GPL"); | |
301 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
a808ad3b | 302 | MODULE_DESCRIPTION("OF Platform driver for NDFC"); |