Commit | Line | Data |
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ce4c61f1 TG |
1 | /* |
2 | * drivers/mtd/ndfc.c | |
3 | * | |
4 | * Overview: | |
a808ad3b | 5 | * Platform independent driver for NDFC (NanD Flash Controller) |
ce4c61f1 TG |
6 | * integrated into EP440 cores |
7 | * | |
a808ad3b SM |
8 | * Ported to an OF platform driver by Sean MacLennan |
9 | * | |
10 | * The NDFC supports multiple chips, but this driver only supports a | |
11 | * single chip since I do not have access to any boards with | |
12 | * multiple chips. | |
13 | * | |
ce4c61f1 TG |
14 | * Author: Thomas Gleixner |
15 | * | |
16 | * Copyright 2006 IBM | |
a808ad3b SM |
17 | * Copyright 2008 PIKA Technologies |
18 | * Sean MacLennan <smaclennan@pikatech.com> | |
ce4c61f1 TG |
19 | * |
20 | * This program is free software; you can redistribute it and/or modify it | |
21 | * under the terms of the GNU General Public License as published by the | |
22 | * Free Software Foundation; either version 2 of the License, or (at your | |
23 | * option) any later version. | |
24 | * | |
25 | */ | |
26 | #include <linux/module.h> | |
27 | #include <linux/mtd/nand.h> | |
28 | #include <linux/mtd/nand_ecc.h> | |
29 | #include <linux/mtd/partitions.h> | |
30 | #include <linux/mtd/ndfc.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
ce4c61f1 | 32 | #include <linux/mtd/mtd.h> |
a808ad3b | 33 | #include <linux/of_platform.h> |
ce4c61f1 | 34 | #include <asm/io.h> |
ce4c61f1 | 35 | |
ce4c61f1 TG |
36 | |
37 | struct ndfc_controller { | |
a808ad3b SM |
38 | struct of_device *ofdev; |
39 | void __iomem *ndfcbase; | |
40 | struct mtd_info mtd; | |
41 | struct nand_chip chip; | |
42 | int chip_select; | |
43 | struct nand_hw_control ndfc_control; | |
44 | #ifdef CONFIG_MTD_PARTITIONS | |
45 | struct mtd_partition *parts; | |
46 | #endif | |
ce4c61f1 TG |
47 | }; |
48 | ||
49 | static struct ndfc_controller ndfc_ctrl; | |
50 | ||
51 | static void ndfc_select_chip(struct mtd_info *mtd, int chip) | |
52 | { | |
53 | uint32_t ccr; | |
54 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
ce4c61f1 | 55 | |
a808ad3b | 56 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 TG |
57 | if (chip >= 0) { |
58 | ccr &= ~NDFC_CCR_BS_MASK; | |
a808ad3b | 59 | ccr |= NDFC_CCR_BS(chip + ndfc->chip_select); |
ce4c61f1 TG |
60 | } else |
61 | ccr |= NDFC_CCR_RESET_CE; | |
a808ad3b | 62 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
63 | } |
64 | ||
7abd3ef9 | 65 | static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
ce4c61f1 | 66 | { |
1794c130 | 67 | struct ndfc_controller *ndfc = &ndfc_ctrl; |
ce4c61f1 | 68 | |
7abd3ef9 TG |
69 | if (cmd == NAND_CMD_NONE) |
70 | return; | |
71 | ||
72 | if (ctrl & NAND_CLE) | |
1794c130 | 73 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD); |
7abd3ef9 | 74 | else |
1794c130 | 75 | writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE); |
ce4c61f1 TG |
76 | } |
77 | ||
78 | static int ndfc_ready(struct mtd_info *mtd) | |
79 | { | |
80 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
81 | ||
a808ad3b | 82 | return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY; |
ce4c61f1 TG |
83 | } |
84 | ||
85 | static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode) | |
86 | { | |
87 | uint32_t ccr; | |
88 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
89 | ||
a808ad3b | 90 | ccr = in_be32(ndfc->ndfcbase + NDFC_CCR); |
ce4c61f1 | 91 | ccr |= NDFC_CCR_RESET_ECC; |
a808ad3b | 92 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 TG |
93 | wmb(); |
94 | } | |
95 | ||
96 | static int ndfc_calculate_ecc(struct mtd_info *mtd, | |
97 | const u_char *dat, u_char *ecc_code) | |
98 | { | |
99 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
100 | uint32_t ecc; | |
101 | uint8_t *p = (uint8_t *)&ecc; | |
102 | ||
103 | wmb(); | |
a808ad3b SM |
104 | ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); |
105 | /* The NDFC uses Smart Media (SMC) bytes order */ | |
76c23c32 FK |
106 | ecc_code[0] = p[1]; |
107 | ecc_code[1] = p[2]; | |
ce4c61f1 TG |
108 | ecc_code[2] = p[3]; |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | /* | |
114 | * Speedups for buffer read/write/verify | |
115 | * | |
116 | * NDFC allows 32bit read/write of data. So we can speed up the buffer | |
117 | * functions. No further checking, as nand_base will always read/write | |
118 | * page aligned. | |
119 | */ | |
120 | static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
121 | { | |
122 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
123 | uint32_t *p = (uint32_t *) buf; | |
124 | ||
125 | for(;len > 0; len -= 4) | |
a808ad3b | 126 | *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA); |
ce4c61f1 TG |
127 | } |
128 | ||
129 | static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
130 | { | |
131 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
132 | uint32_t *p = (uint32_t *) buf; | |
133 | ||
134 | for(;len > 0; len -= 4) | |
a808ad3b | 135 | out_be32(ndfc->ndfcbase + NDFC_DATA, *p++); |
ce4c61f1 TG |
136 | } |
137 | ||
138 | static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
139 | { | |
140 | struct ndfc_controller *ndfc = &ndfc_ctrl; | |
141 | uint32_t *p = (uint32_t *) buf; | |
142 | ||
143 | for(;len > 0; len -= 4) | |
a808ad3b | 144 | if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA)) |
ce4c61f1 TG |
145 | return -EFAULT; |
146 | return 0; | |
147 | } | |
148 | ||
149 | /* | |
150 | * Initialize chip structure | |
151 | */ | |
a808ad3b SM |
152 | static int ndfc_chip_init(struct ndfc_controller *ndfc, |
153 | struct device_node *node) | |
ce4c61f1 | 154 | { |
a808ad3b SM |
155 | #ifdef CONFIG_MTD_PARTITIONS |
156 | #ifdef CONFIG_MTD_CMDLINE_PARTS | |
157 | static const char *part_types[] = { "cmdlinepart", NULL }; | |
158 | #else | |
159 | static const char *part_types[] = { NULL }; | |
160 | #endif | |
161 | #endif | |
162 | struct device_node *flash_np; | |
163 | struct nand_chip *chip = &ndfc->chip; | |
164 | int ret; | |
ce4c61f1 TG |
165 | |
166 | chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; | |
167 | chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; | |
7abd3ef9 | 168 | chip->cmd_ctrl = ndfc_hwcontrol; |
ce4c61f1 TG |
169 | chip->dev_ready = ndfc_ready; |
170 | chip->select_chip = ndfc_select_chip; | |
171 | chip->chip_delay = 50; | |
ce4c61f1 TG |
172 | chip->controller = &ndfc->ndfc_control; |
173 | chip->read_buf = ndfc_read_buf; | |
174 | chip->write_buf = ndfc_write_buf; | |
175 | chip->verify_buf = ndfc_verify_buf; | |
6dfc6d25 TG |
176 | chip->ecc.correct = nand_correct_data; |
177 | chip->ecc.hwctl = ndfc_enable_hwecc; | |
178 | chip->ecc.calculate = ndfc_calculate_ecc; | |
179 | chip->ecc.mode = NAND_ECC_HW; | |
180 | chip->ecc.size = 256; | |
181 | chip->ecc.bytes = 3; | |
ce4c61f1 | 182 | |
a808ad3b SM |
183 | ndfc->mtd.priv = chip; |
184 | ndfc->mtd.owner = THIS_MODULE; | |
ce4c61f1 | 185 | |
a808ad3b SM |
186 | flash_np = of_get_next_child(node, NULL); |
187 | if (!flash_np) | |
ce4c61f1 | 188 | return -ENODEV; |
a808ad3b SM |
189 | |
190 | ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s", | |
c36f1e33 | 191 | dev_name(&ndfc->ofdev->dev), flash_np->name); |
a808ad3b SM |
192 | if (!ndfc->mtd.name) { |
193 | ret = -ENOMEM; | |
194 | goto err; | |
ce4c61f1 TG |
195 | } |
196 | ||
a808ad3b SM |
197 | ret = nand_scan(&ndfc->mtd, 1); |
198 | if (ret) | |
199 | goto err; | |
ce4c61f1 | 200 | |
a808ad3b SM |
201 | #ifdef CONFIG_MTD_PARTITIONS |
202 | ret = parse_mtd_partitions(&ndfc->mtd, part_types, &ndfc->parts, 0); | |
203 | if (ret < 0) | |
204 | goto err; | |
205 | ||
206 | #ifdef CONFIG_MTD_OF_PARTS | |
207 | if (ret == 0) { | |
208 | ret = of_mtd_parse_partitions(&ndfc->ofdev->dev, flash_np, | |
209 | &ndfc->parts); | |
210 | if (ret < 0) | |
211 | goto err; | |
212 | } | |
ce4c61f1 TG |
213 | #endif |
214 | ||
a808ad3b SM |
215 | if (ret > 0) |
216 | ret = add_mtd_partitions(&ndfc->mtd, ndfc->parts, ret); | |
217 | else | |
218 | #endif | |
219 | ret = add_mtd_device(&ndfc->mtd); | |
ce4c61f1 | 220 | |
a808ad3b SM |
221 | err: |
222 | of_node_put(flash_np); | |
223 | if (ret) | |
224 | kfree(ndfc->mtd.name); | |
225 | return ret; | |
ce4c61f1 TG |
226 | } |
227 | ||
a808ad3b SM |
228 | static int __devinit ndfc_probe(struct of_device *ofdev, |
229 | const struct of_device_id *match) | |
ce4c61f1 | 230 | { |
ce4c61f1 | 231 | struct ndfc_controller *ndfc = &ndfc_ctrl; |
a808ad3b SM |
232 | const u32 *reg; |
233 | u32 ccr; | |
234 | int err, len; | |
ce4c61f1 | 235 | |
a808ad3b SM |
236 | spin_lock_init(&ndfc->ndfc_control.lock); |
237 | init_waitqueue_head(&ndfc->ndfc_control.wq); | |
238 | ndfc->ofdev = ofdev; | |
239 | dev_set_drvdata(&ofdev->dev, ndfc); | |
240 | ||
241 | /* Read the reg property to get the chip select */ | |
61c7a080 | 242 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
a808ad3b SM |
243 | if (reg == NULL || len != 12) { |
244 | dev_err(&ofdev->dev, "unable read reg property (%d)\n", len); | |
245 | return -ENOENT; | |
246 | } | |
247 | ndfc->chip_select = reg[0]; | |
248 | ||
61c7a080 | 249 | ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0); |
ce4c61f1 | 250 | if (!ndfc->ndfcbase) { |
a808ad3b | 251 | dev_err(&ofdev->dev, "failed to get memory\n"); |
ce4c61f1 TG |
252 | return -EIO; |
253 | } | |
254 | ||
a808ad3b | 255 | ccr = NDFC_CCR_BS(ndfc->chip_select); |
ce4c61f1 | 256 | |
a808ad3b | 257 | /* It is ok if ccr does not exist - just default to 0 */ |
61c7a080 | 258 | reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); |
a808ad3b SM |
259 | if (reg) |
260 | ccr |= *reg; | |
ce4c61f1 | 261 | |
a808ad3b | 262 | out_be32(ndfc->ndfcbase + NDFC_CCR, ccr); |
ce4c61f1 | 263 | |
a808ad3b | 264 | /* Set the bank settings if given */ |
61c7a080 | 265 | reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); |
a808ad3b SM |
266 | if (reg) { |
267 | int offset = NDFC_BCFG0 + (ndfc->chip_select << 2); | |
268 | out_be32(ndfc->ndfcbase + offset, *reg); | |
269 | } | |
270 | ||
61c7a080 | 271 | err = ndfc_chip_init(ndfc, ofdev->dev.of_node); |
a808ad3b SM |
272 | if (err) { |
273 | iounmap(ndfc->ndfcbase); | |
274 | return err; | |
275 | } | |
ce4c61f1 TG |
276 | |
277 | return 0; | |
278 | } | |
279 | ||
a808ad3b | 280 | static int __devexit ndfc_remove(struct of_device *ofdev) |
ce4c61f1 | 281 | { |
a808ad3b | 282 | struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev); |
ce4c61f1 | 283 | |
a808ad3b | 284 | nand_release(&ndfc->mtd); |
ce4c61f1 | 285 | |
ce4c61f1 TG |
286 | return 0; |
287 | } | |
288 | ||
a808ad3b SM |
289 | static const struct of_device_id ndfc_match[] = { |
290 | { .compatible = "ibm,ndfc", }, | |
291 | {} | |
ce4c61f1 | 292 | }; |
a808ad3b | 293 | MODULE_DEVICE_TABLE(of, ndfc_match); |
ce4c61f1 | 294 | |
a808ad3b SM |
295 | static struct of_platform_driver ndfc_driver = { |
296 | .driver = { | |
4018294b GL |
297 | .name = "ndfc", |
298 | .owner = THIS_MODULE, | |
299 | .of_match_table = ndfc_match, | |
ce4c61f1 | 300 | }, |
a808ad3b SM |
301 | .probe = ndfc_probe, |
302 | .remove = __devexit_p(ndfc_remove), | |
ce4c61f1 TG |
303 | }; |
304 | ||
305 | static int __init ndfc_nand_init(void) | |
306 | { | |
a808ad3b | 307 | return of_register_platform_driver(&ndfc_driver); |
ce4c61f1 TG |
308 | } |
309 | ||
310 | static void __exit ndfc_nand_exit(void) | |
311 | { | |
a808ad3b | 312 | of_unregister_platform_driver(&ndfc_driver); |
ce4c61f1 TG |
313 | } |
314 | ||
315 | module_init(ndfc_nand_init); | |
316 | module_exit(ndfc_nand_exit); | |
317 | ||
318 | MODULE_LICENSE("GPL"); | |
319 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
a808ad3b | 320 | MODULE_DESCRIPTION("OF Platform driver for NDFC"); |