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1da177e4 LT |
1 | /* |
2 | * NAND flash simulator. | |
3 | * | |
4 | * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org> | |
5 | * | |
61b03bd7 | 6 | * Copyright (C) 2004 Nokia Corporation |
1da177e4 LT |
7 | * |
8 | * Note: NS means "NAND Simulator". | |
9 | * Note: Input means input TO flash chip, output means output FROM chip. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2, or (at your option) any later | |
14 | * version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General | |
19 | * Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA | |
24 | * | |
51502287 | 25 | * $Id: nandsim.c,v 1.8 2005/03/19 15:33:56 dedekind Exp $ |
1da177e4 LT |
26 | */ |
27 | ||
1da177e4 LT |
28 | #include <linux/init.h> |
29 | #include <linux/types.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/moduleparam.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/errno.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/mtd/mtd.h> | |
37 | #include <linux/mtd/nand.h> | |
38 | #include <linux/mtd/partitions.h> | |
39 | #include <linux/delay.h> | |
1da177e4 LT |
40 | |
41 | /* Default simulator parameters values */ | |
42 | #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \ | |
43 | !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \ | |
44 | !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \ | |
45 | !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE) | |
46 | #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98 | |
47 | #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39 | |
48 | #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */ | |
49 | #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */ | |
50 | #endif | |
51 | ||
52 | #ifndef CONFIG_NANDSIM_ACCESS_DELAY | |
53 | #define CONFIG_NANDSIM_ACCESS_DELAY 25 | |
54 | #endif | |
55 | #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY | |
56 | #define CONFIG_NANDSIM_PROGRAMM_DELAY 200 | |
57 | #endif | |
58 | #ifndef CONFIG_NANDSIM_ERASE_DELAY | |
59 | #define CONFIG_NANDSIM_ERASE_DELAY 2 | |
60 | #endif | |
61 | #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE | |
62 | #define CONFIG_NANDSIM_OUTPUT_CYCLE 40 | |
63 | #endif | |
64 | #ifndef CONFIG_NANDSIM_INPUT_CYCLE | |
65 | #define CONFIG_NANDSIM_INPUT_CYCLE 50 | |
66 | #endif | |
67 | #ifndef CONFIG_NANDSIM_BUS_WIDTH | |
68 | #define CONFIG_NANDSIM_BUS_WIDTH 8 | |
69 | #endif | |
70 | #ifndef CONFIG_NANDSIM_DO_DELAYS | |
71 | #define CONFIG_NANDSIM_DO_DELAYS 0 | |
72 | #endif | |
73 | #ifndef CONFIG_NANDSIM_LOG | |
74 | #define CONFIG_NANDSIM_LOG 0 | |
75 | #endif | |
76 | #ifndef CONFIG_NANDSIM_DBG | |
77 | #define CONFIG_NANDSIM_DBG 0 | |
78 | #endif | |
79 | ||
80 | static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE; | |
81 | static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE; | |
82 | static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE; | |
83 | static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE; | |
84 | static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY; | |
85 | static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY; | |
86 | static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY; | |
87 | static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE; | |
88 | static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE; | |
89 | static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH; | |
90 | static uint do_delays = CONFIG_NANDSIM_DO_DELAYS; | |
91 | static uint log = CONFIG_NANDSIM_LOG; | |
92 | static uint dbg = CONFIG_NANDSIM_DBG; | |
93 | ||
94 | module_param(first_id_byte, uint, 0400); | |
95 | module_param(second_id_byte, uint, 0400); | |
96 | module_param(third_id_byte, uint, 0400); | |
97 | module_param(fourth_id_byte, uint, 0400); | |
98 | module_param(access_delay, uint, 0400); | |
99 | module_param(programm_delay, uint, 0400); | |
100 | module_param(erase_delay, uint, 0400); | |
101 | module_param(output_cycle, uint, 0400); | |
102 | module_param(input_cycle, uint, 0400); | |
103 | module_param(bus_width, uint, 0400); | |
104 | module_param(do_delays, uint, 0400); | |
105 | module_param(log, uint, 0400); | |
106 | module_param(dbg, uint, 0400); | |
107 | ||
108 | MODULE_PARM_DESC(first_id_byte, "The fist byte returned by NAND Flash 'read ID' command (manufaturer ID)"); | |
109 | MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)"); | |
110 | MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command"); | |
111 | MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command"); | |
112 | MODULE_PARM_DESC(access_delay, "Initial page access delay (microiseconds)"); | |
113 | MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds"); | |
114 | MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)"); | |
115 | MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanodeconds)"); | |
116 | MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanodeconds)"); | |
117 | MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)"); | |
118 | MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero"); | |
119 | MODULE_PARM_DESC(log, "Perform logging if not zero"); | |
120 | MODULE_PARM_DESC(dbg, "Output debug information if not zero"); | |
121 | ||
122 | /* The largest possible page size */ | |
123 | #define NS_LARGEST_PAGE_SIZE 2048 | |
61b03bd7 | 124 | |
1da177e4 LT |
125 | /* The prefix for simulator output */ |
126 | #define NS_OUTPUT_PREFIX "[nandsim]" | |
127 | ||
128 | /* Simulator's output macros (logging, debugging, warning, error) */ | |
129 | #define NS_LOG(args...) \ | |
130 | do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0) | |
131 | #define NS_DBG(args...) \ | |
132 | do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0) | |
133 | #define NS_WARN(args...) \ | |
134 | do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warnig: " args); } while(0) | |
135 | #define NS_ERR(args...) \ | |
136 | do { printk(KERN_ERR NS_OUTPUT_PREFIX " errorr: " args); } while(0) | |
137 | ||
138 | /* Busy-wait delay macros (microseconds, milliseconds) */ | |
139 | #define NS_UDELAY(us) \ | |
140 | do { if (do_delays) udelay(us); } while(0) | |
141 | #define NS_MDELAY(us) \ | |
142 | do { if (do_delays) mdelay(us); } while(0) | |
61b03bd7 | 143 | |
1da177e4 LT |
144 | /* Is the nandsim structure initialized ? */ |
145 | #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0) | |
146 | ||
147 | /* Good operation completion status */ | |
148 | #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0))) | |
149 | ||
150 | /* Operation failed completion status */ | |
61b03bd7 | 151 | #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns)) |
1da177e4 LT |
152 | |
153 | /* Calculate the page offset in flash RAM image by (row, column) address */ | |
154 | #define NS_RAW_OFFSET(ns) \ | |
155 | (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column) | |
61b03bd7 | 156 | |
1da177e4 LT |
157 | /* Calculate the OOB offset in flash RAM image by (row, column) address */ |
158 | #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz) | |
159 | ||
160 | /* After a command is input, the simulator goes to one of the following states */ | |
161 | #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */ | |
162 | #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */ | |
163 | #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */ | |
164 | #define STATE_CMD_PAGEPROG 0x00000004 /* start page programm */ | |
165 | #define STATE_CMD_READOOB 0x00000005 /* read OOB area */ | |
166 | #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */ | |
167 | #define STATE_CMD_STATUS 0x00000007 /* read status */ | |
168 | #define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */ | |
169 | #define STATE_CMD_SEQIN 0x00000009 /* sequential data imput */ | |
170 | #define STATE_CMD_READID 0x0000000A /* read ID */ | |
171 | #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */ | |
172 | #define STATE_CMD_RESET 0x0000000C /* reset */ | |
173 | #define STATE_CMD_MASK 0x0000000F /* command states mask */ | |
174 | ||
175 | /* After an addres is input, the simulator goes to one of these states */ | |
176 | #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */ | |
177 | #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */ | |
178 | #define STATE_ADDR_ZERO 0x00000030 /* one byte zero address was accepted */ | |
179 | #define STATE_ADDR_MASK 0x00000030 /* address states mask */ | |
180 | ||
181 | /* Durind data input/output the simulator is in these states */ | |
182 | #define STATE_DATAIN 0x00000100 /* waiting for data input */ | |
183 | #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */ | |
184 | ||
185 | #define STATE_DATAOUT 0x00001000 /* waiting for page data output */ | |
186 | #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */ | |
187 | #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */ | |
188 | #define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */ | |
189 | #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */ | |
190 | ||
191 | /* Previous operation is done, ready to accept new requests */ | |
192 | #define STATE_READY 0x00000000 | |
193 | ||
194 | /* This state is used to mark that the next state isn't known yet */ | |
195 | #define STATE_UNKNOWN 0x10000000 | |
196 | ||
197 | /* Simulator's actions bit masks */ | |
198 | #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */ | |
199 | #define ACTION_PRGPAGE 0x00200000 /* programm the internal buffer to flash */ | |
200 | #define ACTION_SECERASE 0x00300000 /* erase sector */ | |
201 | #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */ | |
202 | #define ACTION_HALFOFF 0x00500000 /* add to address half of page */ | |
203 | #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */ | |
204 | #define ACTION_MASK 0x00700000 /* action mask */ | |
205 | ||
206 | #define NS_OPER_NUM 12 /* Number of operations supported by the simulator */ | |
207 | #define NS_OPER_STATES 6 /* Maximum number of states in operation */ | |
208 | ||
209 | #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */ | |
210 | #define OPT_PAGE256 0x00000001 /* 256-byte page chips */ | |
211 | #define OPT_PAGE512 0x00000002 /* 512-byte page chips */ | |
212 | #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */ | |
213 | #define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */ | |
214 | #define OPT_AUTOINCR 0x00000020 /* page number auto inctimentation is possible */ | |
215 | #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */ | |
216 | #define OPT_LARGEPAGE (OPT_PAGE2048) /* 2048-byte page chips */ | |
217 | #define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */ | |
218 | ||
219 | /* Remove action bits ftom state */ | |
220 | #define NS_STATE(x) ((x) & ~ACTION_MASK) | |
61b03bd7 TG |
221 | |
222 | /* | |
1da177e4 LT |
223 | * Maximum previous states which need to be saved. Currently saving is |
224 | * only needed for page programm operation with preceeded read command | |
225 | * (which is only valid for 512-byte pages). | |
226 | */ | |
227 | #define NS_MAX_PREVSTATES 1 | |
228 | ||
d086d436 VK |
229 | /* |
230 | * A union to represent flash memory contents and flash buffer. | |
231 | */ | |
232 | union ns_mem { | |
233 | u_char *byte; /* for byte access */ | |
234 | uint16_t *word; /* for 16-bit word access */ | |
235 | }; | |
236 | ||
61b03bd7 | 237 | /* |
1da177e4 LT |
238 | * The structure which describes all the internal simulator data. |
239 | */ | |
240 | struct nandsim { | |
241 | struct mtd_partition part; | |
242 | ||
243 | uint busw; /* flash chip bus width (8 or 16) */ | |
244 | u_char ids[4]; /* chip's ID bytes */ | |
245 | uint32_t options; /* chip's characteristic bits */ | |
246 | uint32_t state; /* current chip state */ | |
247 | uint32_t nxstate; /* next expected state */ | |
61b03bd7 | 248 | |
1da177e4 LT |
249 | uint32_t *op; /* current operation, NULL operations isn't known yet */ |
250 | uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */ | |
251 | uint16_t npstates; /* number of previous states saved */ | |
252 | uint16_t stateidx; /* current state index */ | |
253 | ||
d086d436 VK |
254 | /* The simulated NAND flash pages array */ |
255 | union ns_mem *pages; | |
1da177e4 LT |
256 | |
257 | /* Internal buffer of page + OOB size bytes */ | |
d086d436 | 258 | union ns_mem buf; |
1da177e4 LT |
259 | |
260 | /* NAND flash "geometry" */ | |
261 | struct nandsin_geometry { | |
262 | uint32_t totsz; /* total flash size, bytes */ | |
263 | uint32_t secsz; /* flash sector (erase block) size, bytes */ | |
264 | uint pgsz; /* NAND flash page size, bytes */ | |
265 | uint oobsz; /* page OOB area size, bytes */ | |
266 | uint32_t totszoob; /* total flash size including OOB, bytes */ | |
267 | uint pgszoob; /* page size including OOB , bytes*/ | |
268 | uint secszoob; /* sector size including OOB, bytes */ | |
269 | uint pgnum; /* total number of pages */ | |
270 | uint pgsec; /* number of pages per sector */ | |
271 | uint secshift; /* bits number in sector size */ | |
272 | uint pgshift; /* bits number in page size */ | |
273 | uint oobshift; /* bits number in OOB size */ | |
274 | uint pgaddrbytes; /* bytes per page address */ | |
275 | uint secaddrbytes; /* bytes per sector address */ | |
276 | uint idbytes; /* the number ID bytes that this chip outputs */ | |
277 | } geom; | |
278 | ||
279 | /* NAND flash internal registers */ | |
280 | struct nandsim_regs { | |
281 | unsigned command; /* the command register */ | |
282 | u_char status; /* the status register */ | |
283 | uint row; /* the page number */ | |
284 | uint column; /* the offset within page */ | |
285 | uint count; /* internal counter */ | |
286 | uint num; /* number of bytes which must be processed */ | |
287 | uint off; /* fixed page offset */ | |
288 | } regs; | |
289 | ||
290 | /* NAND flash lines state */ | |
291 | struct ns_lines_status { | |
292 | int ce; /* chip Enable */ | |
293 | int cle; /* command Latch Enable */ | |
294 | int ale; /* address Latch Enable */ | |
295 | int wp; /* write Protect */ | |
296 | } lines; | |
297 | }; | |
298 | ||
299 | /* | |
300 | * Operations array. To perform any operation the simulator must pass | |
301 | * through the correspondent states chain. | |
302 | */ | |
303 | static struct nandsim_operations { | |
304 | uint32_t reqopts; /* options which are required to perform the operation */ | |
305 | uint32_t states[NS_OPER_STATES]; /* operation's states */ | |
306 | } ops[NS_OPER_NUM] = { | |
307 | /* Read page + OOB from the beginning */ | |
308 | {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY, | |
309 | STATE_DATAOUT, STATE_READY}}, | |
310 | /* Read page + OOB from the second half */ | |
311 | {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY, | |
312 | STATE_DATAOUT, STATE_READY}}, | |
313 | /* Read OOB */ | |
314 | {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY, | |
315 | STATE_DATAOUT, STATE_READY}}, | |
316 | /* Programm page starting from the beginning */ | |
317 | {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN, | |
318 | STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, | |
319 | /* Programm page starting from the beginning */ | |
320 | {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE, | |
321 | STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, | |
322 | /* Programm page starting from the second half */ | |
323 | {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE, | |
324 | STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, | |
325 | /* Programm OOB */ | |
326 | {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE, | |
327 | STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, | |
328 | /* Erase sector */ | |
329 | {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}}, | |
330 | /* Read status */ | |
331 | {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}}, | |
332 | /* Read multi-plane status */ | |
333 | {OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}}, | |
334 | /* Read ID */ | |
335 | {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}}, | |
336 | /* Large page devices read page */ | |
337 | {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY, | |
338 | STATE_DATAOUT, STATE_READY}} | |
339 | }; | |
340 | ||
341 | /* MTD structure for NAND controller */ | |
342 | static struct mtd_info *nsmtd; | |
343 | ||
344 | static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE]; | |
345 | ||
d086d436 VK |
346 | /* |
347 | * Allocate array of page pointers and initialize the array to NULL | |
348 | * pointers. | |
349 | * | |
350 | * RETURNS: 0 if success, -ENOMEM if memory alloc fails. | |
351 | */ | |
a5602146 | 352 | static int alloc_device(struct nandsim *ns) |
d086d436 VK |
353 | { |
354 | int i; | |
355 | ||
356 | ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem)); | |
357 | if (!ns->pages) { | |
358 | NS_ERR("alloc_map: unable to allocate page array\n"); | |
359 | return -ENOMEM; | |
360 | } | |
361 | for (i = 0; i < ns->geom.pgnum; i++) { | |
362 | ns->pages[i].byte = NULL; | |
363 | } | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | /* | |
369 | * Free any allocated pages, and free the array of page pointers. | |
370 | */ | |
a5602146 | 371 | static void free_device(struct nandsim *ns) |
d086d436 VK |
372 | { |
373 | int i; | |
374 | ||
375 | if (ns->pages) { | |
376 | for (i = 0; i < ns->geom.pgnum; i++) { | |
377 | if (ns->pages[i].byte) | |
378 | kfree(ns->pages[i].byte); | |
379 | } | |
380 | vfree(ns->pages); | |
381 | } | |
382 | } | |
383 | ||
1da177e4 LT |
384 | /* |
385 | * Initialize the nandsim structure. | |
386 | * | |
387 | * RETURNS: 0 if success, -ERRNO if failure. | |
388 | */ | |
a5602146 | 389 | static int init_nandsim(struct mtd_info *mtd) |
1da177e4 LT |
390 | { |
391 | struct nand_chip *chip = (struct nand_chip *)mtd->priv; | |
392 | struct nandsim *ns = (struct nandsim *)(chip->priv); | |
393 | int i; | |
394 | ||
395 | if (NS_IS_INITIALIZED(ns)) { | |
396 | NS_ERR("init_nandsim: nandsim is already initialized\n"); | |
397 | return -EIO; | |
398 | } | |
399 | ||
400 | /* Force mtd to not do delays */ | |
401 | chip->chip_delay = 0; | |
402 | ||
403 | /* Initialize the NAND flash parameters */ | |
404 | ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8; | |
405 | ns->geom.totsz = mtd->size; | |
28318776 | 406 | ns->geom.pgsz = mtd->writesize; |
1da177e4 LT |
407 | ns->geom.oobsz = mtd->oobsize; |
408 | ns->geom.secsz = mtd->erasesize; | |
409 | ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz; | |
410 | ns->geom.pgnum = ns->geom.totsz / ns->geom.pgsz; | |
411 | ns->geom.totszoob = ns->geom.totsz + ns->geom.pgnum * ns->geom.oobsz; | |
412 | ns->geom.secshift = ffs(ns->geom.secsz) - 1; | |
413 | ns->geom.pgshift = chip->page_shift; | |
414 | ns->geom.oobshift = ffs(ns->geom.oobsz) - 1; | |
415 | ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz; | |
416 | ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec; | |
417 | ns->options = 0; | |
418 | ||
419 | if (ns->geom.pgsz == 256) { | |
420 | ns->options |= OPT_PAGE256; | |
421 | } | |
422 | else if (ns->geom.pgsz == 512) { | |
423 | ns->options |= (OPT_PAGE512 | OPT_AUTOINCR); | |
424 | if (ns->busw == 8) | |
425 | ns->options |= OPT_PAGE512_8BIT; | |
426 | } else if (ns->geom.pgsz == 2048) { | |
427 | ns->options |= OPT_PAGE2048; | |
428 | } else { | |
429 | NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz); | |
430 | return -EIO; | |
431 | } | |
432 | ||
433 | if (ns->options & OPT_SMALLPAGE) { | |
434 | if (ns->geom.totsz < (64 << 20)) { | |
435 | ns->geom.pgaddrbytes = 3; | |
436 | ns->geom.secaddrbytes = 2; | |
437 | } else { | |
438 | ns->geom.pgaddrbytes = 4; | |
439 | ns->geom.secaddrbytes = 3; | |
440 | } | |
441 | } else { | |
442 | if (ns->geom.totsz <= (128 << 20)) { | |
443 | ns->geom.pgaddrbytes = 5; | |
444 | ns->geom.secaddrbytes = 2; | |
445 | } else { | |
446 | ns->geom.pgaddrbytes = 5; | |
447 | ns->geom.secaddrbytes = 3; | |
448 | } | |
449 | } | |
61b03bd7 | 450 | |
1da177e4 LT |
451 | /* Detect how many ID bytes the NAND chip outputs */ |
452 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { | |
453 | if (second_id_byte != nand_flash_ids[i].id) | |
454 | continue; | |
455 | if (!(nand_flash_ids[i].options & NAND_NO_AUTOINCR)) | |
456 | ns->options |= OPT_AUTOINCR; | |
457 | } | |
458 | ||
459 | if (ns->busw == 16) | |
460 | NS_WARN("16-bit flashes support wasn't tested\n"); | |
461 | ||
462 | printk("flash size: %u MiB\n", ns->geom.totsz >> 20); | |
463 | printk("page size: %u bytes\n", ns->geom.pgsz); | |
464 | printk("OOB area size: %u bytes\n", ns->geom.oobsz); | |
465 | printk("sector size: %u KiB\n", ns->geom.secsz >> 10); | |
466 | printk("pages number: %u\n", ns->geom.pgnum); | |
467 | printk("pages per sector: %u\n", ns->geom.pgsec); | |
468 | printk("bus width: %u\n", ns->busw); | |
469 | printk("bits in sector size: %u\n", ns->geom.secshift); | |
470 | printk("bits in page size: %u\n", ns->geom.pgshift); | |
471 | printk("bits in OOB size: %u\n", ns->geom.oobshift); | |
472 | printk("flash size with OOB: %u KiB\n", ns->geom.totszoob >> 10); | |
473 | printk("page address bytes: %u\n", ns->geom.pgaddrbytes); | |
474 | printk("sector address bytes: %u\n", ns->geom.secaddrbytes); | |
475 | printk("options: %#x\n", ns->options); | |
476 | ||
d086d436 VK |
477 | if (alloc_device(ns) != 0) |
478 | goto error; | |
1da177e4 LT |
479 | |
480 | /* Allocate / initialize the internal buffer */ | |
481 | ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL); | |
482 | if (!ns->buf.byte) { | |
483 | NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n", | |
484 | ns->geom.pgszoob); | |
485 | goto error; | |
486 | } | |
487 | memset(ns->buf.byte, 0xFF, ns->geom.pgszoob); | |
488 | ||
489 | /* Fill the partition_info structure */ | |
490 | ns->part.name = "NAND simulator partition"; | |
491 | ns->part.offset = 0; | |
492 | ns->part.size = ns->geom.totsz; | |
493 | ||
494 | return 0; | |
495 | ||
496 | error: | |
d086d436 | 497 | free_device(ns); |
1da177e4 LT |
498 | |
499 | return -ENOMEM; | |
500 | } | |
501 | ||
502 | /* | |
503 | * Free the nandsim structure. | |
504 | */ | |
a5602146 | 505 | static void free_nandsim(struct nandsim *ns) |
1da177e4 LT |
506 | { |
507 | kfree(ns->buf.byte); | |
d086d436 | 508 | free_device(ns); |
1da177e4 LT |
509 | |
510 | return; | |
511 | } | |
512 | ||
513 | /* | |
514 | * Returns the string representation of 'state' state. | |
515 | */ | |
a5602146 | 516 | static char *get_state_name(uint32_t state) |
1da177e4 LT |
517 | { |
518 | switch (NS_STATE(state)) { | |
519 | case STATE_CMD_READ0: | |
520 | return "STATE_CMD_READ0"; | |
521 | case STATE_CMD_READ1: | |
522 | return "STATE_CMD_READ1"; | |
523 | case STATE_CMD_PAGEPROG: | |
524 | return "STATE_CMD_PAGEPROG"; | |
525 | case STATE_CMD_READOOB: | |
526 | return "STATE_CMD_READOOB"; | |
527 | case STATE_CMD_READSTART: | |
528 | return "STATE_CMD_READSTART"; | |
529 | case STATE_CMD_ERASE1: | |
530 | return "STATE_CMD_ERASE1"; | |
531 | case STATE_CMD_STATUS: | |
532 | return "STATE_CMD_STATUS"; | |
533 | case STATE_CMD_STATUS_M: | |
534 | return "STATE_CMD_STATUS_M"; | |
535 | case STATE_CMD_SEQIN: | |
536 | return "STATE_CMD_SEQIN"; | |
537 | case STATE_CMD_READID: | |
538 | return "STATE_CMD_READID"; | |
539 | case STATE_CMD_ERASE2: | |
540 | return "STATE_CMD_ERASE2"; | |
541 | case STATE_CMD_RESET: | |
542 | return "STATE_CMD_RESET"; | |
543 | case STATE_ADDR_PAGE: | |
544 | return "STATE_ADDR_PAGE"; | |
545 | case STATE_ADDR_SEC: | |
546 | return "STATE_ADDR_SEC"; | |
547 | case STATE_ADDR_ZERO: | |
548 | return "STATE_ADDR_ZERO"; | |
549 | case STATE_DATAIN: | |
550 | return "STATE_DATAIN"; | |
551 | case STATE_DATAOUT: | |
552 | return "STATE_DATAOUT"; | |
553 | case STATE_DATAOUT_ID: | |
554 | return "STATE_DATAOUT_ID"; | |
555 | case STATE_DATAOUT_STATUS: | |
556 | return "STATE_DATAOUT_STATUS"; | |
557 | case STATE_DATAOUT_STATUS_M: | |
558 | return "STATE_DATAOUT_STATUS_M"; | |
559 | case STATE_READY: | |
560 | return "STATE_READY"; | |
561 | case STATE_UNKNOWN: | |
562 | return "STATE_UNKNOWN"; | |
563 | } | |
564 | ||
565 | NS_ERR("get_state_name: unknown state, BUG\n"); | |
566 | return NULL; | |
567 | } | |
568 | ||
569 | /* | |
570 | * Check if command is valid. | |
571 | * | |
572 | * RETURNS: 1 if wrong command, 0 if right. | |
573 | */ | |
a5602146 | 574 | static int check_command(int cmd) |
1da177e4 LT |
575 | { |
576 | switch (cmd) { | |
61b03bd7 | 577 | |
1da177e4 LT |
578 | case NAND_CMD_READ0: |
579 | case NAND_CMD_READSTART: | |
580 | case NAND_CMD_PAGEPROG: | |
581 | case NAND_CMD_READOOB: | |
582 | case NAND_CMD_ERASE1: | |
583 | case NAND_CMD_STATUS: | |
584 | case NAND_CMD_SEQIN: | |
585 | case NAND_CMD_READID: | |
586 | case NAND_CMD_ERASE2: | |
587 | case NAND_CMD_RESET: | |
588 | case NAND_CMD_READ1: | |
589 | return 0; | |
61b03bd7 | 590 | |
1da177e4 LT |
591 | case NAND_CMD_STATUS_MULTI: |
592 | default: | |
593 | return 1; | |
594 | } | |
595 | } | |
596 | ||
597 | /* | |
598 | * Returns state after command is accepted by command number. | |
599 | */ | |
a5602146 | 600 | static uint32_t get_state_by_command(unsigned command) |
1da177e4 LT |
601 | { |
602 | switch (command) { | |
603 | case NAND_CMD_READ0: | |
604 | return STATE_CMD_READ0; | |
605 | case NAND_CMD_READ1: | |
606 | return STATE_CMD_READ1; | |
607 | case NAND_CMD_PAGEPROG: | |
608 | return STATE_CMD_PAGEPROG; | |
609 | case NAND_CMD_READSTART: | |
610 | return STATE_CMD_READSTART; | |
611 | case NAND_CMD_READOOB: | |
612 | return STATE_CMD_READOOB; | |
613 | case NAND_CMD_ERASE1: | |
614 | return STATE_CMD_ERASE1; | |
615 | case NAND_CMD_STATUS: | |
616 | return STATE_CMD_STATUS; | |
617 | case NAND_CMD_STATUS_MULTI: | |
618 | return STATE_CMD_STATUS_M; | |
619 | case NAND_CMD_SEQIN: | |
620 | return STATE_CMD_SEQIN; | |
621 | case NAND_CMD_READID: | |
622 | return STATE_CMD_READID; | |
623 | case NAND_CMD_ERASE2: | |
624 | return STATE_CMD_ERASE2; | |
625 | case NAND_CMD_RESET: | |
626 | return STATE_CMD_RESET; | |
627 | } | |
628 | ||
629 | NS_ERR("get_state_by_command: unknown command, BUG\n"); | |
630 | return 0; | |
631 | } | |
632 | ||
633 | /* | |
634 | * Move an address byte to the correspondent internal register. | |
635 | */ | |
a5602146 | 636 | static inline void accept_addr_byte(struct nandsim *ns, u_char bt) |
1da177e4 LT |
637 | { |
638 | uint byte = (uint)bt; | |
61b03bd7 | 639 | |
1da177e4 LT |
640 | if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) |
641 | ns->regs.column |= (byte << 8 * ns->regs.count); | |
642 | else { | |
643 | ns->regs.row |= (byte << 8 * (ns->regs.count - | |
644 | ns->geom.pgaddrbytes + | |
645 | ns->geom.secaddrbytes)); | |
646 | } | |
647 | ||
648 | return; | |
649 | } | |
61b03bd7 | 650 | |
1da177e4 LT |
651 | /* |
652 | * Switch to STATE_READY state. | |
653 | */ | |
a5602146 | 654 | static inline void switch_to_ready_state(struct nandsim *ns, u_char status) |
1da177e4 LT |
655 | { |
656 | NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY)); | |
657 | ||
658 | ns->state = STATE_READY; | |
659 | ns->nxstate = STATE_UNKNOWN; | |
660 | ns->op = NULL; | |
661 | ns->npstates = 0; | |
662 | ns->stateidx = 0; | |
663 | ns->regs.num = 0; | |
664 | ns->regs.count = 0; | |
665 | ns->regs.off = 0; | |
666 | ns->regs.row = 0; | |
667 | ns->regs.column = 0; | |
668 | ns->regs.status = status; | |
669 | } | |
670 | ||
671 | /* | |
672 | * If the operation isn't known yet, try to find it in the global array | |
673 | * of supported operations. | |
674 | * | |
675 | * Operation can be unknown because of the following. | |
676 | * 1. New command was accepted and this is the firs call to find the | |
677 | * correspondent states chain. In this case ns->npstates = 0; | |
678 | * 2. There is several operations which begin with the same command(s) | |
679 | * (for example program from the second half and read from the | |
680 | * second half operations both begin with the READ1 command). In this | |
681 | * case the ns->pstates[] array contains previous states. | |
61b03bd7 | 682 | * |
1da177e4 LT |
683 | * Thus, the function tries to find operation containing the following |
684 | * states (if the 'flag' parameter is 0): | |
685 | * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state | |
686 | * | |
687 | * If (one and only one) matching operation is found, it is accepted ( | |
688 | * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is | |
689 | * zeroed). | |
61b03bd7 | 690 | * |
1da177e4 LT |
691 | * If there are several maches, the current state is pushed to the |
692 | * ns->pstates. | |
693 | * | |
694 | * The operation can be unknown only while commands are input to the chip. | |
695 | * As soon as address command is accepted, the operation must be known. | |
696 | * In such situation the function is called with 'flag' != 0, and the | |
697 | * operation is searched using the following pattern: | |
698 | * ns->pstates[0], ... ns->pstates[ns->npstates], <address input> | |
61b03bd7 | 699 | * |
1da177e4 LT |
700 | * It is supposed that this pattern must either match one operation on |
701 | * none. There can't be ambiguity in that case. | |
702 | * | |
703 | * If no matches found, the functions does the following: | |
704 | * 1. if there are saved states present, try to ignore them and search | |
705 | * again only using the last command. If nothing was found, switch | |
706 | * to the STATE_READY state. | |
707 | * 2. if there are no saved states, switch to the STATE_READY state. | |
708 | * | |
709 | * RETURNS: -2 - no matched operations found. | |
710 | * -1 - several matches. | |
711 | * 0 - operation is found. | |
712 | */ | |
a5602146 | 713 | static int find_operation(struct nandsim *ns, uint32_t flag) |
1da177e4 LT |
714 | { |
715 | int opsfound = 0; | |
716 | int i, j, idx = 0; | |
61b03bd7 | 717 | |
1da177e4 LT |
718 | for (i = 0; i < NS_OPER_NUM; i++) { |
719 | ||
720 | int found = 1; | |
61b03bd7 | 721 | |
1da177e4 LT |
722 | if (!(ns->options & ops[i].reqopts)) |
723 | /* Ignore operations we can't perform */ | |
724 | continue; | |
61b03bd7 | 725 | |
1da177e4 LT |
726 | if (flag) { |
727 | if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK)) | |
728 | continue; | |
729 | } else { | |
730 | if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates])) | |
731 | continue; | |
732 | } | |
733 | ||
61b03bd7 | 734 | for (j = 0; j < ns->npstates; j++) |
1da177e4 LT |
735 | if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j]) |
736 | && (ns->options & ops[idx].reqopts)) { | |
737 | found = 0; | |
738 | break; | |
739 | } | |
740 | ||
741 | if (found) { | |
742 | idx = i; | |
743 | opsfound += 1; | |
744 | } | |
745 | } | |
746 | ||
747 | if (opsfound == 1) { | |
748 | /* Exact match */ | |
749 | ns->op = &ops[idx].states[0]; | |
750 | if (flag) { | |
61b03bd7 | 751 | /* |
1da177e4 LT |
752 | * In this case the find_operation function was |
753 | * called when address has just began input. But it isn't | |
754 | * yet fully input and the current state must | |
755 | * not be one of STATE_ADDR_*, but the STATE_ADDR_* | |
756 | * state must be the next state (ns->nxstate). | |
757 | */ | |
758 | ns->stateidx = ns->npstates - 1; | |
759 | } else { | |
760 | ns->stateidx = ns->npstates; | |
761 | } | |
762 | ns->npstates = 0; | |
763 | ns->state = ns->op[ns->stateidx]; | |
764 | ns->nxstate = ns->op[ns->stateidx + 1]; | |
765 | NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n", | |
766 | idx, get_state_name(ns->state), get_state_name(ns->nxstate)); | |
767 | return 0; | |
768 | } | |
61b03bd7 | 769 | |
1da177e4 LT |
770 | if (opsfound == 0) { |
771 | /* Nothing was found. Try to ignore previous commands (if any) and search again */ | |
772 | if (ns->npstates != 0) { | |
773 | NS_DBG("find_operation: no operation found, try again with state %s\n", | |
774 | get_state_name(ns->state)); | |
775 | ns->npstates = 0; | |
776 | return find_operation(ns, 0); | |
777 | ||
778 | } | |
779 | NS_DBG("find_operation: no operations found\n"); | |
780 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
781 | return -2; | |
782 | } | |
61b03bd7 | 783 | |
1da177e4 LT |
784 | if (flag) { |
785 | /* This shouldn't happen */ | |
786 | NS_DBG("find_operation: BUG, operation must be known if address is input\n"); | |
787 | return -2; | |
788 | } | |
61b03bd7 | 789 | |
1da177e4 LT |
790 | NS_DBG("find_operation: there is still ambiguity\n"); |
791 | ||
792 | ns->pstates[ns->npstates++] = ns->state; | |
793 | ||
794 | return -1; | |
795 | } | |
796 | ||
d086d436 VK |
797 | /* |
798 | * Returns a pointer to the current page. | |
799 | */ | |
800 | static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns) | |
801 | { | |
802 | return &(ns->pages[ns->regs.row]); | |
803 | } | |
804 | ||
805 | /* | |
806 | * Retuns a pointer to the current byte, within the current page. | |
807 | */ | |
808 | static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns) | |
809 | { | |
810 | return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off; | |
811 | } | |
812 | ||
813 | /* | |
814 | * Fill the NAND buffer with data read from the specified page. | |
815 | */ | |
816 | static void read_page(struct nandsim *ns, int num) | |
817 | { | |
818 | union ns_mem *mypage; | |
819 | ||
820 | mypage = NS_GET_PAGE(ns); | |
821 | if (mypage->byte == NULL) { | |
822 | NS_DBG("read_page: page %d not allocated\n", ns->regs.row); | |
823 | memset(ns->buf.byte, 0xFF, num); | |
824 | } else { | |
825 | NS_DBG("read_page: page %d allocated, reading from %d\n", | |
826 | ns->regs.row, ns->regs.column + ns->regs.off); | |
827 | memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num); | |
828 | } | |
829 | } | |
830 | ||
831 | /* | |
832 | * Erase all pages in the specified sector. | |
833 | */ | |
834 | static void erase_sector(struct nandsim *ns) | |
835 | { | |
836 | union ns_mem *mypage; | |
837 | int i; | |
838 | ||
839 | mypage = NS_GET_PAGE(ns); | |
840 | for (i = 0; i < ns->geom.pgsec; i++) { | |
841 | if (mypage->byte != NULL) { | |
842 | NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i); | |
843 | kfree(mypage->byte); | |
844 | mypage->byte = NULL; | |
845 | } | |
846 | mypage++; | |
847 | } | |
848 | } | |
849 | ||
850 | /* | |
851 | * Program the specified page with the contents from the NAND buffer. | |
852 | */ | |
853 | static int prog_page(struct nandsim *ns, int num) | |
854 | { | |
855 | union ns_mem *mypage; | |
856 | u_char *pg_off; | |
857 | ||
858 | mypage = NS_GET_PAGE(ns); | |
859 | if (mypage->byte == NULL) { | |
860 | NS_DBG("prog_page: allocating page %d\n", ns->regs.row); | |
861 | mypage->byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL); | |
862 | if (mypage->byte == NULL) { | |
863 | NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row); | |
864 | return -1; | |
865 | } | |
866 | memset(mypage->byte, 0xFF, ns->geom.pgszoob); | |
867 | } | |
868 | ||
869 | pg_off = NS_PAGE_BYTE_OFF(ns); | |
870 | memcpy(pg_off, ns->buf.byte, num); | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
1da177e4 LT |
875 | /* |
876 | * If state has any action bit, perform this action. | |
877 | * | |
878 | * RETURNS: 0 if success, -1 if error. | |
879 | */ | |
a5602146 | 880 | static int do_state_action(struct nandsim *ns, uint32_t action) |
1da177e4 | 881 | { |
d086d436 | 882 | int num; |
1da177e4 LT |
883 | int busdiv = ns->busw == 8 ? 1 : 2; |
884 | ||
885 | action &= ACTION_MASK; | |
61b03bd7 | 886 | |
1da177e4 LT |
887 | /* Check that page address input is correct */ |
888 | if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) { | |
889 | NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row); | |
890 | return -1; | |
891 | } | |
892 | ||
893 | switch (action) { | |
894 | ||
895 | case ACTION_CPY: | |
896 | /* | |
897 | * Copy page data to the internal buffer. | |
898 | */ | |
899 | ||
900 | /* Column shouldn't be very large */ | |
901 | if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) { | |
902 | NS_ERR("do_state_action: column number is too large\n"); | |
903 | break; | |
904 | } | |
905 | num = ns->geom.pgszoob - ns->regs.off - ns->regs.column; | |
d086d436 | 906 | read_page(ns, num); |
1da177e4 LT |
907 | |
908 | NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n", | |
909 | num, NS_RAW_OFFSET(ns) + ns->regs.off); | |
61b03bd7 | 910 | |
1da177e4 LT |
911 | if (ns->regs.off == 0) |
912 | NS_LOG("read page %d\n", ns->regs.row); | |
913 | else if (ns->regs.off < ns->geom.pgsz) | |
914 | NS_LOG("read page %d (second half)\n", ns->regs.row); | |
915 | else | |
916 | NS_LOG("read OOB of page %d\n", ns->regs.row); | |
61b03bd7 | 917 | |
1da177e4 LT |
918 | NS_UDELAY(access_delay); |
919 | NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv); | |
920 | ||
921 | break; | |
922 | ||
923 | case ACTION_SECERASE: | |
924 | /* | |
925 | * Erase sector. | |
926 | */ | |
61b03bd7 | 927 | |
1da177e4 LT |
928 | if (ns->lines.wp) { |
929 | NS_ERR("do_state_action: device is write-protected, ignore sector erase\n"); | |
930 | return -1; | |
931 | } | |
61b03bd7 | 932 | |
1da177e4 LT |
933 | if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec |
934 | || (ns->regs.row & ~(ns->geom.secsz - 1))) { | |
935 | NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row); | |
936 | return -1; | |
937 | } | |
61b03bd7 | 938 | |
1da177e4 LT |
939 | ns->regs.row = (ns->regs.row << |
940 | 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column; | |
941 | ns->regs.column = 0; | |
61b03bd7 | 942 | |
1da177e4 LT |
943 | NS_DBG("do_state_action: erase sector at address %#x, off = %d\n", |
944 | ns->regs.row, NS_RAW_OFFSET(ns)); | |
945 | NS_LOG("erase sector %d\n", ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift)); | |
946 | ||
d086d436 | 947 | erase_sector(ns); |
61b03bd7 | 948 | |
1da177e4 | 949 | NS_MDELAY(erase_delay); |
61b03bd7 | 950 | |
1da177e4 LT |
951 | break; |
952 | ||
953 | case ACTION_PRGPAGE: | |
954 | /* | |
955 | * Programm page - move internal buffer data to the page. | |
956 | */ | |
957 | ||
958 | if (ns->lines.wp) { | |
959 | NS_WARN("do_state_action: device is write-protected, programm\n"); | |
960 | return -1; | |
961 | } | |
962 | ||
963 | num = ns->geom.pgszoob - ns->regs.off - ns->regs.column; | |
964 | if (num != ns->regs.count) { | |
965 | NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n", | |
966 | ns->regs.count, num); | |
967 | return -1; | |
968 | } | |
969 | ||
d086d436 VK |
970 | if (prog_page(ns, num) == -1) |
971 | return -1; | |
1da177e4 LT |
972 | |
973 | NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n", | |
974 | num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off); | |
975 | NS_LOG("programm page %d\n", ns->regs.row); | |
61b03bd7 | 976 | |
1da177e4 LT |
977 | NS_UDELAY(programm_delay); |
978 | NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv); | |
61b03bd7 | 979 | |
1da177e4 | 980 | break; |
61b03bd7 | 981 | |
1da177e4 LT |
982 | case ACTION_ZEROOFF: |
983 | NS_DBG("do_state_action: set internal offset to 0\n"); | |
984 | ns->regs.off = 0; | |
985 | break; | |
986 | ||
987 | case ACTION_HALFOFF: | |
988 | if (!(ns->options & OPT_PAGE512_8BIT)) { | |
989 | NS_ERR("do_state_action: BUG! can't skip half of page for non-512" | |
990 | "byte page size 8x chips\n"); | |
991 | return -1; | |
992 | } | |
993 | NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2); | |
994 | ns->regs.off = ns->geom.pgsz/2; | |
995 | break; | |
996 | ||
997 | case ACTION_OOBOFF: | |
998 | NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz); | |
999 | ns->regs.off = ns->geom.pgsz; | |
1000 | break; | |
61b03bd7 | 1001 | |
1da177e4 LT |
1002 | default: |
1003 | NS_DBG("do_state_action: BUG! unknown action\n"); | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * Switch simulator's state. | |
1011 | */ | |
a5602146 | 1012 | static void switch_state(struct nandsim *ns) |
1da177e4 LT |
1013 | { |
1014 | if (ns->op) { | |
1015 | /* | |
1016 | * The current operation have already been identified. | |
1017 | * Just follow the states chain. | |
1018 | */ | |
61b03bd7 | 1019 | |
1da177e4 LT |
1020 | ns->stateidx += 1; |
1021 | ns->state = ns->nxstate; | |
1022 | ns->nxstate = ns->op[ns->stateidx + 1]; | |
1023 | ||
1024 | NS_DBG("switch_state: operation is known, switch to the next state, " | |
1025 | "state: %s, nxstate: %s\n", | |
1026 | get_state_name(ns->state), get_state_name(ns->nxstate)); | |
1027 | ||
1028 | /* See, whether we need to do some action */ | |
1029 | if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) { | |
1030 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1031 | return; | |
1032 | } | |
61b03bd7 | 1033 | |
1da177e4 LT |
1034 | } else { |
1035 | /* | |
1036 | * We don't yet know which operation we perform. | |
1037 | * Try to identify it. | |
1038 | */ | |
1039 | ||
61b03bd7 | 1040 | /* |
1da177e4 LT |
1041 | * The only event causing the switch_state function to |
1042 | * be called with yet unknown operation is new command. | |
1043 | */ | |
1044 | ns->state = get_state_by_command(ns->regs.command); | |
1045 | ||
1046 | NS_DBG("switch_state: operation is unknown, try to find it\n"); | |
1047 | ||
1048 | if (find_operation(ns, 0) != 0) | |
1049 | return; | |
1050 | ||
1051 | if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) { | |
1052 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1053 | return; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | /* For 16x devices column means the page offset in words */ | |
1058 | if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) { | |
1059 | NS_DBG("switch_state: double the column number for 16x device\n"); | |
1060 | ns->regs.column <<= 1; | |
1061 | } | |
1062 | ||
1063 | if (NS_STATE(ns->nxstate) == STATE_READY) { | |
1064 | /* | |
1065 | * The current state is the last. Return to STATE_READY | |
1066 | */ | |
1067 | ||
1068 | u_char status = NS_STATUS_OK(ns); | |
61b03bd7 | 1069 | |
1da177e4 LT |
1070 | /* In case of data states, see if all bytes were input/output */ |
1071 | if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) | |
1072 | && ns->regs.count != ns->regs.num) { | |
1073 | NS_WARN("switch_state: not all bytes were processed, %d left\n", | |
1074 | ns->regs.num - ns->regs.count); | |
1075 | status = NS_STATUS_FAILED(ns); | |
1076 | } | |
61b03bd7 | 1077 | |
1da177e4 LT |
1078 | NS_DBG("switch_state: operation complete, switch to STATE_READY state\n"); |
1079 | ||
1080 | switch_to_ready_state(ns, status); | |
1081 | ||
1082 | return; | |
1083 | } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) { | |
61b03bd7 | 1084 | /* |
1da177e4 LT |
1085 | * If the next state is data input/output, switch to it now |
1086 | */ | |
61b03bd7 | 1087 | |
1da177e4 LT |
1088 | ns->state = ns->nxstate; |
1089 | ns->nxstate = ns->op[++ns->stateidx + 1]; | |
1090 | ns->regs.num = ns->regs.count = 0; | |
1091 | ||
1092 | NS_DBG("switch_state: the next state is data I/O, switch, " | |
1093 | "state: %s, nxstate: %s\n", | |
1094 | get_state_name(ns->state), get_state_name(ns->nxstate)); | |
1095 | ||
1096 | /* | |
1097 | * Set the internal register to the count of bytes which | |
1098 | * are expected to be input or output | |
1099 | */ | |
1100 | switch (NS_STATE(ns->state)) { | |
1101 | case STATE_DATAIN: | |
1102 | case STATE_DATAOUT: | |
1103 | ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column; | |
1104 | break; | |
61b03bd7 | 1105 | |
1da177e4 LT |
1106 | case STATE_DATAOUT_ID: |
1107 | ns->regs.num = ns->geom.idbytes; | |
1108 | break; | |
61b03bd7 | 1109 | |
1da177e4 LT |
1110 | case STATE_DATAOUT_STATUS: |
1111 | case STATE_DATAOUT_STATUS_M: | |
1112 | ns->regs.count = ns->regs.num = 0; | |
1113 | break; | |
61b03bd7 | 1114 | |
1da177e4 LT |
1115 | default: |
1116 | NS_ERR("switch_state: BUG! unknown data state\n"); | |
1117 | } | |
1118 | ||
1119 | } else if (ns->nxstate & STATE_ADDR_MASK) { | |
1120 | /* | |
1121 | * If the next state is address input, set the internal | |
1122 | * register to the number of expected address bytes | |
1123 | */ | |
1124 | ||
1125 | ns->regs.count = 0; | |
61b03bd7 | 1126 | |
1da177e4 LT |
1127 | switch (NS_STATE(ns->nxstate)) { |
1128 | case STATE_ADDR_PAGE: | |
1129 | ns->regs.num = ns->geom.pgaddrbytes; | |
61b03bd7 | 1130 | |
1da177e4 LT |
1131 | break; |
1132 | case STATE_ADDR_SEC: | |
1133 | ns->regs.num = ns->geom.secaddrbytes; | |
1134 | break; | |
61b03bd7 | 1135 | |
1da177e4 LT |
1136 | case STATE_ADDR_ZERO: |
1137 | ns->regs.num = 1; | |
1138 | break; | |
1139 | ||
1140 | default: | |
1141 | NS_ERR("switch_state: BUG! unknown address state\n"); | |
1142 | } | |
1143 | } else { | |
61b03bd7 | 1144 | /* |
1da177e4 LT |
1145 | * Just reset internal counters. |
1146 | */ | |
1147 | ||
1148 | ns->regs.num = 0; | |
1149 | ns->regs.count = 0; | |
1150 | } | |
1151 | } | |
1152 | ||
a5602146 | 1153 | static u_char ns_nand_read_byte(struct mtd_info *mtd) |
1da177e4 LT |
1154 | { |
1155 | struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv; | |
1156 | u_char outb = 0x00; | |
1157 | ||
1158 | /* Sanity and correctness checks */ | |
1159 | if (!ns->lines.ce) { | |
1160 | NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb); | |
1161 | return outb; | |
1162 | } | |
1163 | if (ns->lines.ale || ns->lines.cle) { | |
1164 | NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb); | |
1165 | return outb; | |
1166 | } | |
1167 | if (!(ns->state & STATE_DATAOUT_MASK)) { | |
1168 | NS_WARN("read_byte: unexpected data output cycle, state is %s " | |
1169 | "return %#x\n", get_state_name(ns->state), (uint)outb); | |
1170 | return outb; | |
1171 | } | |
1172 | ||
1173 | /* Status register may be read as many times as it is wanted */ | |
1174 | if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) { | |
1175 | NS_DBG("read_byte: return %#x status\n", ns->regs.status); | |
1176 | return ns->regs.status; | |
1177 | } | |
1178 | ||
1179 | /* Check if there is any data in the internal buffer which may be read */ | |
1180 | if (ns->regs.count == ns->regs.num) { | |
1181 | NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb); | |
1182 | return outb; | |
1183 | } | |
1184 | ||
1185 | switch (NS_STATE(ns->state)) { | |
1186 | case STATE_DATAOUT: | |
1187 | if (ns->busw == 8) { | |
1188 | outb = ns->buf.byte[ns->regs.count]; | |
1189 | ns->regs.count += 1; | |
1190 | } else { | |
1191 | outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]); | |
1192 | ns->regs.count += 2; | |
1193 | } | |
1194 | break; | |
1195 | case STATE_DATAOUT_ID: | |
1196 | NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num); | |
1197 | outb = ns->ids[ns->regs.count]; | |
1198 | ns->regs.count += 1; | |
1199 | break; | |
1200 | default: | |
1201 | BUG(); | |
1202 | } | |
61b03bd7 | 1203 | |
1da177e4 LT |
1204 | if (ns->regs.count == ns->regs.num) { |
1205 | NS_DBG("read_byte: all bytes were read\n"); | |
1206 | ||
1207 | /* | |
1208 | * The OPT_AUTOINCR allows to read next conseqitive pages without | |
1209 | * new read operation cycle. | |
1210 | */ | |
1211 | if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) { | |
1212 | ns->regs.count = 0; | |
1213 | if (ns->regs.row + 1 < ns->geom.pgnum) | |
1214 | ns->regs.row += 1; | |
1215 | NS_DBG("read_byte: switch to the next page (%#x)\n", ns->regs.row); | |
1216 | do_state_action(ns, ACTION_CPY); | |
1217 | } | |
1218 | else if (NS_STATE(ns->nxstate) == STATE_READY) | |
1219 | switch_state(ns); | |
61b03bd7 | 1220 | |
1da177e4 | 1221 | } |
61b03bd7 | 1222 | |
1da177e4 LT |
1223 | return outb; |
1224 | } | |
1225 | ||
a5602146 | 1226 | static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte) |
1da177e4 LT |
1227 | { |
1228 | struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv; | |
61b03bd7 | 1229 | |
1da177e4 LT |
1230 | /* Sanity and correctness checks */ |
1231 | if (!ns->lines.ce) { | |
1232 | NS_ERR("write_byte: chip is disabled, ignore write\n"); | |
1233 | return; | |
1234 | } | |
1235 | if (ns->lines.ale && ns->lines.cle) { | |
1236 | NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n"); | |
1237 | return; | |
1238 | } | |
61b03bd7 | 1239 | |
1da177e4 LT |
1240 | if (ns->lines.cle == 1) { |
1241 | /* | |
1242 | * The byte written is a command. | |
1243 | */ | |
1244 | ||
1245 | if (byte == NAND_CMD_RESET) { | |
1246 | NS_LOG("reset chip\n"); | |
1247 | switch_to_ready_state(ns, NS_STATUS_OK(ns)); | |
1248 | return; | |
1249 | } | |
1250 | ||
61b03bd7 | 1251 | /* |
1da177e4 LT |
1252 | * Chip might still be in STATE_DATAOUT |
1253 | * (if OPT_AUTOINCR feature is supported), STATE_DATAOUT_STATUS or | |
1254 | * STATE_DATAOUT_STATUS_M state. If so, switch state. | |
1255 | */ | |
1256 | if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS | |
1257 | || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M | |
1258 | || ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT)) | |
1259 | switch_state(ns); | |
1260 | ||
1261 | /* Check if chip is expecting command */ | |
1262 | if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) { | |
1263 | /* | |
1264 | * We are in situation when something else (not command) | |
1265 | * was expected but command was input. In this case ignore | |
1266 | * previous command(s)/state(s) and accept the last one. | |
1267 | */ | |
1268 | NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, " | |
1269 | "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate)); | |
1270 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1271 | } | |
61b03bd7 | 1272 | |
1da177e4 LT |
1273 | /* Check that the command byte is correct */ |
1274 | if (check_command(byte)) { | |
1275 | NS_ERR("write_byte: unknown command %#x\n", (uint)byte); | |
1276 | return; | |
1277 | } | |
61b03bd7 | 1278 | |
1da177e4 LT |
1279 | NS_DBG("command byte corresponding to %s state accepted\n", |
1280 | get_state_name(get_state_by_command(byte))); | |
1281 | ns->regs.command = byte; | |
1282 | switch_state(ns); | |
1283 | ||
1284 | } else if (ns->lines.ale == 1) { | |
1285 | /* | |
1286 | * The byte written is an address. | |
1287 | */ | |
1288 | ||
1289 | if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) { | |
1290 | ||
1291 | NS_DBG("write_byte: operation isn't known yet, identify it\n"); | |
1292 | ||
1293 | if (find_operation(ns, 1) < 0) | |
1294 | return; | |
61b03bd7 | 1295 | |
1da177e4 LT |
1296 | if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) { |
1297 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1298 | return; | |
1299 | } | |
61b03bd7 | 1300 | |
1da177e4 LT |
1301 | ns->regs.count = 0; |
1302 | switch (NS_STATE(ns->nxstate)) { | |
1303 | case STATE_ADDR_PAGE: | |
1304 | ns->regs.num = ns->geom.pgaddrbytes; | |
1305 | break; | |
1306 | case STATE_ADDR_SEC: | |
1307 | ns->regs.num = ns->geom.secaddrbytes; | |
1308 | break; | |
1309 | case STATE_ADDR_ZERO: | |
1310 | ns->regs.num = 1; | |
1311 | break; | |
1312 | default: | |
1313 | BUG(); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | /* Check that chip is expecting address */ | |
1318 | if (!(ns->nxstate & STATE_ADDR_MASK)) { | |
1319 | NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, " | |
1320 | "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate)); | |
1321 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1322 | return; | |
1323 | } | |
61b03bd7 | 1324 | |
1da177e4 LT |
1325 | /* Check if this is expected byte */ |
1326 | if (ns->regs.count == ns->regs.num) { | |
1327 | NS_ERR("write_byte: no more address bytes expected\n"); | |
1328 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1329 | return; | |
1330 | } | |
1331 | ||
1332 | accept_addr_byte(ns, byte); | |
1333 | ||
1334 | ns->regs.count += 1; | |
1335 | ||
1336 | NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n", | |
1337 | (uint)byte, ns->regs.count, ns->regs.num); | |
1338 | ||
1339 | if (ns->regs.count == ns->regs.num) { | |
1340 | NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column); | |
1341 | switch_state(ns); | |
1342 | } | |
61b03bd7 | 1343 | |
1da177e4 LT |
1344 | } else { |
1345 | /* | |
1346 | * The byte written is an input data. | |
1347 | */ | |
61b03bd7 | 1348 | |
1da177e4 LT |
1349 | /* Check that chip is expecting data input */ |
1350 | if (!(ns->state & STATE_DATAIN_MASK)) { | |
1351 | NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, " | |
1352 | "switch to %s\n", (uint)byte, | |
1353 | get_state_name(ns->state), get_state_name(STATE_READY)); | |
1354 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1355 | return; | |
1356 | } | |
1357 | ||
1358 | /* Check if this is expected byte */ | |
1359 | if (ns->regs.count == ns->regs.num) { | |
1360 | NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n", | |
1361 | ns->regs.num); | |
1362 | return; | |
1363 | } | |
1364 | ||
1365 | if (ns->busw == 8) { | |
1366 | ns->buf.byte[ns->regs.count] = byte; | |
1367 | ns->regs.count += 1; | |
1368 | } else { | |
1369 | ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte); | |
1370 | ns->regs.count += 2; | |
1371 | } | |
1372 | } | |
1373 | ||
1374 | return; | |
1375 | } | |
1376 | ||
7abd3ef9 TG |
1377 | static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask) |
1378 | { | |
1379 | struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; | |
1380 | ||
1381 | ns->lines.cle = bitmask & NAND_CLE ? 1 : 0; | |
1382 | ns->lines.ale = bitmask & NAND_ALE ? 1 : 0; | |
1383 | ns->lines.ce = bitmask & NAND_NCE ? 1 : 0; | |
1384 | ||
1385 | if (cmd != NAND_CMD_NONE) | |
1386 | ns_nand_write_byte(mtd, cmd); | |
1387 | } | |
1388 | ||
a5602146 | 1389 | static int ns_device_ready(struct mtd_info *mtd) |
1da177e4 LT |
1390 | { |
1391 | NS_DBG("device_ready\n"); | |
1392 | return 1; | |
1393 | } | |
1394 | ||
a5602146 | 1395 | static uint16_t ns_nand_read_word(struct mtd_info *mtd) |
1da177e4 LT |
1396 | { |
1397 | struct nand_chip *chip = (struct nand_chip *)mtd->priv; | |
1398 | ||
1399 | NS_DBG("read_word\n"); | |
61b03bd7 | 1400 | |
1da177e4 LT |
1401 | return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8); |
1402 | } | |
1403 | ||
a5602146 | 1404 | static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
1da177e4 LT |
1405 | { |
1406 | struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv; | |
1407 | ||
1408 | /* Check that chip is expecting data input */ | |
1409 | if (!(ns->state & STATE_DATAIN_MASK)) { | |
1410 | NS_ERR("write_buf: data input isn't expected, state is %s, " | |
1411 | "switch to STATE_READY\n", get_state_name(ns->state)); | |
1412 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1413 | return; | |
1414 | } | |
1415 | ||
1416 | /* Check if these are expected bytes */ | |
1417 | if (ns->regs.count + len > ns->regs.num) { | |
1418 | NS_ERR("write_buf: too many input bytes\n"); | |
1419 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1420 | return; | |
1421 | } | |
1422 | ||
1423 | memcpy(ns->buf.byte + ns->regs.count, buf, len); | |
1424 | ns->regs.count += len; | |
61b03bd7 | 1425 | |
1da177e4 LT |
1426 | if (ns->regs.count == ns->regs.num) { |
1427 | NS_DBG("write_buf: %d bytes were written\n", ns->regs.count); | |
1428 | } | |
1429 | } | |
1430 | ||
a5602146 | 1431 | static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
1da177e4 LT |
1432 | { |
1433 | struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv; | |
1434 | ||
1435 | /* Sanity and correctness checks */ | |
1436 | if (!ns->lines.ce) { | |
1437 | NS_ERR("read_buf: chip is disabled\n"); | |
1438 | return; | |
1439 | } | |
1440 | if (ns->lines.ale || ns->lines.cle) { | |
1441 | NS_ERR("read_buf: ALE or CLE pin is high\n"); | |
1442 | return; | |
1443 | } | |
1444 | if (!(ns->state & STATE_DATAOUT_MASK)) { | |
1445 | NS_WARN("read_buf: unexpected data output cycle, current state is %s\n", | |
1446 | get_state_name(ns->state)); | |
1447 | return; | |
1448 | } | |
1449 | ||
1450 | if (NS_STATE(ns->state) != STATE_DATAOUT) { | |
1451 | int i; | |
1452 | ||
1453 | for (i = 0; i < len; i++) | |
1454 | buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd); | |
1455 | ||
1456 | return; | |
1457 | } | |
1458 | ||
1459 | /* Check if these are expected bytes */ | |
1460 | if (ns->regs.count + len > ns->regs.num) { | |
1461 | NS_ERR("read_buf: too many bytes to read\n"); | |
1462 | switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); | |
1463 | return; | |
1464 | } | |
1465 | ||
1466 | memcpy(buf, ns->buf.byte + ns->regs.count, len); | |
1467 | ns->regs.count += len; | |
61b03bd7 | 1468 | |
1da177e4 LT |
1469 | if (ns->regs.count == ns->regs.num) { |
1470 | if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) { | |
1471 | ns->regs.count = 0; | |
1472 | if (ns->regs.row + 1 < ns->geom.pgnum) | |
1473 | ns->regs.row += 1; | |
1474 | NS_DBG("read_buf: switch to the next page (%#x)\n", ns->regs.row); | |
1475 | do_state_action(ns, ACTION_CPY); | |
1476 | } | |
1477 | else if (NS_STATE(ns->nxstate) == STATE_READY) | |
1478 | switch_state(ns); | |
1479 | } | |
61b03bd7 | 1480 | |
1da177e4 LT |
1481 | return; |
1482 | } | |
1483 | ||
a5602146 | 1484 | static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
1da177e4 LT |
1485 | { |
1486 | ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len); | |
1487 | ||
1488 | if (!memcmp(buf, &ns_verify_buf[0], len)) { | |
1489 | NS_DBG("verify_buf: the buffer is OK\n"); | |
1490 | return 0; | |
1491 | } else { | |
1492 | NS_DBG("verify_buf: the buffer is wrong\n"); | |
1493 | return -EFAULT; | |
1494 | } | |
1495 | } | |
1496 | ||
1da177e4 LT |
1497 | /* |
1498 | * Module initialization function | |
1499 | */ | |
2b9175c1 | 1500 | static int __init ns_init_module(void) |
1da177e4 LT |
1501 | { |
1502 | struct nand_chip *chip; | |
1503 | struct nandsim *nand; | |
1504 | int retval = -ENOMEM; | |
1505 | ||
1506 | if (bus_width != 8 && bus_width != 16) { | |
1507 | NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width); | |
1508 | return -EINVAL; | |
1509 | } | |
61b03bd7 | 1510 | |
1da177e4 LT |
1511 | /* Allocate and initialize mtd_info, nand_chip and nandsim structures */ |
1512 | nsmtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip) | |
1513 | + sizeof(struct nandsim), GFP_KERNEL); | |
1514 | if (!nsmtd) { | |
1515 | NS_ERR("unable to allocate core structures.\n"); | |
1516 | return -ENOMEM; | |
1517 | } | |
1518 | memset(nsmtd, 0, sizeof(struct mtd_info) + sizeof(struct nand_chip) + | |
1519 | sizeof(struct nandsim)); | |
1520 | chip = (struct nand_chip *)(nsmtd + 1); | |
1521 | nsmtd->priv = (void *)chip; | |
1522 | nand = (struct nandsim *)(chip + 1); | |
61b03bd7 | 1523 | chip->priv = (void *)nand; |
1da177e4 LT |
1524 | |
1525 | /* | |
1526 | * Register simulator's callbacks. | |
1527 | */ | |
7abd3ef9 | 1528 | chip->cmd_ctrl = ns_hwcontrol; |
1da177e4 LT |
1529 | chip->read_byte = ns_nand_read_byte; |
1530 | chip->dev_ready = ns_device_ready; | |
1da177e4 LT |
1531 | chip->write_buf = ns_nand_write_buf; |
1532 | chip->read_buf = ns_nand_read_buf; | |
1533 | chip->verify_buf = ns_nand_verify_buf; | |
1da177e4 | 1534 | chip->read_word = ns_nand_read_word; |
6dfc6d25 | 1535 | chip->ecc.mode = NAND_ECC_SOFT; |
51502287 | 1536 | chip->options |= NAND_SKIP_BBTSCAN; |
1da177e4 | 1537 | |
61b03bd7 | 1538 | /* |
1da177e4 | 1539 | * Perform minimum nandsim structure initialization to handle |
61b03bd7 | 1540 | * the initial ID read command correctly |
1da177e4 LT |
1541 | */ |
1542 | if (third_id_byte != 0xFF || fourth_id_byte != 0xFF) | |
1543 | nand->geom.idbytes = 4; | |
1544 | else | |
1545 | nand->geom.idbytes = 2; | |
1546 | nand->regs.status = NS_STATUS_OK(nand); | |
1547 | nand->nxstate = STATE_UNKNOWN; | |
1548 | nand->options |= OPT_PAGE256; /* temporary value */ | |
1549 | nand->ids[0] = first_id_byte; | |
1550 | nand->ids[1] = second_id_byte; | |
1551 | nand->ids[2] = third_id_byte; | |
1552 | nand->ids[3] = fourth_id_byte; | |
1553 | if (bus_width == 16) { | |
1554 | nand->busw = 16; | |
1555 | chip->options |= NAND_BUSWIDTH_16; | |
1556 | } | |
1557 | ||
552d9205 DW |
1558 | nsmtd->owner = THIS_MODULE; |
1559 | ||
1da177e4 LT |
1560 | if ((retval = nand_scan(nsmtd, 1)) != 0) { |
1561 | NS_ERR("can't register NAND Simulator\n"); | |
1562 | if (retval > 0) | |
1563 | retval = -ENXIO; | |
1564 | goto error; | |
1565 | } | |
1566 | ||
51502287 AB |
1567 | if ((retval = init_nandsim(nsmtd)) != 0) { |
1568 | NS_ERR("scan_bbt: can't initialize the nandsim structure\n"); | |
1569 | goto error; | |
1570 | } | |
61b03bd7 | 1571 | |
51502287 AB |
1572 | if ((retval = nand_default_bbt(nsmtd)) != 0) { |
1573 | free_nandsim(nand); | |
1574 | goto error; | |
1575 | } | |
1576 | ||
1da177e4 LT |
1577 | /* Register NAND as one big partition */ |
1578 | add_mtd_partitions(nsmtd, &nand->part, 1); | |
1579 | ||
1580 | return 0; | |
1581 | ||
1582 | error: | |
1583 | kfree(nsmtd); | |
1584 | ||
1585 | return retval; | |
1586 | } | |
1587 | ||
1588 | module_init(ns_init_module); | |
1589 | ||
1590 | /* | |
1591 | * Module clean-up function | |
1592 | */ | |
1593 | static void __exit ns_cleanup_module(void) | |
1594 | { | |
1595 | struct nandsim *ns = (struct nandsim *)(((struct nand_chip *)nsmtd->priv)->priv); | |
1596 | ||
1597 | free_nandsim(ns); /* Free nandsim private resources */ | |
1598 | nand_release(nsmtd); /* Unregisterd drived */ | |
1599 | kfree(nsmtd); /* Free other structures */ | |
1600 | } | |
1601 | ||
1602 | module_exit(ns_cleanup_module); | |
1603 | ||
1604 | MODULE_LICENSE ("GPL"); | |
1605 | MODULE_AUTHOR ("Artem B. Bityuckiy"); | |
1606 | MODULE_DESCRIPTION ("The NAND flash simulator"); | |
1607 |