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mtd: add new fields to nand_flash_dev{}
[linux-2.6-block.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
38#include <linux/types.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/nand_ecc.h>
193bd400 42#include <linux/mtd/nand_bch.h>
1da177e4
LT		 43#include <linux/interrupt.h>
44#include <linux/bitops.h>
8fe833c1 45#include <linux/leds.h>
7351d3a5 46#include <linux/io.h>
1da177e4 47#include <linux/mtd/partitions.h>
1da177e4
LT		 48
49/* Define default oob placement schemes for large and small page devices */
5bd34c09 50static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 51 .eccbytes = 3,
52 .eccpos = {0, 1, 2},
5bd34c09
TG		 53 .oobfree = {
54 {.offset = 3,
55 .length = 2},
56 {.offset = 6,
f8ac0414 57 .length = 2} }
1da177e4
LT		 58};
59
5bd34c09 60static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 61 .eccbytes = 6,
62 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 63 .oobfree = {
64 {.offset = 8,
f8ac0414 65 . length = 8} }
1da177e4
LT		 66};
67
5bd34c09 68static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 69 .eccbytes = 24,
70 .eccpos = {
e0c7d767
DW		 71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 74 .oobfree = {
75 {.offset = 2,
f8ac0414 76 .length = 38} }
1da177e4
LT		 77};
78
81ec5364
TG		 79static struct nand_ecclayout nand_oob_128 = {
80 .eccbytes = 48,
81 .eccpos = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
88 .oobfree = {
89 {.offset = 2,
f8ac0414 90 .length = 78} }
81ec5364
TG		 91};
92
6a8214aa 93static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 94
8593fbc6
TG		 95static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
97
d470a97c 98/*
8e87d782 99 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 100 * compiled away when LED support is disabled.
101 */
102DEFINE_LED_TRIGGER(nand_led_trigger);
103
6fe5a6ac
VS		 104static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
106{
107 struct nand_chip *chip = mtd->priv;
108 int ret = 0;
109
110 /* Start address must align on block boundary */
111 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 112 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 113 ret = -EINVAL;
114 }
115
116 /* Length must align on block boundary */
117 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 118 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 119 ret = -EINVAL;
120 }
121
6fe5a6ac
VS		 122 return ret;
123}
124
1da177e4
LT		 125/**
126 * nand_release_device - [GENERIC] release chip
8b6e50c9 127 * @mtd: MTD device structure
61b03bd7 128 *
b0bb6903 129 * Release chip lock and wake up anyone waiting on the device.
1da177e4 130 */
e0c7d767 131static void nand_release_device(struct mtd_info *mtd)
1da177e4 132{
ace4dfee 133 struct nand_chip *chip = mtd->priv;
1da177e4 134
a36ed299 135 /* Release the controller and the chip */
ace4dfee
TG		 136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
1da177e4
LT		 141}
142
143/**
144 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 145 * @mtd: MTD device structure
1da177e4 146 *
7854d3f7 147 * Default read function for 8bit buswidth
1da177e4 148 */
58dd8f2b 149static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 150{
ace4dfee
TG		 151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
1da177e4
LT		 153}
154
1da177e4 155/**
064a7694 156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
7854d3f7 157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 158 * @mtd: MTD device structure
1da177e4 159 *
7854d3f7
BN		 160 * Default read function for 16bit buswidth with endianness conversion.
161 *
1da177e4 162 */
58dd8f2b 163static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 164{
ace4dfee
TG		 165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 167}
168
1da177e4
LT		 169/**
170 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 171 * @mtd: MTD device structure
1da177e4 172 *
7854d3f7 173 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 174 */
175static u16 nand_read_word(struct mtd_info *mtd)
176{
ace4dfee
TG		 177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
1da177e4
LT		 179}
180
1da177e4
LT		 181/**
182 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 185 *
186 * Default select function for 1 chip devices.
187 */
ace4dfee 188static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 189{
ace4dfee
TG		 190 struct nand_chip *chip = mtd->priv;
191
192 switch (chipnr) {
1da177e4 193 case -1:
ace4dfee 194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 195 break;
196 case 0:
1da177e4
LT		 197 break;
198
199 default:
200 BUG();
201 }
202}
203
204/**
205 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 206 * @mtd: MTD device structure
207 * @buf: data buffer
208 * @len: number of bytes to write
1da177e4 209 *
7854d3f7 210 * Default write function for 8bit buswidth.
1da177e4 211 */
58dd8f2b 212static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 213{
214 int i;
ace4dfee 215 struct nand_chip *chip = mtd->priv;
1da177e4 216
e0c7d767 217 for (i = 0; i < len; i++)
ace4dfee 218 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 219}
220
221/**
61b03bd7 222 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 223 * @mtd: MTD device structure
224 * @buf: buffer to store date
225 * @len: number of bytes to read
1da177e4 226 *
7854d3f7 227 * Default read function for 8bit buswidth.
1da177e4 228 */
58dd8f2b 229static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 230{
231 int i;
ace4dfee 232 struct nand_chip *chip = mtd->priv;
1da177e4 233
e0c7d767 234 for (i = 0; i < len; i++)
ace4dfee 235 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 236}
237
1da177e4
LT		 238/**
239 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 240 * @mtd: MTD device structure
241 * @buf: data buffer
242 * @len: number of bytes to write
1da177e4 243 *
7854d3f7 244 * Default write function for 16bit buswidth.
1da177e4 245 */
58dd8f2b 246static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 247{
248 int i;
ace4dfee 249 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 250 u16 *p = (u16 *) buf;
251 len >>= 1;
61b03bd7 252
e0c7d767 253 for (i = 0; i < len; i++)
ace4dfee 254 writew(p[i], chip->IO_ADDR_W);
61b03bd7 255
1da177e4
LT		 256}
257
258/**
61b03bd7 259 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 260 * @mtd: MTD device structure
261 * @buf: buffer to store date
262 * @len: number of bytes to read
1da177e4 263 *
7854d3f7 264 * Default read function for 16bit buswidth.
1da177e4 265 */
58dd8f2b 266static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 267{
268 int i;
ace4dfee 269 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 270 u16 *p = (u16 *) buf;
271 len >>= 1;
272
e0c7d767 273 for (i = 0; i < len; i++)
ace4dfee 274 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 275}
276
1da177e4
LT		 277/**
278 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 279 * @mtd: MTD device structure
280 * @ofs: offset from device start
281 * @getchip: 0, if the chip is already selected
1da177e4 282 *
61b03bd7 283 * Check, if the block is bad.
1da177e4
LT		 284 */
285static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
286{
cdbec050 287 int page, chipnr, res = 0, i = 0;
ace4dfee 288 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 289 u16 bad;
290
5fb1549d 291 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 292 ofs += mtd->erasesize - mtd->writesize;
293
1a12f46a
TK		 294 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
295
1da177e4 296 if (getchip) {
ace4dfee 297 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 298
6a8214aa 299 nand_get_device(mtd, FL_READING);
1da177e4
LT		 300
301 /* Select the NAND device */
ace4dfee 302 chip->select_chip(mtd, chipnr);
1a12f46a 303 }
1da177e4 304
cdbec050
BN		 305 do {
306 if (chip->options & NAND_BUSWIDTH_16) {
307 chip->cmdfunc(mtd, NAND_CMD_READOOB,
308 chip->badblockpos & 0xFE, page);
309 bad = cpu_to_le16(chip->read_word(mtd));
310 if (chip->badblockpos & 0x1)
311 bad >>= 8;
312 else
313 bad &= 0xFF;
314 } else {
315 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
316 page);
317 bad = chip->read_byte(mtd);
318 }
319
320 if (likely(chip->badblockbits == 8))
321 res = bad != 0xFF;
e0b58d0a 322 else
cdbec050
BN		 323 res = hweight8(bad) < chip->badblockbits;
324 ofs += mtd->writesize;
325 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
326 i++;
327 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 328
b0bb6903
HS		 329 if (getchip) {
330 chip->select_chip(mtd, -1);
1da177e4 331 nand_release_device(mtd);
b0bb6903 332 }
61b03bd7 333
1da177e4
LT		 334 return res;
335}
336
337/**
338 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 339 * @mtd: MTD device structure
340 * @ofs: offset from device start
1da177e4 341 *
8b6e50c9 342 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 343 * specific driver. We try operations in the following order, according to our
344 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
345 * (1) erase the affected block, to allow OOB marker to be written cleanly
346 * (2) update in-memory BBT
347 * (3) write bad block marker to OOB area of affected block
348 * (4) update flash-based BBT
349 * Note that we retain the first error encountered in (3) or (4), finish the
350 * procedures, and dump the error in the end.
1da177e4
LT		 351*/
352static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
353{
ace4dfee 354 struct nand_chip *chip = mtd->priv;
58dd8f2b 355 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 356 int block, res, ret = 0, i = 0;
357 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 358
e2414f4c 359 if (write_oob) {
00918429
BN		 360 struct erase_info einfo;
361
362 /* Attempt erase before marking OOB */
363 memset(&einfo, 0, sizeof(einfo));
364 einfo.mtd = mtd;
365 einfo.addr = ofs;
366 einfo.len = 1 << chip->phys_erase_shift;
367 nand_erase_nand(mtd, &einfo, 0);
368 }
369
1da177e4 370 /* Get block number */
4226b510 371 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 372 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 373 if (chip->bbt)
374 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 375
e2414f4c
BN		 376 /* Write bad block marker to OOB */
377 if (write_oob) {
4a89ff88 378 struct mtd_oob_ops ops;
df698621 379 loff_t wr_ofs = ofs;
4a89ff88 380
6a8214aa 381 nand_get_device(mtd, FL_WRITING);
f1a28c02 382
4a89ff88
BN		 383 ops.datbuf = NULL;
384 ops.oobbuf = buf;
85443319
BN		 385 ops.ooboffs = chip->badblockpos;
386 if (chip->options & NAND_BUSWIDTH_16) {
387 ops.ooboffs &= ~0x01;
388 ops.len = ops.ooblen = 2;
389 } else {
390 ops.len = ops.ooblen = 1;
391 }
23b1a99b 392 ops.mode = MTD_OPS_PLACE_OOB;
df698621 393
e2414f4c 394 /* Write to first/last page(s) if necessary */
df698621
BN		 395 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
396 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 397 do {
e2414f4c
BN		 398 res = nand_do_write_oob(mtd, wr_ofs, &ops);
399 if (!ret)
400 ret = res;
02ed70bb 401
02ed70bb 402 i++;
df698621 403 wr_ofs += mtd->writesize;
e2414f4c 404 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 405
c0b8ba7b 406 nand_release_device(mtd);
f1a28c02 407 }
e2414f4c
BN		 408
409 /* Update flash-based bad block table */
410 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
411 res = nand_update_bbt(mtd, ofs);
412 if (!ret)
413 ret = res;
414 }
415
f1a28c02
TG		 416 if (!ret)
417 mtd->ecc_stats.badblocks++;
c0b8ba7b 418
f1a28c02 419 return ret;
1da177e4
LT		 420}
421
61b03bd7 422/**
1da177e4 423 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 424 * @mtd: MTD device structure
1da177e4 425 *
8b6e50c9
BN		 426 * Check, if the device is write protected. The function expects, that the
427 * device is already selected.
1da177e4 428 */
e0c7d767 429static int nand_check_wp(struct mtd_info *mtd)
1da177e4 430{
ace4dfee 431 struct nand_chip *chip = mtd->priv;
93edbad6 432
8b6e50c9 433 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 434 if (chip->options & NAND_BROKEN_XD)
435 return 0;
436
1da177e4 437 /* Check the WP bit */
ace4dfee
TG		 438 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
439 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 440}
441
442/**
443 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 444 * @mtd: MTD device structure
445 * @ofs: offset from device start
446 * @getchip: 0, if the chip is already selected
447 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 448 *
449 * Check, if the block is bad. Either by reading the bad block table or
450 * calling of the scan function.
451 */
2c0a2bed
TG		 452static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
453 int allowbbt)
1da177e4 454{
ace4dfee 455 struct nand_chip *chip = mtd->priv;
61b03bd7 456
ace4dfee
TG		 457 if (!chip->bbt)
458 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 459
1da177e4 460 /* Return info from the table */
e0c7d767 461 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 462}
463
2af7c653
SK		 464/**
465 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 466 * @mtd: MTD device structure
467 * @timeo: Timeout
2af7c653
SK		 468 *
469 * Helper function for nand_wait_ready used when needing to wait in interrupt
470 * context.
471 */
472static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
473{
474 struct nand_chip *chip = mtd->priv;
475 int i;
476
477 /* Wait for the device to get ready */
478 for (i = 0; i < timeo; i++) {
479 if (chip->dev_ready(mtd))
480 break;
481 touch_softlockup_watchdog();
482 mdelay(1);
483 }
484}
485
7854d3f7 486/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 487void nand_wait_ready(struct mtd_info *mtd)
3b88775c 488{
ace4dfee 489 struct nand_chip *chip = mtd->priv;
ca6a2489 490 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 491
2af7c653
SK		 492 /* 400ms timeout */
493 if (in_interrupt() || oops_in_progress)
494 return panic_nand_wait_ready(mtd, 400);
495
8fe833c1 496 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 497 /* Wait until command is processed or timeout occurs */
3b88775c 498 do {
ace4dfee 499 if (chip->dev_ready(mtd))
8fe833c1 500 break;
8446f1d3 501 touch_softlockup_watchdog();
61b03bd7 502 } while (time_before(jiffies, timeo));
8fe833c1 503 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 504}
4b648b02 505EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 506
1da177e4
LT		 507/**
508 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 509 * @mtd: MTD device structure
510 * @command: the command to be sent
511 * @column: the column address for this command, -1 if none
512 * @page_addr: the page address for this command, -1 if none
1da177e4 513 *
8b6e50c9 514 * Send command to NAND device. This function is used for small page devices
51148f1f 515 * (512 Bytes per page).
1da177e4 516 */
7abd3ef9
TG		 517static void nand_command(struct mtd_info *mtd, unsigned int command,
518 int column, int page_addr)
1da177e4 519{
ace4dfee 520 register struct nand_chip *chip = mtd->priv;
7abd3ef9 521 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 522
8b6e50c9 523 /* Write out the command to the device */
1da177e4
LT		 524 if (command == NAND_CMD_SEQIN) {
525 int readcmd;
526
28318776 527 if (column >= mtd->writesize) {
1da177e4 528 /* OOB area */
28318776 529 column -= mtd->writesize;
1da177e4
LT		 530 readcmd = NAND_CMD_READOOB;
531 } else if (column < 256) {
532 /* First 256 bytes --> READ0 */
533 readcmd = NAND_CMD_READ0;
534 } else {
535 column -= 256;
536 readcmd = NAND_CMD_READ1;
537 }
ace4dfee 538 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 539 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 540 }
ace4dfee 541 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 542
8b6e50c9 543 /* Address cycle, when necessary */
7abd3ef9
TG		 544 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
545 /* Serially input address */
546 if (column != -1) {
547 /* Adjust columns for 16 bit buswidth */
ace4dfee 548 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 549 column >>= 1;
ace4dfee 550 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 551 ctrl &= ~NAND_CTRL_CHANGE;
552 }
553 if (page_addr != -1) {
ace4dfee 554 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 555 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 556 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 557 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 558 if (chip->chipsize > (32 << 20))
559 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 560 }
ace4dfee 561 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 562
563 /*
8b6e50c9
BN		 564 * Program and erase have their own busy handlers status and sequential
565 * in needs no delay
e0c7d767 566 */
1da177e4 567 switch (command) {
61b03bd7 568
1da177e4
LT		 569 case NAND_CMD_PAGEPROG:
570 case NAND_CMD_ERASE1:
571 case NAND_CMD_ERASE2:
572 case NAND_CMD_SEQIN:
573 case NAND_CMD_STATUS:
574 return;
575
576 case NAND_CMD_RESET:
ace4dfee 577 if (chip->dev_ready)
1da177e4 578 break;
ace4dfee
TG		 579 udelay(chip->chip_delay);
580 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 581 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 582 chip->cmd_ctrl(mtd,
583 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 584 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
585 ;
1da177e4
LT		 586 return;
587
e0c7d767 588 /* This applies to read commands */
1da177e4 589 default:
61b03bd7 590 /*
1da177e4
LT		 591 * If we don't have access to the busy pin, we apply the given
592 * command delay
e0c7d767 593 */
ace4dfee
TG		 594 if (!chip->dev_ready) {
595 udelay(chip->chip_delay);
1da177e4 596 return;
61b03bd7 597 }
1da177e4 598 }
8b6e50c9
BN		 599 /*
600 * Apply this short delay always to ensure that we do wait tWB in
601 * any case on any machine.
602 */
e0c7d767 603 ndelay(100);
3b88775c
TG		 604
605 nand_wait_ready(mtd);
1da177e4
LT		 606}
607
608/**
609 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 610 * @mtd: MTD device structure
611 * @command: the command to be sent
612 * @column: the column address for this command, -1 if none
613 * @page_addr: the page address for this command, -1 if none
1da177e4 614 *
7abd3ef9 615 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 616 * devices. We don't have the separate regions as we have in the small page
617 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 618 */
7abd3ef9
TG		 619static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
620 int column, int page_addr)
1da177e4 621{
ace4dfee 622 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 623
624 /* Emulate NAND_CMD_READOOB */
625 if (command == NAND_CMD_READOOB) {
28318776 626 column += mtd->writesize;
1da177e4
LT		 627 command = NAND_CMD_READ0;
628 }
61b03bd7 629
7abd3ef9 630 /* Command latch cycle */
fb066ada 631 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 632
633 if (column != -1 || page_addr != -1) {
7abd3ef9 634 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 635
636 /* Serially input address */
637 if (column != -1) {
638 /* Adjust columns for 16 bit buswidth */
ace4dfee 639 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 640 column >>= 1;
ace4dfee 641 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 642 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 643 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 644 }
1da177e4 645 if (page_addr != -1) {
ace4dfee
TG		 646 chip->cmd_ctrl(mtd, page_addr, ctrl);
647 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 648 NAND_NCE | NAND_ALE);
1da177e4 649 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 650 if (chip->chipsize > (128 << 20))
651 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 652 NAND_NCE | NAND_ALE);
1da177e4 653 }
1da177e4 654 }
ace4dfee 655 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 656
657 /*
8b6e50c9
BN		 658 * Program and erase have their own busy handlers status, sequential
659 * in, and deplete1 need no delay.
30f464b7 660 */
1da177e4 661 switch (command) {
61b03bd7 662
1da177e4
LT		 663 case NAND_CMD_CACHEDPROG:
664 case NAND_CMD_PAGEPROG:
665 case NAND_CMD_ERASE1:
666 case NAND_CMD_ERASE2:
667 case NAND_CMD_SEQIN:
7bc3312b 668 case NAND_CMD_RNDIN:
1da177e4 669 case NAND_CMD_STATUS:
30f464b7 670 return;
1da177e4
LT		 671
672 case NAND_CMD_RESET:
ace4dfee 673 if (chip->dev_ready)
1da177e4 674 break;
ace4dfee 675 udelay(chip->chip_delay);
12efdde3
TG		 676 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
677 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
678 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
679 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 680 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
681 ;
1da177e4
LT		 682 return;
683
7bc3312b
TG		 684 case NAND_CMD_RNDOUT:
685 /* No ready / busy check necessary */
686 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
687 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
688 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
689 NAND_NCE | NAND_CTRL_CHANGE);
690 return;
691
1da177e4 692 case NAND_CMD_READ0:
12efdde3
TG		 693 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
694 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
695 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
696 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 697
e0c7d767 698 /* This applies to read commands */
1da177e4 699 default:
61b03bd7 700 /*
1da177e4 701 * If we don't have access to the busy pin, we apply the given
8b6e50c9 702 * command delay.
e0c7d767 703 */
ace4dfee
TG		 704 if (!chip->dev_ready) {
705 udelay(chip->chip_delay);
1da177e4 706 return;
61b03bd7 707 }
1da177e4 708 }
3b88775c 709
8b6e50c9
BN		 710 /*
711 * Apply this short delay always to ensure that we do wait tWB in
712 * any case on any machine.
713 */
e0c7d767 714 ndelay(100);
3b88775c
TG		 715
716 nand_wait_ready(mtd);
1da177e4
LT		 717}
718
2af7c653
SK		 719/**
720 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 721 * @chip: the nand chip descriptor
722 * @mtd: MTD device structure
723 * @new_state: the state which is requested
2af7c653
SK		 724 *
725 * Used when in panic, no locks are taken.
726 */
727static void panic_nand_get_device(struct nand_chip *chip,
728 struct mtd_info *mtd, int new_state)
729{
7854d3f7 730 /* Hardware controller shared among independent devices */
2af7c653
SK		 731 chip->controller->active = chip;
732 chip->state = new_state;
733}
734
1da177e4
LT		 735/**
736 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 737 * @mtd: MTD device structure
738 * @new_state: the state which is requested
1da177e4
LT		 739 *
740 * Get the device and lock it for exclusive access
741 */
2c0a2bed 742static int
6a8214aa 743nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 744{
6a8214aa 745 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 746 spinlock_t *lock = &chip->controller->lock;
747 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 748 DECLARE_WAITQUEUE(wait, current);
7351d3a5 749retry:
0dfc6246
TG		 750 spin_lock(lock);
751
b8b3ee9a 752 /* Hardware controller shared among independent devices */
ace4dfee
TG		 753 if (!chip->controller->active)
754 chip->controller->active = chip;
a36ed299 755
ace4dfee
TG		 756 if (chip->controller->active == chip && chip->state == FL_READY) {
757 chip->state = new_state;
0dfc6246 758 spin_unlock(lock);
962034f4
VW		 759 return 0;
760 }
761 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 762 if (chip->controller->active->state == FL_PM_SUSPENDED) {
763 chip->state = FL_PM_SUSPENDED;
764 spin_unlock(lock);
765 return 0;
6b0d9a84 766 }
0dfc6246
TG		 767 }
768 set_current_state(TASK_UNINTERRUPTIBLE);
769 add_wait_queue(wq, &wait);
770 spin_unlock(lock);
771 schedule();
772 remove_wait_queue(wq, &wait);
1da177e4
LT		 773 goto retry;
774}
775
2af7c653 776/**
8b6e50c9
BN		 777 * panic_nand_wait - [GENERIC] wait until the command is done
778 * @mtd: MTD device structure
779 * @chip: NAND chip structure
780 * @timeo: timeout
2af7c653
SK		 781 *
782 * Wait for command done. This is a helper function for nand_wait used when
783 * we are in interrupt context. May happen when in panic and trying to write
b595076a 784 * an oops through mtdoops.
2af7c653
SK		 785 */
786static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
787 unsigned long timeo)
788{
789 int i;
790 for (i = 0; i < timeo; i++) {
791 if (chip->dev_ready) {
792 if (chip->dev_ready(mtd))
793 break;
794 } else {
795 if (chip->read_byte(mtd) & NAND_STATUS_READY)
796 break;
797 }
798 mdelay(1);
f8ac0414 799 }
2af7c653
SK		 800}
801
1da177e4 802/**
8b6e50c9
BN		 803 * nand_wait - [DEFAULT] wait until the command is done
804 * @mtd: MTD device structure
805 * @chip: NAND chip structure
1da177e4 806 *
8b6e50c9
BN		 807 * Wait for command done. This applies to erase and program only. Erase can
808 * take up to 400ms and program up to 20ms according to general NAND and
809 * SmartMedia specs.
844d3b42 810 */
7bc3312b 811static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 812{
813
7bc3312b 814 int status, state = chip->state;
6d2559f8 815 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 816
8fe833c1
RP		 817 led_trigger_event(nand_led_trigger, LED_FULL);
818
8b6e50c9
BN		 819 /*
820 * Apply this short delay always to ensure that we do wait tWB in any
821 * case on any machine.
822 */
e0c7d767 823 ndelay(100);
1da177e4 824
14c65786 825 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 826
2af7c653
SK		 827 if (in_interrupt() || oops_in_progress)
828 panic_nand_wait(mtd, chip, timeo);
829 else {
6d2559f8 830 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 831 while (time_before(jiffies, timeo)) {
832 if (chip->dev_ready) {
833 if (chip->dev_ready(mtd))
834 break;
835 } else {
836 if (chip->read_byte(mtd) & NAND_STATUS_READY)
837 break;
838 }
839 cond_resched();
1da177e4 840 }
1da177e4 841 }
8fe833c1
RP		 842 led_trigger_event(nand_led_trigger, LED_OFF);
843
ace4dfee 844 status = (int)chip->read_byte(mtd);
f251b8df
MC		 845 /* This can happen if in case of timeout or buggy dev_ready */
846 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 847 return status;
848}
849
7d70f334 850/**
b6d676db 851 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 852 * @mtd: mtd info
853 * @ofs: offset to start unlock from
854 * @len: length to unlock
8b6e50c9
BN		 855 * @invert: when = 0, unlock the range of blocks within the lower and
856 * upper boundary address
857 * when = 1, unlock the range of blocks outside the boundaries
858 * of the lower and upper boundary address
7d70f334 859 *
8b6e50c9 860 * Returs unlock status.
7d70f334
VS		 861 */
862static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
863 uint64_t len, int invert)
864{
865 int ret = 0;
866 int status, page;
867 struct nand_chip *chip = mtd->priv;
868
869 /* Submit address of first page to unlock */
870 page = ofs >> chip->page_shift;
871 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
872
873 /* Submit address of last page to unlock */
874 page = (ofs + len) >> chip->page_shift;
875 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
876 (page | invert) & chip->pagemask);
877
878 /* Call wait ready function */
879 status = chip->waitfunc(mtd, chip);
7d70f334 880 /* See if device thinks it succeeded */
74830966 881 if (status & NAND_STATUS_FAIL) {
289c0522 882 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 883 __func__, status);
884 ret = -EIO;
885 }
886
887 return ret;
888}
889
890/**
b6d676db 891 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 892 * @mtd: mtd info
893 * @ofs: offset to start unlock from
894 * @len: length to unlock
7d70f334 895 *
8b6e50c9 896 * Returns unlock status.
7d70f334
VS		 897 */
898int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
899{
900 int ret = 0;
901 int chipnr;
902 struct nand_chip *chip = mtd->priv;
903
289c0522 904 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 905 __func__, (unsigned long long)ofs, len);
906
907 if (check_offs_len(mtd, ofs, len))
908 ret = -EINVAL;
909
910 /* Align to last block address if size addresses end of the device */
911 if (ofs + len == mtd->size)
912 len -= mtd->erasesize;
913
6a8214aa 914 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 915
916 /* Shift to get chip number */
917 chipnr = ofs >> chip->chip_shift;
918
919 chip->select_chip(mtd, chipnr);
920
921 /* Check, if it is write protected */
922 if (nand_check_wp(mtd)) {
289c0522 923 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 924 __func__);
925 ret = -EIO;
926 goto out;
927 }
928
929 ret = __nand_unlock(mtd, ofs, len, 0);
930
931out:
b0bb6903 932 chip->select_chip(mtd, -1);
7d70f334
VS		 933 nand_release_device(mtd);
934
935 return ret;
936}
7351d3a5 937EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 938
939/**
b6d676db 940 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 941 * @mtd: mtd info
942 * @ofs: offset to start unlock from
943 * @len: length to unlock
7d70f334 944 *
8b6e50c9
BN		 945 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
946 * have this feature, but it allows only to lock all blocks, not for specified
947 * range for block. Implementing 'lock' feature by making use of 'unlock', for
948 * now.
7d70f334 949 *
8b6e50c9 950 * Returns lock status.
7d70f334
VS		 951 */
952int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
953{
954 int ret = 0;
955 int chipnr, status, page;
956 struct nand_chip *chip = mtd->priv;
957
289c0522 958 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 959 __func__, (unsigned long long)ofs, len);
960
961 if (check_offs_len(mtd, ofs, len))
962 ret = -EINVAL;
963
6a8214aa 964 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 965
966 /* Shift to get chip number */
967 chipnr = ofs >> chip->chip_shift;
968
969 chip->select_chip(mtd, chipnr);
970
971 /* Check, if it is write protected */
972 if (nand_check_wp(mtd)) {
289c0522 973 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 974 __func__);
975 status = MTD_ERASE_FAILED;
976 ret = -EIO;
977 goto out;
978 }
979
980 /* Submit address of first page to lock */
981 page = ofs >> chip->page_shift;
982 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
983
984 /* Call wait ready function */
985 status = chip->waitfunc(mtd, chip);
7d70f334 986 /* See if device thinks it succeeded */
74830966 987 if (status & NAND_STATUS_FAIL) {
289c0522 988 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 989 __func__, status);
990 ret = -EIO;
991 goto out;
992 }
993
994 ret = __nand_unlock(mtd, ofs, len, 0x1);
995
996out:
b0bb6903 997 chip->select_chip(mtd, -1);
7d70f334
VS		 998 nand_release_device(mtd);
999
1000 return ret;
1001}
7351d3a5 1002EXPORT_SYMBOL(nand_lock);
7d70f334 1003
8593fbc6 1004/**
7854d3f7 1005 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1006 * @mtd: mtd info structure
1007 * @chip: nand chip info structure
1008 * @buf: buffer to store read data
1fbb938d 1009 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1010 * @page: page number to read
52ff49df 1011 *
7854d3f7 1012 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1013 */
1014static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1015 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1016{
1017 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1018 if (oob_required)
1019 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1020 return 0;
1021}
1022
52ff49df 1023/**
7854d3f7 1024 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1025 * @mtd: mtd info structure
1026 * @chip: nand chip info structure
1027 * @buf: buffer to store read data
1fbb938d 1028 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1029 * @page: page number to read
52ff49df
DB		 1030 *
1031 * We need a special oob layout and handling even when OOB isn't used.
1032 */
7351d3a5 1033static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1034 struct nand_chip *chip, uint8_t *buf,
1035 int oob_required, int page)
52ff49df
DB		 1036{
1037 int eccsize = chip->ecc.size;
1038 int eccbytes = chip->ecc.bytes;
1039 uint8_t *oob = chip->oob_poi;
1040 int steps, size;
1041
1042 for (steps = chip->ecc.steps; steps > 0; steps--) {
1043 chip->read_buf(mtd, buf, eccsize);
1044 buf += eccsize;
1045
1046 if (chip->ecc.prepad) {
1047 chip->read_buf(mtd, oob, chip->ecc.prepad);
1048 oob += chip->ecc.prepad;
1049 }
1050
1051 chip->read_buf(mtd, oob, eccbytes);
1052 oob += eccbytes;
1053
1054 if (chip->ecc.postpad) {
1055 chip->read_buf(mtd, oob, chip->ecc.postpad);
1056 oob += chip->ecc.postpad;
1057 }
1058 }
1059
1060 size = mtd->oobsize - (oob - chip->oob_poi);
1061 if (size)
1062 chip->read_buf(mtd, oob, size);
1063
1064 return 0;
1065}
1066
1da177e4 1067/**
7854d3f7 1068 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1069 * @mtd: mtd info structure
1070 * @chip: nand chip info structure
1071 * @buf: buffer to store read data
1fbb938d 1072 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1073 * @page: page number to read
068e3c0a 1074 */
f5bbdacc 1075static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1076 uint8_t *buf, int oob_required, int page)
1da177e4 1077{
f5bbdacc
TG		 1078 int i, eccsize = chip->ecc.size;
1079 int eccbytes = chip->ecc.bytes;
1080 int eccsteps = chip->ecc.steps;
1081 uint8_t *p = buf;
4bf63fcb
DW		 1082 uint8_t *ecc_calc = chip->buffers->ecccalc;
1083 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1084 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1085 unsigned int max_bitflips = 0;
f5bbdacc 1086
1fbb938d 1087 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1088
1089 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1090 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1091
1092 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1093 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1094
1095 eccsteps = chip->ecc.steps;
1096 p = buf;
1097
1098 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1099 int stat;
1100
1101 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1102 if (stat < 0) {
f5bbdacc 1103 mtd->ecc_stats.failed++;
3f91e94f 1104 } else {
f5bbdacc 1105 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1106 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1107 }
f5bbdacc 1108 }
3f91e94f 1109 return max_bitflips;
22c60f5f 1110}
1da177e4 1111
3d459559 1112/**
7854d3f7 1113 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1114 * @mtd: mtd info structure
1115 * @chip: nand chip info structure
1116 * @data_offs: offset of requested data within the page
1117 * @readlen: data length
1118 * @bufpoi: buffer to store read data
3d459559 1119 */
7351d3a5
FF		 1120static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1121 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1122{
1123 int start_step, end_step, num_steps;
1124 uint32_t *eccpos = chip->ecc.layout->eccpos;
1125 uint8_t *p;
1126 int data_col_addr, i, gaps = 0;
1127 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1128 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1129 int index = 0;
3f91e94f 1130 unsigned int max_bitflips = 0;
3d459559 1131
7854d3f7 1132 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1133 start_step = data_offs / chip->ecc.size;
1134 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1135 num_steps = end_step - start_step + 1;
1136
8b6e50c9 1137 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1138 datafrag_len = num_steps * chip->ecc.size;
1139 eccfrag_len = num_steps * chip->ecc.bytes;
1140
1141 data_col_addr = start_step * chip->ecc.size;
1142 /* If we read not a page aligned data */
1143 if (data_col_addr != 0)
1144 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1145
1146 p = bufpoi + data_col_addr;
1147 chip->read_buf(mtd, p, datafrag_len);
1148
8b6e50c9 1149 /* Calculate ECC */
3d459559
AK		 1150 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1151 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1152
8b6e50c9
BN		 1153 /*
1154 * The performance is faster if we position offsets according to
7854d3f7 1155 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1156 */
3d459559
AK		 1157 for (i = 0; i < eccfrag_len - 1; i++) {
1158 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1159 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1160 gaps = 1;
1161 break;
1162 }
1163 }
1164 if (gaps) {
1165 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1166 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1167 } else {
8b6e50c9 1168 /*
7854d3f7 1169 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1170 * about buswidth alignment in read_buf.
1171 */
7351d3a5
FF		 1172 index = start_step * chip->ecc.bytes;
1173
1174 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1175 aligned_len = eccfrag_len;
7351d3a5 1176 if (eccpos[index] & (busw - 1))
3d459559 1177 aligned_len++;
7351d3a5 1178 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1179 aligned_len++;
1180
7351d3a5
FF		 1181 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1182 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1183 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1184 }
1185
1186 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1187 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1188
1189 p = bufpoi + data_col_addr;
1190 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1191 int stat;
1192
7351d3a5
FF		 1193 stat = chip->ecc.correct(mtd, p,
1194 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1195 if (stat < 0) {
3d459559 1196 mtd->ecc_stats.failed++;
3f91e94f 1197 } else {
3d459559 1198 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1199 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1200 }
3d459559 1201 }
3f91e94f 1202 return max_bitflips;
3d459559
AK		 1203}
1204
068e3c0a 1205/**
7854d3f7 1206 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1207 * @mtd: mtd info structure
1208 * @chip: nand chip info structure
1209 * @buf: buffer to store read data
1fbb938d 1210 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1211 * @page: page number to read
068e3c0a 1212 *
7854d3f7 1213 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1214 */
f5bbdacc 1215static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1216 uint8_t *buf, int oob_required, int page)
1da177e4 1217{
f5bbdacc
TG		 1218 int i, eccsize = chip->ecc.size;
1219 int eccbytes = chip->ecc.bytes;
1220 int eccsteps = chip->ecc.steps;
1221 uint8_t *p = buf;
4bf63fcb
DW		 1222 uint8_t *ecc_calc = chip->buffers->ecccalc;
1223 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1224 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1225 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1226
1227 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1228 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1229 chip->read_buf(mtd, p, eccsize);
1230 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1231 }
f75e5097 1232 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1233
f5bbdacc 1234 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1235 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1236
f5bbdacc
TG		 1237 eccsteps = chip->ecc.steps;
1238 p = buf;
61b03bd7 1239
f5bbdacc
TG		 1240 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1241 int stat;
1da177e4 1242
f5bbdacc 1243 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1244 if (stat < 0) {
f5bbdacc 1245 mtd->ecc_stats.failed++;
3f91e94f 1246 } else {
f5bbdacc 1247 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1248 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1249 }
f5bbdacc 1250 }
3f91e94f 1251 return max_bitflips;
f5bbdacc 1252}
1da177e4 1253
6e0cb135 1254/**
7854d3f7 1255 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1256 * @mtd: mtd info structure
1257 * @chip: nand chip info structure
1258 * @buf: buffer to store read data
1fbb938d 1259 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1260 * @page: page number to read
6e0cb135 1261 *
8b6e50c9
BN		 1262 * Hardware ECC for large page chips, require OOB to be read first. For this
1263 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1264 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1265 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1266 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1267 */
1268static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1269 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1270{
1271 int i, eccsize = chip->ecc.size;
1272 int eccbytes = chip->ecc.bytes;
1273 int eccsteps = chip->ecc.steps;
1274 uint8_t *p = buf;
1275 uint8_t *ecc_code = chip->buffers->ecccode;
1276 uint32_t *eccpos = chip->ecc.layout->eccpos;
1277 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1278 unsigned int max_bitflips = 0;
6e0cb135
SN		 1279
1280 /* Read the OOB area first */
1281 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1282 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1283 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1284
1285 for (i = 0; i < chip->ecc.total; i++)
1286 ecc_code[i] = chip->oob_poi[eccpos[i]];
1287
1288 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289 int stat;
1290
1291 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1292 chip->read_buf(mtd, p, eccsize);
1293 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1294
1295 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1296 if (stat < 0) {
6e0cb135 1297 mtd->ecc_stats.failed++;
3f91e94f 1298 } else {
6e0cb135 1299 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1300 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1301 }
6e0cb135 1302 }
3f91e94f 1303 return max_bitflips;
6e0cb135
SN		 1304}
1305
f5bbdacc 1306/**
7854d3f7 1307 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1308 * @mtd: mtd info structure
1309 * @chip: nand chip info structure
1310 * @buf: buffer to store read data
1fbb938d 1311 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1312 * @page: page number to read
f5bbdacc 1313 *
8b6e50c9
BN		 1314 * The hw generator calculates the error syndrome automatically. Therefore we
1315 * need a special oob layout and handling.
f5bbdacc
TG		 1316 */
1317static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1318 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1319{
1320 int i, eccsize = chip->ecc.size;
1321 int eccbytes = chip->ecc.bytes;
1322 int eccsteps = chip->ecc.steps;
1323 uint8_t *p = buf;
f75e5097 1324 uint8_t *oob = chip->oob_poi;
3f91e94f 1325 unsigned int max_bitflips = 0;
1da177e4 1326
f5bbdacc
TG		 1327 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1328 int stat;
61b03bd7 1329
f5bbdacc
TG		 1330 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1331 chip->read_buf(mtd, p, eccsize);
1da177e4 1332
f5bbdacc
TG		 1333 if (chip->ecc.prepad) {
1334 chip->read_buf(mtd, oob, chip->ecc.prepad);
1335 oob += chip->ecc.prepad;
1336 }
1da177e4 1337
f5bbdacc
TG		 1338 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1339 chip->read_buf(mtd, oob, eccbytes);
1340 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1341
3f91e94f 1342 if (stat < 0) {
f5bbdacc 1343 mtd->ecc_stats.failed++;
3f91e94f 1344 } else {
f5bbdacc 1345 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1346 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1347 }
61b03bd7 1348
f5bbdacc 1349 oob += eccbytes;
1da177e4 1350
f5bbdacc
TG		 1351 if (chip->ecc.postpad) {
1352 chip->read_buf(mtd, oob, chip->ecc.postpad);
1353 oob += chip->ecc.postpad;
61b03bd7 1354 }
f5bbdacc 1355 }
1da177e4 1356
f5bbdacc 1357 /* Calculate remaining oob bytes */
7e4178f9 1358 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1359 if (i)
1360 chip->read_buf(mtd, oob, i);
61b03bd7 1361
3f91e94f 1362 return max_bitflips;
f5bbdacc 1363}
1da177e4 1364
f5bbdacc 1365/**
7854d3f7 1366 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1367 * @chip: nand chip structure
1368 * @oob: oob destination address
1369 * @ops: oob ops structure
1370 * @len: size of oob to transfer
8593fbc6
TG		 1371 */
1372static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1373 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1374{
f8ac0414 1375 switch (ops->mode) {
8593fbc6 1376
0612b9dd
BN		 1377 case MTD_OPS_PLACE_OOB:
1378 case MTD_OPS_RAW:
8593fbc6
TG		 1379 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1380 return oob + len;
1381
0612b9dd 1382 case MTD_OPS_AUTO_OOB: {
8593fbc6 1383 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1384 uint32_t boffs = 0, roffs = ops->ooboffs;
1385 size_t bytes = 0;
8593fbc6 1386
f8ac0414 1387 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1388 /* Read request not from offset 0? */
7bc3312b
TG		 1389 if (unlikely(roffs)) {
1390 if (roffs >= free->length) {
1391 roffs -= free->length;
1392 continue;
1393 }
1394 boffs = free->offset + roffs;
1395 bytes = min_t(size_t, len,
1396 (free->length - roffs));
1397 roffs = 0;
1398 } else {
1399 bytes = min_t(size_t, len, free->length);
1400 boffs = free->offset;
1401 }
1402 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1403 oob += bytes;
1404 }
1405 return oob;
1406 }
1407 default:
1408 BUG();
1409 }
1410 return NULL;
1411}
1412
1413/**
7854d3f7 1414 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1415 * @mtd: MTD device structure
1416 * @from: offset to read from
1417 * @ops: oob ops structure
f5bbdacc
TG		 1418 *
1419 * Internal function. Called with chip held.
1420 */
8593fbc6
TG		 1421static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1422 struct mtd_oob_ops *ops)
f5bbdacc 1423{
e47f3db4 1424 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1425 struct nand_chip *chip = mtd->priv;
1426 struct mtd_ecc_stats stats;
f5bbdacc 1427 int ret = 0;
8593fbc6 1428 uint32_t readlen = ops->len;
7014568b 1429 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1430 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1431 mtd->oobavail : mtd->oobsize;
1432
8593fbc6 1433 uint8_t *bufpoi, *oob, *buf;
edbc4540 1434 unsigned int max_bitflips = 0;
1da177e4 1435
f5bbdacc 1436 stats = mtd->ecc_stats;
1da177e4 1437
f5bbdacc
TG		 1438 chipnr = (int)(from >> chip->chip_shift);
1439 chip->select_chip(mtd, chipnr);
61b03bd7 1440
f5bbdacc
TG		 1441 realpage = (int)(from >> chip->page_shift);
1442 page = realpage & chip->pagemask;
1da177e4 1443
f5bbdacc 1444 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1445
8593fbc6
TG		 1446 buf = ops->datbuf;
1447 oob = ops->oobbuf;
e47f3db4 1448 oob_required = oob ? 1 : 0;
8593fbc6 1449
f8ac0414 1450 while (1) {
f5bbdacc
TG		 1451 bytes = min(mtd->writesize - col, readlen);
1452 aligned = (bytes == mtd->writesize);
61b03bd7 1453
8b6e50c9 1454 /* Is the current page in the buffer? */
8593fbc6 1455 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1456 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1457
c00a0991 1458 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1459
edbc4540
MD		 1460 /*
1461 * Now read the page into the buffer. Absent an error,
1462 * the read methods return max bitflips per ecc step.
1463 */
0612b9dd 1464 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1465 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1466 oob_required,
1467 page);
a5ff4f10
JW		 1468 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1469 !oob)
7351d3a5
FF		 1470 ret = chip->ecc.read_subpage(mtd, chip,
1471 col, bytes, bufpoi);
956e944c 1472 else
46a8cf2d 1473 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1474 oob_required, page);
6d77b9d0
BN		 1475 if (ret < 0) {
1476 if (!aligned)
1477 /* Invalidate page cache */
1478 chip->pagebuf = -1;
1da177e4 1479 break;
6d77b9d0 1480 }
f5bbdacc 1481
edbc4540
MD		 1482 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1483
f5bbdacc
TG		 1484 /* Transfer not aligned data */
1485 if (!aligned) {
a5ff4f10 1486 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1487 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1488 (ops->mode != MTD_OPS_RAW)) {
3d459559 1489 chip->pagebuf = realpage;
edbc4540
MD		 1490 chip->pagebuf_bitflips = ret;
1491 } else {
6d77b9d0
BN		 1492 /* Invalidate page cache */
1493 chip->pagebuf = -1;
edbc4540 1494 }
4bf63fcb 1495 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1496 }
1497
8593fbc6
TG		 1498 buf += bytes;
1499
1500 if (unlikely(oob)) {
b64d39d8
ML		 1501 int toread = min(oobreadlen, max_oobsize);
1502
1503 if (toread) {
1504 oob = nand_transfer_oob(chip,
1505 oob, ops, toread);
1506 oobreadlen -= toread;
1507 }
8593fbc6 1508 }
5bc7c33c
BN		 1509
1510 if (chip->options & NAND_NEED_READRDY) {
1511 /* Apply delay or wait for ready/busy pin */
1512 if (!chip->dev_ready)
1513 udelay(chip->chip_delay);
1514 else
1515 nand_wait_ready(mtd);
1516 }
8593fbc6 1517 } else {
4bf63fcb 1518 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1519 buf += bytes;
edbc4540
MD		 1520 max_bitflips = max_t(unsigned int, max_bitflips,
1521 chip->pagebuf_bitflips);
8593fbc6 1522 }
1da177e4 1523
f5bbdacc 1524 readlen -= bytes;
61b03bd7 1525
f5bbdacc 1526 if (!readlen)
61b03bd7 1527 break;
1da177e4 1528
8b6e50c9 1529 /* For subsequent reads align to page boundary */
1da177e4
LT		 1530 col = 0;
1531 /* Increment page address */
1532 realpage++;
1533
ace4dfee 1534 page = realpage & chip->pagemask;
1da177e4
LT		 1535 /* Check, if we cross a chip boundary */
1536 if (!page) {
1537 chipnr++;
ace4dfee
TG		 1538 chip->select_chip(mtd, -1);
1539 chip->select_chip(mtd, chipnr);
1da177e4 1540 }
1da177e4 1541 }
b0bb6903 1542 chip->select_chip(mtd, -1);
1da177e4 1543
8593fbc6 1544 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1545 if (oob)
1546 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1547
3f91e94f 1548 if (ret < 0)
f5bbdacc
TG		 1549 return ret;
1550
9a1fcdfd
TG		 1551 if (mtd->ecc_stats.failed - stats.failed)
1552 return -EBADMSG;
1553
edbc4540 1554 return max_bitflips;
f5bbdacc
TG		 1555}
1556
1557/**
25985edc 1558 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1559 * @mtd: MTD device structure
1560 * @from: offset to read from
1561 * @len: number of bytes to read
1562 * @retlen: pointer to variable to store the number of read bytes
1563 * @buf: the databuffer to put data
f5bbdacc 1564 *
8b6e50c9 1565 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1566 */
1567static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1568 size_t *retlen, uint8_t *buf)
1569{
4a89ff88 1570 struct mtd_oob_ops ops;
f5bbdacc
TG		 1571 int ret;
1572
6a8214aa 1573 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 1574 ops.len = len;
1575 ops.datbuf = buf;
1576 ops.oobbuf = NULL;
11041ae6 1577 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1578 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1579 *retlen = ops.retlen;
f5bbdacc 1580 nand_release_device(mtd);
f5bbdacc 1581 return ret;
1da177e4
LT		 1582}
1583
7bc3312b 1584/**
7854d3f7 1585 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1586 * @mtd: mtd info structure
1587 * @chip: nand chip info structure
1588 * @page: page number to read
7bc3312b
TG		 1589 */
1590static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1591 int page)
7bc3312b 1592{
5c2ffb11 1593 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1594 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1595 return 0;
7bc3312b
TG		 1596}
1597
1598/**
7854d3f7 1599 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1600 * with syndromes
8b6e50c9
BN		 1601 * @mtd: mtd info structure
1602 * @chip: nand chip info structure
1603 * @page: page number to read
7bc3312b
TG		 1604 */
1605static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1606 int page)
7bc3312b
TG		 1607{
1608 uint8_t *buf = chip->oob_poi;
1609 int length = mtd->oobsize;
1610 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1611 int eccsize = chip->ecc.size;
1612 uint8_t *bufpoi = buf;
1613 int i, toread, sndrnd = 0, pos;
1614
1615 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1616 for (i = 0; i < chip->ecc.steps; i++) {
1617 if (sndrnd) {
1618 pos = eccsize + i * (eccsize + chunk);
1619 if (mtd->writesize > 512)
1620 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1621 else
1622 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1623 } else
1624 sndrnd = 1;
1625 toread = min_t(int, length, chunk);
1626 chip->read_buf(mtd, bufpoi, toread);
1627 bufpoi += toread;
1628 length -= toread;
1629 }
1630 if (length > 0)
1631 chip->read_buf(mtd, bufpoi, length);
1632
5c2ffb11 1633 return 0;
7bc3312b
TG		 1634}
1635
1636/**
7854d3f7 1637 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1638 * @mtd: mtd info structure
1639 * @chip: nand chip info structure
1640 * @page: page number to write
7bc3312b
TG		 1641 */
1642static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1643 int page)
1644{
1645 int status = 0;
1646 const uint8_t *buf = chip->oob_poi;
1647 int length = mtd->oobsize;
1648
1649 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1650 chip->write_buf(mtd, buf, length);
1651 /* Send command to program the OOB data */
1652 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1653
1654 status = chip->waitfunc(mtd, chip);
1655
0d420f9d 1656 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1657}
1658
1659/**
7854d3f7 1660 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1661 * with syndrome - only for large page flash
1662 * @mtd: mtd info structure
1663 * @chip: nand chip info structure
1664 * @page: page number to write
7bc3312b
TG		 1665 */
1666static int nand_write_oob_syndrome(struct mtd_info *mtd,
1667 struct nand_chip *chip, int page)
1668{
1669 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1670 int eccsize = chip->ecc.size, length = mtd->oobsize;
1671 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1672 const uint8_t *bufpoi = chip->oob_poi;
1673
1674 /*
1675 * data-ecc-data-ecc ... ecc-oob
1676 * or
1677 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1678 */
1679 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1680 pos = steps * (eccsize + chunk);
1681 steps = 0;
1682 } else
8b0036ee 1683 pos = eccsize;
7bc3312b
TG		 1684
1685 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1686 for (i = 0; i < steps; i++) {
1687 if (sndcmd) {
1688 if (mtd->writesize <= 512) {
1689 uint32_t fill = 0xFFFFFFFF;
1690
1691 len = eccsize;
1692 while (len > 0) {
1693 int num = min_t(int, len, 4);
1694 chip->write_buf(mtd, (uint8_t *)&fill,
1695 num);
1696 len -= num;
1697 }
1698 } else {
1699 pos = eccsize + i * (eccsize + chunk);
1700 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1701 }
1702 } else
1703 sndcmd = 1;
1704 len = min_t(int, length, chunk);
1705 chip->write_buf(mtd, bufpoi, len);
1706 bufpoi += len;
1707 length -= len;
1708 }
1709 if (length > 0)
1710 chip->write_buf(mtd, bufpoi, length);
1711
1712 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1713 status = chip->waitfunc(mtd, chip);
1714
1715 return status & NAND_STATUS_FAIL ? -EIO : 0;
1716}
1717
1da177e4 1718/**
7854d3f7 1719 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1720 * @mtd: MTD device structure
1721 * @from: offset to read from
1722 * @ops: oob operations description structure
1da177e4 1723 *
8b6e50c9 1724 * NAND read out-of-band data from the spare area.
1da177e4 1725 */
8593fbc6
TG		 1726static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1727 struct mtd_oob_ops *ops)
1da177e4 1728{
c00a0991 1729 int page, realpage, chipnr;
ace4dfee 1730 struct nand_chip *chip = mtd->priv;
041e4575 1731 struct mtd_ecc_stats stats;
7014568b
VW		 1732 int readlen = ops->ooblen;
1733 int len;
7bc3312b 1734 uint8_t *buf = ops->oobbuf;
1951f2f7 1735 int ret = 0;
61b03bd7 1736
289c0522 1737 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1738 __func__, (unsigned long long)from, readlen);
1da177e4 1739
041e4575
BN		 1740 stats = mtd->ecc_stats;
1741
0612b9dd 1742 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1743 len = chip->ecc.layout->oobavail;
03736155
AH		 1744 else
1745 len = mtd->oobsize;
1746
1747 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1748 pr_debug("%s: attempt to start read outside oob\n",
1749 __func__);
03736155
AH		 1750 return -EINVAL;
1751 }
1752
1753 /* Do not allow reads past end of device */
1754 if (unlikely(from >= mtd->size ||
1755 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1756 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1757 pr_debug("%s: attempt to read beyond end of device\n",
1758 __func__);
03736155
AH		 1759 return -EINVAL;
1760 }
7014568b 1761
7314e9e7 1762 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1763 chip->select_chip(mtd, chipnr);
1da177e4 1764
7314e9e7
TG		 1765 /* Shift to get page */
1766 realpage = (int)(from >> chip->page_shift);
1767 page = realpage & chip->pagemask;
1da177e4 1768
f8ac0414 1769 while (1) {
0612b9dd 1770 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1771 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1772 else
1951f2f7
SL		 1773 ret = chip->ecc.read_oob(mtd, chip, page);
1774
1775 if (ret < 0)
1776 break;
7014568b
VW		 1777
1778 len = min(len, readlen);
1779 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1780
5bc7c33c
BN		 1781 if (chip->options & NAND_NEED_READRDY) {
1782 /* Apply delay or wait for ready/busy pin */
1783 if (!chip->dev_ready)
1784 udelay(chip->chip_delay);
1785 else
1786 nand_wait_ready(mtd);
1787 }
1788
7014568b 1789 readlen -= len;
0d420f9d
SZ		 1790 if (!readlen)
1791 break;
1792
7314e9e7
TG		 1793 /* Increment page address */
1794 realpage++;
1795
1796 page = realpage & chip->pagemask;
1797 /* Check, if we cross a chip boundary */
1798 if (!page) {
1799 chipnr++;
1800 chip->select_chip(mtd, -1);
1801 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1802 }
1803 }
b0bb6903 1804 chip->select_chip(mtd, -1);
1da177e4 1805
1951f2f7
SL		 1806 ops->oobretlen = ops->ooblen - readlen;
1807
1808 if (ret < 0)
1809 return ret;
041e4575
BN		 1810
1811 if (mtd->ecc_stats.failed - stats.failed)
1812 return -EBADMSG;
1813
1814 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1815}
1816
1817/**
8593fbc6 1818 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1819 * @mtd: MTD device structure
1820 * @from: offset to read from
1821 * @ops: oob operation description structure
1da177e4 1822 *
8b6e50c9 1823 * NAND read data and/or out-of-band data.
1da177e4 1824 */
8593fbc6
TG		 1825static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1826 struct mtd_oob_ops *ops)
1da177e4 1827{
8593fbc6
TG		 1828 int ret = -ENOTSUPP;
1829
1830 ops->retlen = 0;
1da177e4
LT		 1831
1832 /* Do not allow reads past end of device */
7014568b 1833 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1834 pr_debug("%s: attempt to read beyond end of device\n",
1835 __func__);
1da177e4
LT		 1836 return -EINVAL;
1837 }
1838
6a8214aa 1839 nand_get_device(mtd, FL_READING);
1da177e4 1840
f8ac0414 1841 switch (ops->mode) {
0612b9dd
BN		 1842 case MTD_OPS_PLACE_OOB:
1843 case MTD_OPS_AUTO_OOB:
1844 case MTD_OPS_RAW:
8593fbc6 1845 break;
1da177e4 1846
8593fbc6
TG		 1847 default:
1848 goto out;
1849 }
1da177e4 1850
8593fbc6
TG		 1851 if (!ops->datbuf)
1852 ret = nand_do_read_oob(mtd, from, ops);
1853 else
1854 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1855
7351d3a5 1856out:
8593fbc6
TG		 1857 nand_release_device(mtd);
1858 return ret;
1859}
61b03bd7 1860
1da177e4 1861
8593fbc6 1862/**
7854d3f7 1863 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1864 * @mtd: mtd info structure
1865 * @chip: nand chip info structure
1866 * @buf: data buffer
1fbb938d 1867 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1868 *
7854d3f7 1869 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1870 */
fdbad98d 1871static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1872 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1873{
1874 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1875 if (oob_required)
1876 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1877
1878 return 0;
1da177e4
LT		 1879}
1880
52ff49df 1881/**
7854d3f7 1882 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1883 * @mtd: mtd info structure
1884 * @chip: nand chip info structure
1885 * @buf: data buffer
1fbb938d 1886 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1887 *
1888 * We need a special oob layout and handling even when ECC isn't checked.
1889 */
fdbad98d 1890static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1891 struct nand_chip *chip,
1fbb938d 1892 const uint8_t *buf, int oob_required)
52ff49df
DB		 1893{
1894 int eccsize = chip->ecc.size;
1895 int eccbytes = chip->ecc.bytes;
1896 uint8_t *oob = chip->oob_poi;
1897 int steps, size;
1898
1899 for (steps = chip->ecc.steps; steps > 0; steps--) {
1900 chip->write_buf(mtd, buf, eccsize);
1901 buf += eccsize;
1902
1903 if (chip->ecc.prepad) {
1904 chip->write_buf(mtd, oob, chip->ecc.prepad);
1905 oob += chip->ecc.prepad;
1906 }
1907
1908 chip->read_buf(mtd, oob, eccbytes);
1909 oob += eccbytes;
1910
1911 if (chip->ecc.postpad) {
1912 chip->write_buf(mtd, oob, chip->ecc.postpad);
1913 oob += chip->ecc.postpad;
1914 }
1915 }
1916
1917 size = mtd->oobsize - (oob - chip->oob_poi);
1918 if (size)
1919 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 1920
1921 return 0;
52ff49df 1922}
9223a456 1923/**
7854d3f7 1924 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1925 * @mtd: mtd info structure
1926 * @chip: nand chip info structure
1927 * @buf: data buffer
1fbb938d 1928 * @oob_required: must write chip->oob_poi to OOB
9223a456 1929 */
fdbad98d 1930static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1931 const uint8_t *buf, int oob_required)
9223a456 1932{
f75e5097
TG		 1933 int i, eccsize = chip->ecc.size;
1934 int eccbytes = chip->ecc.bytes;
1935 int eccsteps = chip->ecc.steps;
4bf63fcb 1936 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1937 const uint8_t *p = buf;
8b099a39 1938 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1939
7854d3f7 1940 /* Software ECC calculation */
8593fbc6
TG		 1941 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1942 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1943
8593fbc6
TG		 1944 for (i = 0; i < chip->ecc.total; i++)
1945 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1946
fdbad98d 1947 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1948}
9223a456 1949
f75e5097 1950/**
7854d3f7 1951 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1952 * @mtd: mtd info structure
1953 * @chip: nand chip info structure
1954 * @buf: data buffer
1fbb938d 1955 * @oob_required: must write chip->oob_poi to OOB
f75e5097 1956 */
fdbad98d 1957static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1958 const uint8_t *buf, int oob_required)
f75e5097
TG		 1959{
1960 int i, eccsize = chip->ecc.size;
1961 int eccbytes = chip->ecc.bytes;
1962 int eccsteps = chip->ecc.steps;
4bf63fcb 1963 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1964 const uint8_t *p = buf;
8b099a39 1965 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1966
f75e5097
TG		 1967 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1968 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1969 chip->write_buf(mtd, p, eccsize);
f75e5097 1970 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1971 }
1972
f75e5097
TG		 1973 for (i = 0; i < chip->ecc.total; i++)
1974 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1975
1976 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1977
1978 return 0;
9223a456
TG		 1979}
1980
61b03bd7 1981/**
7854d3f7 1982 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 1983 * @mtd: mtd info structure
1984 * @chip: nand chip info structure
1985 * @buf: data buffer
1fbb938d 1986 * @oob_required: must write chip->oob_poi to OOB
1da177e4 1987 *
8b6e50c9
BN		 1988 * The hw generator calculates the error syndrome automatically. Therefore we
1989 * need a special oob layout and handling.
f75e5097 1990 */
fdbad98d 1991static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1992 struct nand_chip *chip,
1993 const uint8_t *buf, int oob_required)
1da177e4 1994{
f75e5097
TG		 1995 int i, eccsize = chip->ecc.size;
1996 int eccbytes = chip->ecc.bytes;
1997 int eccsteps = chip->ecc.steps;
1998 const uint8_t *p = buf;
1999 uint8_t *oob = chip->oob_poi;
1da177e4 2000
f75e5097 2001 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2002
f75e5097
TG		 2003 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2004 chip->write_buf(mtd, p, eccsize);
61b03bd7 2005
f75e5097
TG		 2006 if (chip->ecc.prepad) {
2007 chip->write_buf(mtd, oob, chip->ecc.prepad);
2008 oob += chip->ecc.prepad;
2009 }
2010
2011 chip->ecc.calculate(mtd, p, oob);
2012 chip->write_buf(mtd, oob, eccbytes);
2013 oob += eccbytes;
2014
2015 if (chip->ecc.postpad) {
2016 chip->write_buf(mtd, oob, chip->ecc.postpad);
2017 oob += chip->ecc.postpad;
1da177e4 2018 }
1da177e4 2019 }
f75e5097
TG		 2020
2021 /* Calculate remaining oob bytes */
7e4178f9 2022 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2023 if (i)
2024 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2025
2026 return 0;
f75e5097
TG		 2027}
2028
2029/**
956e944c 2030 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2031 * @mtd: MTD device structure
2032 * @chip: NAND chip descriptor
2033 * @buf: the data to write
1fbb938d 2034 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2035 * @page: page number to write
2036 * @cached: cached programming
2037 * @raw: use _raw version of write_page
f75e5097
TG		 2038 */
2039static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d
BN		 2040 const uint8_t *buf, int oob_required, int page,
2041 int cached, int raw)
f75e5097
TG		 2042{
2043 int status;
2044
2045 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2046
956e944c 2047 if (unlikely(raw))
fdbad98d 2048 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
956e944c 2049 else
fdbad98d
JW		 2050 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2051
2052 if (status < 0)
2053 return status;
f75e5097
TG		 2054
2055 /*
7854d3f7 2056 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2057 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2058 */
2059 cached = 0;
2060
3239a6cd 2061 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2062
2063 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2064 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2065 /*
2066 * See if operation failed and additional status checks are
8b6e50c9 2067 * available.
f75e5097
TG		 2068 */
2069 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2070 status = chip->errstat(mtd, chip, FL_WRITING, status,
2071 page);
2072
2073 if (status & NAND_STATUS_FAIL)
2074 return -EIO;
2075 } else {
2076 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2077 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2078 }
2079
f75e5097 2080 return 0;
1da177e4
LT		 2081}
2082
8593fbc6 2083/**
7854d3f7 2084 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2085 * @mtd: MTD device structure
8b6e50c9
BN		 2086 * @oob: oob data buffer
2087 * @len: oob data write length
2088 * @ops: oob ops structure
8593fbc6 2089 */
f722013e
TAA		 2090static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2091 struct mtd_oob_ops *ops)
8593fbc6 2092{
f722013e
TAA		 2093 struct nand_chip *chip = mtd->priv;
2094
2095 /*
2096 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2097 * data from a previous OOB read.
2098 */
2099 memset(chip->oob_poi, 0xff, mtd->oobsize);
2100
f8ac0414 2101 switch (ops->mode) {
8593fbc6 2102
0612b9dd
BN		 2103 case MTD_OPS_PLACE_OOB:
2104 case MTD_OPS_RAW:
8593fbc6
TG		 2105 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2106 return oob + len;
2107
0612b9dd 2108 case MTD_OPS_AUTO_OOB: {
8593fbc6 2109 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2110 uint32_t boffs = 0, woffs = ops->ooboffs;
2111 size_t bytes = 0;
8593fbc6 2112
f8ac0414 2113 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2114 /* Write request not from offset 0? */
7bc3312b
TG		 2115 if (unlikely(woffs)) {
2116 if (woffs >= free->length) {
2117 woffs -= free->length;
2118 continue;
2119 }
2120 boffs = free->offset + woffs;
2121 bytes = min_t(size_t, len,
2122 (free->length - woffs));
2123 woffs = 0;
2124 } else {
2125 bytes = min_t(size_t, len, free->length);
2126 boffs = free->offset;
2127 }
8b0036ee 2128 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2129 oob += bytes;
2130 }
2131 return oob;
2132 }
2133 default:
2134 BUG();
2135 }
2136 return NULL;
2137}
2138
f8ac0414 2139#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2140
2141/**
7854d3f7 2142 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2143 * @mtd: MTD device structure
2144 * @to: offset to write to
2145 * @ops: oob operations description structure
1da177e4 2146 *
8b6e50c9 2147 * NAND write with ECC.
1da177e4 2148 */
8593fbc6
TG		 2149static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2150 struct mtd_oob_ops *ops)
1da177e4 2151{
29072b96 2152 int chipnr, realpage, page, blockmask, column;
ace4dfee 2153 struct nand_chip *chip = mtd->priv;
8593fbc6 2154 uint32_t writelen = ops->len;
782ce79a
ML		 2155
2156 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2157 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2158 mtd->oobavail : mtd->oobsize;
2159
8593fbc6
TG		 2160 uint8_t *oob = ops->oobbuf;
2161 uint8_t *buf = ops->datbuf;
29072b96 2162 int ret, subpage;
e47f3db4 2163 int oob_required = oob ? 1 : 0;
1da177e4 2164
8593fbc6 2165 ops->retlen = 0;
29072b96
TG		 2166 if (!writelen)
2167 return 0;
1da177e4 2168
8b6e50c9 2169 /* Reject writes, which are not page aligned */
8593fbc6 2170 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2171 pr_notice("%s: attempt to write non page aligned data\n",
2172 __func__);
1da177e4
LT		 2173 return -EINVAL;
2174 }
2175
29072b96
TG		 2176 column = to & (mtd->writesize - 1);
2177 subpage = column || (writelen & (mtd->writesize - 1));
2178
2179 if (subpage && oob)
2180 return -EINVAL;
1da177e4 2181
6a930961
TG		 2182 chipnr = (int)(to >> chip->chip_shift);
2183 chip->select_chip(mtd, chipnr);
2184
1da177e4 2185 /* Check, if it is write protected */
b0bb6903
HS		 2186 if (nand_check_wp(mtd)) {
2187 ret = -EIO;
2188 goto err_out;
2189 }
1da177e4 2190
f75e5097
TG		 2191 realpage = (int)(to >> chip->page_shift);
2192 page = realpage & chip->pagemask;
2193 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2194
2195 /* Invalidate the page cache, when we write to the cached page */
2196 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2197 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2198 chip->pagebuf = -1;
61b03bd7 2199
782ce79a 2200 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2201 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2202 ret = -EINVAL;
2203 goto err_out;
2204 }
782ce79a 2205
f8ac0414 2206 while (1) {
29072b96 2207 int bytes = mtd->writesize;
f75e5097 2208 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2209 uint8_t *wbuf = buf;
2210
8b6e50c9 2211 /* Partial page write? */
29072b96
TG		 2212 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2213 cached = 0;
2214 bytes = min_t(int, bytes - column, (int) writelen);
2215 chip->pagebuf = -1;
2216 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2217 memcpy(&chip->buffers->databuf[column], buf, bytes);
2218 wbuf = chip->buffers->databuf;
2219 }
1da177e4 2220
782ce79a
ML		 2221 if (unlikely(oob)) {
2222 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2223 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2224 oobwritelen -= len;
f722013e
TAA		 2225 } else {
2226 /* We still need to erase leftover OOB data */
2227 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2228 }
8593fbc6 2229
e47f3db4
BN		 2230 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2231 cached, (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2232 if (ret)
2233 break;
2234
2235 writelen -= bytes;
2236 if (!writelen)
2237 break;
2238
29072b96 2239 column = 0;
f75e5097
TG		 2240 buf += bytes;
2241 realpage++;
2242
2243 page = realpage & chip->pagemask;
2244 /* Check, if we cross a chip boundary */
2245 if (!page) {
2246 chipnr++;
2247 chip->select_chip(mtd, -1);
2248 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2249 }
2250 }
8593fbc6 2251
8593fbc6 2252 ops->retlen = ops->len - writelen;
7014568b
VW		 2253 if (unlikely(oob))
2254 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2255
2256err_out:
2257 chip->select_chip(mtd, -1);
1da177e4
LT		 2258 return ret;
2259}
2260
2af7c653
SK		 2261/**
2262 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2263 * @mtd: MTD device structure
2264 * @to: offset to write to
2265 * @len: number of bytes to write
2266 * @retlen: pointer to variable to store the number of written bytes
2267 * @buf: the data to write
2af7c653
SK		 2268 *
2269 * NAND write with ECC. Used when performing writes in interrupt context, this
2270 * may for example be called by mtdoops when writing an oops while in panic.
2271 */
2272static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2273 size_t *retlen, const uint8_t *buf)
2274{
2275 struct nand_chip *chip = mtd->priv;
4a89ff88 2276 struct mtd_oob_ops ops;
2af7c653
SK		 2277 int ret;
2278
8b6e50c9 2279 /* Wait for the device to get ready */
2af7c653
SK		 2280 panic_nand_wait(mtd, chip, 400);
2281
8b6e50c9 2282 /* Grab the device */
2af7c653
SK		 2283 panic_nand_get_device(chip, mtd, FL_WRITING);
2284
4a89ff88
BN		 2285 ops.len = len;
2286 ops.datbuf = (uint8_t *)buf;
2287 ops.oobbuf = NULL;
11041ae6 2288 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2289
4a89ff88 2290 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2291
4a89ff88 2292 *retlen = ops.retlen;
2af7c653
SK		 2293 return ret;
2294}
2295
f75e5097 2296/**
8593fbc6 2297 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2298 * @mtd: MTD device structure
2299 * @to: offset to write to
2300 * @len: number of bytes to write
2301 * @retlen: pointer to variable to store the number of written bytes
2302 * @buf: the data to write
f75e5097 2303 *
8b6e50c9 2304 * NAND write with ECC.
f75e5097 2305 */
8593fbc6
TG		 2306static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2307 size_t *retlen, const uint8_t *buf)
f75e5097 2308{
4a89ff88 2309 struct mtd_oob_ops ops;
f75e5097
TG		 2310 int ret;
2311
6a8214aa 2312 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 2313 ops.len = len;
2314 ops.datbuf = (uint8_t *)buf;
2315 ops.oobbuf = NULL;
11041ae6 2316 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2317 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2318 *retlen = ops.retlen;
f75e5097 2319 nand_release_device(mtd);
8593fbc6 2320 return ret;
f75e5097 2321}
7314e9e7 2322
1da177e4 2323/**
8593fbc6 2324 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2325 * @mtd: MTD device structure
2326 * @to: offset to write to
2327 * @ops: oob operation description structure
1da177e4 2328 *
8b6e50c9 2329 * NAND write out-of-band.
1da177e4 2330 */
8593fbc6
TG		 2331static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2332 struct mtd_oob_ops *ops)
1da177e4 2333{
03736155 2334 int chipnr, page, status, len;
ace4dfee 2335 struct nand_chip *chip = mtd->priv;
1da177e4 2336
289c0522 2337 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2338 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2339
0612b9dd 2340 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2341 len = chip->ecc.layout->oobavail;
2342 else
2343 len = mtd->oobsize;
2344
1da177e4 2345 /* Do not allow write past end of page */
03736155 2346 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2347 pr_debug("%s: attempt to write past end of page\n",
2348 __func__);
1da177e4
LT		 2349 return -EINVAL;
2350 }
2351
03736155 2352 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2353 pr_debug("%s: attempt to start write outside oob\n",
2354 __func__);
03736155
AH		 2355 return -EINVAL;
2356 }
2357
775adc3d 2358 /* Do not allow write past end of device */
03736155
AH		 2359 if (unlikely(to >= mtd->size ||
2360 ops->ooboffs + ops->ooblen >
2361 ((mtd->size >> chip->page_shift) -
2362 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2363 pr_debug("%s: attempt to write beyond end of device\n",
2364 __func__);
03736155
AH		 2365 return -EINVAL;
2366 }
2367
7314e9e7 2368 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2369 chip->select_chip(mtd, chipnr);
1da177e4 2370
7314e9e7
TG		 2371 /* Shift to get page */
2372 page = (int)(to >> chip->page_shift);
2373
2374 /*
2375 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2376 * of my DiskOnChip 2000 test units) will clear the whole data page too
2377 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2378 * it in the doc2000 driver in August 1999. dwmw2.
2379 */
ace4dfee 2380 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2381
2382 /* Check, if it is write protected */
b0bb6903
HS		 2383 if (nand_check_wp(mtd)) {
2384 chip->select_chip(mtd, -1);
8593fbc6 2385 return -EROFS;
b0bb6903 2386 }
61b03bd7 2387
1da177e4 2388 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2389 if (page == chip->pagebuf)
2390 chip->pagebuf = -1;
1da177e4 2391
f722013e 2392 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2393
0612b9dd 2394 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2395 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2396 else
2397 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2398
b0bb6903
HS		 2399 chip->select_chip(mtd, -1);
2400
7bc3312b
TG		 2401 if (status)
2402 return status;
1da177e4 2403
7014568b 2404 ops->oobretlen = ops->ooblen;
1da177e4 2405
7bc3312b 2406 return 0;
8593fbc6
TG		 2407}
2408
2409/**
2410 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2411 * @mtd: MTD device structure
2412 * @to: offset to write to
2413 * @ops: oob operation description structure
8593fbc6
TG		 2414 */
2415static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2416 struct mtd_oob_ops *ops)
2417{
8593fbc6
TG		 2418 int ret = -ENOTSUPP;
2419
2420 ops->retlen = 0;
2421
2422 /* Do not allow writes past end of device */
7014568b 2423 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2424 pr_debug("%s: attempt to write beyond end of device\n",
2425 __func__);
8593fbc6
TG		 2426 return -EINVAL;
2427 }
2428
6a8214aa 2429 nand_get_device(mtd, FL_WRITING);
8593fbc6 2430
f8ac0414 2431 switch (ops->mode) {
0612b9dd
BN		 2432 case MTD_OPS_PLACE_OOB:
2433 case MTD_OPS_AUTO_OOB:
2434 case MTD_OPS_RAW:
8593fbc6
TG		 2435 break;
2436
2437 default:
2438 goto out;
2439 }
2440
2441 if (!ops->datbuf)
2442 ret = nand_do_write_oob(mtd, to, ops);
2443 else
2444 ret = nand_do_write_ops(mtd, to, ops);
2445
7351d3a5 2446out:
1da177e4 2447 nand_release_device(mtd);
1da177e4
LT		 2448 return ret;
2449}
2450
1da177e4 2451/**
7854d3f7 2452 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2453 * @mtd: MTD device structure
2454 * @page: the page address of the block which will be erased
1da177e4 2455 *
8b6e50c9 2456 * Standard erase command for NAND chips.
1da177e4 2457 */
e0c7d767 2458static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2459{
ace4dfee 2460 struct nand_chip *chip = mtd->priv;
1da177e4 2461 /* Send commands to erase a block */
ace4dfee
TG		 2462 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2463 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2464}
2465
1da177e4
LT		 2466/**
2467 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2468 * @mtd: MTD device structure
2469 * @instr: erase instruction
1da177e4 2470 *
8b6e50c9 2471 * Erase one ore more blocks.
1da177e4 2472 */
e0c7d767 2473static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2474{
e0c7d767 2475 return nand_erase_nand(mtd, instr, 0);
1da177e4 2476}
61b03bd7 2477
1da177e4 2478/**
7854d3f7 2479 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2480 * @mtd: MTD device structure
2481 * @instr: erase instruction
2482 * @allowbbt: allow erasing the bbt area
1da177e4 2483 *
8b6e50c9 2484 * Erase one ore more blocks.
1da177e4 2485 */
ace4dfee
TG		 2486int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2487 int allowbbt)
1da177e4 2488{
69423d99 2489 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2490 struct nand_chip *chip = mtd->priv;
69423d99 2491 loff_t len;
1da177e4 2492
289c0522
BN		 2493 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2494 __func__, (unsigned long long)instr->addr,
2495 (unsigned long long)instr->len);
1da177e4 2496
6fe5a6ac 2497 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2498 return -EINVAL;
1da177e4 2499
1da177e4 2500 /* Grab the lock and see if the device is available */
6a8214aa 2501 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2502
2503 /* Shift to get first page */
ace4dfee
TG		 2504 page = (int)(instr->addr >> chip->page_shift);
2505 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2506
2507 /* Calculate pages in each block */
ace4dfee 2508 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2509
2510 /* Select the NAND device */
ace4dfee 2511 chip->select_chip(mtd, chipnr);
1da177e4 2512
1da177e4
LT		 2513 /* Check, if it is write protected */
2514 if (nand_check_wp(mtd)) {
289c0522
BN		 2515 pr_debug("%s: device is write protected!\n",
2516 __func__);
1da177e4
LT		 2517 instr->state = MTD_ERASE_FAILED;
2518 goto erase_exit;
2519 }
2520
2521 /* Loop through the pages */
2522 len = instr->len;
2523
2524 instr->state = MTD_ERASING;
2525
2526 while (len) {
12183a20 2527 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2528 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2529 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2530 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2531 __func__, page);
1da177e4
LT		 2532 instr->state = MTD_ERASE_FAILED;
2533 goto erase_exit;
2534 }
61b03bd7 2535
ace4dfee
TG		 2536 /*
2537 * Invalidate the page cache, if we erase the block which
8b6e50c9 2538 * contains the current cached page.
ace4dfee
TG		 2539 */
2540 if (page <= chip->pagebuf && chip->pagebuf <
2541 (page + pages_per_block))
2542 chip->pagebuf = -1;
1da177e4 2543
ace4dfee 2544 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2545
7bc3312b 2546 status = chip->waitfunc(mtd, chip);
1da177e4 2547
ace4dfee
TG		 2548 /*
2549 * See if operation failed and additional status checks are
2550 * available
2551 */
2552 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2553 status = chip->errstat(mtd, chip, FL_ERASING,
2554 status, page);
068e3c0a 2555
1da177e4 2556 /* See if block erase succeeded */
a4ab4c5d 2557 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2558 pr_debug("%s: failed erase, page 0x%08x\n",
2559 __func__, page);
1da177e4 2560 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2561 instr->fail_addr =
2562 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2563 goto erase_exit;
2564 }
30f464b7 2565
1da177e4 2566 /* Increment page address and decrement length */
ace4dfee 2567 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2568 page += pages_per_block;
2569
2570 /* Check, if we cross a chip boundary */
ace4dfee 2571 if (len && !(page & chip->pagemask)) {
1da177e4 2572 chipnr++;
ace4dfee
TG		 2573 chip->select_chip(mtd, -1);
2574 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2575 }
2576 }
2577 instr->state = MTD_ERASE_DONE;
2578
7351d3a5 2579erase_exit:
1da177e4
LT		 2580
2581 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2582
2583 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2584 chip->select_chip(mtd, -1);
1da177e4
LT		 2585 nand_release_device(mtd);
2586
49defc01
DW		 2587 /* Do call back function */
2588 if (!ret)
2589 mtd_erase_callback(instr);
2590
1da177e4
LT		 2591 /* Return more or less happy */
2592 return ret;
2593}
2594
2595/**
2596 * nand_sync - [MTD Interface] sync
8b6e50c9 2597 * @mtd: MTD device structure
1da177e4 2598 *
8b6e50c9 2599 * Sync is actually a wait for chip ready function.
1da177e4 2600 */
e0c7d767 2601static void nand_sync(struct mtd_info *mtd)
1da177e4 2602{
289c0522 2603 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2604
2605 /* Grab the lock and see if the device is available */
6a8214aa 2606 nand_get_device(mtd, FL_SYNCING);
1da177e4 2607 /* Release it and go back */
e0c7d767 2608 nand_release_device(mtd);
1da177e4
LT		 2609}
2610
1da177e4 2611/**
ace4dfee 2612 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2613 * @mtd: MTD device structure
2614 * @offs: offset relative to mtd start
1da177e4 2615 */
ace4dfee 2616static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2617{
ace4dfee 2618 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2619}
2620
2621/**
ace4dfee 2622 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2623 * @mtd: MTD device structure
2624 * @ofs: offset relative to mtd start
1da177e4 2625 */
e0c7d767 2626static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2627{
ace4dfee 2628 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2629 int ret;
2630
f8ac0414
FF		 2631 ret = nand_block_isbad(mtd, ofs);
2632 if (ret) {
8b6e50c9 2633 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2634 if (ret > 0)
2635 return 0;
e0c7d767
DW		 2636 return ret;
2637 }
1da177e4 2638
ace4dfee 2639 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2640}
2641
7db03ecc
HS		 2642/**
2643 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2644 * @mtd: MTD device structure
2645 * @chip: nand chip info structure
2646 * @addr: feature address.
2647 * @subfeature_param: the subfeature parameters, a four bytes array.
2648 */
2649static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2650 int addr, uint8_t *subfeature_param)
2651{
2652 int status;
2653
2654 if (!chip->onfi_version)
2655 return -EINVAL;
2656
2657 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2658 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2659 status = chip->waitfunc(mtd, chip);
2660 if (status & NAND_STATUS_FAIL)
2661 return -EIO;
2662 return 0;
2663}
2664
2665/**
2666 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2667 * @mtd: MTD device structure
2668 * @chip: nand chip info structure
2669 * @addr: feature address.
2670 * @subfeature_param: the subfeature parameters, a four bytes array.
2671 */
2672static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2673 int addr, uint8_t *subfeature_param)
2674{
2675 if (!chip->onfi_version)
2676 return -EINVAL;
2677
2678 /* clear the sub feature parameters */
2679 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2680
2681 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2682 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2683 return 0;
2684}
2685
962034f4
VW		 2686/**
2687 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2688 * @mtd: MTD device structure
962034f4
VW		 2689 */
2690static int nand_suspend(struct mtd_info *mtd)
2691{
6a8214aa 2692 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2693}
2694
2695/**
2696 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2697 * @mtd: MTD device structure
962034f4
VW		 2698 */
2699static void nand_resume(struct mtd_info *mtd)
2700{
ace4dfee 2701 struct nand_chip *chip = mtd->priv;
962034f4 2702
ace4dfee 2703 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2704 nand_release_device(mtd);
2705 else
d0370219
BN		 2706 pr_err("%s called for a chip which is not in suspended state\n",
2707 __func__);
962034f4
VW		 2708}
2709
8b6e50c9 2710/* Set default functions */
ace4dfee 2711static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2712{
1da177e4 2713 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2714 if (!chip->chip_delay)
2715 chip->chip_delay = 20;
1da177e4
LT		 2716
2717 /* check, if a user supplied command function given */
ace4dfee
TG		 2718 if (chip->cmdfunc == NULL)
2719 chip->cmdfunc = nand_command;
1da177e4
LT		 2720
2721 /* check, if a user supplied wait function given */
ace4dfee
TG		 2722 if (chip->waitfunc == NULL)
2723 chip->waitfunc = nand_wait;
2724
2725 if (!chip->select_chip)
2726 chip->select_chip = nand_select_chip;
2727 if (!chip->read_byte)
2728 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2729 if (!chip->read_word)
2730 chip->read_word = nand_read_word;
2731 if (!chip->block_bad)
2732 chip->block_bad = nand_block_bad;
2733 if (!chip->block_markbad)
2734 chip->block_markbad = nand_default_block_markbad;
2735 if (!chip->write_buf)
2736 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2737 if (!chip->read_buf)
2738 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2739 if (!chip->scan_bbt)
2740 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2741
2742 if (!chip->controller) {
2743 chip->controller = &chip->hwcontrol;
2744 spin_lock_init(&chip->controller->lock);
2745 init_waitqueue_head(&chip->controller->wq);
2746 }
2747
7aa65bfd
TG		 2748}
2749
8b6e50c9 2750/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2751static void sanitize_string(uint8_t *s, size_t len)
2752{
2753 ssize_t i;
2754
8b6e50c9 2755 /* Null terminate */
d1e1f4e4
FF		 2756 s[len - 1] = 0;
2757
8b6e50c9 2758 /* Remove non printable chars */
d1e1f4e4
FF		 2759 for (i = 0; i < len - 1; i++) {
2760 if (s[i] < ' ' || s[i] > 127)
2761 s[i] = '?';
2762 }
2763
8b6e50c9 2764 /* Remove trailing spaces */
d1e1f4e4
FF		 2765 strim(s);
2766}
2767
2768static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2769{
2770 int i;
2771 while (len--) {
2772 crc ^= *p++ << 8;
2773 for (i = 0; i < 8; i++)
2774 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2775 }
2776
2777 return crc;
2778}
2779
6fb277ba 2780/*
8b6e50c9 2781 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2782 */
2783static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2784 int *busw)
6fb277ba
FF		 2785{
2786 struct nand_onfi_params *p = &chip->onfi_params;
2787 int i;
2788 int val;
2789
0ce82b7f
MC		 2790 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2791 if (chip->options & NAND_BUSWIDTH_16) {
2792 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2793 return 0;
2794 }
7854d3f7 2795 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2796 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2797 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2798 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2799 return 0;
2800
6fb277ba
FF		 2801 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2802 for (i = 0; i < 3; i++) {
2803 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2804 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2805 le16_to_cpu(p->crc)) {
9a4d4d69 2806 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2807 break;
2808 }
2809 }
2810
2811 if (i == 3)
2812 return 0;
2813
8b6e50c9 2814 /* Check version */
6fb277ba 2815 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2816 if (val & (1 << 5))
2817 chip->onfi_version = 23;
2818 else if (val & (1 << 4))
6fb277ba
FF		 2819 chip->onfi_version = 22;
2820 else if (val & (1 << 3))
2821 chip->onfi_version = 21;
2822 else if (val & (1 << 2))
2823 chip->onfi_version = 20;
b7b1a29d 2824 else if (val & (1 << 1))
6fb277ba 2825 chip->onfi_version = 10;
b7b1a29d
BN		 2826
2827 if (!chip->onfi_version) {
d0370219 2828 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2829 return 0;
2830 }
6fb277ba
FF		 2831
2832 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2833 sanitize_string(p->model, sizeof(p->model));
2834 if (!mtd->name)
2835 mtd->name = p->model;
2836 mtd->writesize = le32_to_cpu(p->byte_per_page);
2837 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2838 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2839 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2840 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2841 *busw = 0;
6fb277ba 2842 if (le16_to_cpu(p->features) & 1)
08c248fb 2843 *busw = NAND_BUSWIDTH_16;
6fb277ba 2844
d42b5de3 2845 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2846 return 1;
2847}
2848
e3b88bd6
BN		 2849/*
2850 * nand_id_has_period - Check if an ID string has a given wraparound period
2851 * @id_data: the ID string
2852 * @arrlen: the length of the @id_data array
2853 * @period: the period of repitition
2854 *
2855 * Check if an ID string is repeated within a given sequence of bytes at
2856 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 2857 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 2858 * if the repetition has a period of @period; otherwise, returns zero.
2859 */
2860static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2861{
2862 int i, j;
2863 for (i = 0; i < period; i++)
2864 for (j = i + period; j < arrlen; j += period)
2865 if (id_data[i] != id_data[j])
2866 return 0;
2867 return 1;
2868}
2869
2870/*
2871 * nand_id_len - Get the length of an ID string returned by CMD_READID
2872 * @id_data: the ID string
2873 * @arrlen: the length of the @id_data array
2874
2875 * Returns the length of the ID string, according to known wraparound/trailing
2876 * zero patterns. If no pattern exists, returns the length of the array.
2877 */
2878static int nand_id_len(u8 *id_data, int arrlen)
2879{
2880 int last_nonzero, period;
2881
2882 /* Find last non-zero byte */
2883 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2884 if (id_data[last_nonzero])
2885 break;
2886
2887 /* All zeros */
2888 if (last_nonzero < 0)
2889 return 0;
2890
2891 /* Calculate wraparound period */
2892 for (period = 1; period < arrlen; period++)
2893 if (nand_id_has_period(id_data, arrlen, period))
2894 break;
2895
2896 /* There's a repeated pattern */
2897 if (period < arrlen)
2898 return period;
2899
2900 /* There are trailing zeros */
2901 if (last_nonzero < arrlen - 1)
2902 return last_nonzero + 1;
2903
2904 /* No pattern detected */
2905 return arrlen;
2906}
2907
fc09bbc0
BN		 2908/*
2909 * Many new NAND share similar device ID codes, which represent the size of the
2910 * chip. The rest of the parameters must be decoded according to generic or
2911 * manufacturer-specific "extended ID" decoding patterns.
2912 */
2913static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2914 u8 id_data[8], int *busw)
2915{
e3b88bd6 2916 int extid, id_len;
fc09bbc0
BN		 2917 /* The 3rd id byte holds MLC / multichip data */
2918 chip->cellinfo = id_data[2];
2919 /* The 4th id byte is the important one */
2920 extid = id_data[3];
2921
e3b88bd6
BN		 2922 id_len = nand_id_len(id_data, 8);
2923
fc09bbc0
BN		 2924 /*
2925 * Field definitions are in the following datasheets:
2926 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 2927 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 2928 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 2929 *
af451af4
BN		 2930 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2931 * ID to decide what to do.
fc09bbc0 2932 */
af451af4 2933 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
6924d99f 2934 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
af451af4 2935 id_data[5] != 0x00) {
fc09bbc0
BN		 2936 /* Calc pagesize */
2937 mtd->writesize = 2048 << (extid & 0x03);
2938 extid >>= 2;
2939 /* Calc oobsize */
e2d3a35e 2940 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 2941 case 1:
2942 mtd->oobsize = 128;
2943 break;
2944 case 2:
2945 mtd->oobsize = 218;
2946 break;
2947 case 3:
2948 mtd->oobsize = 400;
2949 break;
e2d3a35e 2950 case 4:
fc09bbc0
BN		 2951 mtd->oobsize = 436;
2952 break;
e2d3a35e
BN		 2953 case 5:
2954 mtd->oobsize = 512;
2955 break;
2956 case 6:
2957 default: /* Other cases are "reserved" (unknown) */
2958 mtd->oobsize = 640;
2959 break;
fc09bbc0
BN		 2960 }
2961 extid >>= 2;
2962 /* Calc blocksize */
2963 mtd->erasesize = (128 * 1024) <<
2964 (((extid >> 1) & 0x04) | (extid & 0x03));
2965 *busw = 0;
73ca392f
BN		 2966 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
2967 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2968 unsigned int tmp;
2969
2970 /* Calc pagesize */
2971 mtd->writesize = 2048 << (extid & 0x03);
2972 extid >>= 2;
2973 /* Calc oobsize */
2974 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
2975 case 0:
2976 mtd->oobsize = 128;
2977 break;
2978 case 1:
2979 mtd->oobsize = 224;
2980 break;
2981 case 2:
2982 mtd->oobsize = 448;
2983 break;
2984 case 3:
2985 mtd->oobsize = 64;
2986 break;
2987 case 4:
2988 mtd->oobsize = 32;
2989 break;
2990 case 5:
2991 mtd->oobsize = 16;
2992 break;
2993 default:
2994 mtd->oobsize = 640;
2995 break;
2996 }
2997 extid >>= 2;
2998 /* Calc blocksize */
2999 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3000 if (tmp < 0x03)
3001 mtd->erasesize = (128 * 1024) << tmp;
3002 else if (tmp == 0x03)
3003 mtd->erasesize = 768 * 1024;
3004 else
3005 mtd->erasesize = (64 * 1024) << tmp;
3006 *busw = 0;
fc09bbc0
BN		 3007 } else {
3008 /* Calc pagesize */
3009 mtd->writesize = 1024 << (extid & 0x03);
3010 extid >>= 2;
3011 /* Calc oobsize */
3012 mtd->oobsize = (8 << (extid & 0x01)) *
3013 (mtd->writesize >> 9);
3014 extid >>= 2;
3015 /* Calc blocksize. Blocksize is multiples of 64KiB */
3016 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3017 extid >>= 2;
3018 /* Get buswidth information */
3019 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3020 }
3021}
3022
f23a481c
BN		 3023/*
3024 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3025 * decodes a matching ID table entry and assigns the MTD size parameters for
3026 * the chip.
3027 */
3028static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3029 struct nand_flash_dev *type, u8 id_data[8],
3030 int *busw)
3031{
3032 int maf_id = id_data[0];
3033
3034 mtd->erasesize = type->erasesize;
3035 mtd->writesize = type->pagesize;
3036 mtd->oobsize = mtd->writesize / 32;
3037 *busw = type->options & NAND_BUSWIDTH_16;
3038
3039 /*
3040 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3041 * some Spansion chips have erasesize that conflicts with size
3042 * listed in nand_ids table.
3043 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3044 */
3045 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3046 && id_data[6] == 0x00 && id_data[7] == 0x00
3047 && mtd->writesize == 512) {
3048 mtd->erasesize = 128 * 1024;
3049 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3050 }
3051}
3052
7e74c2d7
BN		 3053/*
3054 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3055 * heuristic patterns using various detected parameters (e.g., manufacturer,
3056 * page size, cell-type information).
3057 */
3058static void nand_decode_bbm_options(struct mtd_info *mtd,
3059 struct nand_chip *chip, u8 id_data[8])
3060{
3061 int maf_id = id_data[0];
3062
3063 /* Set the bad block position */
3064 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3065 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3066 else
3067 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3068
3069 /*
3070 * Bad block marker is stored in the last page of each block on Samsung
3071 * and Hynix MLC devices; stored in first two pages of each block on
3072 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3073 * AMD/Spansion, and Macronix. All others scan only the first page.
3074 */
3075 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3076 (maf_id == NAND_MFR_SAMSUNG ||
3077 maf_id == NAND_MFR_HYNIX))
3078 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3079 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3080 (maf_id == NAND_MFR_SAMSUNG ||
3081 maf_id == NAND_MFR_HYNIX ||
3082 maf_id == NAND_MFR_TOSHIBA ||
3083 maf_id == NAND_MFR_AMD ||
3084 maf_id == NAND_MFR_MACRONIX)) ||
3085 (mtd->writesize == 2048 &&
3086 maf_id == NAND_MFR_MICRON))
3087 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3088}
3089
7aa65bfd 3090/*
8b6e50c9 3091 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3092 */
3093static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3094 struct nand_chip *chip,
7351d3a5
FF		 3095 int busw,
3096 int *maf_id, int *dev_id,
5e81e88a 3097 struct nand_flash_dev *type)
7aa65bfd 3098{
d1e1f4e4 3099 int i, maf_idx;
426c457a 3100 u8 id_data[8];
1da177e4
LT		 3101
3102 /* Select the device */
ace4dfee 3103 chip->select_chip(mtd, 0);
1da177e4 3104
ef89a880
KB		 3105 /*
3106 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3107 * after power-up.
ef89a880
KB		 3108 */
3109 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3110
1da177e4 3111 /* Send the command for reading device ID */
ace4dfee 3112 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3113
3114 /* Read manufacturer and device IDs */
ace4dfee 3115 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3116 *dev_id = chip->read_byte(mtd);
1da177e4 3117
8b6e50c9
BN		 3118 /*
3119 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3120 * interface concerns can cause random data which looks like a
3121 * possibly credible NAND flash to appear. If the two results do
3122 * not match, ignore the device completely.
3123 */
3124
3125 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3126
4aef9b78
BN		 3127 /* Read entire ID string */
3128 for (i = 0; i < 8; i++)
426c457a 3129 id_data[i] = chip->read_byte(mtd);
ed8165c7 3130
d1e1f4e4 3131 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 3132 pr_info("%s: second ID read did not match "
d0370219
BN		 3133 "%02x,%02x against %02x,%02x\n", __func__,
3134 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3135 return ERR_PTR(-ENODEV);
3136 }
3137
7aa65bfd 3138 if (!type)
5e81e88a
DW		 3139 type = nand_flash_ids;
3140
3141 for (; type->name != NULL; type++)
68aa352d 3142 if (*dev_id == type->dev_id)
f8ac0414 3143 break;
5e81e88a 3144
d1e1f4e4
FF		 3145 chip->onfi_version = 0;
3146 if (!type->name || !type->pagesize) {
6fb277ba 3147 /* Check is chip is ONFI compliant */
47450b35 3148 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3149 goto ident_done;
d1e1f4e4
FF		 3150 }
3151
5e81e88a 3152 if (!type->name)
7aa65bfd
TG		 3153 return ERR_PTR(-ENODEV);
3154
ba0251fe
TG		 3155 if (!mtd->name)
3156 mtd->name = type->name;
3157
69423d99 3158 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3159
12a40a57 3160 if (!type->pagesize && chip->init_size) {
8b6e50c9 3161 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3162 busw = chip->init_size(mtd, chip, id_data);
3163 } else if (!type->pagesize) {
fc09bbc0
BN		 3164 /* Decode parameters from extended ID */
3165 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3166 } else {
f23a481c 3167 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3168 }
bf7a01bf
BN		 3169 /* Get chip options */
3170 chip->options |= type->options;
d1e1f4e4 3171
8b6e50c9
BN		 3172 /*
3173 * Check if chip is not a Samsung device. Do not clear the
3174 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3175 */
3176 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3177 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3178ident_done:
3179
7aa65bfd 3180 /* Try to identify manufacturer */
9a909867 3181 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3182 if (nand_manuf_ids[maf_idx].id == *maf_id)
3183 break;
3184 }
0ea4a755 3185
64b37b2a
MC		 3186 if (chip->options & NAND_BUSWIDTH_AUTO) {
3187 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3188 chip->options |= busw;
3189 nand_set_defaults(chip, busw);
3190 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3191 /*
3192 * Check, if buswidth is correct. Hardware drivers should set
3193 * chip correct!
3194 */
9a4d4d69 3195 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3196 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3197 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3198 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3199 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3200 busw ? 16 : 8);
7aa65bfd
TG		 3201 return ERR_PTR(-EINVAL);
3202 }
61b03bd7 3203
7e74c2d7
BN		 3204 nand_decode_bbm_options(mtd, chip, id_data);
3205
7aa65bfd 3206 /* Calculate the address shift from the page size */
ace4dfee 3207 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3208 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3209 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3210
ace4dfee 3211 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3212 ffs(mtd->erasesize) - 1;
69423d99
AH		 3213 if (chip->chipsize & 0xffffffff)
3214 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3215 else {
3216 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3217 chip->chip_shift += 32 - 1;
3218 }
1da177e4 3219
26d9be11 3220 chip->badblockbits = 8;
14c65786 3221 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3222
8b6e50c9 3223 /* Do not replace user supplied command function! */
ace4dfee
TG		 3224 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3225 chip->cmdfunc = nand_command_lp;
7aa65bfd 3226
886bd33d 3227 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
2fd71a29 3228 " %dMiB, page size: %d, OOB size: %d\n",
886bd33d
HS		 3229 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3230 chip->onfi_version ? chip->onfi_params.model : type->name,
2fd71a29 3231 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3232
3233 return type;
3234}
3235
7aa65bfd 3236/**
3b85c321 3237 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3238 * @mtd: MTD device structure
3239 * @maxchips: number of chips to scan for
3240 * @table: alternative NAND ID table
7aa65bfd 3241 *
8b6e50c9
BN		 3242 * This is the first phase of the normal nand_scan() function. It reads the
3243 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3244 *
3b85c321 3245 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3246 */
5e81e88a
DW		 3247int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3248 struct nand_flash_dev *table)
7aa65bfd 3249{
d1e1f4e4 3250 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3251 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3252 struct nand_flash_dev *type;
3253
7aa65bfd 3254 /* Get buswidth to select the correct functions */
ace4dfee 3255 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3256 /* Set the default functions */
ace4dfee 3257 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3258
3259 /* Read the flash type */
7351d3a5
FF		 3260 type = nand_get_flash_type(mtd, chip, busw,
3261 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3262
3263 if (IS_ERR(type)) {
b1c6e6db 3264 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3265 pr_warn("No NAND device found\n");
ace4dfee 3266 chip->select_chip(mtd, -1);
7aa65bfd 3267 return PTR_ERR(type);
1da177e4
LT		 3268 }
3269
07300164
HS		 3270 chip->select_chip(mtd, -1);
3271
7aa65bfd 3272 /* Check for a chip array */
e0c7d767 3273 for (i = 1; i < maxchips; i++) {
ace4dfee 3274 chip->select_chip(mtd, i);
ef89a880
KB		 3275 /* See comment in nand_get_flash_type for reset */
3276 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3277 /* Send the command for reading device ID */
ace4dfee 3278 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3279 /* Read manufacturer and device IDs */
ace4dfee 3280 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3281 nand_dev_id != chip->read_byte(mtd)) {
3282 chip->select_chip(mtd, -1);
1da177e4 3283 break;
07300164
HS		 3284 }
3285 chip->select_chip(mtd, -1);
1da177e4
LT		 3286 }
3287 if (i > 1)
9a4d4d69 3288 pr_info("%d NAND chips detected\n", i);
61b03bd7 3289
1da177e4 3290 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3291 chip->numchips = i;
3292 mtd->size = i * chip->chipsize;
7aa65bfd 3293
3b85c321
DW		 3294 return 0;
3295}
7351d3a5 3296EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3297
3298
3299/**
3300 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3301 * @mtd: MTD device structure
3b85c321 3302 *
8b6e50c9
BN		 3303 * This is the second phase of the normal nand_scan() function. It fills out
3304 * all the uninitialized function pointers with the defaults and scans for a
3305 * bad block table if appropriate.
3b85c321
DW		 3306 */
3307int nand_scan_tail(struct mtd_info *mtd)
3308{
3309 int i;
3310 struct nand_chip *chip = mtd->priv;
3311
e2414f4c
BN		 3312 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3313 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3314 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3315
4bf63fcb
DW		 3316 if (!(chip->options & NAND_OWN_BUFFERS))
3317 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3318 if (!chip->buffers)
3319 return -ENOMEM;
3320
7dcdcbef 3321 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3322 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3323
7aa65bfd 3324 /*
8b6e50c9 3325 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3326 */
193bd400 3327 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3328 switch (mtd->oobsize) {
1da177e4 3329 case 8:
5bd34c09 3330 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3331 break;
3332 case 16:
5bd34c09 3333 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3334 break;
3335 case 64:
5bd34c09 3336 chip->ecc.layout = &nand_oob_64;
1da177e4 3337 break;
81ec5364
TG		 3338 case 128:
3339 chip->ecc.layout = &nand_oob_128;
3340 break;
1da177e4 3341 default:
d0370219
BN		 3342 pr_warn("No oob scheme defined for oobsize %d\n",
3343 mtd->oobsize);
1da177e4
LT		 3344 BUG();
3345 }
3346 }
61b03bd7 3347
956e944c
DW		 3348 if (!chip->write_page)
3349 chip->write_page = nand_write_page;
3350
7db03ecc
HS		 3351 /* set for ONFI nand */
3352 if (!chip->onfi_set_features)
3353 chip->onfi_set_features = nand_onfi_set_features;
3354 if (!chip->onfi_get_features)
3355 chip->onfi_get_features = nand_onfi_get_features;
3356
61b03bd7 3357 /*
8b6e50c9 3358 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3359 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3360 */
956e944c 3361
ace4dfee 3362 switch (chip->ecc.mode) {
6e0cb135
SN		 3363 case NAND_ECC_HW_OOB_FIRST:
3364 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3365 if (!chip->ecc.calculate || !chip->ecc.correct ||
3366 !chip->ecc.hwctl) {
9a4d4d69 3367 pr_warn("No ECC functions supplied; "
d0370219 3368 "hardware ECC not possible\n");
6e0cb135
SN		 3369 BUG();
3370 }
3371 if (!chip->ecc.read_page)
3372 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3373
6dfc6d25 3374 case NAND_ECC_HW:
8b6e50c9 3375 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3376 if (!chip->ecc.read_page)
3377 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3378 if (!chip->ecc.write_page)
3379 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3380 if (!chip->ecc.read_page_raw)
3381 chip->ecc.read_page_raw = nand_read_page_raw;
3382 if (!chip->ecc.write_page_raw)
3383 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3384 if (!chip->ecc.read_oob)
3385 chip->ecc.read_oob = nand_read_oob_std;
3386 if (!chip->ecc.write_oob)
3387 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3388
6dfc6d25 3389 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3390 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3391 !chip->ecc.hwctl) &&
3392 (!chip->ecc.read_page ||
1c45f604 3393 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3394 !chip->ecc.write_page ||
1c45f604 3395 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3396 pr_warn("No ECC functions supplied; "
d0370219 3397 "hardware ECC not possible\n");
6dfc6d25
TG		 3398 BUG();
3399 }
8b6e50c9 3400 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3401 if (!chip->ecc.read_page)
3402 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3403 if (!chip->ecc.write_page)
3404 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3405 if (!chip->ecc.read_page_raw)
3406 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3407 if (!chip->ecc.write_page_raw)
3408 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3409 if (!chip->ecc.read_oob)
3410 chip->ecc.read_oob = nand_read_oob_syndrome;
3411 if (!chip->ecc.write_oob)
3412 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3413
e2788c98
MD		 3414 if (mtd->writesize >= chip->ecc.size) {
3415 if (!chip->ecc.strength) {
3416 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3417 BUG();
3418 }
6dfc6d25 3419 break;
e2788c98 3420 }
9a4d4d69 3421 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3422 "%d byte page size, fallback to SW ECC\n",
3423 chip->ecc.size, mtd->writesize);
ace4dfee 3424 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3425
6dfc6d25 3426 case NAND_ECC_SOFT:
ace4dfee
TG		 3427 chip->ecc.calculate = nand_calculate_ecc;
3428 chip->ecc.correct = nand_correct_data;
f5bbdacc 3429 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3430 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3431 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3432 chip->ecc.read_page_raw = nand_read_page_raw;
3433 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3434 chip->ecc.read_oob = nand_read_oob_std;
3435 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3436 if (!chip->ecc.size)
3437 chip->ecc.size = 256;
ace4dfee 3438 chip->ecc.bytes = 3;
6a918bad 3439 chip->ecc.strength = 1;
1da177e4 3440 break;
61b03bd7 3441
193bd400
ID		 3442 case NAND_ECC_SOFT_BCH:
3443 if (!mtd_nand_has_bch()) {
9a4d4d69 3444 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3445 BUG();
3446 }
3447 chip->ecc.calculate = nand_bch_calculate_ecc;
3448 chip->ecc.correct = nand_bch_correct_data;
3449 chip->ecc.read_page = nand_read_page_swecc;
3450 chip->ecc.read_subpage = nand_read_subpage;
3451 chip->ecc.write_page = nand_write_page_swecc;
3452 chip->ecc.read_page_raw = nand_read_page_raw;
3453 chip->ecc.write_page_raw = nand_write_page_raw;
3454 chip->ecc.read_oob = nand_read_oob_std;
3455 chip->ecc.write_oob = nand_write_oob_std;
3456 /*
3457 * Board driver should supply ecc.size and ecc.bytes values to
3458 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3459 * for details. Otherwise, default to 4 bits for large page
3460 * devices.
193bd400
ID		 3461 */
3462 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3463 chip->ecc.size = 512;
3464 chip->ecc.bytes = 7;
3465 }
3466 chip->ecc.priv = nand_bch_init(mtd,
3467 chip->ecc.size,
3468 chip->ecc.bytes,
3469 &chip->ecc.layout);
3470 if (!chip->ecc.priv) {
9a4d4d69 3471 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3472 BUG();
3473 }
6a918bad 3474 chip->ecc.strength =
e2788c98 3475 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3476 break;
3477
61b03bd7 3478 case NAND_ECC_NONE:
9a4d4d69 3479 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3480 "This is not recommended!\n");
8593fbc6
TG		 3481 chip->ecc.read_page = nand_read_page_raw;
3482 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3483 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3484 chip->ecc.read_page_raw = nand_read_page_raw;
3485 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3486 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3487 chip->ecc.size = mtd->writesize;
3488 chip->ecc.bytes = 0;
6a918bad 3489 chip->ecc.strength = 0;
1da177e4 3490 break;
956e944c 3491
1da177e4 3492 default:
d0370219 3493 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3494 BUG();
1da177e4 3495 }
61b03bd7 3496
9ce244b3 3497 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3498 if (!chip->ecc.read_oob_raw)
3499 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3500 if (!chip->ecc.write_oob_raw)
3501 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3502
5bd34c09
TG		 3503 /*
3504 * The number of bytes available for a client to place data into
8b6e50c9 3505 * the out of band area.
5bd34c09
TG		 3506 */
3507 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3508 for (i = 0; chip->ecc.layout->oobfree[i].length
3509 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3510 chip->ecc.layout->oobavail +=
3511 chip->ecc.layout->oobfree[i].length;
1f92267c 3512 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3513
7aa65bfd
TG		 3514 /*
3515 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3516 * mode.
7aa65bfd 3517 */
ace4dfee 3518 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3519 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3520 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3521 BUG();
1da177e4 3522 }
f5bbdacc 3523 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3524
8b6e50c9 3525 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3526 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3527 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3528 switch (chip->ecc.steps) {
29072b96
TG		 3529 case 2:
3530 mtd->subpage_sft = 1;
3531 break;
3532 case 4:
3533 case 8:
81ec5364 3534 case 16:
29072b96
TG		 3535 mtd->subpage_sft = 2;
3536 break;
3537 }
3538 }
3539 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3540
04bbd0ea 3541 /* Initialize state */
ace4dfee 3542 chip->state = FL_READY;
1da177e4 3543
1da177e4 3544 /* Invalidate the pagebuffer reference */
ace4dfee 3545 chip->pagebuf = -1;
1da177e4 3546
a5ff4f10
JW		 3547 /* Large page NAND with SOFT_ECC should support subpage reads */
3548 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3549 chip->options |= NAND_SUBPAGE_READ;
3550
1da177e4
LT		 3551 /* Fill in remaining MTD driver data */
3552 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3553 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3554 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3555 mtd->_erase = nand_erase;
3556 mtd->_point = NULL;
3557 mtd->_unpoint = NULL;
3558 mtd->_read = nand_read;
3559 mtd->_write = nand_write;
3560 mtd->_panic_write = panic_nand_write;
3561 mtd->_read_oob = nand_read_oob;
3562 mtd->_write_oob = nand_write_oob;
3563 mtd->_sync = nand_sync;
3564 mtd->_lock = NULL;
3565 mtd->_unlock = NULL;
3566 mtd->_suspend = nand_suspend;
3567 mtd->_resume = nand_resume;
3568 mtd->_block_isbad = nand_block_isbad;
3569 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3570 mtd->writebufsize = mtd->writesize;
1da177e4 3571
6a918bad 3572 /* propagate ecc info to mtd_info */
5bd34c09 3573 mtd->ecclayout = chip->ecc.layout;
86c2072b 3574 mtd->ecc_strength = chip->ecc.strength;
ea3b2ea2
SL		 3575 /*
3576 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3577 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3578 * properly set.
3579 */
3580 if (!mtd->bitflip_threshold)
3581 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3582
0040bf38 3583 /* Check, if we should skip the bad block table scan */
ace4dfee 3584 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3585 return 0;
1da177e4
LT		 3586
3587 /* Build bad block table */
ace4dfee 3588 return chip->scan_bbt(mtd);
1da177e4 3589}
7351d3a5 3590EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3591
8b6e50c9
BN		 3592/*
3593 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3594 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3595 * to call us from in-kernel code if the core NAND support is modular.
3596 */
3b85c321
DW		 3597#ifdef MODULE
3598#define caller_is_module() (1)
3599#else
3600#define caller_is_module() \
a6e6abd5 3601 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3602#endif
3603
3604/**
3605 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3606 * @mtd: MTD device structure
3607 * @maxchips: number of chips to scan for
3b85c321 3608 *
8b6e50c9
BN		 3609 * This fills out all the uninitialized function pointers with the defaults.
3610 * The flash ID is read and the mtd/chip structures are filled with the
3611 * appropriate values. The mtd->owner field must be set to the module of the
3612 * caller.
3b85c321
DW		 3613 */
3614int nand_scan(struct mtd_info *mtd, int maxchips)
3615{
3616 int ret;
3617
3618 /* Many callers got this wrong, so check for it for a while... */
3619 if (!mtd->owner && caller_is_module()) {
d0370219 3620 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3621 BUG();
3622 }
3623
5e81e88a 3624 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3625 if (!ret)
3626 ret = nand_scan_tail(mtd);
3627 return ret;
3628}
7351d3a5 3629EXPORT_SYMBOL(nand_scan);
3b85c321 3630
1da177e4 3631/**
61b03bd7 3632 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3633 * @mtd: MTD device structure
3634 */
e0c7d767 3635void nand_release(struct mtd_info *mtd)
1da177e4 3636{
ace4dfee 3637 struct nand_chip *chip = mtd->priv;
1da177e4 3638
193bd400
ID		 3639 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3640 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3641
5ffcaf3d 3642 mtd_device_unregister(mtd);
1da177e4 3643
fa671646 3644 /* Free bad block table memory */
ace4dfee 3645 kfree(chip->bbt);
4bf63fcb
DW		 3646 if (!(chip->options & NAND_OWN_BUFFERS))
3647 kfree(chip->buffers);
58373ff0
BN		 3648
3649 /* Free bad block descriptor memory */
3650 if (chip->badblock_pattern && chip->badblock_pattern->options
3651 & NAND_BBT_DYNAMICSTRUCT)
3652 kfree(chip->badblock_pattern);
1da177e4 3653}
e0c7d767 3654EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3655
3656static int __init nand_base_init(void)
3657{
3658 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3659 return 0;
3660}
3661
3662static void __exit nand_base_exit(void)
3663{
3664 led_trigger_unregister_simple(nand_led_trigger);
3665}
3666
3667module_init(nand_base_init);
3668module_exit(nand_base_exit);
3669
e0c7d767 3670MODULE_LICENSE("GPL");
7351d3a5
FF		 3671MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3672MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3673MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)