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mtd: nand: fix interpretation of NAND_CMD_NONE in nand_command[_lp]()
[linux-2.6-block.git] / drivers / mtd / nand / nand_base.c
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1da177e4 1/*
1da177e4
LT		 2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
61b03bd7 5 *
1da177e4 6 * Additional technical information is available on
8b2b403c 7 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 8 *
1da177e4 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 11 *
ace4dfee 12 * Credits:
61b03bd7
TG		 13 * David Woodhouse for adding multichip support
14 *
1da177e4
LT		 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
ace4dfee 18 * TODO:
1da177e4
LT		 19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 21 * if we have HW ECC support.
c0b8ba7b 22 * BBT table is not serialized, has to be fixed
1da177e4 23 *
1da177e4
LT		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
20171642
EG		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
66507c7b 38#include <linux/mm.h>
38b8d208 39#include <linux/nmi.h>
1da177e4
LT		 40#include <linux/types.h>
41#include <linux/mtd/mtd.h>
d4092d76 42#include <linux/mtd/rawnand.h>
1da177e4 43#include <linux/mtd/nand_ecc.h>
193bd400 44#include <linux/mtd/nand_bch.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
7351d3a5 47#include <linux/io.h>
1da177e4 48#include <linux/mtd/partitions.h>
d48f62b9 49#include <linux/of.h>
1da177e4 50
41b207a7
BB		 51static int nand_get_device(struct mtd_info *mtd, int new_state);
52
53static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
54 struct mtd_oob_ops *ops);
1da177e4
LT		 55
56/* Define default oob placement schemes for large and small page devices */
41b207a7
BB		 57static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
58 struct mtd_oob_region *oobregion)
59{
60 struct nand_chip *chip = mtd_to_nand(mtd);
61 struct nand_ecc_ctrl *ecc = &chip->ecc;
1da177e4 62
41b207a7
BB		 63 if (section > 1)
64 return -ERANGE;
1da177e4 65
41b207a7
BB		 66 if (!section) {
67 oobregion->offset = 0;
f7f8c175
MR		 68 if (mtd->oobsize == 16)
69 oobregion->length = 4;
70 else
71 oobregion->length = 3;
41b207a7 72 } else {
f7f8c175
MR		 73 if (mtd->oobsize == 8)
74 return -ERANGE;
75
41b207a7
BB		 76 oobregion->offset = 6;
77 oobregion->length = ecc->total - 4;
78 }
1da177e4 79
41b207a7
BB		 80 return 0;
81}
82
83static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
84 struct mtd_oob_region *oobregion)
85{
86 if (section > 1)
87 return -ERANGE;
1da177e4 88
41b207a7
BB		 89 if (mtd->oobsize == 16) {
90 if (section)
91 return -ERANGE;
92
93 oobregion->length = 8;
94 oobregion->offset = 8;
95 } else {
96 oobregion->length = 2;
97 if (!section)
98 oobregion->offset = 3;
99 else
100 oobregion->offset = 6;
101 }
102
103 return 0;
104}
105
106const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
107 .ecc = nand_ooblayout_ecc_sp,
108 .free = nand_ooblayout_free_sp,
81ec5364 109};
41b207a7 110EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
81ec5364 111
41b207a7
BB		 112static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
113 struct mtd_oob_region *oobregion)
114{
115 struct nand_chip *chip = mtd_to_nand(mtd);
116 struct nand_ecc_ctrl *ecc = &chip->ecc;
1da177e4 117
882fd157 118 if (section || !ecc->total)
41b207a7 119 return -ERANGE;
8593fbc6 120
41b207a7
BB		 121 oobregion->length = ecc->total;
122 oobregion->offset = mtd->oobsize - oobregion->length;
123
124 return 0;
125}
126
127static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
128 struct mtd_oob_region *oobregion)
129{
130 struct nand_chip *chip = mtd_to_nand(mtd);
131 struct nand_ecc_ctrl *ecc = &chip->ecc;
132
133 if (section)
134 return -ERANGE;
135
136 oobregion->length = mtd->oobsize - ecc->total - 2;
137 oobregion->offset = 2;
138
139 return 0;
140}
141
142const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
143 .ecc = nand_ooblayout_ecc_lp,
144 .free = nand_ooblayout_free_lp,
145};
146EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
d470a97c 147
6a623e07
AC		 148/*
149 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
150 * are placed at a fixed offset.
151 */
152static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
153 struct mtd_oob_region *oobregion)
154{
155 struct nand_chip *chip = mtd_to_nand(mtd);
156 struct nand_ecc_ctrl *ecc = &chip->ecc;
157
158 if (section)
159 return -ERANGE;
160
161 switch (mtd->oobsize) {
162 case 64:
163 oobregion->offset = 40;
164 break;
165 case 128:
166 oobregion->offset = 80;
167 break;
168 default:
169 return -EINVAL;
170 }
171
172 oobregion->length = ecc->total;
173 if (oobregion->offset + oobregion->length > mtd->oobsize)
174 return -ERANGE;
175
176 return 0;
177}
178
179static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
180 struct mtd_oob_region *oobregion)
181{
182 struct nand_chip *chip = mtd_to_nand(mtd);
183 struct nand_ecc_ctrl *ecc = &chip->ecc;
184 int ecc_offset = 0;
185
186 if (section < 0 || section > 1)
187 return -ERANGE;
188
189 switch (mtd->oobsize) {
190 case 64:
191 ecc_offset = 40;
192 break;
193 case 128:
194 ecc_offset = 80;
195 break;
196 default:
197 return -EINVAL;
198 }
199
200 if (section == 0) {
201 oobregion->offset = 2;
202 oobregion->length = ecc_offset - 2;
203 } else {
204 oobregion->offset = ecc_offset + ecc->total;
205 oobregion->length = mtd->oobsize - oobregion->offset;
206 }
207
208 return 0;
209}
210
d4ed3b90 211static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
6a623e07
AC		 212 .ecc = nand_ooblayout_ecc_lp_hamming,
213 .free = nand_ooblayout_free_lp_hamming,
214};
215
6fe5a6ac
VS		 216static int check_offs_len(struct mtd_info *mtd,
217 loff_t ofs, uint64_t len)
218{
862eba51 219 struct nand_chip *chip = mtd_to_nand(mtd);
6fe5a6ac
VS		 220 int ret = 0;
221
222 /* Start address must align on block boundary */
daae74ca 223 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 224 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 225 ret = -EINVAL;
226 }
227
228 /* Length must align on block boundary */
daae74ca 229 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 230 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 231 ret = -EINVAL;
232 }
233
6fe5a6ac
VS		 234 return ret;
235}
236
1da177e4
LT		 237/**
238 * nand_release_device - [GENERIC] release chip
8b6e50c9 239 * @mtd: MTD device structure
61b03bd7 240 *
b0bb6903 241 * Release chip lock and wake up anyone waiting on the device.
1da177e4 242 */
e0c7d767 243static void nand_release_device(struct mtd_info *mtd)
1da177e4 244{
862eba51 245 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 246
a36ed299 247 /* Release the controller and the chip */
ace4dfee
TG		 248 spin_lock(&chip->controller->lock);
249 chip->controller->active = NULL;
250 chip->state = FL_READY;
251 wake_up(&chip->controller->wq);
252 spin_unlock(&chip->controller->lock);
1da177e4
LT		 253}
254
255/**
256 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 257 * @mtd: MTD device structure
1da177e4 258 *
7854d3f7 259 * Default read function for 8bit buswidth
1da177e4 260 */
58dd8f2b 261static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 262{
862eba51 263 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 264 return readb(chip->IO_ADDR_R);
1da177e4
LT		 265}
266
1da177e4 267/**
7854d3f7 268 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 269 * @mtd: MTD device structure
1da177e4 270 *
7854d3f7
BN		 271 * Default read function for 16bit buswidth with endianness conversion.
272 *
1da177e4 273 */
58dd8f2b 274static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 275{
862eba51 276 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 277 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 278}
279
1da177e4
LT		 280/**
281 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 282 * @mtd: MTD device structure
1da177e4 283 *
7854d3f7 284 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 285 */
286static u16 nand_read_word(struct mtd_info *mtd)
287{
862eba51 288 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 289 return readw(chip->IO_ADDR_R);
1da177e4
LT		 290}
291
1da177e4
LT		 292/**
293 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 294 * @mtd: MTD device structure
295 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 296 *
297 * Default select function for 1 chip devices.
298 */
ace4dfee 299static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 300{
862eba51 301 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 302
303 switch (chipnr) {
1da177e4 304 case -1:
ace4dfee 305 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 306 break;
307 case 0:
1da177e4
LT		 308 break;
309
310 default:
311 BUG();
312 }
313}
314
05f78359
UKK		 315/**
316 * nand_write_byte - [DEFAULT] write single byte to chip
317 * @mtd: MTD device structure
318 * @byte: value to write
319 *
320 * Default function to write a byte to I/O[7:0]
321 */
322static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
323{
862eba51 324 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 325
326 chip->write_buf(mtd, &byte, 1);
327}
328
329/**
330 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
331 * @mtd: MTD device structure
332 * @byte: value to write
333 *
334 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
335 */
336static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
337{
862eba51 338 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 339 uint16_t word = byte;
340
341 /*
342 * It's not entirely clear what should happen to I/O[15:8] when writing
343 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
344 *
345 * When the host supports a 16-bit bus width, only data is
346 * transferred at the 16-bit width. All address and command line
347 * transfers shall use only the lower 8-bits of the data bus. During
348 * command transfers, the host may place any value on the upper
349 * 8-bits of the data bus. During address transfers, the host shall
350 * set the upper 8-bits of the data bus to 00h.
351 *
352 * One user of the write_byte callback is nand_onfi_set_features. The
353 * four parameters are specified to be written to I/O[7:0], but this is
354 * neither an address nor a command transfer. Let's assume a 0 on the
355 * upper I/O lines is OK.
356 */
357 chip->write_buf(mtd, (uint8_t *)&word, 2);
358}
359
1da177e4
LT		 360/**
361 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 362 * @mtd: MTD device structure
363 * @buf: data buffer
364 * @len: number of bytes to write
1da177e4 365 *
7854d3f7 366 * Default write function for 8bit buswidth.
1da177e4 367 */
58dd8f2b 368static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 369{
862eba51 370 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 371
76413839 372 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 373}
374
375/**
61b03bd7 376 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 377 * @mtd: MTD device structure
378 * @buf: buffer to store date
379 * @len: number of bytes to read
1da177e4 380 *
7854d3f7 381 * Default read function for 8bit buswidth.
1da177e4 382 */
58dd8f2b 383static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 384{
862eba51 385 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 386
76413839 387 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 388}
389
1da177e4
LT		 390/**
391 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 392 * @mtd: MTD device structure
393 * @buf: data buffer
394 * @len: number of bytes to write
1da177e4 395 *
7854d3f7 396 * Default write function for 16bit buswidth.
1da177e4 397 */
58dd8f2b 398static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 399{
862eba51 400 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 401 u16 *p = (u16 *) buf;
61b03bd7 402
76413839 403 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 404}
405
406/**
61b03bd7 407 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 408 * @mtd: MTD device structure
409 * @buf: buffer to store date
410 * @len: number of bytes to read
1da177e4 411 *
7854d3f7 412 * Default read function for 16bit buswidth.
1da177e4 413 */
58dd8f2b 414static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 415{
862eba51 416 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 417 u16 *p = (u16 *) buf;
1da177e4 418
76413839 419 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 420}
421
1da177e4
LT		 422/**
423 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 424 * @mtd: MTD device structure
425 * @ofs: offset from device start
1da177e4 426 *
61b03bd7 427 * Check, if the block is bad.
1da177e4 428 */
9f3e0429 429static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1da177e4 430{
c120e75e 431 int page, page_end, res;
862eba51 432 struct nand_chip *chip = mtd_to_nand(mtd);
c120e75e 433 u8 bad;
1da177e4 434
5fb1549d 435 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 436 ofs += mtd->erasesize - mtd->writesize;
437
1a12f46a 438 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
c120e75e 439 page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1);
1a12f46a 440
c120e75e
MY		 441 for (; page < page_end; page++) {
442 res = chip->ecc.read_oob(mtd, chip, page);
443 if (res)
444 return res;
445
446 bad = chip->oob_poi[chip->badblockpos];
cdbec050
BN		 447
448 if (likely(chip->badblockbits == 8))
449 res = bad != 0xFF;
e0b58d0a 450 else
cdbec050 451 res = hweight8(bad) < chip->badblockbits;
c120e75e
MY		 452 if (res)
453 return res;
454 }
e0b58d0a 455
c120e75e 456 return 0;
1da177e4
LT		 457}
458
459/**
5a0edb25 460 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 461 * @mtd: MTD device structure
462 * @ofs: offset from device start
1da177e4 463 *
8b6e50c9 464 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 465 * specific driver. It provides the details for writing a bad block marker to a
466 * block.
467 */
468static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
469{
862eba51 470 struct nand_chip *chip = mtd_to_nand(mtd);
5a0edb25
BN		 471 struct mtd_oob_ops ops;
472 uint8_t buf[2] = { 0, 0 };
473 int ret = 0, res, i = 0;
474
0ec56dc4 475 memset(&ops, 0, sizeof(ops));
5a0edb25
BN		 476 ops.oobbuf = buf;
477 ops.ooboffs = chip->badblockpos;
478 if (chip->options & NAND_BUSWIDTH_16) {
479 ops.ooboffs &= ~0x01;
480 ops.len = ops.ooblen = 2;
481 } else {
482 ops.len = ops.ooblen = 1;
483 }
484 ops.mode = MTD_OPS_PLACE_OOB;
485
486 /* Write to first/last page(s) if necessary */
487 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
488 ofs += mtd->erasesize - mtd->writesize;
489 do {
490 res = nand_do_write_oob(mtd, ofs, &ops);
491 if (!ret)
492 ret = res;
493
494 i++;
495 ofs += mtd->writesize;
496 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
497
498 return ret;
499}
500
501/**
502 * nand_block_markbad_lowlevel - mark a block bad
503 * @mtd: MTD device structure
504 * @ofs: offset from device start
505 *
506 * This function performs the generic NAND bad block marking steps (i.e., bad
507 * block table(s) and/or marker(s)). We only allow the hardware driver to
508 * specify how to write bad block markers to OOB (chip->block_markbad).
509 *
b32843b7 510 * We try operations in the following order:
b6f6c294 511 *
e2414f4c 512 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 513 * (2) write bad block marker to OOB area of affected block (unless flag
514 * NAND_BBT_NO_OOB_BBM is present)
515 * (3) update the BBT
b6f6c294 516 *
b32843b7 517 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 518 * procedures, and dump the error in the end.
1da177e4 519*/
5a0edb25 520static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 521{
862eba51 522 struct nand_chip *chip = mtd_to_nand(mtd);
b32843b7 523 int res, ret = 0;
61b03bd7 524
b32843b7 525 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 526 struct erase_info einfo;
527
528 /* Attempt erase before marking OOB */
529 memset(&einfo, 0, sizeof(einfo));
530 einfo.mtd = mtd;
531 einfo.addr = ofs;
daae74ca 532 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 533 nand_erase_nand(mtd, &einfo, 0);
1da177e4 534
b32843b7 535 /* Write bad block marker to OOB */
6a8214aa 536 nand_get_device(mtd, FL_WRITING);
5a0edb25 537 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 538 nand_release_device(mtd);
f1a28c02 539 }
e2414f4c 540
b32843b7
BN		 541 /* Mark block bad in BBT */
542 if (chip->bbt) {
543 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 544 if (!ret)
545 ret = res;
546 }
547
f1a28c02
TG		 548 if (!ret)
549 mtd->ecc_stats.badblocks++;
c0b8ba7b 550
f1a28c02 551 return ret;
1da177e4
LT		 552}
553
61b03bd7 554/**
1da177e4 555 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 556 * @mtd: MTD device structure
1da177e4 557 *
8b6e50c9
BN		 558 * Check, if the device is write protected. The function expects, that the
559 * device is already selected.
1da177e4 560 */
e0c7d767 561static int nand_check_wp(struct mtd_info *mtd)
1da177e4 562{
862eba51 563 struct nand_chip *chip = mtd_to_nand(mtd);
93edbad6 564
8b6e50c9 565 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 566 if (chip->options & NAND_BROKEN_XD)
567 return 0;
568
1da177e4 569 /* Check the WP bit */
ace4dfee
TG		 570 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
571 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 572}
573
8471bb73 574/**
c30e1f79 575 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 576 * @mtd: MTD device structure
577 * @ofs: offset from device start
578 *
c30e1f79 579 * Check if the block is marked as reserved.
8471bb73
EG		 580 */
581static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
582{
862eba51 583 struct nand_chip *chip = mtd_to_nand(mtd);
8471bb73
EG		 584
585 if (!chip->bbt)
586 return 0;
587 /* Return info from the table */
588 return nand_isreserved_bbt(mtd, ofs);
589}
590
1da177e4
LT		 591/**
592 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 593 * @mtd: MTD device structure
594 * @ofs: offset from device start
8b6e50c9 595 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 596 *
597 * Check, if the block is bad. Either by reading the bad block table or
598 * calling of the scan function.
599 */
9f3e0429 600static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
1da177e4 601{
862eba51 602 struct nand_chip *chip = mtd_to_nand(mtd);
61b03bd7 603
ace4dfee 604 if (!chip->bbt)
9f3e0429 605 return chip->block_bad(mtd, ofs);
61b03bd7 606
1da177e4 607 /* Return info from the table */
e0c7d767 608 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 609}
610
2af7c653
SK		 611/**
612 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 613 * @mtd: MTD device structure
614 * @timeo: Timeout
2af7c653
SK		 615 *
616 * Helper function for nand_wait_ready used when needing to wait in interrupt
617 * context.
618 */
619static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
620{
862eba51 621 struct nand_chip *chip = mtd_to_nand(mtd);
2af7c653
SK		 622 int i;
623
624 /* Wait for the device to get ready */
625 for (i = 0; i < timeo; i++) {
626 if (chip->dev_ready(mtd))
627 break;
628 touch_softlockup_watchdog();
629 mdelay(1);
630 }
631}
632
b70af9be
AS		 633/**
634 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
635 * @mtd: MTD device structure
636 *
637 * Wait for the ready pin after a command, and warn if a timeout occurs.
638 */
4b648b02 639void nand_wait_ready(struct mtd_info *mtd)
3b88775c 640{
862eba51 641 struct nand_chip *chip = mtd_to_nand(mtd);
b70af9be 642 unsigned long timeo = 400;
3b88775c 643
2af7c653 644 if (in_interrupt() || oops_in_progress)
b70af9be 645 return panic_nand_wait_ready(mtd, timeo);
2af7c653 646
7854d3f7 647 /* Wait until command is processed or timeout occurs */
b70af9be 648 timeo = jiffies + msecs_to_jiffies(timeo);
3b88775c 649 do {
ace4dfee 650 if (chip->dev_ready(mtd))
4c7e054f 651 return;
b70af9be 652 cond_resched();
61b03bd7 653 } while (time_before(jiffies, timeo));
b70af9be 654
9ebfdf5b
BN		 655 if (!chip->dev_ready(mtd))
656 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
3b88775c 657}
4b648b02 658EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 659
60c70d66
RQ		 660/**
661 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
662 * @mtd: MTD device structure
663 * @timeo: Timeout in ms
664 *
665 * Wait for status ready (i.e. command done) or timeout.
666 */
667static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
668{
862eba51 669 register struct nand_chip *chip = mtd_to_nand(mtd);
60c70d66
RQ		 670
671 timeo = jiffies + msecs_to_jiffies(timeo);
672 do {
673 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
674 break;
675 touch_softlockup_watchdog();
676 } while (time_before(jiffies, timeo));
677};
678
1da177e4
LT		 679/**
680 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 681 * @mtd: MTD device structure
682 * @command: the command to be sent
683 * @column: the column address for this command, -1 if none
684 * @page_addr: the page address for this command, -1 if none
1da177e4 685 *
8b6e50c9 686 * Send command to NAND device. This function is used for small page devices
51148f1f 687 * (512 Bytes per page).
1da177e4 688 */
7abd3ef9
TG		 689static void nand_command(struct mtd_info *mtd, unsigned int command,
690 int column, int page_addr)
1da177e4 691{
862eba51 692 register struct nand_chip *chip = mtd_to_nand(mtd);
7abd3ef9 693 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 694
8b6e50c9 695 /* Write out the command to the device */
1da177e4
LT		 696 if (command == NAND_CMD_SEQIN) {
697 int readcmd;
698
28318776 699 if (column >= mtd->writesize) {
1da177e4 700 /* OOB area */
28318776 701 column -= mtd->writesize;
1da177e4
LT		 702 readcmd = NAND_CMD_READOOB;
703 } else if (column < 256) {
704 /* First 256 bytes --> READ0 */
705 readcmd = NAND_CMD_READ0;
706 } else {
707 column -= 256;
708 readcmd = NAND_CMD_READ1;
709 }
ace4dfee 710 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 711 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 712 }
df467899
MR		 713 if (command != NAND_CMD_NONE)
714 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 715
8b6e50c9 716 /* Address cycle, when necessary */
7abd3ef9
TG		 717 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
718 /* Serially input address */
719 if (column != -1) {
720 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 721 if (chip->options & NAND_BUSWIDTH_16 &&
722 !nand_opcode_8bits(command))
7abd3ef9 723 column >>= 1;
ace4dfee 724 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 725 ctrl &= ~NAND_CTRL_CHANGE;
726 }
727 if (page_addr != -1) {
ace4dfee 728 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 729 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 730 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
14157f86 731 if (chip->options & NAND_ROW_ADDR_3)
ace4dfee 732 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 733 }
ace4dfee 734 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 735
736 /*
8b6e50c9
BN		 737 * Program and erase have their own busy handlers status and sequential
738 * in needs no delay
e0c7d767 739 */
1da177e4 740 switch (command) {
61b03bd7 741
df467899 742 case NAND_CMD_NONE:
1da177e4
LT		 743 case NAND_CMD_PAGEPROG:
744 case NAND_CMD_ERASE1:
745 case NAND_CMD_ERASE2:
746 case NAND_CMD_SEQIN:
747 case NAND_CMD_STATUS:
3158fa0e 748 case NAND_CMD_READID:
c5d664aa 749 case NAND_CMD_SET_FEATURES:
1da177e4
LT		 750 return;
751
752 case NAND_CMD_RESET:
ace4dfee 753 if (chip->dev_ready)
1da177e4 754 break;
ace4dfee
TG		 755 udelay(chip->chip_delay);
756 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 757 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 758 chip->cmd_ctrl(mtd,
759 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 760 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
761 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 762 return;
763
e0c7d767 764 /* This applies to read commands */
2165c4a1
BB		 765 case NAND_CMD_READ0:
766 /*
767 * READ0 is sometimes used to exit GET STATUS mode. When this
768 * is the case no address cycles are requested, and we can use
769 * this information to detect that we should not wait for the
770 * device to be ready.
771 */
772 if (column == -1 && page_addr == -1)
773 return;
774
1da177e4 775 default:
61b03bd7 776 /*
1da177e4
LT		 777 * If we don't have access to the busy pin, we apply the given
778 * command delay
e0c7d767 779 */
ace4dfee
TG		 780 if (!chip->dev_ready) {
781 udelay(chip->chip_delay);
1da177e4 782 return;
61b03bd7 783 }
1da177e4 784 }
8b6e50c9
BN		 785 /*
786 * Apply this short delay always to ensure that we do wait tWB in
787 * any case on any machine.
788 */
e0c7d767 789 ndelay(100);
3b88775c
TG		 790
791 nand_wait_ready(mtd);
1da177e4
LT		 792}
793
6ea40a3b
BB		 794static void nand_ccs_delay(struct nand_chip *chip)
795{
796 /*
797 * The controller already takes care of waiting for tCCS when the RNDIN
798 * or RNDOUT command is sent, return directly.
799 */
800 if (!(chip->options & NAND_WAIT_TCCS))
801 return;
802
803 /*
804 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
805 * (which should be safe for all NANDs).
806 */
807 if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
808 ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
809 else
810 ndelay(500);
811}
812
1da177e4
LT		 813/**
814 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 815 * @mtd: MTD device structure
816 * @command: the command to be sent
817 * @column: the column address for this command, -1 if none
818 * @page_addr: the page address for this command, -1 if none
1da177e4 819 *
7abd3ef9 820 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 821 * devices. We don't have the separate regions as we have in the small page
822 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 823 */
7abd3ef9
TG		 824static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
825 int column, int page_addr)
1da177e4 826{
862eba51 827 register struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 828
829 /* Emulate NAND_CMD_READOOB */
830 if (command == NAND_CMD_READOOB) {
28318776 831 column += mtd->writesize;
1da177e4
LT		 832 command = NAND_CMD_READ0;
833 }
61b03bd7 834
7abd3ef9 835 /* Command latch cycle */
df467899
MR		 836 if (command != NAND_CMD_NONE)
837 chip->cmd_ctrl(mtd, command,
838 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 839
840 if (column != -1 || page_addr != -1) {
7abd3ef9 841 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 842
843 /* Serially input address */
844 if (column != -1) {
845 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 846 if (chip->options & NAND_BUSWIDTH_16 &&
847 !nand_opcode_8bits(command))
1da177e4 848 column >>= 1;
ace4dfee 849 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 850 ctrl &= ~NAND_CTRL_CHANGE;
fde85cfd 851
f5b88de2 852 /* Only output a single addr cycle for 8bits opcodes. */
fde85cfd
BB		 853 if (!nand_opcode_8bits(command))
854 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 855 }
1da177e4 856 if (page_addr != -1) {
ace4dfee
TG		 857 chip->cmd_ctrl(mtd, page_addr, ctrl);
858 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 859 NAND_NCE | NAND_ALE);
14157f86 860 if (chip->options & NAND_ROW_ADDR_3)
ace4dfee 861 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 862 NAND_NCE | NAND_ALE);
1da177e4 863 }
1da177e4 864 }
ace4dfee 865 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 866
867 /*
8b6e50c9 868 * Program and erase have their own busy handlers status, sequential
7a442f17 869 * in and status need no delay.
30f464b7 870 */
1da177e4 871 switch (command) {
61b03bd7 872
df467899 873 case NAND_CMD_NONE:
1da177e4
LT		 874 case NAND_CMD_CACHEDPROG:
875 case NAND_CMD_PAGEPROG:
876 case NAND_CMD_ERASE1:
877 case NAND_CMD_ERASE2:
878 case NAND_CMD_SEQIN:
879 case NAND_CMD_STATUS:
3158fa0e 880 case NAND_CMD_READID:
c5d664aa 881 case NAND_CMD_SET_FEATURES:
30f464b7 882 return;
1da177e4 883
6ea40a3b
BB		 884 case NAND_CMD_RNDIN:
885 nand_ccs_delay(chip);
886 return;
887
1da177e4 888 case NAND_CMD_RESET:
ace4dfee 889 if (chip->dev_ready)
1da177e4 890 break;
ace4dfee 891 udelay(chip->chip_delay);
12efdde3
TG		 892 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
893 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
894 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
895 NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 896 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
897 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 898 return;
899
7bc3312b
TG		 900 case NAND_CMD_RNDOUT:
901 /* No ready / busy check necessary */
902 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
903 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
904 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
905 NAND_NCE | NAND_CTRL_CHANGE);
6ea40a3b
BB		 906
907 nand_ccs_delay(chip);
7bc3312b
TG		 908 return;
909
1da177e4 910 case NAND_CMD_READ0:
2165c4a1
BB		 911 /*
912 * READ0 is sometimes used to exit GET STATUS mode. When this
913 * is the case no address cycles are requested, and we can use
914 * this information to detect that READSTART should not be
915 * issued.
916 */
917 if (column == -1 && page_addr == -1)
918 return;
919
12efdde3
TG		 920 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
921 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
922 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
923 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 924
e0c7d767 925 /* This applies to read commands */
1da177e4 926 default:
61b03bd7 927 /*
1da177e4 928 * If we don't have access to the busy pin, we apply the given
8b6e50c9 929 * command delay.
e0c7d767 930 */
ace4dfee
TG		 931 if (!chip->dev_ready) {
932 udelay(chip->chip_delay);
1da177e4 933 return;
61b03bd7 934 }
1da177e4 935 }
3b88775c 936
8b6e50c9
BN		 937 /*
938 * Apply this short delay always to ensure that we do wait tWB in
939 * any case on any machine.
940 */
e0c7d767 941 ndelay(100);
3b88775c
TG		 942
943 nand_wait_ready(mtd);
1da177e4
LT		 944}
945
2af7c653
SK		 946/**
947 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 948 * @chip: the nand chip descriptor
949 * @mtd: MTD device structure
950 * @new_state: the state which is requested
2af7c653
SK		 951 *
952 * Used when in panic, no locks are taken.
953 */
954static void panic_nand_get_device(struct nand_chip *chip,
955 struct mtd_info *mtd, int new_state)
956{
7854d3f7 957 /* Hardware controller shared among independent devices */
2af7c653
SK		 958 chip->controller->active = chip;
959 chip->state = new_state;
960}
961
1da177e4
LT		 962/**
963 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 964 * @mtd: MTD device structure
965 * @new_state: the state which is requested
1da177e4
LT		 966 *
967 * Get the device and lock it for exclusive access
968 */
2c0a2bed 969static int
6a8214aa 970nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 971{
862eba51 972 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 973 spinlock_t *lock = &chip->controller->lock;
974 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 975 DECLARE_WAITQUEUE(wait, current);
7351d3a5 976retry:
0dfc6246
TG		 977 spin_lock(lock);
978
b8b3ee9a 979 /* Hardware controller shared among independent devices */
ace4dfee
TG		 980 if (!chip->controller->active)
981 chip->controller->active = chip;
a36ed299 982
ace4dfee
TG		 983 if (chip->controller->active == chip && chip->state == FL_READY) {
984 chip->state = new_state;
0dfc6246 985 spin_unlock(lock);
962034f4
VW		 986 return 0;
987 }
988 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 989 if (chip->controller->active->state == FL_PM_SUSPENDED) {
990 chip->state = FL_PM_SUSPENDED;
991 spin_unlock(lock);
992 return 0;
6b0d9a84 993 }
0dfc6246
TG		 994 }
995 set_current_state(TASK_UNINTERRUPTIBLE);
996 add_wait_queue(wq, &wait);
997 spin_unlock(lock);
998 schedule();
999 remove_wait_queue(wq, &wait);
1da177e4
LT		 1000 goto retry;
1001}
1002
2af7c653 1003/**
8b6e50c9
BN		 1004 * panic_nand_wait - [GENERIC] wait until the command is done
1005 * @mtd: MTD device structure
1006 * @chip: NAND chip structure
1007 * @timeo: timeout
2af7c653
SK		 1008 *
1009 * Wait for command done. This is a helper function for nand_wait used when
1010 * we are in interrupt context. May happen when in panic and trying to write
b595076a 1011 * an oops through mtdoops.
2af7c653
SK		 1012 */
1013static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
1014 unsigned long timeo)
1015{
1016 int i;
1017 for (i = 0; i < timeo; i++) {
1018 if (chip->dev_ready) {
1019 if (chip->dev_ready(mtd))
1020 break;
1021 } else {
1022 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1023 break;
1024 }
1025 mdelay(1);
f8ac0414 1026 }
2af7c653
SK		 1027}
1028
1da177e4 1029/**
8b6e50c9
BN		 1030 * nand_wait - [DEFAULT] wait until the command is done
1031 * @mtd: MTD device structure
1032 * @chip: NAND chip structure
1da177e4 1033 *
b70af9be 1034 * Wait for command done. This applies to erase and program only.
844d3b42 1035 */
7bc3312b 1036static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 1037{
1038
b70af9be
AS		 1039 int status;
1040 unsigned long timeo = 400;
1da177e4 1041
8b6e50c9
BN		 1042 /*
1043 * Apply this short delay always to ensure that we do wait tWB in any
1044 * case on any machine.
1045 */
e0c7d767 1046 ndelay(100);
1da177e4 1047
14c65786 1048 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 1049
2af7c653
SK		 1050 if (in_interrupt() || oops_in_progress)
1051 panic_nand_wait(mtd, chip, timeo);
1052 else {
6d2559f8 1053 timeo = jiffies + msecs_to_jiffies(timeo);
b70af9be 1054 do {
2af7c653
SK		 1055 if (chip->dev_ready) {
1056 if (chip->dev_ready(mtd))
1057 break;
1058 } else {
1059 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1060 break;
1061 }
1062 cond_resched();
b70af9be 1063 } while (time_before(jiffies, timeo));
1da177e4 1064 }
8fe833c1 1065
ace4dfee 1066 status = (int)chip->read_byte(mtd);
f251b8df
MC		 1067 /* This can happen if in case of timeout or buggy dev_ready */
1068 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 1069 return status;
1070}
1071
d8e725dd
BB		 1072/**
1073 * nand_reset_data_interface - Reset data interface and timings
1074 * @chip: The NAND chip
104e442a 1075 * @chipnr: Internal die id
d8e725dd
BB		 1076 *
1077 * Reset the Data interface and timings to ONFI mode 0.
1078 *
1079 * Returns 0 for success or negative error code otherwise.
1080 */
104e442a 1081static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
d8e725dd
BB		 1082{
1083 struct mtd_info *mtd = nand_to_mtd(chip);
1084 const struct nand_data_interface *conf;
1085 int ret;
1086
1087 if (!chip->setup_data_interface)
1088 return 0;
1089
1090 /*
1091 * The ONFI specification says:
1092 * "
1093 * To transition from NV-DDR or NV-DDR2 to the SDR data
1094 * interface, the host shall use the Reset (FFh) command
1095 * using SDR timing mode 0. A device in any timing mode is
1096 * required to recognize Reset (FFh) command issued in SDR
1097 * timing mode 0.
1098 * "
1099 *
1100 * Configure the data interface in SDR mode and set the
1101 * timings to timing mode 0.
1102 */
1103
1104 conf = nand_get_default_data_interface();
104e442a 1105 ret = chip->setup_data_interface(mtd, chipnr, conf);
d8e725dd
BB		 1106 if (ret)
1107 pr_err("Failed to configure data interface to SDR timing mode 0\n");
1108
1109 return ret;
1110}
1111
1112/**
1113 * nand_setup_data_interface - Setup the best data interface and timings
1114 * @chip: The NAND chip
104e442a 1115 * @chipnr: Internal die id
d8e725dd
BB		 1116 *
1117 * Find and configure the best data interface and NAND timings supported by
1118 * the chip and the driver.
1119 * First tries to retrieve supported timing modes from ONFI information,
1120 * and if the NAND chip does not support ONFI, relies on the
1121 * ->onfi_timing_mode_default specified in the nand_ids table.
1122 *
1123 * Returns 0 for success or negative error code otherwise.
1124 */
104e442a 1125static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
d8e725dd
BB		 1126{
1127 struct mtd_info *mtd = nand_to_mtd(chip);
1128 int ret;
1129
1130 if (!chip->setup_data_interface || !chip->data_interface)
1131 return 0;
1132
1133 /*
1134 * Ensure the timing mode has been changed on the chip side
1135 * before changing timings on the controller side.
1136 */
a11bf5ed
BB		 1137 if (chip->onfi_version &&
1138 (le16_to_cpu(chip->onfi_params.opt_cmd) &
1139 ONFI_OPT_CMD_SET_GET_FEATURES)) {
d8e725dd
BB		 1140 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1141 chip->onfi_timing_mode_default,
1142 };
1143
1144 ret = chip->onfi_set_features(mtd, chip,
1145 ONFI_FEATURE_ADDR_TIMING_MODE,
1146 tmode_param);
1147 if (ret)
1148 goto err;
1149 }
1150
104e442a 1151 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
d8e725dd
BB		 1152err:
1153 return ret;
1154}
1155
1156/**
1157 * nand_init_data_interface - find the best data interface and timings
1158 * @chip: The NAND chip
1159 *
1160 * Find the best data interface and NAND timings supported by the chip
1161 * and the driver.
1162 * First tries to retrieve supported timing modes from ONFI information,
1163 * and if the NAND chip does not support ONFI, relies on the
1164 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1165 * function nand_chip->data_interface is initialized with the best timing mode
1166 * available.
1167 *
1168 * Returns 0 for success or negative error code otherwise.
1169 */
1170static int nand_init_data_interface(struct nand_chip *chip)
1171{
1172 struct mtd_info *mtd = nand_to_mtd(chip);
1173 int modes, mode, ret;
1174
1175 if (!chip->setup_data_interface)
1176 return 0;
1177
1178 /*
1179 * First try to identify the best timings from ONFI parameters and
1180 * if the NAND does not support ONFI, fallback to the default ONFI
1181 * timing mode.
1182 */
1183 modes = onfi_get_async_timing_mode(chip);
1184 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1185 if (!chip->onfi_timing_mode_default)
1186 return 0;
1187
1188 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1189 }
1190
1191 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1192 GFP_KERNEL);
1193 if (!chip->data_interface)
1194 return -ENOMEM;
1195
1196 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1197 ret = onfi_init_data_interface(chip, chip->data_interface,
1198 NAND_SDR_IFACE, mode);
1199 if (ret)
1200 continue;
1201
104e442a
BB		 1202 /* Pass -1 to only */
1203 ret = chip->setup_data_interface(mtd,
1204 NAND_DATA_IFACE_CHECK_ONLY,
1205 chip->data_interface);
d8e725dd
BB		 1206 if (!ret) {
1207 chip->onfi_timing_mode_default = mode;
1208 break;
1209 }
1210 }
1211
1212 return 0;
1213}
1214
1215static void nand_release_data_interface(struct nand_chip *chip)
1216{
1217 kfree(chip->data_interface);
1218}
1219
2f94abfe
SH		 1220/**
1221 * nand_reset - Reset and initialize a NAND device
1222 * @chip: The NAND chip
73f907fd 1223 * @chipnr: Internal die id
2f94abfe
SH		 1224 *
1225 * Returns 0 for success or negative error code otherwise
1226 */
73f907fd 1227int nand_reset(struct nand_chip *chip, int chipnr)
2f94abfe
SH		 1228{
1229 struct mtd_info *mtd = nand_to_mtd(chip);
d8e725dd
BB		 1230 int ret;
1231
104e442a 1232 ret = nand_reset_data_interface(chip, chipnr);
d8e725dd
BB		 1233 if (ret)
1234 return ret;
2f94abfe 1235
73f907fd
BB		 1236 /*
1237 * The CS line has to be released before we can apply the new NAND
1238 * interface settings, hence this weird ->select_chip() dance.
1239 */
1240 chip->select_chip(mtd, chipnr);
2f94abfe 1241 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
73f907fd 1242 chip->select_chip(mtd, -1);
2f94abfe 1243
73f907fd 1244 chip->select_chip(mtd, chipnr);
104e442a 1245 ret = nand_setup_data_interface(chip, chipnr);
73f907fd 1246 chip->select_chip(mtd, -1);
d8e725dd
BB		 1247 if (ret)
1248 return ret;
1249
2f94abfe
SH		 1250 return 0;
1251}
b9bb9842 1252EXPORT_SYMBOL_GPL(nand_reset);
2f94abfe 1253
730a43fb
BB		 1254/**
1255 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1256 * @buf: buffer to test
1257 * @len: buffer length
1258 * @bitflips_threshold: maximum number of bitflips
1259 *
1260 * Check if a buffer contains only 0xff, which means the underlying region
1261 * has been erased and is ready to be programmed.
1262 * The bitflips_threshold specify the maximum number of bitflips before
1263 * considering the region is not erased.
1264 * Note: The logic of this function has been extracted from the memweight
1265 * implementation, except that nand_check_erased_buf function exit before
1266 * testing the whole buffer if the number of bitflips exceed the
1267 * bitflips_threshold value.
1268 *
1269 * Returns a positive number of bitflips less than or equal to
1270 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1271 * threshold.
1272 */
1273static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1274{
1275 const unsigned char *bitmap = buf;
1276 int bitflips = 0;
1277 int weight;
1278
1279 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1280 len--, bitmap++) {
1281 weight = hweight8(*bitmap);
1282 bitflips += BITS_PER_BYTE - weight;
1283 if (unlikely(bitflips > bitflips_threshold))
1284 return -EBADMSG;
1285 }
1286
1287 for (; len >= sizeof(long);
1288 len -= sizeof(long), bitmap += sizeof(long)) {
086567f1
PM		 1289 unsigned long d = *((unsigned long *)bitmap);
1290 if (d == ~0UL)
1291 continue;
1292 weight = hweight_long(d);
730a43fb
BB		 1293 bitflips += BITS_PER_LONG - weight;
1294 if (unlikely(bitflips > bitflips_threshold))
1295 return -EBADMSG;
1296 }
1297
1298 for (; len > 0; len--, bitmap++) {
1299 weight = hweight8(*bitmap);
1300 bitflips += BITS_PER_BYTE - weight;
1301 if (unlikely(bitflips > bitflips_threshold))
1302 return -EBADMSG;
1303 }
1304
1305 return bitflips;
1306}
1307
1308/**
1309 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1310 * 0xff data
1311 * @data: data buffer to test
1312 * @datalen: data length
1313 * @ecc: ECC buffer
1314 * @ecclen: ECC length
1315 * @extraoob: extra OOB buffer
1316 * @extraooblen: extra OOB length
1317 * @bitflips_threshold: maximum number of bitflips
1318 *
1319 * Check if a data buffer and its associated ECC and OOB data contains only
1320 * 0xff pattern, which means the underlying region has been erased and is
1321 * ready to be programmed.
1322 * The bitflips_threshold specify the maximum number of bitflips before
1323 * considering the region as not erased.
1324 *
1325 * Note:
1326 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1327 * different from the NAND page size. When fixing bitflips, ECC engines will
1328 * report the number of errors per chunk, and the NAND core infrastructure
1329 * expect you to return the maximum number of bitflips for the whole page.
1330 * This is why you should always use this function on a single chunk and
1331 * not on the whole page. After checking each chunk you should update your
1332 * max_bitflips value accordingly.
1333 * 2/ When checking for bitflips in erased pages you should not only check
1334 * the payload data but also their associated ECC data, because a user might
1335 * have programmed almost all bits to 1 but a few. In this case, we
1336 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1337 * this case.
1338 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1339 * data are protected by the ECC engine.
1340 * It could also be used if you support subpages and want to attach some
1341 * extra OOB data to an ECC chunk.
1342 *
1343 * Returns a positive number of bitflips less than or equal to
1344 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1345 * threshold. In case of success, the passed buffers are filled with 0xff.
1346 */
1347int nand_check_erased_ecc_chunk(void *data, int datalen,
1348 void *ecc, int ecclen,
1349 void *extraoob, int extraooblen,
1350 int bitflips_threshold)
1351{
1352 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1353
1354 data_bitflips = nand_check_erased_buf(data, datalen,
1355 bitflips_threshold);
1356 if (data_bitflips < 0)
1357 return data_bitflips;
1358
1359 bitflips_threshold -= data_bitflips;
1360
1361 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1362 if (ecc_bitflips < 0)
1363 return ecc_bitflips;
1364
1365 bitflips_threshold -= ecc_bitflips;
1366
1367 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1368 bitflips_threshold);
1369 if (extraoob_bitflips < 0)
1370 return extraoob_bitflips;
1371
1372 if (data_bitflips)
1373 memset(data, 0xff, datalen);
1374
1375 if (ecc_bitflips)
1376 memset(ecc, 0xff, ecclen);
1377
1378 if (extraoob_bitflips)
1379 memset(extraoob, 0xff, extraooblen);
1380
1381 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1382}
1383EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1384
8593fbc6 1385/**
7854d3f7 1386 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1387 * @mtd: mtd info structure
1388 * @chip: nand chip info structure
1389 * @buf: buffer to store read data
1fbb938d 1390 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1391 * @page: page number to read
52ff49df 1392 *
7854d3f7 1393 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1394 */
cc0f51ec
TP		 1395int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1396 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1397{
1398 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1399 if (oob_required)
1400 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1401 return 0;
1402}
cc0f51ec 1403EXPORT_SYMBOL(nand_read_page_raw);
8593fbc6 1404
52ff49df 1405/**
7854d3f7 1406 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1407 * @mtd: mtd info structure
1408 * @chip: nand chip info structure
1409 * @buf: buffer to store read data
1fbb938d 1410 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1411 * @page: page number to read
52ff49df
DB		 1412 *
1413 * We need a special oob layout and handling even when OOB isn't used.
1414 */
7351d3a5 1415static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1416 struct nand_chip *chip, uint8_t *buf,
1417 int oob_required, int page)
52ff49df
DB		 1418{
1419 int eccsize = chip->ecc.size;
1420 int eccbytes = chip->ecc.bytes;
1421 uint8_t *oob = chip->oob_poi;
1422 int steps, size;
1423
1424 for (steps = chip->ecc.steps; steps > 0; steps--) {
1425 chip->read_buf(mtd, buf, eccsize);
1426 buf += eccsize;
1427
1428 if (chip->ecc.prepad) {
1429 chip->read_buf(mtd, oob, chip->ecc.prepad);
1430 oob += chip->ecc.prepad;
1431 }
1432
1433 chip->read_buf(mtd, oob, eccbytes);
1434 oob += eccbytes;
1435
1436 if (chip->ecc.postpad) {
1437 chip->read_buf(mtd, oob, chip->ecc.postpad);
1438 oob += chip->ecc.postpad;
1439 }
1440 }
1441
1442 size = mtd->oobsize - (oob - chip->oob_poi);
1443 if (size)
1444 chip->read_buf(mtd, oob, size);
1445
1446 return 0;
1447}
1448
1da177e4 1449/**
7854d3f7 1450 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1451 * @mtd: mtd info structure
1452 * @chip: nand chip info structure
1453 * @buf: buffer to store read data
1fbb938d 1454 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1455 * @page: page number to read
068e3c0a 1456 */
f5bbdacc 1457static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1458 uint8_t *buf, int oob_required, int page)
1da177e4 1459{
846031d3 1460 int i, eccsize = chip->ecc.size, ret;
f5bbdacc
TG		 1461 int eccbytes = chip->ecc.bytes;
1462 int eccsteps = chip->ecc.steps;
1463 uint8_t *p = buf;
4bf63fcb
DW		 1464 uint8_t *ecc_calc = chip->buffers->ecccalc;
1465 uint8_t *ecc_code = chip->buffers->ecccode;
3f91e94f 1466 unsigned int max_bitflips = 0;
f5bbdacc 1467
1fbb938d 1468 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1469
1470 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1471 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1472
846031d3
BB		 1473 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1474 chip->ecc.total);
1475 if (ret)
1476 return ret;
f5bbdacc
TG		 1477
1478 eccsteps = chip->ecc.steps;
1479 p = buf;
1480
1481 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1482 int stat;
1483
1484 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1485 if (stat < 0) {
f5bbdacc 1486 mtd->ecc_stats.failed++;
3f91e94f 1487 } else {
f5bbdacc 1488 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1489 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1490 }
f5bbdacc 1491 }
3f91e94f 1492 return max_bitflips;
22c60f5f 1493}
1da177e4 1494
3d459559 1495/**
837a6ba4 1496 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1497 * @mtd: mtd info structure
1498 * @chip: nand chip info structure
1499 * @data_offs: offset of requested data within the page
1500 * @readlen: data length
1501 * @bufpoi: buffer to store read data
e004debd 1502 * @page: page number to read
3d459559 1503 */
7351d3a5 1504static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1505 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1506 int page)
3d459559 1507{
846031d3 1508 int start_step, end_step, num_steps, ret;
3d459559
AK		 1509 uint8_t *p;
1510 int data_col_addr, i, gaps = 0;
1511 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1512 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
846031d3 1513 int index, section = 0;
3f91e94f 1514 unsigned int max_bitflips = 0;
846031d3 1515 struct mtd_oob_region oobregion = { };
3d459559 1516
7854d3f7 1517 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1518 start_step = data_offs / chip->ecc.size;
1519 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1520 num_steps = end_step - start_step + 1;
4a4163ca 1521 index = start_step * chip->ecc.bytes;
3d459559 1522
8b6e50c9 1523 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1524 datafrag_len = num_steps * chip->ecc.size;
1525 eccfrag_len = num_steps * chip->ecc.bytes;
1526
1527 data_col_addr = start_step * chip->ecc.size;
1528 /* If we read not a page aligned data */
1529 if (data_col_addr != 0)
1530 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1531
1532 p = bufpoi + data_col_addr;
1533 chip->read_buf(mtd, p, datafrag_len);
1534
8b6e50c9 1535 /* Calculate ECC */
3d459559
AK		 1536 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1537 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1538
8b6e50c9
BN		 1539 /*
1540 * The performance is faster if we position offsets according to
7854d3f7 1541 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1542 */
846031d3
BB		 1543 ret = mtd_ooblayout_find_eccregion(mtd, index, &section, &oobregion);
1544 if (ret)
1545 return ret;
1546
1547 if (oobregion.length < eccfrag_len)
1548 gaps = 1;
1549
3d459559
AK		 1550 if (gaps) {
1551 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1552 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1553 } else {
8b6e50c9 1554 /*
7854d3f7 1555 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1556 * about buswidth alignment in read_buf.
1557 */
846031d3 1558 aligned_pos = oobregion.offset & ~(busw - 1);
3d459559 1559 aligned_len = eccfrag_len;
846031d3 1560 if (oobregion.offset & (busw - 1))
3d459559 1561 aligned_len++;
846031d3
BB		 1562 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
1563 (busw - 1))
3d459559
AK		 1564 aligned_len++;
1565
7351d3a5 1566 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
846031d3 1567 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1568 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1569 }
1570
846031d3
BB		 1571 ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
1572 chip->oob_poi, index, eccfrag_len);
1573 if (ret)
1574 return ret;
3d459559
AK		 1575
1576 p = bufpoi + data_col_addr;
1577 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1578 int stat;
1579
7351d3a5
FF		 1580 stat = chip->ecc.correct(mtd, p,
1581 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
40cbe6ee
BB		 1582 if (stat == -EBADMSG &&
1583 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1584 /* check for empty pages with bitflips */
1585 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1586 &chip->buffers->ecccode[i],
1587 chip->ecc.bytes,
1588 NULL, 0,
1589 chip->ecc.strength);
1590 }
1591
3f91e94f 1592 if (stat < 0) {
3d459559 1593 mtd->ecc_stats.failed++;
3f91e94f 1594 } else {
3d459559 1595 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1596 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1597 }
3d459559 1598 }
3f91e94f 1599 return max_bitflips;
3d459559
AK		 1600}
1601
068e3c0a 1602/**
7854d3f7 1603 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1604 * @mtd: mtd info structure
1605 * @chip: nand chip info structure
1606 * @buf: buffer to store read data
1fbb938d 1607 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1608 * @page: page number to read
068e3c0a 1609 *
7854d3f7 1610 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1611 */
f5bbdacc 1612static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1613 uint8_t *buf, int oob_required, int page)
1da177e4 1614{
846031d3 1615 int i, eccsize = chip->ecc.size, ret;
f5bbdacc
TG		 1616 int eccbytes = chip->ecc.bytes;
1617 int eccsteps = chip->ecc.steps;
1618 uint8_t *p = buf;
4bf63fcb
DW		 1619 uint8_t *ecc_calc = chip->buffers->ecccalc;
1620 uint8_t *ecc_code = chip->buffers->ecccode;
3f91e94f 1621 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1622
1623 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1624 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1625 chip->read_buf(mtd, p, eccsize);
1626 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1627 }
f75e5097 1628 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1629
846031d3
BB		 1630 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1631 chip->ecc.total);
1632 if (ret)
1633 return ret;
1da177e4 1634
f5bbdacc
TG		 1635 eccsteps = chip->ecc.steps;
1636 p = buf;
61b03bd7 1637
f5bbdacc
TG		 1638 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1639 int stat;
1da177e4 1640
f5bbdacc 1641 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
40cbe6ee
BB		 1642 if (stat == -EBADMSG &&
1643 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1644 /* check for empty pages with bitflips */
1645 stat = nand_check_erased_ecc_chunk(p, eccsize,
1646 &ecc_code[i], eccbytes,
1647 NULL, 0,
1648 chip->ecc.strength);
1649 }
1650
3f91e94f 1651 if (stat < 0) {
f5bbdacc 1652 mtd->ecc_stats.failed++;
3f91e94f 1653 } else {
f5bbdacc 1654 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1655 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1656 }
f5bbdacc 1657 }
3f91e94f 1658 return max_bitflips;
f5bbdacc 1659}
1da177e4 1660
6e0cb135 1661/**
7854d3f7 1662 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1663 * @mtd: mtd info structure
1664 * @chip: nand chip info structure
1665 * @buf: buffer to store read data
1fbb938d 1666 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1667 * @page: page number to read
6e0cb135 1668 *
8b6e50c9
BN		 1669 * Hardware ECC for large page chips, require OOB to be read first. For this
1670 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1671 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1672 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1673 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1674 */
1675static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1676 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135 1677{
846031d3 1678 int i, eccsize = chip->ecc.size, ret;
6e0cb135
SN		 1679 int eccbytes = chip->ecc.bytes;
1680 int eccsteps = chip->ecc.steps;
1681 uint8_t *p = buf;
1682 uint8_t *ecc_code = chip->buffers->ecccode;
6e0cb135 1683 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1684 unsigned int max_bitflips = 0;
6e0cb135
SN		 1685
1686 /* Read the OOB area first */
1687 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1688 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1689 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1690
846031d3
BB		 1691 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1692 chip->ecc.total);
1693 if (ret)
1694 return ret;
6e0cb135
SN		 1695
1696 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1697 int stat;
1698
1699 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1700 chip->read_buf(mtd, p, eccsize);
1701 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1702
1703 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
40cbe6ee
BB		 1704 if (stat == -EBADMSG &&
1705 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1706 /* check for empty pages with bitflips */
1707 stat = nand_check_erased_ecc_chunk(p, eccsize,
1708 &ecc_code[i], eccbytes,
1709 NULL, 0,
1710 chip->ecc.strength);
1711 }
1712
3f91e94f 1713 if (stat < 0) {
6e0cb135 1714 mtd->ecc_stats.failed++;
3f91e94f 1715 } else {
6e0cb135 1716 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1717 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1718 }
6e0cb135 1719 }
3f91e94f 1720 return max_bitflips;
6e0cb135
SN		 1721}
1722
f5bbdacc 1723/**
7854d3f7 1724 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1725 * @mtd: mtd info structure
1726 * @chip: nand chip info structure
1727 * @buf: buffer to store read data
1fbb938d 1728 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1729 * @page: page number to read
f5bbdacc 1730 *
8b6e50c9
BN		 1731 * The hw generator calculates the error syndrome automatically. Therefore we
1732 * need a special oob layout and handling.
f5bbdacc
TG		 1733 */
1734static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1735 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1736{
1737 int i, eccsize = chip->ecc.size;
1738 int eccbytes = chip->ecc.bytes;
1739 int eccsteps = chip->ecc.steps;
40cbe6ee 1740 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
f5bbdacc 1741 uint8_t *p = buf;
f75e5097 1742 uint8_t *oob = chip->oob_poi;
3f91e94f 1743 unsigned int max_bitflips = 0;
1da177e4 1744
f5bbdacc
TG		 1745 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1746 int stat;
61b03bd7 1747
f5bbdacc
TG		 1748 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1749 chip->read_buf(mtd, p, eccsize);
1da177e4 1750
f5bbdacc
TG		 1751 if (chip->ecc.prepad) {
1752 chip->read_buf(mtd, oob, chip->ecc.prepad);
1753 oob += chip->ecc.prepad;
1754 }
1da177e4 1755
f5bbdacc
TG		 1756 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1757 chip->read_buf(mtd, oob, eccbytes);
1758 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1759
f5bbdacc 1760 oob += eccbytes;
1da177e4 1761
f5bbdacc
TG		 1762 if (chip->ecc.postpad) {
1763 chip->read_buf(mtd, oob, chip->ecc.postpad);
1764 oob += chip->ecc.postpad;
61b03bd7 1765 }
40cbe6ee
BB		 1766
1767 if (stat == -EBADMSG &&
1768 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1769 /* check for empty pages with bitflips */
1770 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1771 oob - eccpadbytes,
1772 eccpadbytes,
1773 NULL, 0,
1774 chip->ecc.strength);
1775 }
1776
1777 if (stat < 0) {
1778 mtd->ecc_stats.failed++;
1779 } else {
1780 mtd->ecc_stats.corrected += stat;
1781 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1782 }
f5bbdacc 1783 }
1da177e4 1784
f5bbdacc 1785 /* Calculate remaining oob bytes */
7e4178f9 1786 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1787 if (i)
1788 chip->read_buf(mtd, oob, i);
61b03bd7 1789
3f91e94f 1790 return max_bitflips;
f5bbdacc 1791}
1da177e4 1792
f5bbdacc 1793/**
7854d3f7 1794 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
846031d3 1795 * @mtd: mtd info structure
8b6e50c9
BN		 1796 * @oob: oob destination address
1797 * @ops: oob ops structure
1798 * @len: size of oob to transfer
8593fbc6 1799 */
846031d3 1800static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
7014568b 1801 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1802{
846031d3
BB		 1803 struct nand_chip *chip = mtd_to_nand(mtd);
1804 int ret;
1805
f8ac0414 1806 switch (ops->mode) {
8593fbc6 1807
0612b9dd
BN		 1808 case MTD_OPS_PLACE_OOB:
1809 case MTD_OPS_RAW:
8593fbc6
TG		 1810 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1811 return oob + len;
1812
846031d3
BB		 1813 case MTD_OPS_AUTO_OOB:
1814 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
1815 ops->ooboffs, len);
1816 BUG_ON(ret);
1817 return oob + len;
1818
8593fbc6
TG		 1819 default:
1820 BUG();
1821 }
1822 return NULL;
1823}
1824
ba84fb59
BN		 1825/**
1826 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1827 * @mtd: MTD device structure
1828 * @retry_mode: the retry mode to use
1829 *
1830 * Some vendors supply a special command to shift the Vt threshold, to be used
1831 * when there are too many bitflips in a page (i.e., ECC error). After setting
1832 * a new threshold, the host should retry reading the page.
1833 */
1834static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1835{
862eba51 1836 struct nand_chip *chip = mtd_to_nand(mtd);
ba84fb59
BN		 1837
1838 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1839
1840 if (retry_mode >= chip->read_retries)
1841 return -EINVAL;
1842
1843 if (!chip->setup_read_retry)
1844 return -EOPNOTSUPP;
1845
1846 return chip->setup_read_retry(mtd, retry_mode);
1847}
1848
8593fbc6 1849/**
7854d3f7 1850 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1851 * @mtd: MTD device structure
1852 * @from: offset to read from
1853 * @ops: oob ops structure
f5bbdacc
TG		 1854 *
1855 * Internal function. Called with chip held.
1856 */
8593fbc6
TG		 1857static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1858 struct mtd_oob_ops *ops)
f5bbdacc 1859{
e47f3db4 1860 int chipnr, page, realpage, col, bytes, aligned, oob_required;
862eba51 1861 struct nand_chip *chip = mtd_to_nand(mtd);
f5bbdacc 1862 int ret = 0;
8593fbc6 1863 uint32_t readlen = ops->len;
7014568b 1864 uint32_t oobreadlen = ops->ooblen;
29f1058a 1865 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
9aca334e 1866
8593fbc6 1867 uint8_t *bufpoi, *oob, *buf;
66507c7b 1868 int use_bufpoi;
edbc4540 1869 unsigned int max_bitflips = 0;
ba84fb59 1870 int retry_mode = 0;
b72f3dfb 1871 bool ecc_fail = false;
1da177e4 1872
f5bbdacc
TG		 1873 chipnr = (int)(from >> chip->chip_shift);
1874 chip->select_chip(mtd, chipnr);
61b03bd7 1875
f5bbdacc
TG		 1876 realpage = (int)(from >> chip->page_shift);
1877 page = realpage & chip->pagemask;
1da177e4 1878
f5bbdacc 1879 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1880
8593fbc6
TG		 1881 buf = ops->datbuf;
1882 oob = ops->oobbuf;
e47f3db4 1883 oob_required = oob ? 1 : 0;
8593fbc6 1884
f8ac0414 1885 while (1) {
b72f3dfb
BN		 1886 unsigned int ecc_failures = mtd->ecc_stats.failed;
1887
f5bbdacc
TG		 1888 bytes = min(mtd->writesize - col, readlen);
1889 aligned = (bytes == mtd->writesize);
61b03bd7 1890
66507c7b
KD		 1891 if (!aligned)
1892 use_bufpoi = 1;
1893 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
477544c6
MY		 1894 use_bufpoi = !virt_addr_valid(buf) ||
1895 !IS_ALIGNED((unsigned long)buf,
1896 chip->buf_align);
66507c7b
KD		 1897 else
1898 use_bufpoi = 0;
1899
8b6e50c9 1900 /* Is the current page in the buffer? */
8593fbc6 1901 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1902 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1903
1904 if (use_bufpoi && aligned)
1905 pr_debug("%s: using read bounce buffer for buf@%p\n",
1906 __func__, buf);
61b03bd7 1907
ba84fb59 1908read_retry:
3371d663
MG		 1909 if (nand_standard_page_accessors(&chip->ecc))
1910 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1911
edbc4540
MD		 1912 /*
1913 * Now read the page into the buffer. Absent an error,
1914 * the read methods return max bitflips per ecc step.
1915 */
0612b9dd 1916 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1917 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1918 oob_required,
1919 page);
a5ff4f10
JW		 1920 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1921 !oob)
7351d3a5 1922 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1923 col, bytes, bufpoi,
1924 page);
956e944c 1925 else
46a8cf2d 1926 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1927 oob_required, page);
6d77b9d0 1928 if (ret < 0) {
66507c7b 1929 if (use_bufpoi)
6d77b9d0
BN		 1930 /* Invalidate page cache */
1931 chip->pagebuf = -1;
1da177e4 1932 break;
6d77b9d0 1933 }
f5bbdacc
TG		 1934
1935 /* Transfer not aligned data */
66507c7b 1936 if (use_bufpoi) {
a5ff4f10 1937 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1938 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1939 (ops->mode != MTD_OPS_RAW)) {
3d459559 1940 chip->pagebuf = realpage;
edbc4540
MD		 1941 chip->pagebuf_bitflips = ret;
1942 } else {
6d77b9d0
BN		 1943 /* Invalidate page cache */
1944 chip->pagebuf = -1;
edbc4540 1945 }
4bf63fcb 1946 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1947 }
1948
8593fbc6 1949 if (unlikely(oob)) {
b64d39d8
ML		 1950 int toread = min(oobreadlen, max_oobsize);
1951
1952 if (toread) {
846031d3 1953 oob = nand_transfer_oob(mtd,
b64d39d8
ML		 1954 oob, ops, toread);
1955 oobreadlen -= toread;
1956 }
8593fbc6 1957 }
5bc7c33c
BN		 1958
1959 if (chip->options & NAND_NEED_READRDY) {
1960 /* Apply delay or wait for ready/busy pin */
1961 if (!chip->dev_ready)
1962 udelay(chip->chip_delay);
1963 else
1964 nand_wait_ready(mtd);
1965 }
b72f3dfb 1966
ba84fb59 1967 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1968 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1969 retry_mode++;
1970 ret = nand_setup_read_retry(mtd,
1971 retry_mode);
1972 if (ret < 0)
1973 break;
1974
1975 /* Reset failures; retry */
1976 mtd->ecc_stats.failed = ecc_failures;
1977 goto read_retry;
1978 } else {
1979 /* No more retry modes; real failure */
1980 ecc_fail = true;
1981 }
1982 }
1983
1984 buf += bytes;
07604686 1985 max_bitflips = max_t(unsigned int, max_bitflips, ret);
8593fbc6 1986 } else {
4bf63fcb 1987 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1988 buf += bytes;
edbc4540
MD		 1989 max_bitflips = max_t(unsigned int, max_bitflips,
1990 chip->pagebuf_bitflips);
8593fbc6 1991 }
1da177e4 1992
f5bbdacc 1993 readlen -= bytes;
61b03bd7 1994
ba84fb59
BN		 1995 /* Reset to retry mode 0 */
1996 if (retry_mode) {
1997 ret = nand_setup_read_retry(mtd, 0);
1998 if (ret < 0)
1999 break;
2000 retry_mode = 0;
2001 }
2002
f5bbdacc 2003 if (!readlen)
61b03bd7 2004 break;
1da177e4 2005
8b6e50c9 2006 /* For subsequent reads align to page boundary */
1da177e4
LT		 2007 col = 0;
2008 /* Increment page address */
2009 realpage++;
2010
ace4dfee 2011 page = realpage & chip->pagemask;
1da177e4
LT		 2012 /* Check, if we cross a chip boundary */
2013 if (!page) {
2014 chipnr++;
ace4dfee
TG		 2015 chip->select_chip(mtd, -1);
2016 chip->select_chip(mtd, chipnr);
1da177e4 2017 }
1da177e4 2018 }
b0bb6903 2019 chip->select_chip(mtd, -1);
1da177e4 2020
8593fbc6 2021 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 2022 if (oob)
2023 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 2024
3f91e94f 2025 if (ret < 0)
f5bbdacc
TG		 2026 return ret;
2027
b72f3dfb 2028 if (ecc_fail)
9a1fcdfd
TG		 2029 return -EBADMSG;
2030
edbc4540 2031 return max_bitflips;
f5bbdacc
TG		 2032}
2033
2034/**
25985edc 2035 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 2036 * @mtd: MTD device structure
2037 * @from: offset to read from
2038 * @len: number of bytes to read
2039 * @retlen: pointer to variable to store the number of read bytes
2040 * @buf: the databuffer to put data
f5bbdacc 2041 *
8b6e50c9 2042 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 2043 */
2044static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
2045 size_t *retlen, uint8_t *buf)
2046{
4a89ff88 2047 struct mtd_oob_ops ops;
f5bbdacc
TG		 2048 int ret;
2049
6a8214aa 2050 nand_get_device(mtd, FL_READING);
0ec56dc4 2051 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2052 ops.len = len;
2053 ops.datbuf = buf;
11041ae6 2054 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2055 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 2056 *retlen = ops.retlen;
f5bbdacc 2057 nand_release_device(mtd);
f5bbdacc 2058 return ret;
1da177e4
LT		 2059}
2060
7bc3312b 2061/**
7854d3f7 2062 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 2063 * @mtd: mtd info structure
2064 * @chip: nand chip info structure
2065 * @page: page number to read
7bc3312b 2066 */
9d02fc2a 2067int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b 2068{
5c2ffb11 2069 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 2070 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 2071 return 0;
7bc3312b 2072}
9d02fc2a 2073EXPORT_SYMBOL(nand_read_oob_std);
7bc3312b
TG		 2074
2075/**
7854d3f7 2076 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 2077 * with syndromes
8b6e50c9
BN		 2078 * @mtd: mtd info structure
2079 * @chip: nand chip info structure
2080 * @page: page number to read
7bc3312b 2081 */
9d02fc2a
BB		 2082int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2083 int page)
7bc3312b 2084{
7bc3312b
TG		 2085 int length = mtd->oobsize;
2086 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2087 int eccsize = chip->ecc.size;
2ea69d21 2088 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 2089 int i, toread, sndrnd = 0, pos;
2090
2091 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
2092 for (i = 0; i < chip->ecc.steps; i++) {
2093 if (sndrnd) {
2094 pos = eccsize + i * (eccsize + chunk);
2095 if (mtd->writesize > 512)
2096 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
2097 else
2098 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
2099 } else
2100 sndrnd = 1;
2101 toread = min_t(int, length, chunk);
2102 chip->read_buf(mtd, bufpoi, toread);
2103 bufpoi += toread;
2104 length -= toread;
2105 }
2106 if (length > 0)
2107 chip->read_buf(mtd, bufpoi, length);
2108
5c2ffb11 2109 return 0;
7bc3312b 2110}
9d02fc2a 2111EXPORT_SYMBOL(nand_read_oob_syndrome);
7bc3312b
TG		 2112
2113/**
7854d3f7 2114 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 2115 * @mtd: mtd info structure
2116 * @chip: nand chip info structure
2117 * @page: page number to write
7bc3312b 2118 */
9d02fc2a 2119int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b
TG		 2120{
2121 int status = 0;
2122 const uint8_t *buf = chip->oob_poi;
2123 int length = mtd->oobsize;
2124
2125 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
2126 chip->write_buf(mtd, buf, length);
2127 /* Send command to program the OOB data */
2128 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2129
2130 status = chip->waitfunc(mtd, chip);
2131
0d420f9d 2132 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b 2133}
9d02fc2a 2134EXPORT_SYMBOL(nand_write_oob_std);
7bc3312b
TG		 2135
2136/**
7854d3f7 2137 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 2138 * with syndrome - only for large page flash
2139 * @mtd: mtd info structure
2140 * @chip: nand chip info structure
2141 * @page: page number to write
7bc3312b 2142 */
9d02fc2a
BB		 2143int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2144 int page)
7bc3312b
TG		 2145{
2146 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2147 int eccsize = chip->ecc.size, length = mtd->oobsize;
2148 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2149 const uint8_t *bufpoi = chip->oob_poi;
2150
2151 /*
2152 * data-ecc-data-ecc ... ecc-oob
2153 * or
2154 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2155 */
2156 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2157 pos = steps * (eccsize + chunk);
2158 steps = 0;
2159 } else
8b0036ee 2160 pos = eccsize;
7bc3312b
TG		 2161
2162 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2163 for (i = 0; i < steps; i++) {
2164 if (sndcmd) {
2165 if (mtd->writesize <= 512) {
2166 uint32_t fill = 0xFFFFFFFF;
2167
2168 len = eccsize;
2169 while (len > 0) {
2170 int num = min_t(int, len, 4);
2171 chip->write_buf(mtd, (uint8_t *)&fill,
2172 num);
2173 len -= num;
2174 }
2175 } else {
2176 pos = eccsize + i * (eccsize + chunk);
2177 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2178 }
2179 } else
2180 sndcmd = 1;
2181 len = min_t(int, length, chunk);
2182 chip->write_buf(mtd, bufpoi, len);
2183 bufpoi += len;
2184 length -= len;
2185 }
2186 if (length > 0)
2187 chip->write_buf(mtd, bufpoi, length);
2188
2189 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2190 status = chip->waitfunc(mtd, chip);
2191
2192 return status & NAND_STATUS_FAIL ? -EIO : 0;
2193}
9d02fc2a 2194EXPORT_SYMBOL(nand_write_oob_syndrome);
7bc3312b 2195
1da177e4 2196/**
7854d3f7 2197 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 2198 * @mtd: MTD device structure
2199 * @from: offset to read from
2200 * @ops: oob operations description structure
1da177e4 2201 *
8b6e50c9 2202 * NAND read out-of-band data from the spare area.
1da177e4 2203 */
8593fbc6
TG		 2204static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2205 struct mtd_oob_ops *ops)
1da177e4 2206{
c00a0991 2207 int page, realpage, chipnr;
862eba51 2208 struct nand_chip *chip = mtd_to_nand(mtd);
041e4575 2209 struct mtd_ecc_stats stats;
7014568b
VW		 2210 int readlen = ops->ooblen;
2211 int len;
7bc3312b 2212 uint8_t *buf = ops->oobbuf;
1951f2f7 2213 int ret = 0;
61b03bd7 2214
289c0522 2215 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 2216 __func__, (unsigned long long)from, readlen);
1da177e4 2217
041e4575
BN		 2218 stats = mtd->ecc_stats;
2219
29f1058a 2220 len = mtd_oobavail(mtd, ops);
03736155
AH		 2221
2222 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2223 pr_debug("%s: attempt to start read outside oob\n",
2224 __func__);
03736155
AH		 2225 return -EINVAL;
2226 }
2227
2228 /* Do not allow reads past end of device */
2229 if (unlikely(from >= mtd->size ||
2230 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2231 (from >> chip->page_shift)) * len)) {
289c0522
BN		 2232 pr_debug("%s: attempt to read beyond end of device\n",
2233 __func__);
03736155
AH		 2234 return -EINVAL;
2235 }
7014568b 2236
7314e9e7 2237 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 2238 chip->select_chip(mtd, chipnr);
1da177e4 2239
7314e9e7
TG		 2240 /* Shift to get page */
2241 realpage = (int)(from >> chip->page_shift);
2242 page = realpage & chip->pagemask;
1da177e4 2243
f8ac0414 2244 while (1) {
0612b9dd 2245 if (ops->mode == MTD_OPS_RAW)
1951f2f7 2246 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 2247 else
1951f2f7
SL		 2248 ret = chip->ecc.read_oob(mtd, chip, page);
2249
2250 if (ret < 0)
2251 break;
7014568b
VW		 2252
2253 len = min(len, readlen);
846031d3 2254 buf = nand_transfer_oob(mtd, buf, ops, len);
8593fbc6 2255
5bc7c33c
BN		 2256 if (chip->options & NAND_NEED_READRDY) {
2257 /* Apply delay or wait for ready/busy pin */
2258 if (!chip->dev_ready)
2259 udelay(chip->chip_delay);
2260 else
2261 nand_wait_ready(mtd);
2262 }
2263
7014568b 2264 readlen -= len;
0d420f9d
SZ		 2265 if (!readlen)
2266 break;
2267
7314e9e7
TG		 2268 /* Increment page address */
2269 realpage++;
2270
2271 page = realpage & chip->pagemask;
2272 /* Check, if we cross a chip boundary */
2273 if (!page) {
2274 chipnr++;
2275 chip->select_chip(mtd, -1);
2276 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2277 }
2278 }
b0bb6903 2279 chip->select_chip(mtd, -1);
1da177e4 2280
1951f2f7
SL		 2281 ops->oobretlen = ops->ooblen - readlen;
2282
2283 if (ret < 0)
2284 return ret;
041e4575
BN		 2285
2286 if (mtd->ecc_stats.failed - stats.failed)
2287 return -EBADMSG;
2288
2289 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 2290}
2291
2292/**
8593fbc6 2293 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 2294 * @mtd: MTD device structure
2295 * @from: offset to read from
2296 * @ops: oob operation description structure
1da177e4 2297 *
8b6e50c9 2298 * NAND read data and/or out-of-band data.
1da177e4 2299 */
8593fbc6
TG		 2300static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2301 struct mtd_oob_ops *ops)
1da177e4 2302{
fc6b4d12 2303 int ret;
8593fbc6
TG		 2304
2305 ops->retlen = 0;
1da177e4
LT		 2306
2307 /* Do not allow reads past end of device */
7014568b 2308 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 2309 pr_debug("%s: attempt to read beyond end of device\n",
2310 __func__);
1da177e4
LT		 2311 return -EINVAL;
2312 }
2313
fc6b4d12
AS		 2314 if (ops->mode != MTD_OPS_PLACE_OOB &&
2315 ops->mode != MTD_OPS_AUTO_OOB &&
2316 ops->mode != MTD_OPS_RAW)
2317 return -ENOTSUPP;
1da177e4 2318
fc6b4d12 2319 nand_get_device(mtd, FL_READING);
1da177e4 2320
8593fbc6
TG		 2321 if (!ops->datbuf)
2322 ret = nand_do_read_oob(mtd, from, ops);
2323 else
2324 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 2325
8593fbc6
TG		 2326 nand_release_device(mtd);
2327 return ret;
2328}
61b03bd7 2329
1da177e4 2330
8593fbc6 2331/**
7854d3f7 2332 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2333 * @mtd: mtd info structure
2334 * @chip: nand chip info structure
2335 * @buf: data buffer
1fbb938d 2336 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2337 * @page: page number to write
52ff49df 2338 *
7854d3f7 2339 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2340 */
cc0f51ec
TP		 2341int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2342 const uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 2343{
2344 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2345 if (oob_required)
2346 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2347
2348 return 0;
1da177e4 2349}
cc0f51ec 2350EXPORT_SYMBOL(nand_write_page_raw);
1da177e4 2351
52ff49df 2352/**
7854d3f7 2353 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2354 * @mtd: mtd info structure
2355 * @chip: nand chip info structure
2356 * @buf: data buffer
1fbb938d 2357 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2358 * @page: page number to write
52ff49df
DB		 2359 *
2360 * We need a special oob layout and handling even when ECC isn't checked.
2361 */
fdbad98d 2362static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2363 struct nand_chip *chip,
45aaeff9
BB		 2364 const uint8_t *buf, int oob_required,
2365 int page)
52ff49df
DB		 2366{
2367 int eccsize = chip->ecc.size;
2368 int eccbytes = chip->ecc.bytes;
2369 uint8_t *oob = chip->oob_poi;
2370 int steps, size;
2371
2372 for (steps = chip->ecc.steps; steps > 0; steps--) {
2373 chip->write_buf(mtd, buf, eccsize);
2374 buf += eccsize;
2375
2376 if (chip->ecc.prepad) {
2377 chip->write_buf(mtd, oob, chip->ecc.prepad);
2378 oob += chip->ecc.prepad;
2379 }
2380
60c3bc1f 2381 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2382 oob += eccbytes;
2383
2384 if (chip->ecc.postpad) {
2385 chip->write_buf(mtd, oob, chip->ecc.postpad);
2386 oob += chip->ecc.postpad;
2387 }
2388 }
2389
2390 size = mtd->oobsize - (oob - chip->oob_poi);
2391 if (size)
2392 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2393
2394 return 0;
52ff49df 2395}
9223a456 2396/**
7854d3f7 2397 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2398 * @mtd: mtd info structure
2399 * @chip: nand chip info structure
2400 * @buf: data buffer
1fbb938d 2401 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2402 * @page: page number to write
9223a456 2403 */
fdbad98d 2404static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2405 const uint8_t *buf, int oob_required,
2406 int page)
9223a456 2407{
846031d3 2408 int i, eccsize = chip->ecc.size, ret;
f75e5097
TG		 2409 int eccbytes = chip->ecc.bytes;
2410 int eccsteps = chip->ecc.steps;
4bf63fcb 2411 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2412 const uint8_t *p = buf;
9223a456 2413
7854d3f7 2414 /* Software ECC calculation */
8593fbc6
TG		 2415 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2416 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2417
846031d3
BB		 2418 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2419 chip->ecc.total);
2420 if (ret)
2421 return ret;
9223a456 2422
45aaeff9 2423 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
f75e5097 2424}
9223a456 2425
f75e5097 2426/**
7854d3f7 2427 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2428 * @mtd: mtd info structure
2429 * @chip: nand chip info structure
2430 * @buf: data buffer
1fbb938d 2431 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2432 * @page: page number to write
f75e5097 2433 */
fdbad98d 2434static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2435 const uint8_t *buf, int oob_required,
2436 int page)
f75e5097 2437{
846031d3 2438 int i, eccsize = chip->ecc.size, ret;
f75e5097
TG		 2439 int eccbytes = chip->ecc.bytes;
2440 int eccsteps = chip->ecc.steps;
4bf63fcb 2441 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2442 const uint8_t *p = buf;
9223a456 2443
f75e5097
TG		 2444 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2445 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2446 chip->write_buf(mtd, p, eccsize);
f75e5097 2447 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2448 }
2449
846031d3
BB		 2450 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2451 chip->ecc.total);
2452 if (ret)
2453 return ret;
f75e5097
TG		 2454
2455 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2456
2457 return 0;
9223a456
TG		 2458}
2459
837a6ba4
GP		 2460
2461/**
73c8aaf4 2462 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
837a6ba4
GP		 2463 * @mtd: mtd info structure
2464 * @chip: nand chip info structure
d6a95080 2465 * @offset: column address of subpage within the page
837a6ba4 2466 * @data_len: data length
d6a95080 2467 * @buf: data buffer
837a6ba4 2468 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2469 * @page: page number to write
837a6ba4
GP		 2470 */
2471static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2472 struct nand_chip *chip, uint32_t offset,
d6a95080 2473 uint32_t data_len, const uint8_t *buf,
45aaeff9 2474 int oob_required, int page)
837a6ba4
GP		 2475{
2476 uint8_t *oob_buf = chip->oob_poi;
2477 uint8_t *ecc_calc = chip->buffers->ecccalc;
2478 int ecc_size = chip->ecc.size;
2479 int ecc_bytes = chip->ecc.bytes;
2480 int ecc_steps = chip->ecc.steps;
837a6ba4
GP		 2481 uint32_t start_step = offset / ecc_size;
2482 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2483 int oob_bytes = mtd->oobsize / ecc_steps;
846031d3 2484 int step, ret;
837a6ba4
GP		 2485
2486 for (step = 0; step < ecc_steps; step++) {
2487 /* configure controller for WRITE access */
2488 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2489
2490 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2491 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2492
2493 /* mask ECC of un-touched subpages by padding 0xFF */
2494 if ((step < start_step) || (step > end_step))
2495 memset(ecc_calc, 0xff, ecc_bytes);
2496 else
d6a95080 2497 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2498
2499 /* mask OOB of un-touched subpages by padding 0xFF */
2500 /* if oob_required, preserve OOB metadata of written subpage */
2501 if (!oob_required || (step < start_step) || (step > end_step))
2502 memset(oob_buf, 0xff, oob_bytes);
2503
d6a95080 2504 buf += ecc_size;
837a6ba4
GP		 2505 ecc_calc += ecc_bytes;
2506 oob_buf += oob_bytes;
2507 }
2508
2509 /* copy calculated ECC for whole page to chip->buffer->oob */
2510 /* this include masked-value(0xFF) for unwritten subpages */
2511 ecc_calc = chip->buffers->ecccalc;
846031d3
BB		 2512 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2513 chip->ecc.total);
2514 if (ret)
2515 return ret;
837a6ba4
GP		 2516
2517 /* write OOB buffer to NAND device */
2518 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2519
2520 return 0;
2521}
2522
2523
61b03bd7 2524/**
7854d3f7 2525 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2526 * @mtd: mtd info structure
2527 * @chip: nand chip info structure
2528 * @buf: data buffer
1fbb938d 2529 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2530 * @page: page number to write
1da177e4 2531 *
8b6e50c9
BN		 2532 * The hw generator calculates the error syndrome automatically. Therefore we
2533 * need a special oob layout and handling.
f75e5097 2534 */
fdbad98d 2535static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d 2536 struct nand_chip *chip,
45aaeff9
BB		 2537 const uint8_t *buf, int oob_required,
2538 int page)
1da177e4 2539{
f75e5097
TG		 2540 int i, eccsize = chip->ecc.size;
2541 int eccbytes = chip->ecc.bytes;
2542 int eccsteps = chip->ecc.steps;
2543 const uint8_t *p = buf;
2544 uint8_t *oob = chip->oob_poi;
1da177e4 2545
f75e5097 2546 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2547
f75e5097
TG		 2548 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2549 chip->write_buf(mtd, p, eccsize);
61b03bd7 2550
f75e5097
TG		 2551 if (chip->ecc.prepad) {
2552 chip->write_buf(mtd, oob, chip->ecc.prepad);
2553 oob += chip->ecc.prepad;
2554 }
2555
2556 chip->ecc.calculate(mtd, p, oob);
2557 chip->write_buf(mtd, oob, eccbytes);
2558 oob += eccbytes;
2559
2560 if (chip->ecc.postpad) {
2561 chip->write_buf(mtd, oob, chip->ecc.postpad);
2562 oob += chip->ecc.postpad;
1da177e4 2563 }
1da177e4 2564 }
f75e5097
TG		 2565
2566 /* Calculate remaining oob bytes */
7e4178f9 2567 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2568 if (i)
2569 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2570
2571 return 0;
f75e5097
TG		 2572}
2573
2574/**
f107d7a4 2575 * nand_write_page - write one page
8b6e50c9
BN		 2576 * @mtd: MTD device structure
2577 * @chip: NAND chip descriptor
837a6ba4
GP		 2578 * @offset: address offset within the page
2579 * @data_len: length of actual data to be written
8b6e50c9 2580 * @buf: the data to write
1fbb938d 2581 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9 2582 * @page: page number to write
8b6e50c9 2583 * @raw: use _raw version of write_page
f75e5097
TG		 2584 */
2585static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4 2586 uint32_t offset, int data_len, const uint8_t *buf,
0b4773fd 2587 int oob_required, int page, int raw)
f75e5097 2588{
837a6ba4
GP		 2589 int status, subpage;
2590
2591 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2592 chip->ecc.write_subpage)
2593 subpage = offset || (data_len < mtd->writesize);
2594 else
2595 subpage = 0;
f75e5097 2596
3371d663
MG		 2597 if (nand_standard_page_accessors(&chip->ecc))
2598 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
f75e5097 2599
956e944c 2600 if (unlikely(raw))
837a6ba4 2601 status = chip->ecc.write_page_raw(mtd, chip, buf,
45aaeff9 2602 oob_required, page);
837a6ba4
GP		 2603 else if (subpage)
2604 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
45aaeff9 2605 buf, oob_required, page);
956e944c 2606 else
45aaeff9
BB		 2607 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2608 page);
fdbad98d
JW		 2609
2610 if (status < 0)
2611 return status;
f75e5097 2612
41145649 2613 if (nand_standard_page_accessors(&chip->ecc)) {
0b4773fd 2614 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
f75e5097 2615
7bc3312b 2616 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2617 if (status & NAND_STATUS_FAIL)
2618 return -EIO;
f75e5097
TG		 2619 }
2620
f75e5097 2621 return 0;
1da177e4
LT		 2622}
2623
8593fbc6 2624/**
7854d3f7 2625 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2626 * @mtd: MTD device structure
8b6e50c9
BN		 2627 * @oob: oob data buffer
2628 * @len: oob data write length
2629 * @ops: oob ops structure
8593fbc6 2630 */
f722013e
TAA		 2631static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2632 struct mtd_oob_ops *ops)
8593fbc6 2633{
862eba51 2634 struct nand_chip *chip = mtd_to_nand(mtd);
846031d3 2635 int ret;
f722013e
TAA		 2636
2637 /*
2638 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2639 * data from a previous OOB read.
2640 */
2641 memset(chip->oob_poi, 0xff, mtd->oobsize);
2642
f8ac0414 2643 switch (ops->mode) {
8593fbc6 2644
0612b9dd
BN		 2645 case MTD_OPS_PLACE_OOB:
2646 case MTD_OPS_RAW:
8593fbc6
TG		 2647 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2648 return oob + len;
2649
846031d3
BB		 2650 case MTD_OPS_AUTO_OOB:
2651 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
2652 ops->ooboffs, len);
2653 BUG_ON(ret);
2654 return oob + len;
2655
8593fbc6
TG		 2656 default:
2657 BUG();
2658 }
2659 return NULL;
2660}
2661
f8ac0414 2662#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2663
2664/**
7854d3f7 2665 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2666 * @mtd: MTD device structure
2667 * @to: offset to write to
2668 * @ops: oob operations description structure
1da177e4 2669 *
8b6e50c9 2670 * NAND write with ECC.
1da177e4 2671 */
8593fbc6
TG		 2672static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2673 struct mtd_oob_ops *ops)
1da177e4 2674{
73600b61 2675 int chipnr, realpage, page, column;
862eba51 2676 struct nand_chip *chip = mtd_to_nand(mtd);
8593fbc6 2677 uint32_t writelen = ops->len;
782ce79a
ML		 2678
2679 uint32_t oobwritelen = ops->ooblen;
29f1058a 2680 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
782ce79a 2681
8593fbc6
TG		 2682 uint8_t *oob = ops->oobbuf;
2683 uint8_t *buf = ops->datbuf;
837a6ba4 2684 int ret;
e47f3db4 2685 int oob_required = oob ? 1 : 0;
1da177e4 2686
8593fbc6 2687 ops->retlen = 0;
29072b96
TG		 2688 if (!writelen)
2689 return 0;
1da177e4 2690
8b6e50c9 2691 /* Reject writes, which are not page aligned */
8593fbc6 2692 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2693 pr_notice("%s: attempt to write non page aligned data\n",
2694 __func__);
1da177e4
LT		 2695 return -EINVAL;
2696 }
2697
29072b96 2698 column = to & (mtd->writesize - 1);
1da177e4 2699
6a930961
TG		 2700 chipnr = (int)(to >> chip->chip_shift);
2701 chip->select_chip(mtd, chipnr);
2702
1da177e4 2703 /* Check, if it is write protected */
b0bb6903
HS		 2704 if (nand_check_wp(mtd)) {
2705 ret = -EIO;
2706 goto err_out;
2707 }
1da177e4 2708
f75e5097
TG		 2709 realpage = (int)(to >> chip->page_shift);
2710 page = realpage & chip->pagemask;
f75e5097
TG		 2711
2712 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2713 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2714 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2715 chip->pagebuf = -1;
61b03bd7 2716
782ce79a 2717 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2718 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2719 ret = -EINVAL;
2720 goto err_out;
2721 }
782ce79a 2722
f8ac0414 2723 while (1) {
29072b96 2724 int bytes = mtd->writesize;
29072b96 2725 uint8_t *wbuf = buf;
66507c7b 2726 int use_bufpoi;
144f4c98 2727 int part_pagewr = (column || writelen < mtd->writesize);
66507c7b
KD		 2728
2729 if (part_pagewr)
2730 use_bufpoi = 1;
2731 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
477544c6
MY		 2732 use_bufpoi = !virt_addr_valid(buf) ||
2733 !IS_ALIGNED((unsigned long)buf,
2734 chip->buf_align);
66507c7b
KD		 2735 else
2736 use_bufpoi = 0;
29072b96 2737
66507c7b
KD		 2738 /* Partial page write?, or need to use bounce buffer */
2739 if (use_bufpoi) {
2740 pr_debug("%s: using write bounce buffer for buf@%p\n",
2741 __func__, buf);
66507c7b
KD		 2742 if (part_pagewr)
2743 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2744 chip->pagebuf = -1;
2745 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2746 memcpy(&chip->buffers->databuf[column], buf, bytes);
2747 wbuf = chip->buffers->databuf;
2748 }
1da177e4 2749
782ce79a
ML		 2750 if (unlikely(oob)) {
2751 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2752 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2753 oobwritelen -= len;
f722013e
TAA		 2754 } else {
2755 /* We still need to erase leftover OOB data */
2756 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2757 }
f107d7a4
BB		 2758
2759 ret = nand_write_page(mtd, chip, column, bytes, wbuf,
0b4773fd 2760 oob_required, page,
f107d7a4 2761 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2762 if (ret)
2763 break;
2764
2765 writelen -= bytes;
2766 if (!writelen)
2767 break;
2768
29072b96 2769 column = 0;
f75e5097
TG		 2770 buf += bytes;
2771 realpage++;
2772
2773 page = realpage & chip->pagemask;
2774 /* Check, if we cross a chip boundary */
2775 if (!page) {
2776 chipnr++;
2777 chip->select_chip(mtd, -1);
2778 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2779 }
2780 }
8593fbc6 2781
8593fbc6 2782 ops->retlen = ops->len - writelen;
7014568b
VW		 2783 if (unlikely(oob))
2784 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2785
2786err_out:
2787 chip->select_chip(mtd, -1);
1da177e4
LT		 2788 return ret;
2789}
2790
2af7c653
SK		 2791/**
2792 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2793 * @mtd: MTD device structure
2794 * @to: offset to write to
2795 * @len: number of bytes to write
2796 * @retlen: pointer to variable to store the number of written bytes
2797 * @buf: the data to write
2af7c653
SK		 2798 *
2799 * NAND write with ECC. Used when performing writes in interrupt context, this
2800 * may for example be called by mtdoops when writing an oops while in panic.
2801 */
2802static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2803 size_t *retlen, const uint8_t *buf)
2804{
862eba51 2805 struct nand_chip *chip = mtd_to_nand(mtd);
30863e38 2806 int chipnr = (int)(to >> chip->chip_shift);
4a89ff88 2807 struct mtd_oob_ops ops;
2af7c653
SK		 2808 int ret;
2809
8b6e50c9 2810 /* Grab the device */
2af7c653
SK		 2811 panic_nand_get_device(chip, mtd, FL_WRITING);
2812
30863e38
BT		 2813 chip->select_chip(mtd, chipnr);
2814
2815 /* Wait for the device to get ready */
2816 panic_nand_wait(mtd, chip, 400);
2817
0ec56dc4 2818 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2819 ops.len = len;
2820 ops.datbuf = (uint8_t *)buf;
11041ae6 2821 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2822
4a89ff88 2823 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2824
4a89ff88 2825 *retlen = ops.retlen;
2af7c653
SK		 2826 return ret;
2827}
2828
f75e5097 2829/**
8593fbc6 2830 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2831 * @mtd: MTD device structure
2832 * @to: offset to write to
2833 * @len: number of bytes to write
2834 * @retlen: pointer to variable to store the number of written bytes
2835 * @buf: the data to write
f75e5097 2836 *
8b6e50c9 2837 * NAND write with ECC.
f75e5097 2838 */
8593fbc6
TG		 2839static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2840 size_t *retlen, const uint8_t *buf)
f75e5097 2841{
4a89ff88 2842 struct mtd_oob_ops ops;
f75e5097
TG		 2843 int ret;
2844
6a8214aa 2845 nand_get_device(mtd, FL_WRITING);
0ec56dc4 2846 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2847 ops.len = len;
2848 ops.datbuf = (uint8_t *)buf;
11041ae6 2849 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2850 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2851 *retlen = ops.retlen;
f75e5097 2852 nand_release_device(mtd);
8593fbc6 2853 return ret;
f75e5097 2854}
7314e9e7 2855
1da177e4 2856/**
8593fbc6 2857 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2858 * @mtd: MTD device structure
2859 * @to: offset to write to
2860 * @ops: oob operation description structure
1da177e4 2861 *
8b6e50c9 2862 * NAND write out-of-band.
1da177e4 2863 */
8593fbc6
TG		 2864static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2865 struct mtd_oob_ops *ops)
1da177e4 2866{
03736155 2867 int chipnr, page, status, len;
862eba51 2868 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2869
289c0522 2870 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2871 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2872
29f1058a 2873 len = mtd_oobavail(mtd, ops);
03736155 2874
1da177e4 2875 /* Do not allow write past end of page */
03736155 2876 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2877 pr_debug("%s: attempt to write past end of page\n",
2878 __func__);
1da177e4
LT		 2879 return -EINVAL;
2880 }
2881
03736155 2882 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2883 pr_debug("%s: attempt to start write outside oob\n",
2884 __func__);
03736155
AH		 2885 return -EINVAL;
2886 }
2887
775adc3d 2888 /* Do not allow write past end of device */
03736155
AH		 2889 if (unlikely(to >= mtd->size ||
2890 ops->ooboffs + ops->ooblen >
2891 ((mtd->size >> chip->page_shift) -
2892 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2893 pr_debug("%s: attempt to write beyond end of device\n",
2894 __func__);
03736155
AH		 2895 return -EINVAL;
2896 }
2897
7314e9e7 2898 chipnr = (int)(to >> chip->chip_shift);
7314e9e7
TG		 2899
2900 /*
2901 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2902 * of my DiskOnChip 2000 test units) will clear the whole data page too
2903 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2904 * it in the doc2000 driver in August 1999. dwmw2.
2905 */
73f907fd
BB		 2906 nand_reset(chip, chipnr);
2907
2908 chip->select_chip(mtd, chipnr);
2909
2910 /* Shift to get page */
2911 page = (int)(to >> chip->page_shift);
1da177e4
LT		 2912
2913 /* Check, if it is write protected */
b0bb6903
HS		 2914 if (nand_check_wp(mtd)) {
2915 chip->select_chip(mtd, -1);
8593fbc6 2916 return -EROFS;
b0bb6903 2917 }
61b03bd7 2918
1da177e4 2919 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2920 if (page == chip->pagebuf)
2921 chip->pagebuf = -1;
1da177e4 2922
f722013e 2923 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2924
0612b9dd 2925 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2926 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2927 else
2928 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2929
b0bb6903
HS		 2930 chip->select_chip(mtd, -1);
2931
7bc3312b
TG		 2932 if (status)
2933 return status;
1da177e4 2934
7014568b 2935 ops->oobretlen = ops->ooblen;
1da177e4 2936
7bc3312b 2937 return 0;
8593fbc6
TG		 2938}
2939
2940/**
2941 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2942 * @mtd: MTD device structure
2943 * @to: offset to write to
2944 * @ops: oob operation description structure
8593fbc6
TG		 2945 */
2946static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2947 struct mtd_oob_ops *ops)
2948{
8593fbc6
TG		 2949 int ret = -ENOTSUPP;
2950
2951 ops->retlen = 0;
2952
2953 /* Do not allow writes past end of device */
7014568b 2954 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2955 pr_debug("%s: attempt to write beyond end of device\n",
2956 __func__);
8593fbc6
TG		 2957 return -EINVAL;
2958 }
2959
6a8214aa 2960 nand_get_device(mtd, FL_WRITING);
8593fbc6 2961
f8ac0414 2962 switch (ops->mode) {
0612b9dd
BN		 2963 case MTD_OPS_PLACE_OOB:
2964 case MTD_OPS_AUTO_OOB:
2965 case MTD_OPS_RAW:
8593fbc6
TG		 2966 break;
2967
2968 default:
2969 goto out;
2970 }
2971
2972 if (!ops->datbuf)
2973 ret = nand_do_write_oob(mtd, to, ops);
2974 else
2975 ret = nand_do_write_ops(mtd, to, ops);
2976
7351d3a5 2977out:
1da177e4 2978 nand_release_device(mtd);
1da177e4
LT		 2979 return ret;
2980}
2981
1da177e4 2982/**
49c50b97 2983 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2984 * @mtd: MTD device structure
2985 * @page: the page address of the block which will be erased
1da177e4 2986 *
49c50b97 2987 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2988 */
49c50b97 2989static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2990{
862eba51 2991 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2992 /* Send commands to erase a block */
ace4dfee
TG		 2993 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2994 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2995
2996 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2997}
2998
1da177e4
LT		 2999/**
3000 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 3001 * @mtd: MTD device structure
3002 * @instr: erase instruction
1da177e4 3003 *
8b6e50c9 3004 * Erase one ore more blocks.
1da177e4 3005 */
e0c7d767 3006static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 3007{
e0c7d767 3008 return nand_erase_nand(mtd, instr, 0);
1da177e4 3009}
61b03bd7 3010
1da177e4 3011/**
7854d3f7 3012 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 3013 * @mtd: MTD device structure
3014 * @instr: erase instruction
3015 * @allowbbt: allow erasing the bbt area
1da177e4 3016 *
8b6e50c9 3017 * Erase one ore more blocks.
1da177e4 3018 */
ace4dfee
TG		 3019int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3020 int allowbbt)
1da177e4 3021{
69423d99 3022 int page, status, pages_per_block, ret, chipnr;
862eba51 3023 struct nand_chip *chip = mtd_to_nand(mtd);
69423d99 3024 loff_t len;
1da177e4 3025
289c0522
BN		 3026 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3027 __func__, (unsigned long long)instr->addr,
3028 (unsigned long long)instr->len);
1da177e4 3029
6fe5a6ac 3030 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 3031 return -EINVAL;
1da177e4 3032
1da177e4 3033 /* Grab the lock and see if the device is available */
6a8214aa 3034 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 3035
3036 /* Shift to get first page */
ace4dfee
TG		 3037 page = (int)(instr->addr >> chip->page_shift);
3038 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 3039
3040 /* Calculate pages in each block */
ace4dfee 3041 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 3042
3043 /* Select the NAND device */
ace4dfee 3044 chip->select_chip(mtd, chipnr);
1da177e4 3045
1da177e4
LT		 3046 /* Check, if it is write protected */
3047 if (nand_check_wp(mtd)) {
289c0522
BN		 3048 pr_debug("%s: device is write protected!\n",
3049 __func__);
1da177e4
LT		 3050 instr->state = MTD_ERASE_FAILED;
3051 goto erase_exit;
3052 }
3053
3054 /* Loop through the pages */
3055 len = instr->len;
3056
3057 instr->state = MTD_ERASING;
3058
3059 while (len) {
12183a20 3060 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee 3061 if (nand_block_checkbad(mtd, ((loff_t) page) <<
9f3e0429 3062 chip->page_shift, allowbbt)) {
d0370219
BN		 3063 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3064 __func__, page);
1da177e4
LT		 3065 instr->state = MTD_ERASE_FAILED;
3066 goto erase_exit;
3067 }
61b03bd7 3068
ace4dfee
TG		 3069 /*
3070 * Invalidate the page cache, if we erase the block which
8b6e50c9 3071 * contains the current cached page.
ace4dfee
TG		 3072 */
3073 if (page <= chip->pagebuf && chip->pagebuf <
3074 (page + pages_per_block))
3075 chip->pagebuf = -1;
1da177e4 3076
49c50b97 3077 status = chip->erase(mtd, page & chip->pagemask);
1da177e4
LT		 3078
3079 /* See if block erase succeeded */
a4ab4c5d 3080 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 3081 pr_debug("%s: failed erase, page 0x%08x\n",
3082 __func__, page);
1da177e4 3083 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 3084 instr->fail_addr =
3085 ((loff_t)page << chip->page_shift);
1da177e4
LT		 3086 goto erase_exit;
3087 }
30f464b7 3088
1da177e4 3089 /* Increment page address and decrement length */
daae74ca 3090 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 3091 page += pages_per_block;
3092
3093 /* Check, if we cross a chip boundary */
ace4dfee 3094 if (len && !(page & chip->pagemask)) {
1da177e4 3095 chipnr++;
ace4dfee
TG		 3096 chip->select_chip(mtd, -1);
3097 chip->select_chip(mtd, chipnr);
1da177e4
LT		 3098 }
3099 }
3100 instr->state = MTD_ERASE_DONE;
3101
7351d3a5 3102erase_exit:
1da177e4
LT		 3103
3104 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 3105
3106 /* Deselect and wake up anyone waiting on the device */
b0bb6903 3107 chip->select_chip(mtd, -1);
1da177e4
LT		 3108 nand_release_device(mtd);
3109
49defc01
DW		 3110 /* Do call back function */
3111 if (!ret)
3112 mtd_erase_callback(instr);
3113
1da177e4
LT		 3114 /* Return more or less happy */
3115 return ret;
3116}
3117
3118/**
3119 * nand_sync - [MTD Interface] sync
8b6e50c9 3120 * @mtd: MTD device structure
1da177e4 3121 *
8b6e50c9 3122 * Sync is actually a wait for chip ready function.
1da177e4 3123 */
e0c7d767 3124static void nand_sync(struct mtd_info *mtd)
1da177e4 3125{
289c0522 3126 pr_debug("%s: called\n", __func__);
1da177e4
LT		 3127
3128 /* Grab the lock and see if the device is available */
6a8214aa 3129 nand_get_device(mtd, FL_SYNCING);
1da177e4 3130 /* Release it and go back */
e0c7d767 3131 nand_release_device(mtd);
1da177e4
LT		 3132}
3133
1da177e4 3134/**
ace4dfee 3135 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 3136 * @mtd: MTD device structure
3137 * @offs: offset relative to mtd start
1da177e4 3138 */
ace4dfee 3139static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 3140{
9f3e0429
AT		 3141 struct nand_chip *chip = mtd_to_nand(mtd);
3142 int chipnr = (int)(offs >> chip->chip_shift);
3143 int ret;
3144
3145 /* Select the NAND device */
3146 nand_get_device(mtd, FL_READING);
3147 chip->select_chip(mtd, chipnr);
3148
3149 ret = nand_block_checkbad(mtd, offs, 0);
3150
3151 chip->select_chip(mtd, -1);
3152 nand_release_device(mtd);
3153
3154 return ret;
1da177e4
LT		 3155}
3156
3157/**
ace4dfee 3158 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 3159 * @mtd: MTD device structure
3160 * @ofs: offset relative to mtd start
1da177e4 3161 */
e0c7d767 3162static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 3163{
1da177e4
LT		 3164 int ret;
3165
f8ac0414
FF		 3166 ret = nand_block_isbad(mtd, ofs);
3167 if (ret) {
8b6e50c9 3168 /* If it was bad already, return success and do nothing */
1da177e4
LT		 3169 if (ret > 0)
3170 return 0;
e0c7d767
DW		 3171 return ret;
3172 }
1da177e4 3173
5a0edb25 3174 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 3175}
3176
5671842f
ZB		 3177/**
3178 * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
3179 * @mtd: MTD device structure
3180 * @ofs: offset relative to mtd start
3181 * @len: length of mtd
3182 */
3183static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
3184{
3185 struct nand_chip *chip = mtd_to_nand(mtd);
3186 u32 part_start_block;
3187 u32 part_end_block;
3188 u32 part_start_die;
3189 u32 part_end_die;
3190
3191 /*
3192 * max_bb_per_die and blocks_per_die used to determine
3193 * the maximum bad block count.
3194 */
3195 if (!chip->max_bb_per_die || !chip->blocks_per_die)
3196 return -ENOTSUPP;
3197
3198 /* Get the start and end of the partition in erase blocks. */
3199 part_start_block = mtd_div_by_eb(ofs, mtd);
3200 part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1;
3201
3202 /* Get the start and end LUNs of the partition. */
3203 part_start_die = part_start_block / chip->blocks_per_die;
3204 part_end_die = part_end_block / chip->blocks_per_die;
3205
3206 /*
3207 * Look up the bad blocks per unit and multiply by the number of units
3208 * that the partition spans.
3209 */
3210 return chip->max_bb_per_die * (part_end_die - part_start_die + 1);
3211}
3212
7db03ecc
HS		 3213/**
3214 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3215 * @mtd: MTD device structure
3216 * @chip: nand chip info structure
3217 * @addr: feature address.
3218 * @subfeature_param: the subfeature parameters, a four bytes array.
3219 */
3220static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3221 int addr, uint8_t *subfeature_param)
3222{
3223 int status;
05f78359 3224 int i;
7db03ecc 3225
d914c932
DM		 3226 if (!chip->onfi_version ||
3227 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3228 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3229 return -EINVAL;
3230
3231 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 3232 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3233 chip->write_byte(mtd, subfeature_param[i]);
3234
7db03ecc
HS		 3235 status = chip->waitfunc(mtd, chip);
3236 if (status & NAND_STATUS_FAIL)
3237 return -EIO;
3238 return 0;
3239}
3240
3241/**
3242 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3243 * @mtd: MTD device structure
3244 * @chip: nand chip info structure
3245 * @addr: feature address.
3246 * @subfeature_param: the subfeature parameters, a four bytes array.
3247 */
3248static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3249 int addr, uint8_t *subfeature_param)
3250{
05f78359
UKK		 3251 int i;
3252
d914c932
DM		 3253 if (!chip->onfi_version ||
3254 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3255 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3256 return -EINVAL;
3257
7db03ecc 3258 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 3259 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3260 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 3261 return 0;
3262}
3263
4a78cc64
BB		 3264/**
3265 * nand_onfi_get_set_features_notsupp - set/get features stub returning
3266 * -ENOTSUPP
3267 * @mtd: MTD device structure
3268 * @chip: nand chip info structure
3269 * @addr: feature address.
3270 * @subfeature_param: the subfeature parameters, a four bytes array.
3271 *
3272 * Should be used by NAND controller drivers that do not support the SET/GET
3273 * FEATURES operations.
3274 */
3275int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd,
3276 struct nand_chip *chip, int addr,
3277 u8 *subfeature_param)
3278{
3279 return -ENOTSUPP;
3280}
3281EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp);
3282
962034f4
VW		 3283/**
3284 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 3285 * @mtd: MTD device structure
962034f4
VW		 3286 */
3287static int nand_suspend(struct mtd_info *mtd)
3288{
6a8214aa 3289 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 3290}
3291
3292/**
3293 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 3294 * @mtd: MTD device structure
962034f4
VW		 3295 */
3296static void nand_resume(struct mtd_info *mtd)
3297{
862eba51 3298 struct nand_chip *chip = mtd_to_nand(mtd);
962034f4 3299
ace4dfee 3300 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 3301 nand_release_device(mtd);
3302 else
d0370219
BN		 3303 pr_err("%s called for a chip which is not in suspended state\n",
3304 __func__);
962034f4
VW		 3305}
3306
72ea4036
SB		 3307/**
3308 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3309 * prevent further operations
3310 * @mtd: MTD device structure
3311 */
3312static void nand_shutdown(struct mtd_info *mtd)
3313{
9ca641b0 3314 nand_get_device(mtd, FL_PM_SUSPENDED);
72ea4036
SB		 3315}
3316
8b6e50c9 3317/* Set default functions */
29a198a1 3318static void nand_set_defaults(struct nand_chip *chip)
7aa65bfd 3319{
29a198a1
BB		 3320 unsigned int busw = chip->options & NAND_BUSWIDTH_16;
3321
1da177e4 3322 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 3323 if (!chip->chip_delay)
3324 chip->chip_delay = 20;
1da177e4
LT		 3325
3326 /* check, if a user supplied command function given */
ace4dfee
TG		 3327 if (chip->cmdfunc == NULL)
3328 chip->cmdfunc = nand_command;
1da177e4
LT		 3329
3330 /* check, if a user supplied wait function given */
ace4dfee
TG		 3331 if (chip->waitfunc == NULL)
3332 chip->waitfunc = nand_wait;
3333
3334 if (!chip->select_chip)
3335 chip->select_chip = nand_select_chip;
68e80780 3336
4204cccd
HS		 3337 /* set for ONFI nand */
3338 if (!chip->onfi_set_features)
3339 chip->onfi_set_features = nand_onfi_set_features;
3340 if (!chip->onfi_get_features)
3341 chip->onfi_get_features = nand_onfi_get_features;
3342
68e80780
BN		 3343 /* If called twice, pointers that depend on busw may need to be reset */
3344 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 3345 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3346 if (!chip->read_word)
3347 chip->read_word = nand_read_word;
3348 if (!chip->block_bad)
3349 chip->block_bad = nand_block_bad;
3350 if (!chip->block_markbad)
3351 chip->block_markbad = nand_default_block_markbad;
68e80780 3352 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3353 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 3354 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3355 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 3356 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3357 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3358 if (!chip->scan_bbt)
3359 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3360
3361 if (!chip->controller) {
3362 chip->controller = &chip->hwcontrol;
d45bc58d 3363 nand_hw_control_init(chip->controller);
f75e5097
TG		 3364 }
3365
477544c6
MY		 3366 if (!chip->buf_align)
3367 chip->buf_align = 1;
7aa65bfd
TG		 3368}
3369
8b6e50c9 3370/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3371static void sanitize_string(uint8_t *s, size_t len)
3372{
3373 ssize_t i;
3374
8b6e50c9 3375 /* Null terminate */
d1e1f4e4
FF		 3376 s[len - 1] = 0;
3377
8b6e50c9 3378 /* Remove non printable chars */
d1e1f4e4
FF		 3379 for (i = 0; i < len - 1; i++) {
3380 if (s[i] < ' ' || s[i] > 127)
3381 s[i] = '?';
3382 }
3383
8b6e50c9 3384 /* Remove trailing spaces */
d1e1f4e4
FF		 3385 strim(s);
3386}
3387
3388static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3389{
3390 int i;
3391 while (len--) {
3392 crc ^= *p++ << 8;
3393 for (i = 0; i < 8; i++)
3394 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3395 }
3396
3397 return crc;
3398}
3399
6dcbe0cd 3400/* Parse the Extended Parameter Page. */
cbe435a1
BB		 3401static int nand_flash_detect_ext_param_page(struct nand_chip *chip,
3402 struct nand_onfi_params *p)
6dcbe0cd 3403{
cbe435a1 3404 struct mtd_info *mtd = nand_to_mtd(chip);
6dcbe0cd
HS		 3405 struct onfi_ext_param_page *ep;
3406 struct onfi_ext_section *s;
3407 struct onfi_ext_ecc_info *ecc;
3408 uint8_t *cursor;
3409 int ret = -EINVAL;
3410 int len;
3411 int i;
3412
3413 len = le16_to_cpu(p->ext_param_page_length) * 16;
3414 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3415 if (!ep)
3416 return -ENOMEM;
6dcbe0cd
HS		 3417
3418 /* Send our own NAND_CMD_PARAM. */
3419 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3420
3421 /* Use the Change Read Column command to skip the ONFI param pages. */
3422 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3423 sizeof(*p) * p->num_of_param_pages , -1);
3424
3425 /* Read out the Extended Parameter Page. */
3426 chip->read_buf(mtd, (uint8_t *)ep, len);
3427 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3428 != le16_to_cpu(ep->crc))) {
3429 pr_debug("fail in the CRC.\n");
3430 goto ext_out;
3431 }
3432
3433 /*
3434 * Check the signature.
3435 * Do not strictly follow the ONFI spec, maybe changed in future.
3436 */
3437 if (strncmp(ep->sig, "EPPS", 4)) {
3438 pr_debug("The signature is invalid.\n");
3439 goto ext_out;
3440 }
3441
3442 /* find the ECC section. */
3443 cursor = (uint8_t *)(ep + 1);
3444 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3445 s = ep->sections + i;
3446 if (s->type == ONFI_SECTION_TYPE_2)
3447 break;
3448 cursor += s->length * 16;
3449 }
3450 if (i == ONFI_EXT_SECTION_MAX) {
3451 pr_debug("We can not find the ECC section.\n");
3452 goto ext_out;
3453 }
3454
3455 /* get the info we want. */
3456 ecc = (struct onfi_ext_ecc_info *)cursor;
3457
4ae7d228
BN		 3458 if (!ecc->codeword_size) {
3459 pr_debug("Invalid codeword size\n");
3460 goto ext_out;
6dcbe0cd
HS		 3461 }
3462
4ae7d228
BN		 3463 chip->ecc_strength_ds = ecc->ecc_bits;
3464 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3465 ret = 0;
6dcbe0cd
HS		 3466
3467ext_out:
3468 kfree(ep);
3469 return ret;
3470}
3471
6fb277ba 3472/*
8b6e50c9 3473 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba 3474 */
29a198a1 3475static int nand_flash_detect_onfi(struct nand_chip *chip)
6fb277ba 3476{
cbe435a1 3477 struct mtd_info *mtd = nand_to_mtd(chip);
6fb277ba 3478 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3479 int i, j;
6fb277ba
FF		 3480 int val;
3481
7854d3f7 3482 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3483 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3484 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3485 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3486 return 0;
3487
6fb277ba
FF		 3488 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3489 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3490 for (j = 0; j < sizeof(*p); j++)
3491 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3492 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3493 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3494 break;
3495 }
3496 }
3497
c7f23a70
BN		 3498 if (i == 3) {
3499 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3500 return 0;
c7f23a70 3501 }
6fb277ba 3502
8b6e50c9 3503 /* Check version */
6fb277ba 3504 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3505 if (val & (1 << 5))
3506 chip->onfi_version = 23;
3507 else if (val & (1 << 4))
6fb277ba
FF		 3508 chip->onfi_version = 22;
3509 else if (val & (1 << 3))
3510 chip->onfi_version = 21;
3511 else if (val & (1 << 2))
3512 chip->onfi_version = 20;
b7b1a29d 3513 else if (val & (1 << 1))
6fb277ba 3514 chip->onfi_version = 10;
b7b1a29d
BN		 3515
3516 if (!chip->onfi_version) {
20171642 3517 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3518 return 0;
3519 }
6fb277ba
FF		 3520
3521 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3522 sanitize_string(p->model, sizeof(p->model));
3523 if (!mtd->name)
3524 mtd->name = p->model;
4355b70c 3525
6fb277ba 3526 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3527
3528 /*
3529 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3530 * (don't ask me who thought of this...). MTD assumes that these
3531 * dimensions will be power-of-2, so just truncate the remaining area.
3532 */
3533 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3534 mtd->erasesize *= mtd->writesize;
3535
6fb277ba 3536 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3537
3538 /* See erasesize comment */
3539 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3540 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3541 chip->bits_per_cell = p->bits_per_cell;
e2985fc1 3542
34da5f5f
ZB		 3543 chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun);
3544 chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun);
3545
e2985fc1 3546 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
29a198a1 3547 chip->options |= NAND_BUSWIDTH_16;
6fb277ba 3548
10c86bab
HS		 3549 if (p->ecc_bits != 0xff) {
3550 chip->ecc_strength_ds = p->ecc_bits;
3551 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3552 } else if (chip->onfi_version >= 21 &&
3553 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3554
3555 /*
3556 * The nand_flash_detect_ext_param_page() uses the
3557 * Change Read Column command which maybe not supported
3558 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3559 * now. We do not replace user supplied command function.
3560 */
3561 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3562 chip->cmdfunc = nand_command_lp;
3563
3564 /* The Extended Parameter Page is supported since ONFI 2.1. */
cbe435a1 3565 if (nand_flash_detect_ext_param_page(chip, p))
c7f23a70
BN		 3566 pr_warn("Failed to detect ONFI extended param page\n");
3567 } else {
3568 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3569 }
3570
6fb277ba
FF		 3571 return 1;
3572}
3573
91361818
HS		 3574/*
3575 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3576 */
29a198a1 3577static int nand_flash_detect_jedec(struct nand_chip *chip)
91361818 3578{
cbe435a1 3579 struct mtd_info *mtd = nand_to_mtd(chip);
91361818
HS		 3580 struct nand_jedec_params *p = &chip->jedec_params;
3581 struct jedec_ecc_info *ecc;
3582 int val;
3583 int i, j;
3584
3585 /* Try JEDEC for unknown chip or LP */
3586 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3587 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3588 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3589 chip->read_byte(mtd) != 'C')
3590 return 0;
3591
3592 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3593 for (i = 0; i < 3; i++) {
3594 for (j = 0; j < sizeof(*p); j++)
3595 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3596
3597 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3598 le16_to_cpu(p->crc))
3599 break;
3600 }
3601
3602 if (i == 3) {
3603 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3604 return 0;
3605 }
3606
3607 /* Check version */
3608 val = le16_to_cpu(p->revision);
3609 if (val & (1 << 2))
3610 chip->jedec_version = 10;
3611 else if (val & (1 << 1))
3612 chip->jedec_version = 1; /* vendor specific version */
3613
3614 if (!chip->jedec_version) {
3615 pr_info("unsupported JEDEC version: %d\n", val);
3616 return 0;
3617 }
3618
3619 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3620 sanitize_string(p->model, sizeof(p->model));
3621 if (!mtd->name)
3622 mtd->name = p->model;
3623
3624 mtd->writesize = le32_to_cpu(p->byte_per_page);
3625
3626 /* Please reference to the comment for nand_flash_detect_onfi. */
3627 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3628 mtd->erasesize *= mtd->writesize;
3629
3630 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3631
3632 /* Please reference to the comment for nand_flash_detect_onfi. */
3633 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3634 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3635 chip->bits_per_cell = p->bits_per_cell;
3636
3637 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
29a198a1 3638 chip->options |= NAND_BUSWIDTH_16;
91361818
HS		 3639
3640 /* ECC info */
3641 ecc = &p->ecc_info[0];
3642
3643 if (ecc->codeword_size >= 9) {
3644 chip->ecc_strength_ds = ecc->ecc_bits;
3645 chip->ecc_step_ds = 1 << ecc->codeword_size;
3646 } else {
3647 pr_warn("Invalid codeword size\n");
3648 }
3649
3650 return 1;
3651}
3652
e3b88bd6
BN		 3653/*
3654 * nand_id_has_period - Check if an ID string has a given wraparound period
3655 * @id_data: the ID string
3656 * @arrlen: the length of the @id_data array
3657 * @period: the period of repitition
3658 *
3659 * Check if an ID string is repeated within a given sequence of bytes at
3660 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3661 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3662 * if the repetition has a period of @period; otherwise, returns zero.
3663 */
3664static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3665{
3666 int i, j;
3667 for (i = 0; i < period; i++)
3668 for (j = i + period; j < arrlen; j += period)
3669 if (id_data[i] != id_data[j])
3670 return 0;
3671 return 1;
3672}
3673
3674/*
3675 * nand_id_len - Get the length of an ID string returned by CMD_READID
3676 * @id_data: the ID string
3677 * @arrlen: the length of the @id_data array
3678
3679 * Returns the length of the ID string, according to known wraparound/trailing
3680 * zero patterns. If no pattern exists, returns the length of the array.
3681 */
3682static int nand_id_len(u8 *id_data, int arrlen)
3683{
3684 int last_nonzero, period;
3685
3686 /* Find last non-zero byte */
3687 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3688 if (id_data[last_nonzero])
3689 break;
3690
3691 /* All zeros */
3692 if (last_nonzero < 0)
3693 return 0;
3694
3695 /* Calculate wraparound period */
3696 for (period = 1; period < arrlen; period++)
3697 if (nand_id_has_period(id_data, arrlen, period))
3698 break;
3699
3700 /* There's a repeated pattern */
3701 if (period < arrlen)
3702 return period;
3703
3704 /* There are trailing zeros */
3705 if (last_nonzero < arrlen - 1)
3706 return last_nonzero + 1;
3707
3708 /* No pattern detected */
3709 return arrlen;
3710}
3711
7db906b7
HS		 3712/* Extract the bits of per cell from the 3rd byte of the extended ID */
3713static int nand_get_bits_per_cell(u8 cellinfo)
3714{
3715 int bits;
3716
3717 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3718 bits >>= NAND_CI_CELLTYPE_SHIFT;
3719 return bits + 1;
3720}
3721
fc09bbc0
BN		 3722/*
3723 * Many new NAND share similar device ID codes, which represent the size of the
3724 * chip. The rest of the parameters must be decoded according to generic or
3725 * manufacturer-specific "extended ID" decoding patterns.
3726 */
abbe26d1 3727void nand_decode_ext_id(struct nand_chip *chip)
fc09bbc0 3728{
cbe435a1 3729 struct mtd_info *mtd = nand_to_mtd(chip);
9b2d61f8 3730 int extid;
7f501f0a 3731 u8 *id_data = chip->id.data;
fc09bbc0 3732 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3733 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3734 /* The 4th id byte is the important one */
3735 extid = id_data[3];
3736
01389b6b
BB		 3737 /* Calc pagesize */
3738 mtd->writesize = 1024 << (extid & 0x03);
3739 extid >>= 2;
3740 /* Calc oobsize */
3741 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
3742 extid >>= 2;
3743 /* Calc blocksize. Blocksize is multiples of 64KiB */
3744 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3745 extid >>= 2;
3746 /* Get buswidth information */
3747 if (extid & 0x1)
3748 chip->options |= NAND_BUSWIDTH_16;
fc09bbc0 3749}
abbe26d1 3750EXPORT_SYMBOL_GPL(nand_decode_ext_id);
fc09bbc0 3751
f23a481c
BN		 3752/*
3753 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3754 * decodes a matching ID table entry and assigns the MTD size parameters for
3755 * the chip.
3756 */
29a198a1 3757static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
f23a481c 3758{
cbe435a1 3759 struct mtd_info *mtd = nand_to_mtd(chip);
f23a481c
BN		 3760
3761 mtd->erasesize = type->erasesize;
3762 mtd->writesize = type->pagesize;
3763 mtd->oobsize = mtd->writesize / 32;
f23a481c 3764
1c195e90
HS		 3765 /* All legacy ID NAND are small-page, SLC */
3766 chip->bits_per_cell = 1;
f23a481c
BN		 3767}
3768
7e74c2d7
BN		 3769/*
3770 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3771 * heuristic patterns using various detected parameters (e.g., manufacturer,
3772 * page size, cell-type information).
3773 */
7f501f0a 3774static void nand_decode_bbm_options(struct nand_chip *chip)
7e74c2d7 3775{
cbe435a1 3776 struct mtd_info *mtd = nand_to_mtd(chip);
7e74c2d7
BN		 3777
3778 /* Set the bad block position */
3779 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3780 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3781 else
3782 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
7e74c2d7
BN		 3783}
3784
ec6e87e3
HS		 3785static inline bool is_full_id_nand(struct nand_flash_dev *type)
3786{
3787 return type->id_len;
3788}
3789
cbe435a1 3790static bool find_full_id_nand(struct nand_chip *chip,
29a198a1 3791 struct nand_flash_dev *type)
ec6e87e3 3792{
cbe435a1 3793 struct mtd_info *mtd = nand_to_mtd(chip);
7f501f0a 3794 u8 *id_data = chip->id.data;
cbe435a1 3795
ec6e87e3
HS		 3796 if (!strncmp(type->id, id_data, type->id_len)) {
3797 mtd->writesize = type->pagesize;
3798 mtd->erasesize = type->erasesize;
3799 mtd->oobsize = type->oobsize;
3800
7db906b7 3801 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3802 chip->chipsize = (uint64_t)type->chipsize << 20;
3803 chip->options |= type->options;
57219342
HS		 3804 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3805 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3806 chip->onfi_timing_mode_default =
3807 type->onfi_timing_mode_default;
ec6e87e3 3808
092b6a1d
CZ		 3809 if (!mtd->name)
3810 mtd->name = type->name;
3811
ec6e87e3
HS		 3812 return true;
3813 }
3814 return false;
3815}
3816
abbe26d1
BB		 3817/*
3818 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
3819 * compliant and does not have a full-id or legacy-id entry in the nand_ids
3820 * table.
3821 */
3822static void nand_manufacturer_detect(struct nand_chip *chip)
3823{
3824 /*
3825 * Try manufacturer detection if available and use
3826 * nand_decode_ext_id() otherwise.
3827 */
3828 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
69fc0129
LW		 3829 chip->manufacturer.desc->ops->detect) {
3830 /* The 3rd id byte holds MLC / multichip data */
3831 chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
abbe26d1 3832 chip->manufacturer.desc->ops->detect(chip);
69fc0129 3833 } else {
abbe26d1 3834 nand_decode_ext_id(chip);
69fc0129 3835 }
abbe26d1
BB		 3836}
3837
3838/*
3839 * Manufacturer initialization. This function is called for all NANDs including
3840 * ONFI and JEDEC compliant ones.
3841 * Manufacturer drivers should put all their specific initialization code in
3842 * their ->init() hook.
3843 */
3844static int nand_manufacturer_init(struct nand_chip *chip)
3845{
3846 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
3847 !chip->manufacturer.desc->ops->init)
3848 return 0;
3849
3850 return chip->manufacturer.desc->ops->init(chip);
3851}
3852
3853/*
3854 * Manufacturer cleanup. This function is called for all NANDs including
3855 * ONFI and JEDEC compliant ones.
3856 * Manufacturer drivers should put all their specific cleanup code in their
3857 * ->cleanup() hook.
3858 */
3859static void nand_manufacturer_cleanup(struct nand_chip *chip)
3860{
3861 /* Release manufacturer private data */
3862 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
3863 chip->manufacturer.desc->ops->cleanup)
3864 chip->manufacturer.desc->ops->cleanup(chip);
3865}
3866
7aa65bfd 3867/*
8b6e50c9 3868 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd 3869 */
7bb42799 3870static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
7aa65bfd 3871{
bcc678c2 3872 const struct nand_manufacturer *manufacturer;
cbe435a1 3873 struct mtd_info *mtd = nand_to_mtd(chip);
bb77082f 3874 int busw;
f84674b8 3875 int i;
7f501f0a
BB		 3876 u8 *id_data = chip->id.data;
3877 u8 maf_id, dev_id;
1da177e4 3878
ef89a880
KB		 3879 /*
3880 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3881 * after power-up.
ef89a880 3882 */
73f907fd
BB		 3883 nand_reset(chip, 0);
3884
3885 /* Select the device */
3886 chip->select_chip(mtd, 0);
ef89a880 3887
1da177e4 3888 /* Send the command for reading device ID */
ace4dfee 3889 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3890
3891 /* Read manufacturer and device IDs */
7f501f0a
BB		 3892 maf_id = chip->read_byte(mtd);
3893 dev_id = chip->read_byte(mtd);
1da177e4 3894
8b6e50c9
BN		 3895 /*
3896 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3897 * interface concerns can cause random data which looks like a
3898 * possibly credible NAND flash to appear. If the two results do
3899 * not match, ignore the device completely.
3900 */
3901
3902 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3903
4aef9b78 3904 /* Read entire ID string */
5158bd55 3905 for (i = 0; i < ARRAY_SIZE(chip->id.data); i++)
426c457a 3906 id_data[i] = chip->read_byte(mtd);
ed8165c7 3907
7f501f0a 3908 if (id_data[0] != maf_id || id_data[1] != dev_id) {
20171642 3909 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
7f501f0a 3910 maf_id, dev_id, id_data[0], id_data[1]);
4722c0e9 3911 return -ENODEV;
ed8165c7
BD		 3912 }
3913
5158bd55 3914 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
7f501f0a 3915
abbe26d1
BB		 3916 /* Try to identify manufacturer */
3917 manufacturer = nand_get_manufacturer(maf_id);
3918 chip->manufacturer.desc = manufacturer;
3919
7aa65bfd 3920 if (!type)
5e81e88a
DW		 3921 type = nand_flash_ids;
3922
29a198a1
BB		 3923 /*
3924 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
3925 * override it.
3926 * This is required to make sure initial NAND bus width set by the
3927 * NAND controller driver is coherent with the real NAND bus width
3928 * (extracted by auto-detection code).
3929 */
3930 busw = chip->options & NAND_BUSWIDTH_16;
3931
3932 /*
3933 * The flag is only set (never cleared), reset it to its default value
3934 * before starting auto-detection.
3935 */
3936 chip->options &= ~NAND_BUSWIDTH_16;
3937
ec6e87e3
HS		 3938 for (; type->name != NULL; type++) {
3939 if (is_full_id_nand(type)) {
29a198a1 3940 if (find_full_id_nand(chip, type))
ec6e87e3 3941 goto ident_done;
7f501f0a 3942 } else if (dev_id == type->dev_id) {
db5b09f6 3943 break;
ec6e87e3
HS		 3944 }
3945 }
5e81e88a 3946
d1e1f4e4
FF		 3947 chip->onfi_version = 0;
3948 if (!type->name || !type->pagesize) {
35fc5195 3949 /* Check if the chip is ONFI compliant */
29a198a1 3950 if (nand_flash_detect_onfi(chip))
6fb277ba 3951 goto ident_done;
91361818
HS		 3952
3953 /* Check if the chip is JEDEC compliant */
29a198a1 3954 if (nand_flash_detect_jedec(chip))
91361818 3955 goto ident_done;
d1e1f4e4
FF		 3956 }
3957
5e81e88a 3958 if (!type->name)
4722c0e9 3959 return -ENODEV;
7aa65bfd 3960
ba0251fe
TG		 3961 if (!mtd->name)
3962 mtd->name = type->name;
3963
69423d99 3964 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3965
abbe26d1
BB		 3966 if (!type->pagesize)
3967 nand_manufacturer_detect(chip);
3968 else
29a198a1 3969 nand_decode_id(chip, type);
abbe26d1 3970
bf7a01bf
BN		 3971 /* Get chip options */
3972 chip->options |= type->options;
d1e1f4e4 3973
d1e1f4e4
FF		 3974ident_done:
3975
64b37b2a 3976 if (chip->options & NAND_BUSWIDTH_AUTO) {
29a198a1
BB		 3977 WARN_ON(busw & NAND_BUSWIDTH_16);
3978 nand_set_defaults(chip);
64b37b2a
MC		 3979 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3980 /*
3981 * Check, if buswidth is correct. Hardware drivers should set
3982 * chip correct!
3983 */
20171642 3984 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
7f501f0a 3985 maf_id, dev_id);
bcc678c2
BB		 3986 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
3987 mtd->name);
29a198a1
BB		 3988 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
3989 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
4722c0e9 3990 return -EINVAL;
7aa65bfd 3991 }
61b03bd7 3992
7f501f0a 3993 nand_decode_bbm_options(chip);
7e74c2d7 3994
7aa65bfd 3995 /* Calculate the address shift from the page size */
ace4dfee 3996 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3997 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3998 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3999
ace4dfee 4000 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 4001 ffs(mtd->erasesize) - 1;
69423d99
AH		 4002 if (chip->chipsize & 0xffffffff)
4003 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 4004 else {
4005 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4006 chip->chip_shift += 32 - 1;
4007 }
1da177e4 4008
14157f86
MY		 4009 if (chip->chip_shift - chip->page_shift > 16)
4010 chip->options |= NAND_ROW_ADDR_3;
4011
26d9be11 4012 chip->badblockbits = 8;
49c50b97 4013 chip->erase = single_erase;
7aa65bfd 4014
8b6e50c9 4015 /* Do not replace user supplied command function! */
ace4dfee
TG		 4016 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4017 chip->cmdfunc = nand_command_lp;
7aa65bfd 4018
20171642 4019 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
7f501f0a 4020 maf_id, dev_id);
ffdac6cd
HS		 4021
4022 if (chip->onfi_version)
bcc678c2
BB		 4023 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4024 chip->onfi_params.model);
ffdac6cd 4025 else if (chip->jedec_version)
bcc678c2
BB		 4026 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4027 chip->jedec_params.model);
ffdac6cd 4028 else
bcc678c2
BB		 4029 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4030 type->name);
ffdac6cd 4031
3755a991 4032 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 4033 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 4034 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4722c0e9 4035 return 0;
7aa65bfd
TG		 4036}
4037
d48f62b9
BB		 4038static const char * const nand_ecc_modes[] = {
4039 [NAND_ECC_NONE] = "none",
4040 [NAND_ECC_SOFT] = "soft",
4041 [NAND_ECC_HW] = "hw",
4042 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
4043 [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
785818fa 4044 [NAND_ECC_ON_DIE] = "on-die",
d48f62b9
BB		 4045};
4046
4047static int of_get_nand_ecc_mode(struct device_node *np)
4048{
4049 const char *pm;
4050 int err, i;
4051
4052 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4053 if (err < 0)
4054 return err;
4055
4056 for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
4057 if (!strcasecmp(pm, nand_ecc_modes[i]))
4058 return i;
4059
ae211bcf
RM		 4060 /*
4061 * For backward compatibility we support few obsoleted values that don't
4062 * have their mappings into nand_ecc_modes_t anymore (they were merged
4063 * with other enums).
4064 */
4065 if (!strcasecmp(pm, "soft_bch"))
4066 return NAND_ECC_SOFT;
4067
d48f62b9
BB		 4068 return -ENODEV;
4069}
4070
ba4f46b2
RM		 4071static const char * const nand_ecc_algos[] = {
4072 [NAND_ECC_HAMMING] = "hamming",
4073 [NAND_ECC_BCH] = "bch",
4074};
4075
d48f62b9
BB		 4076static int of_get_nand_ecc_algo(struct device_node *np)
4077{
4078 const char *pm;
ba4f46b2 4079 int err, i;
d48f62b9 4080
ba4f46b2
RM		 4081 err = of_property_read_string(np, "nand-ecc-algo", &pm);
4082 if (!err) {
4083 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4084 if (!strcasecmp(pm, nand_ecc_algos[i]))
4085 return i;
4086 return -ENODEV;
4087 }
d48f62b9
BB		 4088
4089 /*
4090 * For backward compatibility we also read "nand-ecc-mode" checking
4091 * for some obsoleted values that were specifying ECC algorithm.
4092 */
4093 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4094 if (err < 0)
4095 return err;
4096
4097 if (!strcasecmp(pm, "soft"))
4098 return NAND_ECC_HAMMING;
4099 else if (!strcasecmp(pm, "soft_bch"))
4100 return NAND_ECC_BCH;
4101
4102 return -ENODEV;
4103}
4104
4105static int of_get_nand_ecc_step_size(struct device_node *np)
4106{
4107 int ret;
4108 u32 val;
4109
4110 ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
4111 return ret ? ret : val;
4112}
4113
4114static int of_get_nand_ecc_strength(struct device_node *np)
4115{
4116 int ret;
4117 u32 val;
4118
4119 ret = of_property_read_u32(np, "nand-ecc-strength", &val);
4120 return ret ? ret : val;
4121}
4122
4123static int of_get_nand_bus_width(struct device_node *np)
4124{
4125 u32 val;
4126
4127 if (of_property_read_u32(np, "nand-bus-width", &val))
4128 return 8;
4129
4130 switch (val) {
4131 case 8:
4132 case 16:
4133 return val;
4134 default:
4135 return -EIO;
4136 }
4137}
4138
4139static bool of_get_nand_on_flash_bbt(struct device_node *np)
4140{
4141 return of_property_read_bool(np, "nand-on-flash-bbt");
4142}
4143
7194a29a 4144static int nand_dt_init(struct nand_chip *chip)
5844feea 4145{
7194a29a 4146 struct device_node *dn = nand_get_flash_node(chip);
79082457 4147 int ecc_mode, ecc_algo, ecc_strength, ecc_step;
5844feea 4148
7194a29a
BB		 4149 if (!dn)
4150 return 0;
4151
5844feea
BN		 4152 if (of_get_nand_bus_width(dn) == 16)
4153 chip->options |= NAND_BUSWIDTH_16;
4154
4155 if (of_get_nand_on_flash_bbt(dn))
4156 chip->bbt_options |= NAND_BBT_USE_FLASH;
4157
4158 ecc_mode = of_get_nand_ecc_mode(dn);
79082457 4159 ecc_algo = of_get_nand_ecc_algo(dn);
5844feea
BN		 4160 ecc_strength = of_get_nand_ecc_strength(dn);
4161 ecc_step = of_get_nand_ecc_step_size(dn);
4162
5844feea
BN		 4163 if (ecc_mode >= 0)
4164 chip->ecc.mode = ecc_mode;
4165
79082457
RM		 4166 if (ecc_algo >= 0)
4167 chip->ecc.algo = ecc_algo;
4168
5844feea
BN		 4169 if (ecc_strength >= 0)
4170 chip->ecc.strength = ecc_strength;
4171
4172 if (ecc_step > 0)
4173 chip->ecc.size = ecc_step;
4174
ba78ee00
BB		 4175 if (of_property_read_bool(dn, "nand-ecc-maximize"))
4176 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4177
5844feea
BN		 4178 return 0;
4179}
4180
7aa65bfd 4181/**
3b85c321 4182 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4183 * @mtd: MTD device structure
4184 * @maxchips: number of chips to scan for
4185 * @table: alternative NAND ID table
7aa65bfd 4186 *
8b6e50c9
BN		 4187 * This is the first phase of the normal nand_scan() function. It reads the
4188 * flash ID and sets up MTD fields accordingly.
7aa65bfd
TG		 4189 *
4190 */
5e81e88a
DW		 4191int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4192 struct nand_flash_dev *table)
7aa65bfd 4193{
bb77082f 4194 int i, nand_maf_id, nand_dev_id;
862eba51 4195 struct nand_chip *chip = mtd_to_nand(mtd);
5844feea
BN		 4196 int ret;
4197
7194a29a
BB		 4198 ret = nand_dt_init(chip);
4199 if (ret)
4200 return ret;
7aa65bfd 4201
f7a8e38f
BN		 4202 if (!mtd->name && mtd->dev.parent)
4203 mtd->name = dev_name(mtd->dev.parent);
4204
76fe334f
AS		 4205 if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
4206 /*
4207 * Default functions assigned for chip_select() and
4208 * cmdfunc() both expect cmd_ctrl() to be populated,
4209 * so we need to check that that's the case
4210 */
4211 pr_err("chip.cmd_ctrl() callback is not provided");
4212 return -EINVAL;
4213 }
7aa65bfd 4214 /* Set the default functions */
29a198a1 4215 nand_set_defaults(chip);
7aa65bfd
TG		 4216
4217 /* Read the flash type */
7bb42799 4218 ret = nand_detect(chip, table);
4722c0e9 4219 if (ret) {
b1c6e6db 4220 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 4221 pr_warn("No NAND device found\n");
ace4dfee 4222 chip->select_chip(mtd, -1);
4722c0e9 4223 return ret;
1da177e4
LT		 4224 }
4225
7f501f0a
BB		 4226 nand_maf_id = chip->id.data[0];
4227 nand_dev_id = chip->id.data[1];
4228
07300164
HS		 4229 chip->select_chip(mtd, -1);
4230
7aa65bfd 4231 /* Check for a chip array */
e0c7d767 4232 for (i = 1; i < maxchips; i++) {
ef89a880 4233 /* See comment in nand_get_flash_type for reset */
73f907fd
BB		 4234 nand_reset(chip, i);
4235
4236 chip->select_chip(mtd, i);
1da177e4 4237 /* Send the command for reading device ID */
ace4dfee 4238 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 4239 /* Read manufacturer and device IDs */
ace4dfee 4240 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 4241 nand_dev_id != chip->read_byte(mtd)) {
4242 chip->select_chip(mtd, -1);
1da177e4 4243 break;
07300164
HS		 4244 }
4245 chip->select_chip(mtd, -1);
1da177e4
LT		 4246 }
4247 if (i > 1)
20171642 4248 pr_info("%d chips detected\n", i);
61b03bd7 4249
1da177e4 4250 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 4251 chip->numchips = i;
4252 mtd->size = i * chip->chipsize;
7aa65bfd 4253
3b85c321
DW		 4254 return 0;
4255}
7351d3a5 4256EXPORT_SYMBOL(nand_scan_ident);
3b85c321 4257
06f384c9
RM		 4258static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4259{
4260 struct nand_chip *chip = mtd_to_nand(mtd);
4261 struct nand_ecc_ctrl *ecc = &chip->ecc;
4262
e4225ae8 4263 if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
06f384c9
RM		 4264 return -EINVAL;
4265
4266 switch (ecc->algo) {
4267 case NAND_ECC_HAMMING:
4268 ecc->calculate = nand_calculate_ecc;
4269 ecc->correct = nand_correct_data;
4270 ecc->read_page = nand_read_page_swecc;
4271 ecc->read_subpage = nand_read_subpage;
4272 ecc->write_page = nand_write_page_swecc;
4273 ecc->read_page_raw = nand_read_page_raw;
4274 ecc->write_page_raw = nand_write_page_raw;
4275 ecc->read_oob = nand_read_oob_std;
4276 ecc->write_oob = nand_write_oob_std;
4277 if (!ecc->size)
4278 ecc->size = 256;
4279 ecc->bytes = 3;
4280 ecc->strength = 1;
4281 return 0;
4282 case NAND_ECC_BCH:
4283 if (!mtd_nand_has_bch()) {
4284 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4285 return -EINVAL;
4286 }
4287 ecc->calculate = nand_bch_calculate_ecc;
4288 ecc->correct = nand_bch_correct_data;
4289 ecc->read_page = nand_read_page_swecc;
4290 ecc->read_subpage = nand_read_subpage;
4291 ecc->write_page = nand_write_page_swecc;
4292 ecc->read_page_raw = nand_read_page_raw;
4293 ecc->write_page_raw = nand_write_page_raw;
4294 ecc->read_oob = nand_read_oob_std;
4295 ecc->write_oob = nand_write_oob_std;
8bbba481 4296
06f384c9
RM		 4297 /*
4298 * Board driver should supply ecc.size and ecc.strength
4299 * values to select how many bits are correctable.
4300 * Otherwise, default to 4 bits for large page devices.
4301 */
4302 if (!ecc->size && (mtd->oobsize >= 64)) {
4303 ecc->size = 512;
4304 ecc->strength = 4;
4305 }
4306
4307 /*
4308 * if no ecc placement scheme was provided pickup the default
4309 * large page one.
4310 */
4311 if (!mtd->ooblayout) {
4312 /* handle large page devices only */
4313 if (mtd->oobsize < 64) {
4314 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4315 return -EINVAL;
4316 }
4317
4318 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
8bbba481
BB		 4319
4320 }
4321
4322 /*
4323 * We can only maximize ECC config when the default layout is
4324 * used, otherwise we don't know how many bytes can really be
4325 * used.
4326 */
4327 if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
4328 ecc->options & NAND_ECC_MAXIMIZE) {
4329 int steps, bytes;
4330
4331 /* Always prefer 1k blocks over 512bytes ones */
4332 ecc->size = 1024;
4333 steps = mtd->writesize / ecc->size;
4334
4335 /* Reserve 2 bytes for the BBM */
4336 bytes = (mtd->oobsize - 2) / steps;
4337 ecc->strength = bytes * 8 / fls(8 * ecc->size);
06f384c9
RM		 4338 }
4339
4340 /* See nand_bch_init() for details. */
4341 ecc->bytes = 0;
4342 ecc->priv = nand_bch_init(mtd);
4343 if (!ecc->priv) {
4344 WARN(1, "BCH ECC initialization failed!\n");
4345 return -EINVAL;
4346 }
4347 return 0;
4348 default:
4349 WARN(1, "Unsupported ECC algorithm!\n");
4350 return -EINVAL;
4351 }
4352}
4353
2c8f8afa
MY		 4354/**
4355 * nand_check_ecc_caps - check the sanity of preset ECC settings
4356 * @chip: nand chip info structure
4357 * @caps: ECC caps info structure
4358 * @oobavail: OOB size that the ECC engine can use
4359 *
4360 * When ECC step size and strength are already set, check if they are supported
4361 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4362 * On success, the calculated ECC bytes is set.
4363 */
4364int nand_check_ecc_caps(struct nand_chip *chip,
4365 const struct nand_ecc_caps *caps, int oobavail)
4366{
4367 struct mtd_info *mtd = nand_to_mtd(chip);
4368 const struct nand_ecc_step_info *stepinfo;
4369 int preset_step = chip->ecc.size;
4370 int preset_strength = chip->ecc.strength;
4371 int nsteps, ecc_bytes;
4372 int i, j;
4373
4374 if (WARN_ON(oobavail < 0))
4375 return -EINVAL;
4376
4377 if (!preset_step || !preset_strength)
4378 return -ENODATA;
4379
4380 nsteps = mtd->writesize / preset_step;
4381
4382 for (i = 0; i < caps->nstepinfos; i++) {
4383 stepinfo = &caps->stepinfos[i];
4384
4385 if (stepinfo->stepsize != preset_step)
4386 continue;
4387
4388 for (j = 0; j < stepinfo->nstrengths; j++) {
4389 if (stepinfo->strengths[j] != preset_strength)
4390 continue;
4391
4392 ecc_bytes = caps->calc_ecc_bytes(preset_step,
4393 preset_strength);
4394 if (WARN_ON_ONCE(ecc_bytes < 0))
4395 return ecc_bytes;
4396
4397 if (ecc_bytes * nsteps > oobavail) {
4398 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4399 preset_step, preset_strength);
4400 return -ENOSPC;
4401 }
4402
4403 chip->ecc.bytes = ecc_bytes;
4404
4405 return 0;
4406 }
4407 }
4408
4409 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4410 preset_step, preset_strength);
4411
4412 return -ENOTSUPP;
4413}
4414EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
4415
4416/**
4417 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4418 * @chip: nand chip info structure
4419 * @caps: ECC engine caps info structure
4420 * @oobavail: OOB size that the ECC engine can use
4421 *
4422 * If a chip's ECC requirement is provided, try to meet it with the least
4423 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4424 * On success, the chosen ECC settings are set.
4425 */
4426int nand_match_ecc_req(struct nand_chip *chip,
4427 const struct nand_ecc_caps *caps, int oobavail)
4428{
4429 struct mtd_info *mtd = nand_to_mtd(chip);
4430 const struct nand_ecc_step_info *stepinfo;
4431 int req_step = chip->ecc_step_ds;
4432 int req_strength = chip->ecc_strength_ds;
4433 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
4434 int best_step, best_strength, best_ecc_bytes;
4435 int best_ecc_bytes_total = INT_MAX;
4436 int i, j;
4437
4438 if (WARN_ON(oobavail < 0))
4439 return -EINVAL;
4440
4441 /* No information provided by the NAND chip */
4442 if (!req_step || !req_strength)
4443 return -ENOTSUPP;
4444
4445 /* number of correctable bits the chip requires in a page */
4446 req_corr = mtd->writesize / req_step * req_strength;
4447
4448 for (i = 0; i < caps->nstepinfos; i++) {
4449 stepinfo = &caps->stepinfos[i];
4450 step_size = stepinfo->stepsize;
4451
4452 for (j = 0; j < stepinfo->nstrengths; j++) {
4453 strength = stepinfo->strengths[j];
4454
4455 /*
4456 * If both step size and strength are smaller than the
4457 * chip's requirement, it is not easy to compare the
4458 * resulted reliability.
4459 */
4460 if (step_size < req_step && strength < req_strength)
4461 continue;
4462
4463 if (mtd->writesize % step_size)
4464 continue;
4465
4466 nsteps = mtd->writesize / step_size;
4467
4468 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4469 if (WARN_ON_ONCE(ecc_bytes < 0))
4470 continue;
4471 ecc_bytes_total = ecc_bytes * nsteps;
4472
4473 if (ecc_bytes_total > oobavail ||
4474 strength * nsteps < req_corr)
4475 continue;
4476
4477 /*
4478 * We assume the best is to meet the chip's requrement
4479 * with the least number of ECC bytes.
4480 */
4481 if (ecc_bytes_total < best_ecc_bytes_total) {
4482 best_ecc_bytes_total = ecc_bytes_total;
4483 best_step = step_size;
4484 best_strength = strength;
4485 best_ecc_bytes = ecc_bytes;
4486 }
4487 }
4488 }
4489
4490 if (best_ecc_bytes_total == INT_MAX)
4491 return -ENOTSUPP;
4492
4493 chip->ecc.size = best_step;
4494 chip->ecc.strength = best_strength;
4495 chip->ecc.bytes = best_ecc_bytes;
4496
4497 return 0;
4498}
4499EXPORT_SYMBOL_GPL(nand_match_ecc_req);
4500
4501/**
4502 * nand_maximize_ecc - choose the max ECC strength available
4503 * @chip: nand chip info structure
4504 * @caps: ECC engine caps info structure
4505 * @oobavail: OOB size that the ECC engine can use
4506 *
4507 * Choose the max ECC strength that is supported on the controller, and can fit
4508 * within the chip's OOB. On success, the chosen ECC settings are set.
4509 */
4510int nand_maximize_ecc(struct nand_chip *chip,
4511 const struct nand_ecc_caps *caps, int oobavail)
4512{
4513 struct mtd_info *mtd = nand_to_mtd(chip);
4514 const struct nand_ecc_step_info *stepinfo;
4515 int step_size, strength, nsteps, ecc_bytes, corr;
4516 int best_corr = 0;
4517 int best_step = 0;
4518 int best_strength, best_ecc_bytes;
4519 int i, j;
4520
4521 if (WARN_ON(oobavail < 0))
4522 return -EINVAL;
4523
4524 for (i = 0; i < caps->nstepinfos; i++) {
4525 stepinfo = &caps->stepinfos[i];
4526 step_size = stepinfo->stepsize;
4527
4528 /* If chip->ecc.size is already set, respect it */
4529 if (chip->ecc.size && step_size != chip->ecc.size)
4530 continue;
4531
4532 for (j = 0; j < stepinfo->nstrengths; j++) {
4533 strength = stepinfo->strengths[j];
4534
4535 if (mtd->writesize % step_size)
4536 continue;
4537
4538 nsteps = mtd->writesize / step_size;
4539
4540 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4541 if (WARN_ON_ONCE(ecc_bytes < 0))
4542 continue;
4543
4544 if (ecc_bytes * nsteps > oobavail)
4545 continue;
4546
4547 corr = strength * nsteps;
4548
4549 /*
4550 * If the number of correctable bits is the same,
4551 * bigger step_size has more reliability.
4552 */
4553 if (corr > best_corr ||
4554 (corr == best_corr && step_size > best_step)) {
4555 best_corr = corr;
4556 best_step = step_size;
4557 best_strength = strength;
4558 best_ecc_bytes = ecc_bytes;
4559 }
4560 }
4561 }
4562
4563 if (!best_corr)
4564 return -ENOTSUPP;
4565
4566 chip->ecc.size = best_step;
4567 chip->ecc.strength = best_strength;
4568 chip->ecc.bytes = best_ecc_bytes;
4569
4570 return 0;
4571}
4572EXPORT_SYMBOL_GPL(nand_maximize_ecc);
4573
67a9ad9b
EG		 4574/*
4575 * Check if the chip configuration meet the datasheet requirements.
4576
4577 * If our configuration corrects A bits per B bytes and the minimum
4578 * required correction level is X bits per Y bytes, then we must ensure
4579 * both of the following are true:
4580 *
4581 * (1) A / B >= X / Y
4582 * (2) A >= X
4583 *
4584 * Requirement (1) ensures we can correct for the required bitflip density.
4585 * Requirement (2) ensures we can correct even when all bitflips are clumped
4586 * in the same sector.
4587 */
4588static bool nand_ecc_strength_good(struct mtd_info *mtd)
4589{
862eba51 4590 struct nand_chip *chip = mtd_to_nand(mtd);
67a9ad9b
EG		 4591 struct nand_ecc_ctrl *ecc = &chip->ecc;
4592 int corr, ds_corr;
4593
4594 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4595 /* Not enough information */
4596 return true;
4597
4598 /*
4599 * We get the number of corrected bits per page to compare
4600 * the correction density.
4601 */
4602 corr = (mtd->writesize * ecc->strength) / ecc->size;
4603 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4604
4605 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4606}
3b85c321 4607
3371d663
MG		 4608static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4609{
4610 struct nand_ecc_ctrl *ecc = &chip->ecc;
4611
4612 if (nand_standard_page_accessors(ecc))
4613 return false;
4614
4615 /*
4616 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4617 * controller driver implements all the page accessors because
4618 * default helpers are not suitable when the core does not
4619 * send the READ0/PAGEPROG commands.
4620 */
4621 return (!ecc->read_page || !ecc->write_page ||
4622 !ecc->read_page_raw || !ecc->write_page_raw ||
4623 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
4624 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
4625 ecc->hwctl && ecc->calculate));
4626}
4627
3b85c321
DW		 4628/**
4629 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 4630 * @mtd: MTD device structure
3b85c321 4631 *
8b6e50c9
BN		 4632 * This is the second phase of the normal nand_scan() function. It fills out
4633 * all the uninitialized function pointers with the defaults and scans for a
4634 * bad block table if appropriate.
3b85c321
DW		 4635 */
4636int nand_scan_tail(struct mtd_info *mtd)
4637{
862eba51 4638 struct nand_chip *chip = mtd_to_nand(mtd);
97de79e0 4639 struct nand_ecc_ctrl *ecc = &chip->ecc;
3deb9979 4640 struct nand_buffers *nbuf = NULL;
f84674b8 4641 int ret, i;
3b85c321 4642
e2414f4c 4643 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
11eaf6df 4644 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
78771049 4645 !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
f84674b8 4646 return -EINVAL;
78771049 4647 }
e2414f4c 4648
3371d663
MG		 4649 if (invalid_ecc_page_accessors(chip)) {
4650 pr_err("Invalid ECC page accessors setup\n");
f84674b8 4651 return -EINVAL;
3371d663
MG		 4652 }
4653
f02ea4e6 4654 if (!(chip->options & NAND_OWN_BUFFERS)) {
3deb9979 4655 nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL);
f84674b8
BB		 4656 if (!nbuf)
4657 return -ENOMEM;
3deb9979
MY		 4658
4659 nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL);
4660 if (!nbuf->ecccalc) {
4661 ret = -ENOMEM;
f84674b8 4662 goto err_free_nbuf;
3deb9979
MY		 4663 }
4664
4665 nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL);
4666 if (!nbuf->ecccode) {
4667 ret = -ENOMEM;
f84674b8 4668 goto err_free_nbuf;
3deb9979
MY		 4669 }
4670
4671 nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize,
4672 GFP_KERNEL);
4673 if (!nbuf->databuf) {
4674 ret = -ENOMEM;
f84674b8 4675 goto err_free_nbuf;
3deb9979 4676 }
f02ea4e6
HS		 4677
4678 chip->buffers = nbuf;
f84674b8
BB		 4679 } else if (!chip->buffers) {
4680 return -ENOMEM;
f02ea4e6 4681 }
4bf63fcb 4682
f84674b8
BB		 4683 /*
4684 * FIXME: some NAND manufacturer drivers expect the first die to be
4685 * selected when manufacturer->init() is called. They should be fixed
4686 * to explictly select the relevant die when interacting with the NAND
4687 * chip.
4688 */
4689 chip->select_chip(mtd, 0);
4690 ret = nand_manufacturer_init(chip);
4691 chip->select_chip(mtd, -1);
4692 if (ret)
4693 goto err_free_nbuf;
4694
7dcdcbef 4695 /* Set the internal oob buffer location, just after the page data */
784f4d5e 4696 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 4697
7aa65bfd 4698 /*
8b6e50c9 4699 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 4700 */
06f384c9 4701 if (!mtd->ooblayout &&
e4225ae8 4702 !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
61b03bd7 4703 switch (mtd->oobsize) {
1da177e4 4704 case 8:
1da177e4 4705 case 16:
41b207a7 4706 mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
1da177e4
LT		 4707 break;
4708 case 64:
81ec5364 4709 case 128:
6a623e07 4710 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
81ec5364 4711 break;
1da177e4 4712 default:
882fd157
MR		 4713 /*
4714 * Expose the whole OOB area to users if ECC_NONE
4715 * is passed. We could do that for all kind of
4716 * ->oobsize, but we must keep the old large/small
4717 * page with ECC layout when ->oobsize <= 128 for
4718 * compatibility reasons.
4719 */
4720 if (ecc->mode == NAND_ECC_NONE) {
4721 mtd_set_ooblayout(mtd,
4722 &nand_ooblayout_lp_ops);
4723 break;
4724 }
4725
11eaf6df
EG		 4726 WARN(1, "No oob scheme defined for oobsize %d\n",
4727 mtd->oobsize);
4728 ret = -EINVAL;
f84674b8 4729 goto err_nand_manuf_cleanup;
1da177e4
LT		 4730 }
4731 }
61b03bd7 4732
61b03bd7 4733 /*
8b6e50c9 4734 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 4735 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 4736 */
956e944c 4737
97de79e0 4738 switch (ecc->mode) {
6e0cb135
SN		 4739 case NAND_ECC_HW_OOB_FIRST:
4740 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 4741 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
11eaf6df
EG		 4742 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4743 ret = -EINVAL;
f84674b8 4744 goto err_nand_manuf_cleanup;
6e0cb135 4745 }
97de79e0
HS		 4746 if (!ecc->read_page)
4747 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 4748
6dfc6d25 4749 case NAND_ECC_HW:
8b6e50c9 4750 /* Use standard hwecc read page function? */
97de79e0
HS		 4751 if (!ecc->read_page)
4752 ecc->read_page = nand_read_page_hwecc;
4753 if (!ecc->write_page)
4754 ecc->write_page = nand_write_page_hwecc;
4755 if (!ecc->read_page_raw)
4756 ecc->read_page_raw = nand_read_page_raw;
4757 if (!ecc->write_page_raw)
4758 ecc->write_page_raw = nand_write_page_raw;
4759 if (!ecc->read_oob)
4760 ecc->read_oob = nand_read_oob_std;
4761 if (!ecc->write_oob)
4762 ecc->write_oob = nand_write_oob_std;
4763 if (!ecc->read_subpage)
4764 ecc->read_subpage = nand_read_subpage;
44991b3d 4765 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
97de79e0 4766 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4767
6dfc6d25 4768 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 4769 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4770 (!ecc->read_page ||
4771 ecc->read_page == nand_read_page_hwecc ||
4772 !ecc->write_page ||
4773 ecc->write_page == nand_write_page_hwecc)) {
11eaf6df
EG		 4774 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4775 ret = -EINVAL;
f84674b8 4776 goto err_nand_manuf_cleanup;
6dfc6d25 4777 }
8b6e50c9 4778 /* Use standard syndrome read/write page function? */
97de79e0
HS		 4779 if (!ecc->read_page)
4780 ecc->read_page = nand_read_page_syndrome;
4781 if (!ecc->write_page)
4782 ecc->write_page = nand_write_page_syndrome;
4783 if (!ecc->read_page_raw)
4784 ecc->read_page_raw = nand_read_page_raw_syndrome;
4785 if (!ecc->write_page_raw)
4786 ecc->write_page_raw = nand_write_page_raw_syndrome;
4787 if (!ecc->read_oob)
4788 ecc->read_oob = nand_read_oob_syndrome;
4789 if (!ecc->write_oob)
4790 ecc->write_oob = nand_write_oob_syndrome;
4791
4792 if (mtd->writesize >= ecc->size) {
4793 if (!ecc->strength) {
11eaf6df
EG		 4794 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4795 ret = -EINVAL;
f84674b8 4796 goto err_nand_manuf_cleanup;
e2788c98 4797 }
6dfc6d25 4798 break;
e2788c98 4799 }
2ac63d90
RM		 4800 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4801 ecc->size, mtd->writesize);
97de79e0 4802 ecc->mode = NAND_ECC_SOFT;
e9d4faed 4803 ecc->algo = NAND_ECC_HAMMING;
61b03bd7 4804
6dfc6d25 4805 case NAND_ECC_SOFT:
06f384c9
RM		 4806 ret = nand_set_ecc_soft_ops(mtd);
4807 if (ret) {
11eaf6df 4808 ret = -EINVAL;
f84674b8 4809 goto err_nand_manuf_cleanup;
193bd400
ID		 4810 }
4811 break;
4812
785818fa
TP		 4813 case NAND_ECC_ON_DIE:
4814 if (!ecc->read_page || !ecc->write_page) {
4815 WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
4816 ret = -EINVAL;
f84674b8 4817 goto err_nand_manuf_cleanup;
785818fa
TP		 4818 }
4819 if (!ecc->read_oob)
4820 ecc->read_oob = nand_read_oob_std;
4821 if (!ecc->write_oob)
4822 ecc->write_oob = nand_write_oob_std;
4823 break;
4824
61b03bd7 4825 case NAND_ECC_NONE:
2ac63d90 4826 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4827 ecc->read_page = nand_read_page_raw;
4828 ecc->write_page = nand_write_page_raw;
4829 ecc->read_oob = nand_read_oob_std;
4830 ecc->read_page_raw = nand_read_page_raw;
4831 ecc->write_page_raw = nand_write_page_raw;
4832 ecc->write_oob = nand_write_oob_std;
4833 ecc->size = mtd->writesize;
4834 ecc->bytes = 0;
4835 ecc->strength = 0;
1da177e4 4836 break;
956e944c 4837
1da177e4 4838 default:
11eaf6df
EG		 4839 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4840 ret = -EINVAL;
f84674b8 4841 goto err_nand_manuf_cleanup;
1da177e4 4842 }
61b03bd7 4843
9ce244b3 4844 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4845 if (!ecc->read_oob_raw)
4846 ecc->read_oob_raw = ecc->read_oob;
4847 if (!ecc->write_oob_raw)
4848 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4849
846031d3 4850 /* propagate ecc info to mtd_info */
846031d3
BB		 4851 mtd->ecc_strength = ecc->strength;
4852 mtd->ecc_step_size = ecc->size;
67a9ad9b 4853
7aa65bfd
TG		 4854 /*
4855 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4856 * mode.
7aa65bfd 4857 */
97de79e0
HS		 4858 ecc->steps = mtd->writesize / ecc->size;
4859 if (ecc->steps * ecc->size != mtd->writesize) {
11eaf6df
EG		 4860 WARN(1, "Invalid ECC parameters\n");
4861 ret = -EINVAL;
f84674b8 4862 goto err_nand_manuf_cleanup;
1da177e4 4863 }
97de79e0 4864 ecc->total = ecc->steps * ecc->bytes;
79e0348c
MY		 4865 if (ecc->total > mtd->oobsize) {
4866 WARN(1, "Total number of ECC bytes exceeded oobsize\n");
4867 ret = -EINVAL;
f84674b8 4868 goto err_nand_manuf_cleanup;
79e0348c 4869 }
61b03bd7 4870
846031d3
BB		 4871 /*
4872 * The number of bytes available for a client to place data into
4873 * the out of band area.
4874 */
4875 ret = mtd_ooblayout_count_freebytes(mtd);
4876 if (ret < 0)
4877 ret = 0;
4878
4879 mtd->oobavail = ret;
4880
4881 /* ECC sanity check: warn if it's too weak */
4882 if (!nand_ecc_strength_good(mtd))
4883 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4884 mtd->name);
4885
8b6e50c9 4886 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4887 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4888 switch (ecc->steps) {
29072b96
TG		 4889 case 2:
4890 mtd->subpage_sft = 1;
4891 break;
4892 case 4:
4893 case 8:
81ec5364 4894 case 16:
29072b96
TG		 4895 mtd->subpage_sft = 2;
4896 break;
4897 }
4898 }
4899 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4900
04bbd0ea 4901 /* Initialize state */
ace4dfee 4902 chip->state = FL_READY;
1da177e4 4903
1da177e4 4904 /* Invalidate the pagebuffer reference */
ace4dfee 4905 chip->pagebuf = -1;
1da177e4 4906
a5ff4f10 4907 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4908 switch (ecc->mode) {
4909 case NAND_ECC_SOFT:
4007e2d1
RL		 4910 if (chip->page_shift > 9)
4911 chip->options |= NAND_SUBPAGE_READ;
4912 break;
4913
4914 default:
4915 break;
4916 }
a5ff4f10 4917
1da177e4 4918 /* Fill in remaining MTD driver data */
963d1c28 4919 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4920 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4921 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4922 mtd->_erase = nand_erase;
4923 mtd->_point = NULL;
4924 mtd->_unpoint = NULL;
4925 mtd->_read = nand_read;
4926 mtd->_write = nand_write;
4927 mtd->_panic_write = panic_nand_write;
4928 mtd->_read_oob = nand_read_oob;
4929 mtd->_write_oob = nand_write_oob;
4930 mtd->_sync = nand_sync;
4931 mtd->_lock = NULL;
4932 mtd->_unlock = NULL;
4933 mtd->_suspend = nand_suspend;
4934 mtd->_resume = nand_resume;
72ea4036 4935 mtd->_reboot = nand_shutdown;
8471bb73 4936 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4937 mtd->_block_isbad = nand_block_isbad;
4938 mtd->_block_markbad = nand_block_markbad;
5671842f 4939 mtd->_max_bad_blocks = nand_max_bad_blocks;
cbcab65a 4940 mtd->writebufsize = mtd->writesize;
1da177e4 4941
ea3b2ea2
SL		 4942 /*
4943 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4944 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4945 * properly set.
4946 */
4947 if (!mtd->bitflip_threshold)
240181fd 4948 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4949
f84674b8
BB		 4950 /* Initialize the ->data_interface field. */
4951 ret = nand_init_data_interface(chip);
4952 if (ret)
4953 goto err_nand_manuf_cleanup;
4954
4955 /* Enter fastest possible mode on all dies. */
4956 for (i = 0; i < chip->numchips; i++) {
4957 chip->select_chip(mtd, i);
4958 ret = nand_setup_data_interface(chip, i);
4959 chip->select_chip(mtd, -1);
4960
4961 if (ret)
4962 goto err_nand_data_iface_cleanup;
4963 }
4964
0040bf38 4965 /* Check, if we should skip the bad block table scan */
ace4dfee 4966 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4967 return 0;
1da177e4
LT		 4968
4969 /* Build bad block table */
44d4182e
BN		 4970 ret = chip->scan_bbt(mtd);
4971 if (ret)
f84674b8
BB		 4972 goto err_nand_data_iface_cleanup;
4973
44d4182e
BN		 4974 return 0;
4975
f84674b8
BB		 4976err_nand_data_iface_cleanup:
4977 nand_release_data_interface(chip);
4978
4979err_nand_manuf_cleanup:
4980 nand_manufacturer_cleanup(chip);
4981
4982err_free_nbuf:
3deb9979
MY		 4983 if (nbuf) {
4984 kfree(nbuf->databuf);
4985 kfree(nbuf->ecccode);
4986 kfree(nbuf->ecccalc);
4987 kfree(nbuf);
4988 }
78771049 4989
11eaf6df 4990 return ret;
1da177e4 4991}
7351d3a5 4992EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4993
8b6e50c9
BN		 4994/*
4995 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4996 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4997 * to call us from in-kernel code if the core NAND support is modular.
4998 */
3b85c321
DW		 4999#ifdef MODULE
5000#define caller_is_module() (1)
5001#else
5002#define caller_is_module() \
a6e6abd5 5003 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 5004#endif
5005
5006/**
5007 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 5008 * @mtd: MTD device structure
5009 * @maxchips: number of chips to scan for
3b85c321 5010 *
8b6e50c9
BN		 5011 * This fills out all the uninitialized function pointers with the defaults.
5012 * The flash ID is read and the mtd/chip structures are filled with the
20c07a5b 5013 * appropriate values.
3b85c321
DW		 5014 */
5015int nand_scan(struct mtd_info *mtd, int maxchips)
5016{
5017 int ret;
5018
5e81e88a 5019 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 5020 if (!ret)
5021 ret = nand_scan_tail(mtd);
5022 return ret;
5023}
7351d3a5 5024EXPORT_SYMBOL(nand_scan);
3b85c321 5025
1da177e4 5026/**
d44154f9
RW		 5027 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
5028 * @chip: NAND chip object
8b6e50c9 5029 */
d44154f9 5030void nand_cleanup(struct nand_chip *chip)
1da177e4 5031{
e4225ae8 5032 if (chip->ecc.mode == NAND_ECC_SOFT &&
06f384c9 5033 chip->ecc.algo == NAND_ECC_BCH)
193bd400
ID		 5034 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
5035
d8e725dd
BB		 5036 nand_release_data_interface(chip);
5037
fa671646 5038 /* Free bad block table memory */
ace4dfee 5039 kfree(chip->bbt);
3deb9979
MY		 5040 if (!(chip->options & NAND_OWN_BUFFERS) && chip->buffers) {
5041 kfree(chip->buffers->databuf);
5042 kfree(chip->buffers->ecccode);
5043 kfree(chip->buffers->ecccalc);
4bf63fcb 5044 kfree(chip->buffers);
3deb9979 5045 }
58373ff0
BN		 5046
5047 /* Free bad block descriptor memory */
5048 if (chip->badblock_pattern && chip->badblock_pattern->options
5049 & NAND_BBT_DYNAMICSTRUCT)
5050 kfree(chip->badblock_pattern);
abbe26d1
BB		 5051
5052 /* Free manufacturer priv data. */
5053 nand_manufacturer_cleanup(chip);
1da177e4 5054}
d44154f9
RW		 5055EXPORT_SYMBOL_GPL(nand_cleanup);
5056
5057/**
5058 * nand_release - [NAND Interface] Unregister the MTD device and free resources
5059 * held by the NAND device
5060 * @mtd: MTD device structure
5061 */
5062void nand_release(struct mtd_info *mtd)
5063{
5064 mtd_device_unregister(mtd);
5065 nand_cleanup(mtd_to_nand(mtd));
5066}
e0c7d767 5067EXPORT_SYMBOL_GPL(nand_release);
8fe833c1 5068
e0c7d767 5069MODULE_LICENSE("GPL");
7351d3a5
FF		 5070MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5071MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 5072MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)