Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
38b8d208 | 39 | #include <linux/nmi.h> |
1da177e4 LT |
40 | #include <linux/types.h> |
41 | #include <linux/mtd/mtd.h> | |
d4092d76 | 42 | #include <linux/mtd/rawnand.h> |
1da177e4 | 43 | #include <linux/mtd/nand_ecc.h> |
193bd400 | 44 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
45 | #include <linux/interrupt.h> |
46 | #include <linux/bitops.h> | |
7351d3a5 | 47 | #include <linux/io.h> |
1da177e4 | 48 | #include <linux/mtd/partitions.h> |
d48f62b9 | 49 | #include <linux/of.h> |
1da177e4 | 50 | |
41b207a7 BB |
51 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
52 | ||
53 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, | |
54 | struct mtd_oob_ops *ops); | |
1da177e4 LT |
55 | |
56 | /* Define default oob placement schemes for large and small page devices */ | |
41b207a7 BB |
57 | static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, |
58 | struct mtd_oob_region *oobregion) | |
59 | { | |
60 | struct nand_chip *chip = mtd_to_nand(mtd); | |
61 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 62 | |
41b207a7 BB |
63 | if (section > 1) |
64 | return -ERANGE; | |
1da177e4 | 65 | |
41b207a7 BB |
66 | if (!section) { |
67 | oobregion->offset = 0; | |
f7f8c175 MR |
68 | if (mtd->oobsize == 16) |
69 | oobregion->length = 4; | |
70 | else | |
71 | oobregion->length = 3; | |
41b207a7 | 72 | } else { |
f7f8c175 MR |
73 | if (mtd->oobsize == 8) |
74 | return -ERANGE; | |
75 | ||
41b207a7 BB |
76 | oobregion->offset = 6; |
77 | oobregion->length = ecc->total - 4; | |
78 | } | |
1da177e4 | 79 | |
41b207a7 BB |
80 | return 0; |
81 | } | |
82 | ||
83 | static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, | |
84 | struct mtd_oob_region *oobregion) | |
85 | { | |
86 | if (section > 1) | |
87 | return -ERANGE; | |
1da177e4 | 88 | |
41b207a7 BB |
89 | if (mtd->oobsize == 16) { |
90 | if (section) | |
91 | return -ERANGE; | |
92 | ||
93 | oobregion->length = 8; | |
94 | oobregion->offset = 8; | |
95 | } else { | |
96 | oobregion->length = 2; | |
97 | if (!section) | |
98 | oobregion->offset = 3; | |
99 | else | |
100 | oobregion->offset = 6; | |
101 | } | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { | |
107 | .ecc = nand_ooblayout_ecc_sp, | |
108 | .free = nand_ooblayout_free_sp, | |
81ec5364 | 109 | }; |
41b207a7 | 110 | EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); |
81ec5364 | 111 | |
41b207a7 BB |
112 | static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, |
113 | struct mtd_oob_region *oobregion) | |
114 | { | |
115 | struct nand_chip *chip = mtd_to_nand(mtd); | |
116 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 117 | |
882fd157 | 118 | if (section || !ecc->total) |
41b207a7 | 119 | return -ERANGE; |
8593fbc6 | 120 | |
41b207a7 BB |
121 | oobregion->length = ecc->total; |
122 | oobregion->offset = mtd->oobsize - oobregion->length; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, | |
128 | struct mtd_oob_region *oobregion) | |
129 | { | |
130 | struct nand_chip *chip = mtd_to_nand(mtd); | |
131 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
132 | ||
133 | if (section) | |
134 | return -ERANGE; | |
135 | ||
136 | oobregion->length = mtd->oobsize - ecc->total - 2; | |
137 | oobregion->offset = 2; | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { | |
143 | .ecc = nand_ooblayout_ecc_lp, | |
144 | .free = nand_ooblayout_free_lp, | |
145 | }; | |
146 | EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); | |
d470a97c | 147 | |
6a623e07 AC |
148 | /* |
149 | * Support the old "large page" layout used for 1-bit Hamming ECC where ECC | |
150 | * are placed at a fixed offset. | |
151 | */ | |
152 | static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, | |
153 | struct mtd_oob_region *oobregion) | |
154 | { | |
155 | struct nand_chip *chip = mtd_to_nand(mtd); | |
156 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
157 | ||
158 | if (section) | |
159 | return -ERANGE; | |
160 | ||
161 | switch (mtd->oobsize) { | |
162 | case 64: | |
163 | oobregion->offset = 40; | |
164 | break; | |
165 | case 128: | |
166 | oobregion->offset = 80; | |
167 | break; | |
168 | default: | |
169 | return -EINVAL; | |
170 | } | |
171 | ||
172 | oobregion->length = ecc->total; | |
173 | if (oobregion->offset + oobregion->length > mtd->oobsize) | |
174 | return -ERANGE; | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, | |
180 | struct mtd_oob_region *oobregion) | |
181 | { | |
182 | struct nand_chip *chip = mtd_to_nand(mtd); | |
183 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
184 | int ecc_offset = 0; | |
185 | ||
186 | if (section < 0 || section > 1) | |
187 | return -ERANGE; | |
188 | ||
189 | switch (mtd->oobsize) { | |
190 | case 64: | |
191 | ecc_offset = 40; | |
192 | break; | |
193 | case 128: | |
194 | ecc_offset = 80; | |
195 | break; | |
196 | default: | |
197 | return -EINVAL; | |
198 | } | |
199 | ||
200 | if (section == 0) { | |
201 | oobregion->offset = 2; | |
202 | oobregion->length = ecc_offset - 2; | |
203 | } else { | |
204 | oobregion->offset = ecc_offset + ecc->total; | |
205 | oobregion->length = mtd->oobsize - oobregion->offset; | |
206 | } | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
d4ed3b90 | 211 | static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { |
6a623e07 AC |
212 | .ecc = nand_ooblayout_ecc_lp_hamming, |
213 | .free = nand_ooblayout_free_lp_hamming, | |
214 | }; | |
215 | ||
6fe5a6ac VS |
216 | static int check_offs_len(struct mtd_info *mtd, |
217 | loff_t ofs, uint64_t len) | |
218 | { | |
862eba51 | 219 | struct nand_chip *chip = mtd_to_nand(mtd); |
6fe5a6ac VS |
220 | int ret = 0; |
221 | ||
222 | /* Start address must align on block boundary */ | |
daae74ca | 223 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 224 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
225 | ret = -EINVAL; |
226 | } | |
227 | ||
228 | /* Length must align on block boundary */ | |
daae74ca | 229 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 230 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
231 | ret = -EINVAL; |
232 | } | |
233 | ||
6fe5a6ac VS |
234 | return ret; |
235 | } | |
236 | ||
1da177e4 LT |
237 | /** |
238 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 239 | * @mtd: MTD device structure |
61b03bd7 | 240 | * |
b0bb6903 | 241 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 242 | */ |
e0c7d767 | 243 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 244 | { |
862eba51 | 245 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 246 | |
a36ed299 | 247 | /* Release the controller and the chip */ |
ace4dfee TG |
248 | spin_lock(&chip->controller->lock); |
249 | chip->controller->active = NULL; | |
250 | chip->state = FL_READY; | |
251 | wake_up(&chip->controller->wq); | |
252 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
253 | } |
254 | ||
255 | /** | |
256 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 257 | * @mtd: MTD device structure |
1da177e4 | 258 | * |
7854d3f7 | 259 | * Default read function for 8bit buswidth |
1da177e4 | 260 | */ |
58dd8f2b | 261 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 262 | { |
862eba51 | 263 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 264 | return readb(chip->IO_ADDR_R); |
1da177e4 LT |
265 | } |
266 | ||
1da177e4 | 267 | /** |
7854d3f7 | 268 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 269 | * @mtd: MTD device structure |
1da177e4 | 270 | * |
7854d3f7 BN |
271 | * Default read function for 16bit buswidth with endianness conversion. |
272 | * | |
1da177e4 | 273 | */ |
58dd8f2b | 274 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 275 | { |
862eba51 | 276 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 277 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 282 | * @mtd: MTD device structure |
1da177e4 | 283 | * |
7854d3f7 | 284 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
285 | */ |
286 | static u16 nand_read_word(struct mtd_info *mtd) | |
287 | { | |
862eba51 | 288 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 289 | return readw(chip->IO_ADDR_R); |
1da177e4 LT |
290 | } |
291 | ||
1da177e4 LT |
292 | /** |
293 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
294 | * @mtd: MTD device structure |
295 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
296 | * |
297 | * Default select function for 1 chip devices. | |
298 | */ | |
ace4dfee | 299 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 300 | { |
862eba51 | 301 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
302 | |
303 | switch (chipnr) { | |
1da177e4 | 304 | case -1: |
ace4dfee | 305 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
306 | break; |
307 | case 0: | |
1da177e4 LT |
308 | break; |
309 | ||
310 | default: | |
311 | BUG(); | |
312 | } | |
313 | } | |
314 | ||
05f78359 UKK |
315 | /** |
316 | * nand_write_byte - [DEFAULT] write single byte to chip | |
317 | * @mtd: MTD device structure | |
318 | * @byte: value to write | |
319 | * | |
320 | * Default function to write a byte to I/O[7:0] | |
321 | */ | |
322 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
323 | { | |
862eba51 | 324 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
325 | |
326 | chip->write_buf(mtd, &byte, 1); | |
327 | } | |
328 | ||
329 | /** | |
330 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
331 | * @mtd: MTD device structure | |
332 | * @byte: value to write | |
333 | * | |
334 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
335 | */ | |
336 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
337 | { | |
862eba51 | 338 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
339 | uint16_t word = byte; |
340 | ||
341 | /* | |
342 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
343 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
344 | * | |
345 | * When the host supports a 16-bit bus width, only data is | |
346 | * transferred at the 16-bit width. All address and command line | |
347 | * transfers shall use only the lower 8-bits of the data bus. During | |
348 | * command transfers, the host may place any value on the upper | |
349 | * 8-bits of the data bus. During address transfers, the host shall | |
350 | * set the upper 8-bits of the data bus to 00h. | |
351 | * | |
352 | * One user of the write_byte callback is nand_onfi_set_features. The | |
353 | * four parameters are specified to be written to I/O[7:0], but this is | |
354 | * neither an address nor a command transfer. Let's assume a 0 on the | |
355 | * upper I/O lines is OK. | |
356 | */ | |
357 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
358 | } | |
359 | ||
1da177e4 LT |
360 | /** |
361 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
362 | * @mtd: MTD device structure |
363 | * @buf: data buffer | |
364 | * @len: number of bytes to write | |
1da177e4 | 365 | * |
7854d3f7 | 366 | * Default write function for 8bit buswidth. |
1da177e4 | 367 | */ |
58dd8f2b | 368 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 369 | { |
862eba51 | 370 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 371 | |
76413839 | 372 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
373 | } |
374 | ||
375 | /** | |
61b03bd7 | 376 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
377 | * @mtd: MTD device structure |
378 | * @buf: buffer to store date | |
379 | * @len: number of bytes to read | |
1da177e4 | 380 | * |
7854d3f7 | 381 | * Default read function for 8bit buswidth. |
1da177e4 | 382 | */ |
58dd8f2b | 383 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 384 | { |
862eba51 | 385 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 386 | |
76413839 | 387 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
388 | } |
389 | ||
1da177e4 LT |
390 | /** |
391 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
392 | * @mtd: MTD device structure |
393 | * @buf: data buffer | |
394 | * @len: number of bytes to write | |
1da177e4 | 395 | * |
7854d3f7 | 396 | * Default write function for 16bit buswidth. |
1da177e4 | 397 | */ |
58dd8f2b | 398 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 399 | { |
862eba51 | 400 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 401 | u16 *p = (u16 *) buf; |
61b03bd7 | 402 | |
76413839 | 403 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
404 | } |
405 | ||
406 | /** | |
61b03bd7 | 407 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
408 | * @mtd: MTD device structure |
409 | * @buf: buffer to store date | |
410 | * @len: number of bytes to read | |
1da177e4 | 411 | * |
7854d3f7 | 412 | * Default read function for 16bit buswidth. |
1da177e4 | 413 | */ |
58dd8f2b | 414 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 415 | { |
862eba51 | 416 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 417 | u16 *p = (u16 *) buf; |
1da177e4 | 418 | |
76413839 | 419 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
420 | } |
421 | ||
1da177e4 LT |
422 | /** |
423 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
424 | * @mtd: MTD device structure |
425 | * @ofs: offset from device start | |
1da177e4 | 426 | * |
61b03bd7 | 427 | * Check, if the block is bad. |
1da177e4 | 428 | */ |
9f3e0429 | 429 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 430 | { |
c120e75e | 431 | int page, page_end, res; |
862eba51 | 432 | struct nand_chip *chip = mtd_to_nand(mtd); |
c120e75e | 433 | u8 bad; |
1da177e4 | 434 | |
5fb1549d | 435 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
436 | ofs += mtd->erasesize - mtd->writesize; |
437 | ||
1a12f46a | 438 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
c120e75e | 439 | page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1); |
1a12f46a | 440 | |
c120e75e MY |
441 | for (; page < page_end; page++) { |
442 | res = chip->ecc.read_oob(mtd, chip, page); | |
443 | if (res) | |
444 | return res; | |
445 | ||
446 | bad = chip->oob_poi[chip->badblockpos]; | |
cdbec050 BN |
447 | |
448 | if (likely(chip->badblockbits == 8)) | |
449 | res = bad != 0xFF; | |
e0b58d0a | 450 | else |
cdbec050 | 451 | res = hweight8(bad) < chip->badblockbits; |
c120e75e MY |
452 | if (res) |
453 | return res; | |
454 | } | |
e0b58d0a | 455 | |
c120e75e | 456 | return 0; |
1da177e4 LT |
457 | } |
458 | ||
459 | /** | |
5a0edb25 | 460 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
461 | * @mtd: MTD device structure |
462 | * @ofs: offset from device start | |
1da177e4 | 463 | * |
8b6e50c9 | 464 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
465 | * specific driver. It provides the details for writing a bad block marker to a |
466 | * block. | |
467 | */ | |
468 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
469 | { | |
862eba51 | 470 | struct nand_chip *chip = mtd_to_nand(mtd); |
5a0edb25 BN |
471 | struct mtd_oob_ops ops; |
472 | uint8_t buf[2] = { 0, 0 }; | |
473 | int ret = 0, res, i = 0; | |
474 | ||
0ec56dc4 | 475 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
476 | ops.oobbuf = buf; |
477 | ops.ooboffs = chip->badblockpos; | |
478 | if (chip->options & NAND_BUSWIDTH_16) { | |
479 | ops.ooboffs &= ~0x01; | |
480 | ops.len = ops.ooblen = 2; | |
481 | } else { | |
482 | ops.len = ops.ooblen = 1; | |
483 | } | |
484 | ops.mode = MTD_OPS_PLACE_OOB; | |
485 | ||
486 | /* Write to first/last page(s) if necessary */ | |
487 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
488 | ofs += mtd->erasesize - mtd->writesize; | |
489 | do { | |
490 | res = nand_do_write_oob(mtd, ofs, &ops); | |
491 | if (!ret) | |
492 | ret = res; | |
493 | ||
494 | i++; | |
495 | ofs += mtd->writesize; | |
496 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | /** | |
502 | * nand_block_markbad_lowlevel - mark a block bad | |
503 | * @mtd: MTD device structure | |
504 | * @ofs: offset from device start | |
505 | * | |
506 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
507 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
508 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
509 | * | |
b32843b7 | 510 | * We try operations in the following order: |
b6f6c294 | 511 | * |
e2414f4c | 512 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
513 | * (2) write bad block marker to OOB area of affected block (unless flag |
514 | * NAND_BBT_NO_OOB_BBM is present) | |
515 | * (3) update the BBT | |
b6f6c294 | 516 | * |
b32843b7 | 517 | * Note that we retain the first error encountered in (2) or (3), finish the |
e2414f4c | 518 | * procedures, and dump the error in the end. |
1da177e4 | 519 | */ |
5a0edb25 | 520 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 521 | { |
862eba51 | 522 | struct nand_chip *chip = mtd_to_nand(mtd); |
b32843b7 | 523 | int res, ret = 0; |
61b03bd7 | 524 | |
b32843b7 | 525 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
526 | struct erase_info einfo; |
527 | ||
528 | /* Attempt erase before marking OOB */ | |
529 | memset(&einfo, 0, sizeof(einfo)); | |
530 | einfo.mtd = mtd; | |
531 | einfo.addr = ofs; | |
daae74ca | 532 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 533 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 534 | |
b32843b7 | 535 | /* Write bad block marker to OOB */ |
6a8214aa | 536 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 537 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 538 | nand_release_device(mtd); |
f1a28c02 | 539 | } |
e2414f4c | 540 | |
b32843b7 BN |
541 | /* Mark block bad in BBT */ |
542 | if (chip->bbt) { | |
543 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
544 | if (!ret) |
545 | ret = res; | |
546 | } | |
547 | ||
f1a28c02 TG |
548 | if (!ret) |
549 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 550 | |
f1a28c02 | 551 | return ret; |
1da177e4 LT |
552 | } |
553 | ||
61b03bd7 | 554 | /** |
1da177e4 | 555 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 556 | * @mtd: MTD device structure |
1da177e4 | 557 | * |
8b6e50c9 BN |
558 | * Check, if the device is write protected. The function expects, that the |
559 | * device is already selected. | |
1da177e4 | 560 | */ |
e0c7d767 | 561 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 562 | { |
862eba51 | 563 | struct nand_chip *chip = mtd_to_nand(mtd); |
97d90da8 BB |
564 | u8 status; |
565 | int ret; | |
93edbad6 | 566 | |
8b6e50c9 | 567 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
568 | if (chip->options & NAND_BROKEN_XD) |
569 | return 0; | |
570 | ||
1da177e4 | 571 | /* Check the WP bit */ |
97d90da8 BB |
572 | ret = nand_status_op(chip, &status); |
573 | if (ret) | |
574 | return ret; | |
575 | ||
576 | return status & NAND_STATUS_WP ? 0 : 1; | |
1da177e4 LT |
577 | } |
578 | ||
8471bb73 | 579 | /** |
c30e1f79 | 580 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
581 | * @mtd: MTD device structure |
582 | * @ofs: offset from device start | |
583 | * | |
c30e1f79 | 584 | * Check if the block is marked as reserved. |
8471bb73 EG |
585 | */ |
586 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
587 | { | |
862eba51 | 588 | struct nand_chip *chip = mtd_to_nand(mtd); |
8471bb73 EG |
589 | |
590 | if (!chip->bbt) | |
591 | return 0; | |
592 | /* Return info from the table */ | |
593 | return nand_isreserved_bbt(mtd, ofs); | |
594 | } | |
595 | ||
1da177e4 LT |
596 | /** |
597 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
598 | * @mtd: MTD device structure |
599 | * @ofs: offset from device start | |
8b6e50c9 | 600 | * @allowbbt: 1, if its allowed to access the bbt area |
1da177e4 LT |
601 | * |
602 | * Check, if the block is bad. Either by reading the bad block table or | |
603 | * calling of the scan function. | |
604 | */ | |
9f3e0429 | 605 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) |
1da177e4 | 606 | { |
862eba51 | 607 | struct nand_chip *chip = mtd_to_nand(mtd); |
61b03bd7 | 608 | |
ace4dfee | 609 | if (!chip->bbt) |
9f3e0429 | 610 | return chip->block_bad(mtd, ofs); |
61b03bd7 | 611 | |
1da177e4 | 612 | /* Return info from the table */ |
e0c7d767 | 613 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
614 | } |
615 | ||
2af7c653 SK |
616 | /** |
617 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
618 | * @mtd: MTD device structure |
619 | * @timeo: Timeout | |
2af7c653 SK |
620 | * |
621 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
622 | * context. | |
623 | */ | |
624 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
625 | { | |
862eba51 | 626 | struct nand_chip *chip = mtd_to_nand(mtd); |
2af7c653 SK |
627 | int i; |
628 | ||
629 | /* Wait for the device to get ready */ | |
630 | for (i = 0; i < timeo; i++) { | |
631 | if (chip->dev_ready(mtd)) | |
632 | break; | |
633 | touch_softlockup_watchdog(); | |
634 | mdelay(1); | |
635 | } | |
636 | } | |
637 | ||
b70af9be AS |
638 | /** |
639 | * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
640 | * @mtd: MTD device structure | |
641 | * | |
642 | * Wait for the ready pin after a command, and warn if a timeout occurs. | |
643 | */ | |
4b648b02 | 644 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 645 | { |
862eba51 | 646 | struct nand_chip *chip = mtd_to_nand(mtd); |
b70af9be | 647 | unsigned long timeo = 400; |
3b88775c | 648 | |
2af7c653 | 649 | if (in_interrupt() || oops_in_progress) |
b70af9be | 650 | return panic_nand_wait_ready(mtd, timeo); |
2af7c653 | 651 | |
7854d3f7 | 652 | /* Wait until command is processed or timeout occurs */ |
b70af9be | 653 | timeo = jiffies + msecs_to_jiffies(timeo); |
3b88775c | 654 | do { |
ace4dfee | 655 | if (chip->dev_ready(mtd)) |
4c7e054f | 656 | return; |
b70af9be | 657 | cond_resched(); |
61b03bd7 | 658 | } while (time_before(jiffies, timeo)); |
b70af9be | 659 | |
9ebfdf5b BN |
660 | if (!chip->dev_ready(mtd)) |
661 | pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); | |
3b88775c | 662 | } |
4b648b02 | 663 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 664 | |
60c70d66 RQ |
665 | /** |
666 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
667 | * @mtd: MTD device structure | |
668 | * @timeo: Timeout in ms | |
669 | * | |
670 | * Wait for status ready (i.e. command done) or timeout. | |
671 | */ | |
672 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
673 | { | |
862eba51 | 674 | register struct nand_chip *chip = mtd_to_nand(mtd); |
97d90da8 | 675 | int ret; |
60c70d66 RQ |
676 | |
677 | timeo = jiffies + msecs_to_jiffies(timeo); | |
678 | do { | |
97d90da8 BB |
679 | u8 status; |
680 | ||
681 | ret = nand_read_data_op(chip, &status, sizeof(status), true); | |
682 | if (ret) | |
683 | return; | |
684 | ||
685 | if (status & NAND_STATUS_READY) | |
60c70d66 RQ |
686 | break; |
687 | touch_softlockup_watchdog(); | |
688 | } while (time_before(jiffies, timeo)); | |
689 | }; | |
690 | ||
8878b126 MR |
691 | /** |
692 | * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1 | |
693 | * @chip: NAND chip structure | |
694 | * @timeout_ms: Timeout in ms | |
695 | * | |
696 | * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1. | |
697 | * If that does not happen whitin the specified timeout, -ETIMEDOUT is | |
698 | * returned. | |
699 | * | |
700 | * This helper is intended to be used when the controller does not have access | |
701 | * to the NAND R/B pin. | |
702 | * | |
703 | * Be aware that calling this helper from an ->exec_op() implementation means | |
704 | * ->exec_op() must be re-entrant. | |
705 | * | |
706 | * Return 0 if the NAND chip is ready, a negative error otherwise. | |
707 | */ | |
708 | int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms) | |
709 | { | |
710 | u8 status = 0; | |
711 | int ret; | |
712 | ||
713 | if (!chip->exec_op) | |
714 | return -ENOTSUPP; | |
715 | ||
716 | ret = nand_status_op(chip, NULL); | |
717 | if (ret) | |
718 | return ret; | |
719 | ||
720 | timeout_ms = jiffies + msecs_to_jiffies(timeout_ms); | |
721 | do { | |
722 | ret = nand_read_data_op(chip, &status, sizeof(status), true); | |
723 | if (ret) | |
724 | break; | |
725 | ||
726 | if (status & NAND_STATUS_READY) | |
727 | break; | |
728 | ||
729 | /* | |
730 | * Typical lowest execution time for a tR on most NANDs is 10us, | |
731 | * use this as polling delay before doing something smarter (ie. | |
732 | * deriving a delay from the timeout value, timeout_ms/ratio). | |
733 | */ | |
734 | udelay(10); | |
735 | } while (time_before(jiffies, timeout_ms)); | |
736 | ||
737 | /* | |
738 | * We have to exit READ_STATUS mode in order to read real data on the | |
739 | * bus in case the WAITRDY instruction is preceding a DATA_IN | |
740 | * instruction. | |
741 | */ | |
742 | nand_exit_status_op(chip); | |
743 | ||
744 | if (ret) | |
745 | return ret; | |
746 | ||
747 | return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT; | |
748 | }; | |
749 | EXPORT_SYMBOL_GPL(nand_soft_waitrdy); | |
750 | ||
1da177e4 LT |
751 | /** |
752 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
753 | * @mtd: MTD device structure |
754 | * @command: the command to be sent | |
755 | * @column: the column address for this command, -1 if none | |
756 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 757 | * |
8b6e50c9 | 758 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 759 | * (512 Bytes per page). |
1da177e4 | 760 | */ |
7abd3ef9 TG |
761 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
762 | int column, int page_addr) | |
1da177e4 | 763 | { |
862eba51 | 764 | register struct nand_chip *chip = mtd_to_nand(mtd); |
7abd3ef9 | 765 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 766 | |
8b6e50c9 | 767 | /* Write out the command to the device */ |
1da177e4 LT |
768 | if (command == NAND_CMD_SEQIN) { |
769 | int readcmd; | |
770 | ||
28318776 | 771 | if (column >= mtd->writesize) { |
1da177e4 | 772 | /* OOB area */ |
28318776 | 773 | column -= mtd->writesize; |
1da177e4 LT |
774 | readcmd = NAND_CMD_READOOB; |
775 | } else if (column < 256) { | |
776 | /* First 256 bytes --> READ0 */ | |
777 | readcmd = NAND_CMD_READ0; | |
778 | } else { | |
779 | column -= 256; | |
780 | readcmd = NAND_CMD_READ1; | |
781 | } | |
ace4dfee | 782 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 783 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 784 | } |
df467899 MR |
785 | if (command != NAND_CMD_NONE) |
786 | chip->cmd_ctrl(mtd, command, ctrl); | |
1da177e4 | 787 | |
8b6e50c9 | 788 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
789 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
790 | /* Serially input address */ | |
791 | if (column != -1) { | |
792 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
793 | if (chip->options & NAND_BUSWIDTH_16 && |
794 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 795 | column >>= 1; |
ace4dfee | 796 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
797 | ctrl &= ~NAND_CTRL_CHANGE; |
798 | } | |
799 | if (page_addr != -1) { | |
ace4dfee | 800 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 801 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 802 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
14157f86 | 803 | if (chip->options & NAND_ROW_ADDR_3) |
ace4dfee | 804 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); |
1da177e4 | 805 | } |
ace4dfee | 806 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
807 | |
808 | /* | |
8b6e50c9 BN |
809 | * Program and erase have their own busy handlers status and sequential |
810 | * in needs no delay | |
e0c7d767 | 811 | */ |
1da177e4 | 812 | switch (command) { |
61b03bd7 | 813 | |
df467899 | 814 | case NAND_CMD_NONE: |
1da177e4 LT |
815 | case NAND_CMD_PAGEPROG: |
816 | case NAND_CMD_ERASE1: | |
817 | case NAND_CMD_ERASE2: | |
818 | case NAND_CMD_SEQIN: | |
819 | case NAND_CMD_STATUS: | |
3158fa0e | 820 | case NAND_CMD_READID: |
c5d664aa | 821 | case NAND_CMD_SET_FEATURES: |
1da177e4 LT |
822 | return; |
823 | ||
824 | case NAND_CMD_RESET: | |
ace4dfee | 825 | if (chip->dev_ready) |
1da177e4 | 826 | break; |
ace4dfee TG |
827 | udelay(chip->chip_delay); |
828 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 829 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
830 | chip->cmd_ctrl(mtd, |
831 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
832 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
833 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
834 | return; |
835 | ||
e0c7d767 | 836 | /* This applies to read commands */ |
2165c4a1 BB |
837 | case NAND_CMD_READ0: |
838 | /* | |
839 | * READ0 is sometimes used to exit GET STATUS mode. When this | |
840 | * is the case no address cycles are requested, and we can use | |
841 | * this information to detect that we should not wait for the | |
842 | * device to be ready. | |
843 | */ | |
844 | if (column == -1 && page_addr == -1) | |
845 | return; | |
846 | ||
1da177e4 | 847 | default: |
61b03bd7 | 848 | /* |
1da177e4 LT |
849 | * If we don't have access to the busy pin, we apply the given |
850 | * command delay | |
e0c7d767 | 851 | */ |
ace4dfee TG |
852 | if (!chip->dev_ready) { |
853 | udelay(chip->chip_delay); | |
1da177e4 | 854 | return; |
61b03bd7 | 855 | } |
1da177e4 | 856 | } |
8b6e50c9 BN |
857 | /* |
858 | * Apply this short delay always to ensure that we do wait tWB in | |
859 | * any case on any machine. | |
860 | */ | |
e0c7d767 | 861 | ndelay(100); |
3b88775c TG |
862 | |
863 | nand_wait_ready(mtd); | |
1da177e4 LT |
864 | } |
865 | ||
6ea40a3b BB |
866 | static void nand_ccs_delay(struct nand_chip *chip) |
867 | { | |
868 | /* | |
869 | * The controller already takes care of waiting for tCCS when the RNDIN | |
870 | * or RNDOUT command is sent, return directly. | |
871 | */ | |
872 | if (!(chip->options & NAND_WAIT_TCCS)) | |
873 | return; | |
874 | ||
875 | /* | |
876 | * Wait tCCS_min if it is correctly defined, otherwise wait 500ns | |
877 | * (which should be safe for all NANDs). | |
878 | */ | |
17fa8044 MR |
879 | if (chip->setup_data_interface) |
880 | ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000); | |
6ea40a3b BB |
881 | else |
882 | ndelay(500); | |
883 | } | |
884 | ||
1da177e4 LT |
885 | /** |
886 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
887 | * @mtd: MTD device structure |
888 | * @command: the command to be sent | |
889 | * @column: the column address for this command, -1 if none | |
890 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 891 | * |
7abd3ef9 | 892 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
893 | * devices. We don't have the separate regions as we have in the small page |
894 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 895 | */ |
7abd3ef9 TG |
896 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
897 | int column, int page_addr) | |
1da177e4 | 898 | { |
862eba51 | 899 | register struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
900 | |
901 | /* Emulate NAND_CMD_READOOB */ | |
902 | if (command == NAND_CMD_READOOB) { | |
28318776 | 903 | column += mtd->writesize; |
1da177e4 LT |
904 | command = NAND_CMD_READ0; |
905 | } | |
61b03bd7 | 906 | |
7abd3ef9 | 907 | /* Command latch cycle */ |
df467899 MR |
908 | if (command != NAND_CMD_NONE) |
909 | chip->cmd_ctrl(mtd, command, | |
910 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
1da177e4 LT |
911 | |
912 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 913 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
914 | |
915 | /* Serially input address */ | |
916 | if (column != -1) { | |
917 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
918 | if (chip->options & NAND_BUSWIDTH_16 && |
919 | !nand_opcode_8bits(command)) | |
1da177e4 | 920 | column >>= 1; |
ace4dfee | 921 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 922 | ctrl &= ~NAND_CTRL_CHANGE; |
fde85cfd | 923 | |
f5b88de2 | 924 | /* Only output a single addr cycle for 8bits opcodes. */ |
fde85cfd BB |
925 | if (!nand_opcode_8bits(command)) |
926 | chip->cmd_ctrl(mtd, column >> 8, ctrl); | |
61b03bd7 | 927 | } |
1da177e4 | 928 | if (page_addr != -1) { |
ace4dfee TG |
929 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
930 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 931 | NAND_NCE | NAND_ALE); |
14157f86 | 932 | if (chip->options & NAND_ROW_ADDR_3) |
ace4dfee | 933 | chip->cmd_ctrl(mtd, page_addr >> 16, |
7abd3ef9 | 934 | NAND_NCE | NAND_ALE); |
1da177e4 | 935 | } |
1da177e4 | 936 | } |
ace4dfee | 937 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
938 | |
939 | /* | |
8b6e50c9 | 940 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 941 | * in and status need no delay. |
30f464b7 | 942 | */ |
1da177e4 | 943 | switch (command) { |
61b03bd7 | 944 | |
df467899 | 945 | case NAND_CMD_NONE: |
1da177e4 LT |
946 | case NAND_CMD_CACHEDPROG: |
947 | case NAND_CMD_PAGEPROG: | |
948 | case NAND_CMD_ERASE1: | |
949 | case NAND_CMD_ERASE2: | |
950 | case NAND_CMD_SEQIN: | |
951 | case NAND_CMD_STATUS: | |
3158fa0e | 952 | case NAND_CMD_READID: |
c5d664aa | 953 | case NAND_CMD_SET_FEATURES: |
30f464b7 | 954 | return; |
1da177e4 | 955 | |
6ea40a3b BB |
956 | case NAND_CMD_RNDIN: |
957 | nand_ccs_delay(chip); | |
958 | return; | |
959 | ||
1da177e4 | 960 | case NAND_CMD_RESET: |
ace4dfee | 961 | if (chip->dev_ready) |
1da177e4 | 962 | break; |
ace4dfee | 963 | udelay(chip->chip_delay); |
12efdde3 TG |
964 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
965 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
966 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
967 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
968 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
969 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
970 | return; |
971 | ||
7bc3312b TG |
972 | case NAND_CMD_RNDOUT: |
973 | /* No ready / busy check necessary */ | |
974 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
975 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
976 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
977 | NAND_NCE | NAND_CTRL_CHANGE); | |
6ea40a3b BB |
978 | |
979 | nand_ccs_delay(chip); | |
7bc3312b TG |
980 | return; |
981 | ||
1da177e4 | 982 | case NAND_CMD_READ0: |
2165c4a1 BB |
983 | /* |
984 | * READ0 is sometimes used to exit GET STATUS mode. When this | |
985 | * is the case no address cycles are requested, and we can use | |
986 | * this information to detect that READSTART should not be | |
987 | * issued. | |
988 | */ | |
989 | if (column == -1 && page_addr == -1) | |
990 | return; | |
991 | ||
12efdde3 TG |
992 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
993 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
994 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
995 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 996 | |
e0c7d767 | 997 | /* This applies to read commands */ |
1da177e4 | 998 | default: |
61b03bd7 | 999 | /* |
1da177e4 | 1000 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 1001 | * command delay. |
e0c7d767 | 1002 | */ |
ace4dfee TG |
1003 | if (!chip->dev_ready) { |
1004 | udelay(chip->chip_delay); | |
1da177e4 | 1005 | return; |
61b03bd7 | 1006 | } |
1da177e4 | 1007 | } |
3b88775c | 1008 | |
8b6e50c9 BN |
1009 | /* |
1010 | * Apply this short delay always to ensure that we do wait tWB in | |
1011 | * any case on any machine. | |
1012 | */ | |
e0c7d767 | 1013 | ndelay(100); |
3b88775c TG |
1014 | |
1015 | nand_wait_ready(mtd); | |
1da177e4 LT |
1016 | } |
1017 | ||
2af7c653 SK |
1018 | /** |
1019 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
1020 | * @chip: the nand chip descriptor |
1021 | * @mtd: MTD device structure | |
1022 | * @new_state: the state which is requested | |
2af7c653 SK |
1023 | * |
1024 | * Used when in panic, no locks are taken. | |
1025 | */ | |
1026 | static void panic_nand_get_device(struct nand_chip *chip, | |
1027 | struct mtd_info *mtd, int new_state) | |
1028 | { | |
7854d3f7 | 1029 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
1030 | chip->controller->active = chip; |
1031 | chip->state = new_state; | |
1032 | } | |
1033 | ||
1da177e4 LT |
1034 | /** |
1035 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
1036 | * @mtd: MTD device structure |
1037 | * @new_state: the state which is requested | |
1da177e4 LT |
1038 | * |
1039 | * Get the device and lock it for exclusive access | |
1040 | */ | |
2c0a2bed | 1041 | static int |
6a8214aa | 1042 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 1043 | { |
862eba51 | 1044 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
1045 | spinlock_t *lock = &chip->controller->lock; |
1046 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 1047 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 1048 | retry: |
0dfc6246 TG |
1049 | spin_lock(lock); |
1050 | ||
b8b3ee9a | 1051 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
1052 | if (!chip->controller->active) |
1053 | chip->controller->active = chip; | |
a36ed299 | 1054 | |
ace4dfee TG |
1055 | if (chip->controller->active == chip && chip->state == FL_READY) { |
1056 | chip->state = new_state; | |
0dfc6246 | 1057 | spin_unlock(lock); |
962034f4 VW |
1058 | return 0; |
1059 | } | |
1060 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
1061 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
1062 | chip->state = FL_PM_SUSPENDED; | |
1063 | spin_unlock(lock); | |
1064 | return 0; | |
6b0d9a84 | 1065 | } |
0dfc6246 TG |
1066 | } |
1067 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1068 | add_wait_queue(wq, &wait); | |
1069 | spin_unlock(lock); | |
1070 | schedule(); | |
1071 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
1072 | goto retry; |
1073 | } | |
1074 | ||
2af7c653 | 1075 | /** |
8b6e50c9 BN |
1076 | * panic_nand_wait - [GENERIC] wait until the command is done |
1077 | * @mtd: MTD device structure | |
1078 | * @chip: NAND chip structure | |
1079 | * @timeo: timeout | |
2af7c653 SK |
1080 | * |
1081 | * Wait for command done. This is a helper function for nand_wait used when | |
1082 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 1083 | * an oops through mtdoops. |
2af7c653 SK |
1084 | */ |
1085 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
1086 | unsigned long timeo) | |
1087 | { | |
1088 | int i; | |
1089 | for (i = 0; i < timeo; i++) { | |
1090 | if (chip->dev_ready) { | |
1091 | if (chip->dev_ready(mtd)) | |
1092 | break; | |
1093 | } else { | |
97d90da8 BB |
1094 | int ret; |
1095 | u8 status; | |
1096 | ||
1097 | ret = nand_read_data_op(chip, &status, sizeof(status), | |
1098 | true); | |
1099 | if (ret) | |
1100 | return; | |
1101 | ||
1102 | if (status & NAND_STATUS_READY) | |
2af7c653 SK |
1103 | break; |
1104 | } | |
1105 | mdelay(1); | |
f8ac0414 | 1106 | } |
2af7c653 SK |
1107 | } |
1108 | ||
1da177e4 | 1109 | /** |
8b6e50c9 BN |
1110 | * nand_wait - [DEFAULT] wait until the command is done |
1111 | * @mtd: MTD device structure | |
1112 | * @chip: NAND chip structure | |
1da177e4 | 1113 | * |
b70af9be | 1114 | * Wait for command done. This applies to erase and program only. |
844d3b42 | 1115 | */ |
7bc3312b | 1116 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
1117 | { |
1118 | ||
b70af9be | 1119 | unsigned long timeo = 400; |
97d90da8 BB |
1120 | u8 status; |
1121 | int ret; | |
1da177e4 | 1122 | |
8b6e50c9 BN |
1123 | /* |
1124 | * Apply this short delay always to ensure that we do wait tWB in any | |
1125 | * case on any machine. | |
1126 | */ | |
e0c7d767 | 1127 | ndelay(100); |
1da177e4 | 1128 | |
97d90da8 BB |
1129 | ret = nand_status_op(chip, NULL); |
1130 | if (ret) | |
1131 | return ret; | |
1da177e4 | 1132 | |
2af7c653 SK |
1133 | if (in_interrupt() || oops_in_progress) |
1134 | panic_nand_wait(mtd, chip, timeo); | |
1135 | else { | |
6d2559f8 | 1136 | timeo = jiffies + msecs_to_jiffies(timeo); |
b70af9be | 1137 | do { |
2af7c653 SK |
1138 | if (chip->dev_ready) { |
1139 | if (chip->dev_ready(mtd)) | |
1140 | break; | |
1141 | } else { | |
97d90da8 BB |
1142 | ret = nand_read_data_op(chip, &status, |
1143 | sizeof(status), true); | |
1144 | if (ret) | |
1145 | return ret; | |
1146 | ||
1147 | if (status & NAND_STATUS_READY) | |
2af7c653 SK |
1148 | break; |
1149 | } | |
1150 | cond_resched(); | |
b70af9be | 1151 | } while (time_before(jiffies, timeo)); |
1da177e4 | 1152 | } |
8fe833c1 | 1153 | |
97d90da8 BB |
1154 | ret = nand_read_data_op(chip, &status, sizeof(status), true); |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
f251b8df MC |
1158 | /* This can happen if in case of timeout or buggy dev_ready */ |
1159 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
1160 | return status; |
1161 | } | |
1162 | ||
d8e725dd BB |
1163 | /** |
1164 | * nand_reset_data_interface - Reset data interface and timings | |
1165 | * @chip: The NAND chip | |
104e442a | 1166 | * @chipnr: Internal die id |
d8e725dd BB |
1167 | * |
1168 | * Reset the Data interface and timings to ONFI mode 0. | |
1169 | * | |
1170 | * Returns 0 for success or negative error code otherwise. | |
1171 | */ | |
104e442a | 1172 | static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) |
d8e725dd BB |
1173 | { |
1174 | struct mtd_info *mtd = nand_to_mtd(chip); | |
d8e725dd BB |
1175 | int ret; |
1176 | ||
1177 | if (!chip->setup_data_interface) | |
1178 | return 0; | |
1179 | ||
1180 | /* | |
1181 | * The ONFI specification says: | |
1182 | * " | |
1183 | * To transition from NV-DDR or NV-DDR2 to the SDR data | |
1184 | * interface, the host shall use the Reset (FFh) command | |
1185 | * using SDR timing mode 0. A device in any timing mode is | |
1186 | * required to recognize Reset (FFh) command issued in SDR | |
1187 | * timing mode 0. | |
1188 | * " | |
1189 | * | |
1190 | * Configure the data interface in SDR mode and set the | |
1191 | * timings to timing mode 0. | |
1192 | */ | |
1193 | ||
17fa8044 MR |
1194 | onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0); |
1195 | ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface); | |
d8e725dd BB |
1196 | if (ret) |
1197 | pr_err("Failed to configure data interface to SDR timing mode 0\n"); | |
1198 | ||
1199 | return ret; | |
1200 | } | |
1201 | ||
1202 | /** | |
1203 | * nand_setup_data_interface - Setup the best data interface and timings | |
1204 | * @chip: The NAND chip | |
104e442a | 1205 | * @chipnr: Internal die id |
d8e725dd BB |
1206 | * |
1207 | * Find and configure the best data interface and NAND timings supported by | |
1208 | * the chip and the driver. | |
1209 | * First tries to retrieve supported timing modes from ONFI information, | |
1210 | * and if the NAND chip does not support ONFI, relies on the | |
1211 | * ->onfi_timing_mode_default specified in the nand_ids table. | |
1212 | * | |
1213 | * Returns 0 for success or negative error code otherwise. | |
1214 | */ | |
104e442a | 1215 | static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) |
d8e725dd BB |
1216 | { |
1217 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1218 | int ret; | |
1219 | ||
17fa8044 | 1220 | if (!chip->setup_data_interface) |
d8e725dd BB |
1221 | return 0; |
1222 | ||
1223 | /* | |
1224 | * Ensure the timing mode has been changed on the chip side | |
1225 | * before changing timings on the controller side. | |
1226 | */ | |
a11bf5ed BB |
1227 | if (chip->onfi_version && |
1228 | (le16_to_cpu(chip->onfi_params.opt_cmd) & | |
1229 | ONFI_OPT_CMD_SET_GET_FEATURES)) { | |
d8e725dd BB |
1230 | u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { |
1231 | chip->onfi_timing_mode_default, | |
1232 | }; | |
1233 | ||
1234 | ret = chip->onfi_set_features(mtd, chip, | |
1235 | ONFI_FEATURE_ADDR_TIMING_MODE, | |
1236 | tmode_param); | |
1237 | if (ret) | |
1238 | goto err; | |
1239 | } | |
1240 | ||
17fa8044 | 1241 | ret = chip->setup_data_interface(mtd, chipnr, &chip->data_interface); |
d8e725dd BB |
1242 | err: |
1243 | return ret; | |
1244 | } | |
1245 | ||
1246 | /** | |
1247 | * nand_init_data_interface - find the best data interface and timings | |
1248 | * @chip: The NAND chip | |
1249 | * | |
1250 | * Find the best data interface and NAND timings supported by the chip | |
1251 | * and the driver. | |
1252 | * First tries to retrieve supported timing modes from ONFI information, | |
1253 | * and if the NAND chip does not support ONFI, relies on the | |
1254 | * ->onfi_timing_mode_default specified in the nand_ids table. After this | |
1255 | * function nand_chip->data_interface is initialized with the best timing mode | |
1256 | * available. | |
1257 | * | |
1258 | * Returns 0 for success or negative error code otherwise. | |
1259 | */ | |
1260 | static int nand_init_data_interface(struct nand_chip *chip) | |
1261 | { | |
1262 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1263 | int modes, mode, ret; | |
1264 | ||
1265 | if (!chip->setup_data_interface) | |
1266 | return 0; | |
1267 | ||
1268 | /* | |
1269 | * First try to identify the best timings from ONFI parameters and | |
1270 | * if the NAND does not support ONFI, fallback to the default ONFI | |
1271 | * timing mode. | |
1272 | */ | |
1273 | modes = onfi_get_async_timing_mode(chip); | |
1274 | if (modes == ONFI_TIMING_MODE_UNKNOWN) { | |
1275 | if (!chip->onfi_timing_mode_default) | |
1276 | return 0; | |
1277 | ||
1278 | modes = GENMASK(chip->onfi_timing_mode_default, 0); | |
1279 | } | |
1280 | ||
d8e725dd BB |
1281 | |
1282 | for (mode = fls(modes) - 1; mode >= 0; mode--) { | |
17fa8044 | 1283 | ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode); |
d8e725dd BB |
1284 | if (ret) |
1285 | continue; | |
1286 | ||
d787b8b3 MR |
1287 | /* |
1288 | * Pass NAND_DATA_IFACE_CHECK_ONLY to only check if the | |
1289 | * controller supports the requested timings. | |
1290 | */ | |
104e442a BB |
1291 | ret = chip->setup_data_interface(mtd, |
1292 | NAND_DATA_IFACE_CHECK_ONLY, | |
17fa8044 | 1293 | &chip->data_interface); |
d8e725dd BB |
1294 | if (!ret) { |
1295 | chip->onfi_timing_mode_default = mode; | |
1296 | break; | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | return 0; | |
1301 | } | |
1302 | ||
8878b126 MR |
1303 | /** |
1304 | * nand_fill_column_cycles - fill the column cycles of an address | |
1305 | * @chip: The NAND chip | |
1306 | * @addrs: Array of address cycles to fill | |
1307 | * @offset_in_page: The offset in the page | |
1308 | * | |
1309 | * Fills the first or the first two bytes of the @addrs field depending | |
1310 | * on the NAND bus width and the page size. | |
1311 | * | |
1312 | * Returns the number of cycles needed to encode the column, or a negative | |
1313 | * error code in case one of the arguments is invalid. | |
1314 | */ | |
1315 | static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs, | |
1316 | unsigned int offset_in_page) | |
1317 | { | |
1318 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1319 | ||
1320 | /* Make sure the offset is less than the actual page size. */ | |
1321 | if (offset_in_page > mtd->writesize + mtd->oobsize) | |
1322 | return -EINVAL; | |
1323 | ||
1324 | /* | |
1325 | * On small page NANDs, there's a dedicated command to access the OOB | |
1326 | * area, and the column address is relative to the start of the OOB | |
1327 | * area, not the start of the page. Asjust the address accordingly. | |
1328 | */ | |
1329 | if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) | |
1330 | offset_in_page -= mtd->writesize; | |
1331 | ||
1332 | /* | |
1333 | * The offset in page is expressed in bytes, if the NAND bus is 16-bit | |
1334 | * wide, then it must be divided by 2. | |
1335 | */ | |
1336 | if (chip->options & NAND_BUSWIDTH_16) { | |
1337 | if (WARN_ON(offset_in_page % 2)) | |
1338 | return -EINVAL; | |
1339 | ||
1340 | offset_in_page /= 2; | |
1341 | } | |
1342 | ||
1343 | addrs[0] = offset_in_page; | |
1344 | ||
1345 | /* | |
1346 | * Small page NANDs use 1 cycle for the columns, while large page NANDs | |
1347 | * need 2 | |
1348 | */ | |
1349 | if (mtd->writesize <= 512) | |
1350 | return 1; | |
1351 | ||
1352 | addrs[1] = offset_in_page >> 8; | |
1353 | ||
1354 | return 2; | |
1355 | } | |
1356 | ||
1357 | static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page, | |
1358 | unsigned int offset_in_page, void *buf, | |
1359 | unsigned int len) | |
1360 | { | |
1361 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1362 | const struct nand_sdr_timings *sdr = | |
1363 | nand_get_sdr_timings(&chip->data_interface); | |
1364 | u8 addrs[4]; | |
1365 | struct nand_op_instr instrs[] = { | |
1366 | NAND_OP_CMD(NAND_CMD_READ0, 0), | |
1367 | NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)), | |
1368 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max), | |
1369 | PSEC_TO_NSEC(sdr->tRR_min)), | |
1370 | NAND_OP_DATA_IN(len, buf, 0), | |
1371 | }; | |
1372 | struct nand_operation op = NAND_OPERATION(instrs); | |
1373 | int ret; | |
1374 | ||
1375 | /* Drop the DATA_IN instruction if len is set to 0. */ | |
1376 | if (!len) | |
1377 | op.ninstrs--; | |
1378 | ||
1379 | if (offset_in_page >= mtd->writesize) | |
1380 | instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; | |
1381 | else if (offset_in_page >= 256 && | |
1382 | !(chip->options & NAND_BUSWIDTH_16)) | |
1383 | instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; | |
1384 | ||
1385 | ret = nand_fill_column_cycles(chip, addrs, offset_in_page); | |
1386 | if (ret < 0) | |
1387 | return ret; | |
1388 | ||
1389 | addrs[1] = page; | |
1390 | addrs[2] = page >> 8; | |
1391 | ||
1392 | if (chip->options & NAND_ROW_ADDR_3) { | |
1393 | addrs[3] = page >> 16; | |
1394 | instrs[1].ctx.addr.naddrs++; | |
1395 | } | |
1396 | ||
1397 | return nand_exec_op(chip, &op); | |
1398 | } | |
1399 | ||
1400 | static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page, | |
1401 | unsigned int offset_in_page, void *buf, | |
1402 | unsigned int len) | |
1403 | { | |
1404 | const struct nand_sdr_timings *sdr = | |
1405 | nand_get_sdr_timings(&chip->data_interface); | |
1406 | u8 addrs[5]; | |
1407 | struct nand_op_instr instrs[] = { | |
1408 | NAND_OP_CMD(NAND_CMD_READ0, 0), | |
1409 | NAND_OP_ADDR(4, addrs, 0), | |
1410 | NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)), | |
1411 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max), | |
1412 | PSEC_TO_NSEC(sdr->tRR_min)), | |
1413 | NAND_OP_DATA_IN(len, buf, 0), | |
1414 | }; | |
1415 | struct nand_operation op = NAND_OPERATION(instrs); | |
1416 | int ret; | |
1417 | ||
1418 | /* Drop the DATA_IN instruction if len is set to 0. */ | |
1419 | if (!len) | |
1420 | op.ninstrs--; | |
1421 | ||
1422 | ret = nand_fill_column_cycles(chip, addrs, offset_in_page); | |
1423 | if (ret < 0) | |
1424 | return ret; | |
1425 | ||
1426 | addrs[2] = page; | |
1427 | addrs[3] = page >> 8; | |
1428 | ||
1429 | if (chip->options & NAND_ROW_ADDR_3) { | |
1430 | addrs[4] = page >> 16; | |
1431 | instrs[1].ctx.addr.naddrs++; | |
1432 | } | |
1433 | ||
1434 | return nand_exec_op(chip, &op); | |
1435 | } | |
1436 | ||
97d90da8 BB |
1437 | /** |
1438 | * nand_read_page_op - Do a READ PAGE operation | |
1439 | * @chip: The NAND chip | |
1440 | * @page: page to read | |
1441 | * @offset_in_page: offset within the page | |
1442 | * @buf: buffer used to store the data | |
1443 | * @len: length of the buffer | |
1444 | * | |
1445 | * This function issues a READ PAGE operation. | |
1446 | * This function does not select/unselect the CS line. | |
1447 | * | |
1448 | * Returns 0 on success, a negative error code otherwise. | |
1449 | */ | |
1450 | int nand_read_page_op(struct nand_chip *chip, unsigned int page, | |
1451 | unsigned int offset_in_page, void *buf, unsigned int len) | |
1452 | { | |
1453 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1454 | ||
1455 | if (len && !buf) | |
1456 | return -EINVAL; | |
1457 | ||
1458 | if (offset_in_page + len > mtd->writesize + mtd->oobsize) | |
1459 | return -EINVAL; | |
1460 | ||
8878b126 MR |
1461 | if (chip->exec_op) { |
1462 | if (mtd->writesize > 512) | |
1463 | return nand_lp_exec_read_page_op(chip, page, | |
1464 | offset_in_page, buf, | |
1465 | len); | |
1466 | ||
1467 | return nand_sp_exec_read_page_op(chip, page, offset_in_page, | |
1468 | buf, len); | |
1469 | } | |
1470 | ||
97d90da8 BB |
1471 | chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page); |
1472 | if (len) | |
1473 | chip->read_buf(mtd, buf, len); | |
1474 | ||
1475 | return 0; | |
1476 | } | |
1477 | EXPORT_SYMBOL_GPL(nand_read_page_op); | |
1478 | ||
1479 | /** | |
1480 | * nand_read_param_page_op - Do a READ PARAMETER PAGE operation | |
1481 | * @chip: The NAND chip | |
1482 | * @page: parameter page to read | |
1483 | * @buf: buffer used to store the data | |
1484 | * @len: length of the buffer | |
1485 | * | |
1486 | * This function issues a READ PARAMETER PAGE operation. | |
1487 | * This function does not select/unselect the CS line. | |
1488 | * | |
1489 | * Returns 0 on success, a negative error code otherwise. | |
1490 | */ | |
1491 | static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf, | |
1492 | unsigned int len) | |
1493 | { | |
1494 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1495 | unsigned int i; | |
1496 | u8 *p = buf; | |
1497 | ||
1498 | if (len && !buf) | |
1499 | return -EINVAL; | |
1500 | ||
8878b126 MR |
1501 | if (chip->exec_op) { |
1502 | const struct nand_sdr_timings *sdr = | |
1503 | nand_get_sdr_timings(&chip->data_interface); | |
1504 | struct nand_op_instr instrs[] = { | |
1505 | NAND_OP_CMD(NAND_CMD_PARAM, 0), | |
1506 | NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)), | |
1507 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max), | |
1508 | PSEC_TO_NSEC(sdr->tRR_min)), | |
1509 | NAND_OP_8BIT_DATA_IN(len, buf, 0), | |
1510 | }; | |
1511 | struct nand_operation op = NAND_OPERATION(instrs); | |
1512 | ||
1513 | /* Drop the DATA_IN instruction if len is set to 0. */ | |
1514 | if (!len) | |
1515 | op.ninstrs--; | |
1516 | ||
1517 | return nand_exec_op(chip, &op); | |
1518 | } | |
1519 | ||
97d90da8 BB |
1520 | chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1); |
1521 | for (i = 0; i < len; i++) | |
1522 | p[i] = chip->read_byte(mtd); | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | /** | |
1528 | * nand_change_read_column_op - Do a CHANGE READ COLUMN operation | |
1529 | * @chip: The NAND chip | |
1530 | * @offset_in_page: offset within the page | |
1531 | * @buf: buffer used to store the data | |
1532 | * @len: length of the buffer | |
1533 | * @force_8bit: force 8-bit bus access | |
1534 | * | |
1535 | * This function issues a CHANGE READ COLUMN operation. | |
1536 | * This function does not select/unselect the CS line. | |
1537 | * | |
1538 | * Returns 0 on success, a negative error code otherwise. | |
1539 | */ | |
1540 | int nand_change_read_column_op(struct nand_chip *chip, | |
1541 | unsigned int offset_in_page, void *buf, | |
1542 | unsigned int len, bool force_8bit) | |
1543 | { | |
1544 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1545 | ||
1546 | if (len && !buf) | |
1547 | return -EINVAL; | |
1548 | ||
1549 | if (offset_in_page + len > mtd->writesize + mtd->oobsize) | |
1550 | return -EINVAL; | |
1551 | ||
8878b126 MR |
1552 | /* Small page NANDs do not support column change. */ |
1553 | if (mtd->writesize <= 512) | |
1554 | return -ENOTSUPP; | |
1555 | ||
1556 | if (chip->exec_op) { | |
1557 | const struct nand_sdr_timings *sdr = | |
1558 | nand_get_sdr_timings(&chip->data_interface); | |
1559 | u8 addrs[2] = {}; | |
1560 | struct nand_op_instr instrs[] = { | |
1561 | NAND_OP_CMD(NAND_CMD_RNDOUT, 0), | |
1562 | NAND_OP_ADDR(2, addrs, 0), | |
1563 | NAND_OP_CMD(NAND_CMD_RNDOUTSTART, | |
1564 | PSEC_TO_NSEC(sdr->tCCS_min)), | |
1565 | NAND_OP_DATA_IN(len, buf, 0), | |
1566 | }; | |
1567 | struct nand_operation op = NAND_OPERATION(instrs); | |
1568 | int ret; | |
1569 | ||
1570 | ret = nand_fill_column_cycles(chip, addrs, offset_in_page); | |
1571 | if (ret < 0) | |
1572 | return ret; | |
1573 | ||
1574 | /* Drop the DATA_IN instruction if len is set to 0. */ | |
1575 | if (!len) | |
1576 | op.ninstrs--; | |
1577 | ||
1578 | instrs[3].ctx.data.force_8bit = force_8bit; | |
1579 | ||
1580 | return nand_exec_op(chip, &op); | |
1581 | } | |
1582 | ||
97d90da8 BB |
1583 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1); |
1584 | if (len) | |
1585 | chip->read_buf(mtd, buf, len); | |
1586 | ||
1587 | return 0; | |
1588 | } | |
1589 | EXPORT_SYMBOL_GPL(nand_change_read_column_op); | |
1590 | ||
1591 | /** | |
1592 | * nand_read_oob_op - Do a READ OOB operation | |
1593 | * @chip: The NAND chip | |
1594 | * @page: page to read | |
1595 | * @offset_in_oob: offset within the OOB area | |
1596 | * @buf: buffer used to store the data | |
1597 | * @len: length of the buffer | |
1598 | * | |
1599 | * This function issues a READ OOB operation. | |
1600 | * This function does not select/unselect the CS line. | |
1601 | * | |
1602 | * Returns 0 on success, a negative error code otherwise. | |
1603 | */ | |
1604 | int nand_read_oob_op(struct nand_chip *chip, unsigned int page, | |
1605 | unsigned int offset_in_oob, void *buf, unsigned int len) | |
1606 | { | |
1607 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1608 | ||
1609 | if (len && !buf) | |
1610 | return -EINVAL; | |
1611 | ||
1612 | if (offset_in_oob + len > mtd->oobsize) | |
1613 | return -EINVAL; | |
1614 | ||
8878b126 MR |
1615 | if (chip->exec_op) |
1616 | return nand_read_page_op(chip, page, | |
1617 | mtd->writesize + offset_in_oob, | |
1618 | buf, len); | |
1619 | ||
97d90da8 BB |
1620 | chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page); |
1621 | if (len) | |
1622 | chip->read_buf(mtd, buf, len); | |
1623 | ||
1624 | return 0; | |
1625 | } | |
1626 | EXPORT_SYMBOL_GPL(nand_read_oob_op); | |
1627 | ||
8878b126 MR |
1628 | static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page, |
1629 | unsigned int offset_in_page, const void *buf, | |
1630 | unsigned int len, bool prog) | |
1631 | { | |
1632 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1633 | const struct nand_sdr_timings *sdr = | |
1634 | nand_get_sdr_timings(&chip->data_interface); | |
1635 | u8 addrs[5] = {}; | |
1636 | struct nand_op_instr instrs[] = { | |
1637 | /* | |
1638 | * The first instruction will be dropped if we're dealing | |
1639 | * with a large page NAND and adjusted if we're dealing | |
1640 | * with a small page NAND and the page offset is > 255. | |
1641 | */ | |
1642 | NAND_OP_CMD(NAND_CMD_READ0, 0), | |
1643 | NAND_OP_CMD(NAND_CMD_SEQIN, 0), | |
1644 | NAND_OP_ADDR(0, addrs, PSEC_TO_NSEC(sdr->tADL_min)), | |
1645 | NAND_OP_DATA_OUT(len, buf, 0), | |
1646 | NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)), | |
1647 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0), | |
1648 | }; | |
1649 | struct nand_operation op = NAND_OPERATION(instrs); | |
1650 | int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page); | |
1651 | int ret; | |
1652 | u8 status; | |
1653 | ||
1654 | if (naddrs < 0) | |
1655 | return naddrs; | |
1656 | ||
1657 | addrs[naddrs++] = page; | |
1658 | addrs[naddrs++] = page >> 8; | |
1659 | if (chip->options & NAND_ROW_ADDR_3) | |
1660 | addrs[naddrs++] = page >> 16; | |
1661 | ||
1662 | instrs[2].ctx.addr.naddrs = naddrs; | |
1663 | ||
1664 | /* Drop the last two instructions if we're not programming the page. */ | |
1665 | if (!prog) { | |
1666 | op.ninstrs -= 2; | |
1667 | /* Also drop the DATA_OUT instruction if empty. */ | |
1668 | if (!len) | |
1669 | op.ninstrs--; | |
1670 | } | |
1671 | ||
1672 | if (mtd->writesize <= 512) { | |
1673 | /* | |
1674 | * Small pages need some more tweaking: we have to adjust the | |
1675 | * first instruction depending on the page offset we're trying | |
1676 | * to access. | |
1677 | */ | |
1678 | if (offset_in_page >= mtd->writesize) | |
1679 | instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; | |
1680 | else if (offset_in_page >= 256 && | |
1681 | !(chip->options & NAND_BUSWIDTH_16)) | |
1682 | instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; | |
1683 | } else { | |
1684 | /* | |
1685 | * Drop the first command if we're dealing with a large page | |
1686 | * NAND. | |
1687 | */ | |
1688 | op.instrs++; | |
1689 | op.ninstrs--; | |
1690 | } | |
1691 | ||
1692 | ret = nand_exec_op(chip, &op); | |
1693 | if (!prog || ret) | |
1694 | return ret; | |
1695 | ||
1696 | ret = nand_status_op(chip, &status); | |
1697 | if (ret) | |
1698 | return ret; | |
1699 | ||
1700 | return status; | |
1701 | } | |
1702 | ||
97d90da8 BB |
1703 | /** |
1704 | * nand_prog_page_begin_op - starts a PROG PAGE operation | |
1705 | * @chip: The NAND chip | |
1706 | * @page: page to write | |
1707 | * @offset_in_page: offset within the page | |
1708 | * @buf: buffer containing the data to write to the page | |
1709 | * @len: length of the buffer | |
1710 | * | |
1711 | * This function issues the first half of a PROG PAGE operation. | |
1712 | * This function does not select/unselect the CS line. | |
1713 | * | |
1714 | * Returns 0 on success, a negative error code otherwise. | |
1715 | */ | |
1716 | int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, | |
1717 | unsigned int offset_in_page, const void *buf, | |
1718 | unsigned int len) | |
1719 | { | |
1720 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1721 | ||
1722 | if (len && !buf) | |
1723 | return -EINVAL; | |
1724 | ||
1725 | if (offset_in_page + len > mtd->writesize + mtd->oobsize) | |
1726 | return -EINVAL; | |
1727 | ||
8878b126 MR |
1728 | if (chip->exec_op) |
1729 | return nand_exec_prog_page_op(chip, page, offset_in_page, buf, | |
1730 | len, false); | |
1731 | ||
97d90da8 BB |
1732 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page); |
1733 | ||
1734 | if (buf) | |
1735 | chip->write_buf(mtd, buf, len); | |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | EXPORT_SYMBOL_GPL(nand_prog_page_begin_op); | |
1740 | ||
1741 | /** | |
1742 | * nand_prog_page_end_op - ends a PROG PAGE operation | |
1743 | * @chip: The NAND chip | |
1744 | * | |
1745 | * This function issues the second half of a PROG PAGE operation. | |
1746 | * This function does not select/unselect the CS line. | |
1747 | * | |
1748 | * Returns 0 on success, a negative error code otherwise. | |
1749 | */ | |
1750 | int nand_prog_page_end_op(struct nand_chip *chip) | |
1751 | { | |
1752 | struct mtd_info *mtd = nand_to_mtd(chip); | |
8878b126 MR |
1753 | int ret; |
1754 | u8 status; | |
1755 | ||
1756 | if (chip->exec_op) { | |
1757 | const struct nand_sdr_timings *sdr = | |
1758 | nand_get_sdr_timings(&chip->data_interface); | |
1759 | struct nand_op_instr instrs[] = { | |
1760 | NAND_OP_CMD(NAND_CMD_PAGEPROG, | |
1761 | PSEC_TO_NSEC(sdr->tWB_max)), | |
1762 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0), | |
1763 | }; | |
1764 | struct nand_operation op = NAND_OPERATION(instrs); | |
1765 | ||
1766 | ret = nand_exec_op(chip, &op); | |
1767 | if (ret) | |
1768 | return ret; | |
97d90da8 | 1769 | |
8878b126 MR |
1770 | ret = nand_status_op(chip, &status); |
1771 | if (ret) | |
1772 | return ret; | |
1773 | } else { | |
1774 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1775 | ret = chip->waitfunc(mtd, chip); | |
1776 | if (ret < 0) | |
1777 | return ret; | |
1778 | ||
1779 | status = ret; | |
1780 | } | |
97d90da8 | 1781 | |
97d90da8 BB |
1782 | if (status & NAND_STATUS_FAIL) |
1783 | return -EIO; | |
1784 | ||
1785 | return 0; | |
1786 | } | |
1787 | EXPORT_SYMBOL_GPL(nand_prog_page_end_op); | |
1788 | ||
1789 | /** | |
1790 | * nand_prog_page_op - Do a full PROG PAGE operation | |
1791 | * @chip: The NAND chip | |
1792 | * @page: page to write | |
1793 | * @offset_in_page: offset within the page | |
1794 | * @buf: buffer containing the data to write to the page | |
1795 | * @len: length of the buffer | |
1796 | * | |
1797 | * This function issues a full PROG PAGE operation. | |
1798 | * This function does not select/unselect the CS line. | |
1799 | * | |
1800 | * Returns 0 on success, a negative error code otherwise. | |
1801 | */ | |
1802 | int nand_prog_page_op(struct nand_chip *chip, unsigned int page, | |
1803 | unsigned int offset_in_page, const void *buf, | |
1804 | unsigned int len) | |
1805 | { | |
1806 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1807 | int status; | |
1808 | ||
1809 | if (!len || !buf) | |
1810 | return -EINVAL; | |
1811 | ||
1812 | if (offset_in_page + len > mtd->writesize + mtd->oobsize) | |
1813 | return -EINVAL; | |
1814 | ||
8878b126 MR |
1815 | if (chip->exec_op) { |
1816 | status = nand_exec_prog_page_op(chip, page, offset_in_page, buf, | |
1817 | len, true); | |
1818 | } else { | |
1819 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page); | |
1820 | chip->write_buf(mtd, buf, len); | |
1821 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1822 | status = chip->waitfunc(mtd, chip); | |
1823 | } | |
97d90da8 | 1824 | |
97d90da8 BB |
1825 | if (status & NAND_STATUS_FAIL) |
1826 | return -EIO; | |
1827 | ||
1828 | return 0; | |
1829 | } | |
1830 | EXPORT_SYMBOL_GPL(nand_prog_page_op); | |
1831 | ||
1832 | /** | |
1833 | * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation | |
1834 | * @chip: The NAND chip | |
1835 | * @offset_in_page: offset within the page | |
1836 | * @buf: buffer containing the data to send to the NAND | |
1837 | * @len: length of the buffer | |
1838 | * @force_8bit: force 8-bit bus access | |
1839 | * | |
1840 | * This function issues a CHANGE WRITE COLUMN operation. | |
1841 | * This function does not select/unselect the CS line. | |
1842 | * | |
1843 | * Returns 0 on success, a negative error code otherwise. | |
1844 | */ | |
1845 | int nand_change_write_column_op(struct nand_chip *chip, | |
1846 | unsigned int offset_in_page, | |
1847 | const void *buf, unsigned int len, | |
1848 | bool force_8bit) | |
1849 | { | |
1850 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1851 | ||
1852 | if (len && !buf) | |
1853 | return -EINVAL; | |
1854 | ||
1855 | if (offset_in_page + len > mtd->writesize + mtd->oobsize) | |
1856 | return -EINVAL; | |
1857 | ||
8878b126 MR |
1858 | /* Small page NANDs do not support column change. */ |
1859 | if (mtd->writesize <= 512) | |
1860 | return -ENOTSUPP; | |
1861 | ||
1862 | if (chip->exec_op) { | |
1863 | const struct nand_sdr_timings *sdr = | |
1864 | nand_get_sdr_timings(&chip->data_interface); | |
1865 | u8 addrs[2]; | |
1866 | struct nand_op_instr instrs[] = { | |
1867 | NAND_OP_CMD(NAND_CMD_RNDIN, 0), | |
1868 | NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)), | |
1869 | NAND_OP_DATA_OUT(len, buf, 0), | |
1870 | }; | |
1871 | struct nand_operation op = NAND_OPERATION(instrs); | |
1872 | int ret; | |
1873 | ||
1874 | ret = nand_fill_column_cycles(chip, addrs, offset_in_page); | |
1875 | if (ret < 0) | |
1876 | return ret; | |
1877 | ||
1878 | instrs[2].ctx.data.force_8bit = force_8bit; | |
1879 | ||
1880 | /* Drop the DATA_OUT instruction if len is set to 0. */ | |
1881 | if (!len) | |
1882 | op.ninstrs--; | |
1883 | ||
1884 | return nand_exec_op(chip, &op); | |
1885 | } | |
1886 | ||
97d90da8 BB |
1887 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1); |
1888 | if (len) | |
1889 | chip->write_buf(mtd, buf, len); | |
1890 | ||
1891 | return 0; | |
1892 | } | |
1893 | EXPORT_SYMBOL_GPL(nand_change_write_column_op); | |
1894 | ||
1895 | /** | |
1896 | * nand_readid_op - Do a READID operation | |
1897 | * @chip: The NAND chip | |
1898 | * @addr: address cycle to pass after the READID command | |
1899 | * @buf: buffer used to store the ID | |
1900 | * @len: length of the buffer | |
1901 | * | |
1902 | * This function sends a READID command and reads back the ID returned by the | |
1903 | * NAND. | |
1904 | * This function does not select/unselect the CS line. | |
1905 | * | |
1906 | * Returns 0 on success, a negative error code otherwise. | |
1907 | */ | |
1908 | int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, | |
1909 | unsigned int len) | |
1910 | { | |
1911 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1912 | unsigned int i; | |
1913 | u8 *id = buf; | |
1914 | ||
1915 | if (len && !buf) | |
1916 | return -EINVAL; | |
1917 | ||
8878b126 MR |
1918 | if (chip->exec_op) { |
1919 | const struct nand_sdr_timings *sdr = | |
1920 | nand_get_sdr_timings(&chip->data_interface); | |
1921 | struct nand_op_instr instrs[] = { | |
1922 | NAND_OP_CMD(NAND_CMD_READID, 0), | |
1923 | NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)), | |
1924 | NAND_OP_8BIT_DATA_IN(len, buf, 0), | |
1925 | }; | |
1926 | struct nand_operation op = NAND_OPERATION(instrs); | |
1927 | ||
1928 | /* Drop the DATA_IN instruction if len is set to 0. */ | |
1929 | if (!len) | |
1930 | op.ninstrs--; | |
1931 | ||
1932 | return nand_exec_op(chip, &op); | |
1933 | } | |
1934 | ||
97d90da8 BB |
1935 | chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1); |
1936 | ||
1937 | for (i = 0; i < len; i++) | |
1938 | id[i] = chip->read_byte(mtd); | |
1939 | ||
1940 | return 0; | |
1941 | } | |
1942 | EXPORT_SYMBOL_GPL(nand_readid_op); | |
1943 | ||
1944 | /** | |
1945 | * nand_status_op - Do a STATUS operation | |
1946 | * @chip: The NAND chip | |
1947 | * @status: out variable to store the NAND status | |
1948 | * | |
1949 | * This function sends a STATUS command and reads back the status returned by | |
1950 | * the NAND. | |
1951 | * This function does not select/unselect the CS line. | |
1952 | * | |
1953 | * Returns 0 on success, a negative error code otherwise. | |
1954 | */ | |
1955 | int nand_status_op(struct nand_chip *chip, u8 *status) | |
1956 | { | |
1957 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1958 | ||
8878b126 MR |
1959 | if (chip->exec_op) { |
1960 | const struct nand_sdr_timings *sdr = | |
1961 | nand_get_sdr_timings(&chip->data_interface); | |
1962 | struct nand_op_instr instrs[] = { | |
1963 | NAND_OP_CMD(NAND_CMD_STATUS, | |
1964 | PSEC_TO_NSEC(sdr->tADL_min)), | |
1965 | NAND_OP_8BIT_DATA_IN(1, status, 0), | |
1966 | }; | |
1967 | struct nand_operation op = NAND_OPERATION(instrs); | |
1968 | ||
1969 | if (!status) | |
1970 | op.ninstrs--; | |
1971 | ||
1972 | return nand_exec_op(chip, &op); | |
1973 | } | |
1974 | ||
97d90da8 BB |
1975 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1976 | if (status) | |
1977 | *status = chip->read_byte(mtd); | |
1978 | ||
1979 | return 0; | |
1980 | } | |
1981 | EXPORT_SYMBOL_GPL(nand_status_op); | |
1982 | ||
1983 | /** | |
1984 | * nand_exit_status_op - Exit a STATUS operation | |
1985 | * @chip: The NAND chip | |
1986 | * | |
1987 | * This function sends a READ0 command to cancel the effect of the STATUS | |
1988 | * command to avoid reading only the status until a new read command is sent. | |
1989 | * | |
1990 | * This function does not select/unselect the CS line. | |
1991 | * | |
1992 | * Returns 0 on success, a negative error code otherwise. | |
1993 | */ | |
1994 | int nand_exit_status_op(struct nand_chip *chip) | |
1995 | { | |
1996 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1997 | ||
8878b126 MR |
1998 | if (chip->exec_op) { |
1999 | struct nand_op_instr instrs[] = { | |
2000 | NAND_OP_CMD(NAND_CMD_READ0, 0), | |
2001 | }; | |
2002 | struct nand_operation op = NAND_OPERATION(instrs); | |
2003 | ||
2004 | return nand_exec_op(chip, &op); | |
2005 | } | |
2006 | ||
97d90da8 BB |
2007 | chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1); |
2008 | ||
2009 | return 0; | |
2010 | } | |
2011 | EXPORT_SYMBOL_GPL(nand_exit_status_op); | |
2012 | ||
2013 | /** | |
2014 | * nand_erase_op - Do an erase operation | |
2015 | * @chip: The NAND chip | |
2016 | * @eraseblock: block to erase | |
2017 | * | |
2018 | * This function sends an ERASE command and waits for the NAND to be ready | |
2019 | * before returning. | |
2020 | * This function does not select/unselect the CS line. | |
2021 | * | |
2022 | * Returns 0 on success, a negative error code otherwise. | |
2023 | */ | |
2024 | int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock) | |
2025 | { | |
2026 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2027 | unsigned int page = eraseblock << | |
2028 | (chip->phys_erase_shift - chip->page_shift); | |
8878b126 MR |
2029 | int ret; |
2030 | u8 status; | |
97d90da8 | 2031 | |
8878b126 MR |
2032 | if (chip->exec_op) { |
2033 | const struct nand_sdr_timings *sdr = | |
2034 | nand_get_sdr_timings(&chip->data_interface); | |
2035 | u8 addrs[3] = { page, page >> 8, page >> 16 }; | |
2036 | struct nand_op_instr instrs[] = { | |
2037 | NAND_OP_CMD(NAND_CMD_ERASE1, 0), | |
2038 | NAND_OP_ADDR(2, addrs, 0), | |
2039 | NAND_OP_CMD(NAND_CMD_ERASE2, | |
2040 | PSEC_TO_MSEC(sdr->tWB_max)), | |
2041 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tBERS_max), 0), | |
2042 | }; | |
2043 | struct nand_operation op = NAND_OPERATION(instrs); | |
97d90da8 | 2044 | |
8878b126 MR |
2045 | if (chip->options & NAND_ROW_ADDR_3) |
2046 | instrs[1].ctx.addr.naddrs++; | |
2047 | ||
2048 | ret = nand_exec_op(chip, &op); | |
2049 | if (ret) | |
2050 | return ret; | |
2051 | ||
2052 | ret = nand_status_op(chip, &status); | |
2053 | if (ret) | |
2054 | return ret; | |
2055 | } else { | |
2056 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2057 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
2058 | ||
2059 | ret = chip->waitfunc(mtd, chip); | |
2060 | if (ret < 0) | |
2061 | return ret; | |
2062 | ||
2063 | status = ret; | |
2064 | } | |
97d90da8 BB |
2065 | |
2066 | if (status & NAND_STATUS_FAIL) | |
2067 | return -EIO; | |
2068 | ||
2069 | return 0; | |
2070 | } | |
2071 | EXPORT_SYMBOL_GPL(nand_erase_op); | |
2072 | ||
2073 | /** | |
2074 | * nand_set_features_op - Do a SET FEATURES operation | |
2075 | * @chip: The NAND chip | |
2076 | * @feature: feature id | |
2077 | * @data: 4 bytes of data | |
2078 | * | |
2079 | * This function sends a SET FEATURES command and waits for the NAND to be | |
2080 | * ready before returning. | |
2081 | * This function does not select/unselect the CS line. | |
2082 | * | |
2083 | * Returns 0 on success, a negative error code otherwise. | |
2084 | */ | |
2085 | static int nand_set_features_op(struct nand_chip *chip, u8 feature, | |
2086 | const void *data) | |
2087 | { | |
2088 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2089 | const u8 *params = data; | |
8878b126 MR |
2090 | int i, ret; |
2091 | u8 status; | |
97d90da8 | 2092 | |
8878b126 MR |
2093 | if (chip->exec_op) { |
2094 | const struct nand_sdr_timings *sdr = | |
2095 | nand_get_sdr_timings(&chip->data_interface); | |
2096 | struct nand_op_instr instrs[] = { | |
2097 | NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0), | |
2098 | NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)), | |
2099 | NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data, | |
2100 | PSEC_TO_NSEC(sdr->tWB_max)), | |
2101 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 0), | |
2102 | }; | |
2103 | struct nand_operation op = NAND_OPERATION(instrs); | |
2104 | ||
2105 | ret = nand_exec_op(chip, &op); | |
2106 | if (ret) | |
2107 | return ret; | |
2108 | ||
2109 | ret = nand_status_op(chip, &status); | |
2110 | if (ret) | |
2111 | return ret; | |
2112 | } else { | |
2113 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1); | |
2114 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) | |
2115 | chip->write_byte(mtd, params[i]); | |
2116 | ||
2117 | ret = chip->waitfunc(mtd, chip); | |
2118 | if (ret < 0) | |
2119 | return ret; | |
2120 | ||
2121 | status = ret; | |
2122 | } | |
97d90da8 | 2123 | |
97d90da8 BB |
2124 | if (status & NAND_STATUS_FAIL) |
2125 | return -EIO; | |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | /** | |
2131 | * nand_get_features_op - Do a GET FEATURES operation | |
2132 | * @chip: The NAND chip | |
2133 | * @feature: feature id | |
2134 | * @data: 4 bytes of data | |
2135 | * | |
2136 | * This function sends a GET FEATURES command and waits for the NAND to be | |
2137 | * ready before returning. | |
2138 | * This function does not select/unselect the CS line. | |
2139 | * | |
2140 | * Returns 0 on success, a negative error code otherwise. | |
2141 | */ | |
2142 | static int nand_get_features_op(struct nand_chip *chip, u8 feature, | |
2143 | void *data) | |
2144 | { | |
2145 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2146 | u8 *params = data; | |
2147 | int i; | |
2148 | ||
8878b126 MR |
2149 | if (chip->exec_op) { |
2150 | const struct nand_sdr_timings *sdr = | |
2151 | nand_get_sdr_timings(&chip->data_interface); | |
2152 | struct nand_op_instr instrs[] = { | |
2153 | NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0), | |
2154 | NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)), | |
2155 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), | |
2156 | PSEC_TO_NSEC(sdr->tRR_min)), | |
2157 | NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN, | |
2158 | data, 0), | |
2159 | }; | |
2160 | struct nand_operation op = NAND_OPERATION(instrs); | |
2161 | ||
2162 | return nand_exec_op(chip, &op); | |
2163 | } | |
2164 | ||
97d90da8 BB |
2165 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1); |
2166 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) | |
2167 | params[i] = chip->read_byte(mtd); | |
2168 | ||
2169 | return 0; | |
2170 | } | |
2171 | ||
2172 | /** | |
2173 | * nand_reset_op - Do a reset operation | |
2174 | * @chip: The NAND chip | |
2175 | * | |
2176 | * This function sends a RESET command and waits for the NAND to be ready | |
2177 | * before returning. | |
2178 | * This function does not select/unselect the CS line. | |
2179 | * | |
2180 | * Returns 0 on success, a negative error code otherwise. | |
2181 | */ | |
2182 | int nand_reset_op(struct nand_chip *chip) | |
2183 | { | |
2184 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2185 | ||
8878b126 MR |
2186 | if (chip->exec_op) { |
2187 | const struct nand_sdr_timings *sdr = | |
2188 | nand_get_sdr_timings(&chip->data_interface); | |
2189 | struct nand_op_instr instrs[] = { | |
2190 | NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)), | |
2191 | NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0), | |
2192 | }; | |
2193 | struct nand_operation op = NAND_OPERATION(instrs); | |
2194 | ||
2195 | return nand_exec_op(chip, &op); | |
2196 | } | |
2197 | ||
97d90da8 BB |
2198 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
2199 | ||
2200 | return 0; | |
2201 | } | |
2202 | EXPORT_SYMBOL_GPL(nand_reset_op); | |
2203 | ||
2204 | /** | |
2205 | * nand_read_data_op - Read data from the NAND | |
2206 | * @chip: The NAND chip | |
2207 | * @buf: buffer used to store the data | |
2208 | * @len: length of the buffer | |
2209 | * @force_8bit: force 8-bit bus access | |
2210 | * | |
2211 | * This function does a raw data read on the bus. Usually used after launching | |
2212 | * another NAND operation like nand_read_page_op(). | |
2213 | * This function does not select/unselect the CS line. | |
2214 | * | |
2215 | * Returns 0 on success, a negative error code otherwise. | |
2216 | */ | |
2217 | int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, | |
2218 | bool force_8bit) | |
2219 | { | |
2220 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2221 | ||
2222 | if (!len || !buf) | |
2223 | return -EINVAL; | |
2224 | ||
8878b126 MR |
2225 | if (chip->exec_op) { |
2226 | struct nand_op_instr instrs[] = { | |
2227 | NAND_OP_DATA_IN(len, buf, 0), | |
2228 | }; | |
2229 | struct nand_operation op = NAND_OPERATION(instrs); | |
2230 | ||
2231 | instrs[0].ctx.data.force_8bit = force_8bit; | |
2232 | ||
2233 | return nand_exec_op(chip, &op); | |
2234 | } | |
2235 | ||
97d90da8 BB |
2236 | if (force_8bit) { |
2237 | u8 *p = buf; | |
2238 | unsigned int i; | |
2239 | ||
2240 | for (i = 0; i < len; i++) | |
2241 | p[i] = chip->read_byte(mtd); | |
2242 | } else { | |
2243 | chip->read_buf(mtd, buf, len); | |
2244 | } | |
2245 | ||
2246 | return 0; | |
2247 | } | |
2248 | EXPORT_SYMBOL_GPL(nand_read_data_op); | |
2249 | ||
2250 | /** | |
2251 | * nand_write_data_op - Write data from the NAND | |
2252 | * @chip: The NAND chip | |
2253 | * @buf: buffer containing the data to send on the bus | |
2254 | * @len: length of the buffer | |
2255 | * @force_8bit: force 8-bit bus access | |
2256 | * | |
2257 | * This function does a raw data write on the bus. Usually used after launching | |
2258 | * another NAND operation like nand_write_page_begin_op(). | |
2259 | * This function does not select/unselect the CS line. | |
2260 | * | |
2261 | * Returns 0 on success, a negative error code otherwise. | |
2262 | */ | |
2263 | int nand_write_data_op(struct nand_chip *chip, const void *buf, | |
2264 | unsigned int len, bool force_8bit) | |
2265 | { | |
2266 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2267 | ||
2268 | if (!len || !buf) | |
2269 | return -EINVAL; | |
2270 | ||
8878b126 MR |
2271 | if (chip->exec_op) { |
2272 | struct nand_op_instr instrs[] = { | |
2273 | NAND_OP_DATA_OUT(len, buf, 0), | |
2274 | }; | |
2275 | struct nand_operation op = NAND_OPERATION(instrs); | |
2276 | ||
2277 | instrs[0].ctx.data.force_8bit = force_8bit; | |
2278 | ||
2279 | return nand_exec_op(chip, &op); | |
2280 | } | |
2281 | ||
97d90da8 BB |
2282 | if (force_8bit) { |
2283 | const u8 *p = buf; | |
2284 | unsigned int i; | |
2285 | ||
2286 | for (i = 0; i < len; i++) | |
2287 | chip->write_byte(mtd, p[i]); | |
2288 | } else { | |
2289 | chip->write_buf(mtd, buf, len); | |
2290 | } | |
2291 | ||
2292 | return 0; | |
2293 | } | |
2294 | EXPORT_SYMBOL_GPL(nand_write_data_op); | |
2295 | ||
8878b126 MR |
2296 | /** |
2297 | * struct nand_op_parser_ctx - Context used by the parser | |
2298 | * @instrs: array of all the instructions that must be addressed | |
2299 | * @ninstrs: length of the @instrs array | |
2300 | * @subop: Sub-operation to be passed to the NAND controller | |
2301 | * | |
2302 | * This structure is used by the core to split NAND operations into | |
2303 | * sub-operations that can be handled by the NAND controller. | |
2304 | */ | |
2305 | struct nand_op_parser_ctx { | |
2306 | const struct nand_op_instr *instrs; | |
2307 | unsigned int ninstrs; | |
2308 | struct nand_subop subop; | |
2309 | }; | |
2310 | ||
2311 | /** | |
2312 | * nand_op_parser_must_split_instr - Checks if an instruction must be split | |
2313 | * @pat: the parser pattern element that matches @instr | |
2314 | * @instr: pointer to the instruction to check | |
2315 | * @start_offset: this is an in/out parameter. If @instr has already been | |
2316 | * split, then @start_offset is the offset from which to start | |
2317 | * (either an address cycle or an offset in the data buffer). | |
2318 | * Conversely, if the function returns true (ie. instr must be | |
2319 | * split), this parameter is updated to point to the first | |
2320 | * data/address cycle that has not been taken care of. | |
2321 | * | |
2322 | * Some NAND controllers are limited and cannot send X address cycles with a | |
2323 | * unique operation, or cannot read/write more than Y bytes at the same time. | |
2324 | * In this case, split the instruction that does not fit in a single | |
2325 | * controller-operation into two or more chunks. | |
2326 | * | |
2327 | * Returns true if the instruction must be split, false otherwise. | |
2328 | * The @start_offset parameter is also updated to the offset at which the next | |
2329 | * bundle of instruction must start (if an address or a data instruction). | |
2330 | */ | |
2331 | static bool | |
2332 | nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat, | |
2333 | const struct nand_op_instr *instr, | |
2334 | unsigned int *start_offset) | |
2335 | { | |
2336 | switch (pat->type) { | |
2337 | case NAND_OP_ADDR_INSTR: | |
2338 | if (!pat->addr.maxcycles) | |
2339 | break; | |
2340 | ||
2341 | if (instr->ctx.addr.naddrs - *start_offset > | |
2342 | pat->addr.maxcycles) { | |
2343 | *start_offset += pat->addr.maxcycles; | |
2344 | return true; | |
2345 | } | |
2346 | break; | |
2347 | ||
2348 | case NAND_OP_DATA_IN_INSTR: | |
2349 | case NAND_OP_DATA_OUT_INSTR: | |
2350 | if (!pat->data.maxlen) | |
2351 | break; | |
2352 | ||
2353 | if (instr->ctx.data.len - *start_offset > pat->data.maxlen) { | |
2354 | *start_offset += pat->data.maxlen; | |
2355 | return true; | |
2356 | } | |
2357 | break; | |
2358 | ||
2359 | default: | |
2360 | break; | |
2361 | } | |
2362 | ||
2363 | return false; | |
2364 | } | |
2365 | ||
2366 | /** | |
2367 | * nand_op_parser_match_pat - Checks if a pattern matches the instructions | |
2368 | * remaining in the parser context | |
2369 | * @pat: the pattern to test | |
2370 | * @ctx: the parser context structure to match with the pattern @pat | |
2371 | * | |
2372 | * Check if @pat matches the set or a sub-set of instructions remaining in @ctx. | |
2373 | * Returns true if this is the case, false ortherwise. When true is returned, | |
2374 | * @ctx->subop is updated with the set of instructions to be passed to the | |
2375 | * controller driver. | |
2376 | */ | |
2377 | static bool | |
2378 | nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat, | |
2379 | struct nand_op_parser_ctx *ctx) | |
2380 | { | |
2381 | unsigned int instr_offset = ctx->subop.first_instr_start_off; | |
2382 | const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs; | |
2383 | const struct nand_op_instr *instr = ctx->subop.instrs; | |
2384 | unsigned int i, ninstrs; | |
2385 | ||
2386 | for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) { | |
2387 | /* | |
2388 | * The pattern instruction does not match the operation | |
2389 | * instruction. If the instruction is marked optional in the | |
2390 | * pattern definition, we skip the pattern element and continue | |
2391 | * to the next one. If the element is mandatory, there's no | |
2392 | * match and we can return false directly. | |
2393 | */ | |
2394 | if (instr->type != pat->elems[i].type) { | |
2395 | if (!pat->elems[i].optional) | |
2396 | return false; | |
2397 | ||
2398 | continue; | |
2399 | } | |
2400 | ||
2401 | /* | |
2402 | * Now check the pattern element constraints. If the pattern is | |
2403 | * not able to handle the whole instruction in a single step, | |
2404 | * we have to split it. | |
2405 | * The last_instr_end_off value comes back updated to point to | |
2406 | * the position where we have to split the instruction (the | |
2407 | * start of the next subop chunk). | |
2408 | */ | |
2409 | if (nand_op_parser_must_split_instr(&pat->elems[i], instr, | |
2410 | &instr_offset)) { | |
2411 | ninstrs++; | |
2412 | i++; | |
2413 | break; | |
2414 | } | |
2415 | ||
2416 | instr++; | |
2417 | ninstrs++; | |
2418 | instr_offset = 0; | |
2419 | } | |
2420 | ||
2421 | /* | |
2422 | * This can happen if all instructions of a pattern are optional. | |
2423 | * Still, if there's not at least one instruction handled by this | |
2424 | * pattern, this is not a match, and we should try the next one (if | |
2425 | * any). | |
2426 | */ | |
2427 | if (!ninstrs) | |
2428 | return false; | |
2429 | ||
2430 | /* | |
2431 | * We had a match on the pattern head, but the pattern may be longer | |
2432 | * than the instructions we're asked to execute. We need to make sure | |
2433 | * there's no mandatory elements in the pattern tail. | |
2434 | */ | |
2435 | for (; i < pat->nelems; i++) { | |
2436 | if (!pat->elems[i].optional) | |
2437 | return false; | |
2438 | } | |
2439 | ||
2440 | /* | |
2441 | * We have a match: update the subop structure accordingly and return | |
2442 | * true. | |
2443 | */ | |
2444 | ctx->subop.ninstrs = ninstrs; | |
2445 | ctx->subop.last_instr_end_off = instr_offset; | |
2446 | ||
2447 | return true; | |
2448 | } | |
2449 | ||
2450 | #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG) | |
2451 | static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) | |
2452 | { | |
2453 | const struct nand_op_instr *instr; | |
2454 | char *prefix = " "; | |
2455 | unsigned int i; | |
2456 | ||
2457 | pr_debug("executing subop:\n"); | |
2458 | ||
2459 | for (i = 0; i < ctx->ninstrs; i++) { | |
2460 | instr = &ctx->instrs[i]; | |
2461 | ||
2462 | if (instr == &ctx->subop.instrs[0]) | |
2463 | prefix = " ->"; | |
2464 | ||
2465 | switch (instr->type) { | |
2466 | case NAND_OP_CMD_INSTR: | |
2467 | pr_debug("%sCMD [0x%02x]\n", prefix, | |
2468 | instr->ctx.cmd.opcode); | |
2469 | break; | |
2470 | case NAND_OP_ADDR_INSTR: | |
2471 | pr_debug("%sADDR [%d cyc: %*ph]\n", prefix, | |
2472 | instr->ctx.addr.naddrs, | |
2473 | instr->ctx.addr.naddrs < 64 ? | |
2474 | instr->ctx.addr.naddrs : 64, | |
2475 | instr->ctx.addr.addrs); | |
2476 | break; | |
2477 | case NAND_OP_DATA_IN_INSTR: | |
2478 | pr_debug("%sDATA_IN [%d B%s]\n", prefix, | |
2479 | instr->ctx.data.len, | |
2480 | instr->ctx.data.force_8bit ? | |
2481 | ", force 8-bit" : ""); | |
2482 | break; | |
2483 | case NAND_OP_DATA_OUT_INSTR: | |
2484 | pr_debug("%sDATA_OUT [%d B%s]\n", prefix, | |
2485 | instr->ctx.data.len, | |
2486 | instr->ctx.data.force_8bit ? | |
2487 | ", force 8-bit" : ""); | |
2488 | break; | |
2489 | case NAND_OP_WAITRDY_INSTR: | |
2490 | pr_debug("%sWAITRDY [max %d ms]\n", prefix, | |
2491 | instr->ctx.waitrdy.timeout_ms); | |
2492 | break; | |
2493 | } | |
2494 | ||
2495 | if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) | |
2496 | prefix = " "; | |
2497 | } | |
2498 | } | |
2499 | #else | |
2500 | static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) | |
2501 | { | |
2502 | /* NOP */ | |
2503 | } | |
2504 | #endif | |
2505 | ||
2506 | /** | |
2507 | * nand_op_parser_exec_op - exec_op parser | |
2508 | * @chip: the NAND chip | |
2509 | * @parser: patterns description provided by the controller driver | |
2510 | * @op: the NAND operation to address | |
2511 | * @check_only: when true, the function only checks if @op can be handled but | |
2512 | * does not execute the operation | |
2513 | * | |
2514 | * Helper function designed to ease integration of NAND controller drivers that | |
2515 | * only support a limited set of instruction sequences. The supported sequences | |
2516 | * are described in @parser, and the framework takes care of splitting @op into | |
2517 | * multiple sub-operations (if required) and pass them back to the ->exec() | |
2518 | * callback of the matching pattern if @check_only is set to false. | |
2519 | * | |
2520 | * NAND controller drivers should call this function from their own ->exec_op() | |
2521 | * implementation. | |
2522 | * | |
2523 | * Returns 0 on success, a negative error code otherwise. A failure can be | |
2524 | * caused by an unsupported operation (none of the supported patterns is able | |
2525 | * to handle the requested operation), or an error returned by one of the | |
2526 | * matching pattern->exec() hook. | |
2527 | */ | |
2528 | int nand_op_parser_exec_op(struct nand_chip *chip, | |
2529 | const struct nand_op_parser *parser, | |
2530 | const struct nand_operation *op, bool check_only) | |
2531 | { | |
2532 | struct nand_op_parser_ctx ctx = { | |
2533 | .subop.instrs = op->instrs, | |
2534 | .instrs = op->instrs, | |
2535 | .ninstrs = op->ninstrs, | |
2536 | }; | |
2537 | unsigned int i; | |
2538 | ||
2539 | while (ctx.subop.instrs < op->instrs + op->ninstrs) { | |
2540 | int ret; | |
2541 | ||
2542 | for (i = 0; i < parser->npatterns; i++) { | |
2543 | const struct nand_op_parser_pattern *pattern; | |
2544 | ||
2545 | pattern = &parser->patterns[i]; | |
2546 | if (!nand_op_parser_match_pat(pattern, &ctx)) | |
2547 | continue; | |
2548 | ||
2549 | nand_op_parser_trace(&ctx); | |
2550 | ||
2551 | if (check_only) | |
2552 | break; | |
2553 | ||
2554 | ret = pattern->exec(chip, &ctx.subop); | |
2555 | if (ret) | |
2556 | return ret; | |
2557 | ||
2558 | break; | |
2559 | } | |
2560 | ||
2561 | if (i == parser->npatterns) { | |
2562 | pr_debug("->exec_op() parser: pattern not found!\n"); | |
2563 | return -ENOTSUPP; | |
2564 | } | |
2565 | ||
2566 | /* | |
2567 | * Update the context structure by pointing to the start of the | |
2568 | * next subop. | |
2569 | */ | |
2570 | ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs; | |
2571 | if (ctx.subop.last_instr_end_off) | |
2572 | ctx.subop.instrs -= 1; | |
2573 | ||
2574 | ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off; | |
2575 | } | |
2576 | ||
2577 | return 0; | |
2578 | } | |
2579 | EXPORT_SYMBOL_GPL(nand_op_parser_exec_op); | |
2580 | ||
2581 | static bool nand_instr_is_data(const struct nand_op_instr *instr) | |
2582 | { | |
2583 | return instr && (instr->type == NAND_OP_DATA_IN_INSTR || | |
2584 | instr->type == NAND_OP_DATA_OUT_INSTR); | |
2585 | } | |
2586 | ||
2587 | static bool nand_subop_instr_is_valid(const struct nand_subop *subop, | |
2588 | unsigned int instr_idx) | |
2589 | { | |
2590 | return subop && instr_idx < subop->ninstrs; | |
2591 | } | |
2592 | ||
2593 | static int nand_subop_get_start_off(const struct nand_subop *subop, | |
2594 | unsigned int instr_idx) | |
2595 | { | |
2596 | if (instr_idx) | |
2597 | return 0; | |
2598 | ||
2599 | return subop->first_instr_start_off; | |
2600 | } | |
2601 | ||
2602 | /** | |
2603 | * nand_subop_get_addr_start_off - Get the start offset in an address array | |
2604 | * @subop: The entire sub-operation | |
2605 | * @instr_idx: Index of the instruction inside the sub-operation | |
2606 | * | |
2607 | * During driver development, one could be tempted to directly use the | |
2608 | * ->addr.addrs field of address instructions. This is wrong as address | |
2609 | * instructions might be split. | |
2610 | * | |
2611 | * Given an address instruction, returns the offset of the first cycle to issue. | |
2612 | */ | |
2613 | int nand_subop_get_addr_start_off(const struct nand_subop *subop, | |
2614 | unsigned int instr_idx) | |
2615 | { | |
2616 | if (!nand_subop_instr_is_valid(subop, instr_idx) || | |
2617 | subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR) | |
2618 | return -EINVAL; | |
2619 | ||
2620 | return nand_subop_get_start_off(subop, instr_idx); | |
2621 | } | |
2622 | EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off); | |
2623 | ||
2624 | /** | |
2625 | * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert | |
2626 | * @subop: The entire sub-operation | |
2627 | * @instr_idx: Index of the instruction inside the sub-operation | |
2628 | * | |
2629 | * During driver development, one could be tempted to directly use the | |
2630 | * ->addr->naddrs field of a data instruction. This is wrong as instructions | |
2631 | * might be split. | |
2632 | * | |
2633 | * Given an address instruction, returns the number of address cycle to issue. | |
2634 | */ | |
2635 | int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, | |
2636 | unsigned int instr_idx) | |
2637 | { | |
2638 | int start_off, end_off; | |
2639 | ||
2640 | if (!nand_subop_instr_is_valid(subop, instr_idx) || | |
2641 | subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR) | |
2642 | return -EINVAL; | |
2643 | ||
2644 | start_off = nand_subop_get_addr_start_off(subop, instr_idx); | |
2645 | ||
2646 | if (instr_idx == subop->ninstrs - 1 && | |
2647 | subop->last_instr_end_off) | |
2648 | end_off = subop->last_instr_end_off; | |
2649 | else | |
2650 | end_off = subop->instrs[instr_idx].ctx.addr.naddrs; | |
2651 | ||
2652 | return end_off - start_off; | |
2653 | } | |
2654 | EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc); | |
2655 | ||
2656 | /** | |
2657 | * nand_subop_get_data_start_off - Get the start offset in a data array | |
2658 | * @subop: The entire sub-operation | |
2659 | * @instr_idx: Index of the instruction inside the sub-operation | |
2660 | * | |
2661 | * During driver development, one could be tempted to directly use the | |
2662 | * ->data->buf.{in,out} field of data instructions. This is wrong as data | |
2663 | * instructions might be split. | |
2664 | * | |
2665 | * Given a data instruction, returns the offset to start from. | |
2666 | */ | |
2667 | int nand_subop_get_data_start_off(const struct nand_subop *subop, | |
2668 | unsigned int instr_idx) | |
2669 | { | |
2670 | if (!nand_subop_instr_is_valid(subop, instr_idx) || | |
2671 | !nand_instr_is_data(&subop->instrs[instr_idx])) | |
2672 | return -EINVAL; | |
2673 | ||
2674 | return nand_subop_get_start_off(subop, instr_idx); | |
2675 | } | |
2676 | EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off); | |
2677 | ||
2678 | /** | |
2679 | * nand_subop_get_data_len - Get the number of bytes to retrieve | |
2680 | * @subop: The entire sub-operation | |
2681 | * @instr_idx: Index of the instruction inside the sub-operation | |
2682 | * | |
2683 | * During driver development, one could be tempted to directly use the | |
2684 | * ->data->len field of a data instruction. This is wrong as data instructions | |
2685 | * might be split. | |
2686 | * | |
2687 | * Returns the length of the chunk of data to send/receive. | |
2688 | */ | |
2689 | int nand_subop_get_data_len(const struct nand_subop *subop, | |
2690 | unsigned int instr_idx) | |
2691 | { | |
2692 | int start_off = 0, end_off; | |
2693 | ||
2694 | if (!nand_subop_instr_is_valid(subop, instr_idx) || | |
2695 | !nand_instr_is_data(&subop->instrs[instr_idx])) | |
2696 | return -EINVAL; | |
2697 | ||
2698 | start_off = nand_subop_get_data_start_off(subop, instr_idx); | |
2699 | ||
2700 | if (instr_idx == subop->ninstrs - 1 && | |
2701 | subop->last_instr_end_off) | |
2702 | end_off = subop->last_instr_end_off; | |
2703 | else | |
2704 | end_off = subop->instrs[instr_idx].ctx.data.len; | |
2705 | ||
2706 | return end_off - start_off; | |
2707 | } | |
2708 | EXPORT_SYMBOL_GPL(nand_subop_get_data_len); | |
2709 | ||
2f94abfe SH |
2710 | /** |
2711 | * nand_reset - Reset and initialize a NAND device | |
2712 | * @chip: The NAND chip | |
73f907fd | 2713 | * @chipnr: Internal die id |
2f94abfe | 2714 | * |
17fa8044 MR |
2715 | * Save the timings data structure, then apply SDR timings mode 0 (see |
2716 | * nand_reset_data_interface for details), do the reset operation, and | |
2717 | * apply back the previous timings. | |
2718 | * | |
2719 | * Returns 0 on success, a negative error code otherwise. | |
2f94abfe | 2720 | */ |
73f907fd | 2721 | int nand_reset(struct nand_chip *chip, int chipnr) |
2f94abfe SH |
2722 | { |
2723 | struct mtd_info *mtd = nand_to_mtd(chip); | |
17fa8044 | 2724 | struct nand_data_interface saved_data_intf = chip->data_interface; |
d8e725dd BB |
2725 | int ret; |
2726 | ||
104e442a | 2727 | ret = nand_reset_data_interface(chip, chipnr); |
d8e725dd BB |
2728 | if (ret) |
2729 | return ret; | |
2f94abfe | 2730 | |
73f907fd BB |
2731 | /* |
2732 | * The CS line has to be released before we can apply the new NAND | |
2733 | * interface settings, hence this weird ->select_chip() dance. | |
2734 | */ | |
2735 | chip->select_chip(mtd, chipnr); | |
97d90da8 | 2736 | ret = nand_reset_op(chip); |
73f907fd | 2737 | chip->select_chip(mtd, -1); |
97d90da8 BB |
2738 | if (ret) |
2739 | return ret; | |
2f94abfe | 2740 | |
73f907fd | 2741 | chip->select_chip(mtd, chipnr); |
17fa8044 | 2742 | chip->data_interface = saved_data_intf; |
104e442a | 2743 | ret = nand_setup_data_interface(chip, chipnr); |
73f907fd | 2744 | chip->select_chip(mtd, -1); |
d8e725dd BB |
2745 | if (ret) |
2746 | return ret; | |
2747 | ||
2f94abfe SH |
2748 | return 0; |
2749 | } | |
b9bb9842 | 2750 | EXPORT_SYMBOL_GPL(nand_reset); |
2f94abfe | 2751 | |
730a43fb BB |
2752 | /** |
2753 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
2754 | * @buf: buffer to test | |
2755 | * @len: buffer length | |
2756 | * @bitflips_threshold: maximum number of bitflips | |
2757 | * | |
2758 | * Check if a buffer contains only 0xff, which means the underlying region | |
2759 | * has been erased and is ready to be programmed. | |
2760 | * The bitflips_threshold specify the maximum number of bitflips before | |
2761 | * considering the region is not erased. | |
2762 | * Note: The logic of this function has been extracted from the memweight | |
2763 | * implementation, except that nand_check_erased_buf function exit before | |
2764 | * testing the whole buffer if the number of bitflips exceed the | |
2765 | * bitflips_threshold value. | |
2766 | * | |
2767 | * Returns a positive number of bitflips less than or equal to | |
2768 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
2769 | * threshold. | |
2770 | */ | |
2771 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
2772 | { | |
2773 | const unsigned char *bitmap = buf; | |
2774 | int bitflips = 0; | |
2775 | int weight; | |
2776 | ||
2777 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
2778 | len--, bitmap++) { | |
2779 | weight = hweight8(*bitmap); | |
2780 | bitflips += BITS_PER_BYTE - weight; | |
2781 | if (unlikely(bitflips > bitflips_threshold)) | |
2782 | return -EBADMSG; | |
2783 | } | |
2784 | ||
2785 | for (; len >= sizeof(long); | |
2786 | len -= sizeof(long), bitmap += sizeof(long)) { | |
086567f1 PM |
2787 | unsigned long d = *((unsigned long *)bitmap); |
2788 | if (d == ~0UL) | |
2789 | continue; | |
2790 | weight = hweight_long(d); | |
730a43fb BB |
2791 | bitflips += BITS_PER_LONG - weight; |
2792 | if (unlikely(bitflips > bitflips_threshold)) | |
2793 | return -EBADMSG; | |
2794 | } | |
2795 | ||
2796 | for (; len > 0; len--, bitmap++) { | |
2797 | weight = hweight8(*bitmap); | |
2798 | bitflips += BITS_PER_BYTE - weight; | |
2799 | if (unlikely(bitflips > bitflips_threshold)) | |
2800 | return -EBADMSG; | |
2801 | } | |
2802 | ||
2803 | return bitflips; | |
2804 | } | |
2805 | ||
2806 | /** | |
2807 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
2808 | * 0xff data | |
2809 | * @data: data buffer to test | |
2810 | * @datalen: data length | |
2811 | * @ecc: ECC buffer | |
2812 | * @ecclen: ECC length | |
2813 | * @extraoob: extra OOB buffer | |
2814 | * @extraooblen: extra OOB length | |
2815 | * @bitflips_threshold: maximum number of bitflips | |
2816 | * | |
2817 | * Check if a data buffer and its associated ECC and OOB data contains only | |
2818 | * 0xff pattern, which means the underlying region has been erased and is | |
2819 | * ready to be programmed. | |
2820 | * The bitflips_threshold specify the maximum number of bitflips before | |
2821 | * considering the region as not erased. | |
2822 | * | |
2823 | * Note: | |
2824 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
2825 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
2826 | * report the number of errors per chunk, and the NAND core infrastructure | |
2827 | * expect you to return the maximum number of bitflips for the whole page. | |
2828 | * This is why you should always use this function on a single chunk and | |
2829 | * not on the whole page. After checking each chunk you should update your | |
2830 | * max_bitflips value accordingly. | |
2831 | * 2/ When checking for bitflips in erased pages you should not only check | |
2832 | * the payload data but also their associated ECC data, because a user might | |
2833 | * have programmed almost all bits to 1 but a few. In this case, we | |
2834 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
2835 | * this case. | |
2836 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
2837 | * data are protected by the ECC engine. | |
2838 | * It could also be used if you support subpages and want to attach some | |
2839 | * extra OOB data to an ECC chunk. | |
2840 | * | |
2841 | * Returns a positive number of bitflips less than or equal to | |
2842 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
2843 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
2844 | */ | |
2845 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
2846 | void *ecc, int ecclen, | |
2847 | void *extraoob, int extraooblen, | |
2848 | int bitflips_threshold) | |
2849 | { | |
2850 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
2851 | ||
2852 | data_bitflips = nand_check_erased_buf(data, datalen, | |
2853 | bitflips_threshold); | |
2854 | if (data_bitflips < 0) | |
2855 | return data_bitflips; | |
2856 | ||
2857 | bitflips_threshold -= data_bitflips; | |
2858 | ||
2859 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
2860 | if (ecc_bitflips < 0) | |
2861 | return ecc_bitflips; | |
2862 | ||
2863 | bitflips_threshold -= ecc_bitflips; | |
2864 | ||
2865 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
2866 | bitflips_threshold); | |
2867 | if (extraoob_bitflips < 0) | |
2868 | return extraoob_bitflips; | |
2869 | ||
2870 | if (data_bitflips) | |
2871 | memset(data, 0xff, datalen); | |
2872 | ||
2873 | if (ecc_bitflips) | |
2874 | memset(ecc, 0xff, ecclen); | |
2875 | ||
2876 | if (extraoob_bitflips) | |
2877 | memset(extraoob, 0xff, extraooblen); | |
2878 | ||
2879 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
2880 | } | |
2881 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
2882 | ||
8593fbc6 | 2883 | /** |
7854d3f7 | 2884 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
2885 | * @mtd: mtd info structure |
2886 | * @chip: nand chip info structure | |
2887 | * @buf: buffer to store read data | |
1fbb938d | 2888 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 2889 | * @page: page number to read |
52ff49df | 2890 | * |
7854d3f7 | 2891 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2892 | */ |
cc0f51ec TP |
2893 | int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
2894 | uint8_t *buf, int oob_required, int page) | |
8593fbc6 | 2895 | { |
97d90da8 BB |
2896 | int ret; |
2897 | ||
25f815f6 | 2898 | ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); |
97d90da8 BB |
2899 | if (ret) |
2900 | return ret; | |
2901 | ||
2902 | if (oob_required) { | |
2903 | ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, | |
2904 | false); | |
2905 | if (ret) | |
2906 | return ret; | |
2907 | } | |
2908 | ||
8593fbc6 TG |
2909 | return 0; |
2910 | } | |
cc0f51ec | 2911 | EXPORT_SYMBOL(nand_read_page_raw); |
8593fbc6 | 2912 | |
52ff49df | 2913 | /** |
7854d3f7 | 2914 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
2915 | * @mtd: mtd info structure |
2916 | * @chip: nand chip info structure | |
2917 | * @buf: buffer to store read data | |
1fbb938d | 2918 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 2919 | * @page: page number to read |
52ff49df DB |
2920 | * |
2921 | * We need a special oob layout and handling even when OOB isn't used. | |
2922 | */ | |
7351d3a5 | 2923 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2924 | struct nand_chip *chip, uint8_t *buf, |
2925 | int oob_required, int page) | |
52ff49df DB |
2926 | { |
2927 | int eccsize = chip->ecc.size; | |
2928 | int eccbytes = chip->ecc.bytes; | |
2929 | uint8_t *oob = chip->oob_poi; | |
97d90da8 | 2930 | int steps, size, ret; |
52ff49df | 2931 | |
25f815f6 BB |
2932 | ret = nand_read_page_op(chip, page, 0, NULL, 0); |
2933 | if (ret) | |
2934 | return ret; | |
2935 | ||
52ff49df | 2936 | for (steps = chip->ecc.steps; steps > 0; steps--) { |
97d90da8 BB |
2937 | ret = nand_read_data_op(chip, buf, eccsize, false); |
2938 | if (ret) | |
2939 | return ret; | |
2940 | ||
52ff49df DB |
2941 | buf += eccsize; |
2942 | ||
2943 | if (chip->ecc.prepad) { | |
97d90da8 BB |
2944 | ret = nand_read_data_op(chip, oob, chip->ecc.prepad, |
2945 | false); | |
2946 | if (ret) | |
2947 | return ret; | |
2948 | ||
52ff49df DB |
2949 | oob += chip->ecc.prepad; |
2950 | } | |
2951 | ||
97d90da8 BB |
2952 | ret = nand_read_data_op(chip, oob, eccbytes, false); |
2953 | if (ret) | |
2954 | return ret; | |
2955 | ||
52ff49df DB |
2956 | oob += eccbytes; |
2957 | ||
2958 | if (chip->ecc.postpad) { | |
97d90da8 BB |
2959 | ret = nand_read_data_op(chip, oob, chip->ecc.postpad, |
2960 | false); | |
2961 | if (ret) | |
2962 | return ret; | |
2963 | ||
52ff49df DB |
2964 | oob += chip->ecc.postpad; |
2965 | } | |
2966 | } | |
2967 | ||
2968 | size = mtd->oobsize - (oob - chip->oob_poi); | |
97d90da8 BB |
2969 | if (size) { |
2970 | ret = nand_read_data_op(chip, oob, size, false); | |
2971 | if (ret) | |
2972 | return ret; | |
2973 | } | |
52ff49df DB |
2974 | |
2975 | return 0; | |
2976 | } | |
2977 | ||
1da177e4 | 2978 | /** |
7854d3f7 | 2979 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
2980 | * @mtd: mtd info structure |
2981 | * @chip: nand chip info structure | |
2982 | * @buf: buffer to store read data | |
1fbb938d | 2983 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 2984 | * @page: page number to read |
068e3c0a | 2985 | */ |
f5bbdacc | 2986 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2987 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 2988 | { |
846031d3 | 2989 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
2990 | int eccbytes = chip->ecc.bytes; |
2991 | int eccsteps = chip->ecc.steps; | |
2992 | uint8_t *p = buf; | |
c0313b96 MY |
2993 | uint8_t *ecc_calc = chip->ecc.calc_buf; |
2994 | uint8_t *ecc_code = chip->ecc.code_buf; | |
3f91e94f | 2995 | unsigned int max_bitflips = 0; |
f5bbdacc | 2996 | |
1fbb938d | 2997 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
2998 | |
2999 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
3000 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
3001 | ||
846031d3 BB |
3002 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
3003 | chip->ecc.total); | |
3004 | if (ret) | |
3005 | return ret; | |
f5bbdacc TG |
3006 | |
3007 | eccsteps = chip->ecc.steps; | |
3008 | p = buf; | |
3009 | ||
3010 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
3011 | int stat; | |
3012 | ||
3013 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 3014 | if (stat < 0) { |
f5bbdacc | 3015 | mtd->ecc_stats.failed++; |
3f91e94f | 3016 | } else { |
f5bbdacc | 3017 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
3018 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
3019 | } | |
f5bbdacc | 3020 | } |
3f91e94f | 3021 | return max_bitflips; |
22c60f5f | 3022 | } |
1da177e4 | 3023 | |
3d459559 | 3024 | /** |
837a6ba4 | 3025 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
3026 | * @mtd: mtd info structure |
3027 | * @chip: nand chip info structure | |
3028 | * @data_offs: offset of requested data within the page | |
3029 | * @readlen: data length | |
3030 | * @bufpoi: buffer to store read data | |
e004debd | 3031 | * @page: page number to read |
3d459559 | 3032 | */ |
7351d3a5 | 3033 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
3034 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
3035 | int page) | |
3d459559 | 3036 | { |
846031d3 | 3037 | int start_step, end_step, num_steps, ret; |
3d459559 AK |
3038 | uint8_t *p; |
3039 | int data_col_addr, i, gaps = 0; | |
3040 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
3041 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
846031d3 | 3042 | int index, section = 0; |
3f91e94f | 3043 | unsigned int max_bitflips = 0; |
846031d3 | 3044 | struct mtd_oob_region oobregion = { }; |
3d459559 | 3045 | |
7854d3f7 | 3046 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
3047 | start_step = data_offs / chip->ecc.size; |
3048 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
3049 | num_steps = end_step - start_step + 1; | |
4a4163ca | 3050 | index = start_step * chip->ecc.bytes; |
3d459559 | 3051 | |
8b6e50c9 | 3052 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
3053 | datafrag_len = num_steps * chip->ecc.size; |
3054 | eccfrag_len = num_steps * chip->ecc.bytes; | |
3055 | ||
3056 | data_col_addr = start_step * chip->ecc.size; | |
3057 | /* If we read not a page aligned data */ | |
3d459559 | 3058 | p = bufpoi + data_col_addr; |
25f815f6 | 3059 | ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len); |
97d90da8 BB |
3060 | if (ret) |
3061 | return ret; | |
3d459559 | 3062 | |
8b6e50c9 | 3063 | /* Calculate ECC */ |
3d459559 | 3064 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
c0313b96 | 3065 | chip->ecc.calculate(mtd, p, &chip->ecc.calc_buf[i]); |
3d459559 | 3066 | |
8b6e50c9 BN |
3067 | /* |
3068 | * The performance is faster if we position offsets according to | |
7854d3f7 | 3069 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 3070 | */ |
846031d3 BB |
3071 | ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); |
3072 | if (ret) | |
3073 | return ret; | |
3074 | ||
3075 | if (oobregion.length < eccfrag_len) | |
3076 | gaps = 1; | |
3077 | ||
3d459559 | 3078 | if (gaps) { |
97d90da8 BB |
3079 | ret = nand_change_read_column_op(chip, mtd->writesize, |
3080 | chip->oob_poi, mtd->oobsize, | |
3081 | false); | |
3082 | if (ret) | |
3083 | return ret; | |
3d459559 | 3084 | } else { |
8b6e50c9 | 3085 | /* |
7854d3f7 | 3086 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
3087 | * about buswidth alignment in read_buf. |
3088 | */ | |
846031d3 | 3089 | aligned_pos = oobregion.offset & ~(busw - 1); |
3d459559 | 3090 | aligned_len = eccfrag_len; |
846031d3 | 3091 | if (oobregion.offset & (busw - 1)) |
3d459559 | 3092 | aligned_len++; |
846031d3 BB |
3093 | if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & |
3094 | (busw - 1)) | |
3d459559 AK |
3095 | aligned_len++; |
3096 | ||
97d90da8 BB |
3097 | ret = nand_change_read_column_op(chip, |
3098 | mtd->writesize + aligned_pos, | |
3099 | &chip->oob_poi[aligned_pos], | |
3100 | aligned_len, false); | |
3101 | if (ret) | |
3102 | return ret; | |
3d459559 AK |
3103 | } |
3104 | ||
c0313b96 | 3105 | ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, |
846031d3 BB |
3106 | chip->oob_poi, index, eccfrag_len); |
3107 | if (ret) | |
3108 | return ret; | |
3d459559 AK |
3109 | |
3110 | p = bufpoi + data_col_addr; | |
3111 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
3112 | int stat; | |
3113 | ||
c0313b96 MY |
3114 | stat = chip->ecc.correct(mtd, p, &chip->ecc.code_buf[i], |
3115 | &chip->ecc.calc_buf[i]); | |
40cbe6ee BB |
3116 | if (stat == -EBADMSG && |
3117 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
3118 | /* check for empty pages with bitflips */ | |
3119 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
c0313b96 | 3120 | &chip->ecc.code_buf[i], |
40cbe6ee BB |
3121 | chip->ecc.bytes, |
3122 | NULL, 0, | |
3123 | chip->ecc.strength); | |
3124 | } | |
3125 | ||
3f91e94f | 3126 | if (stat < 0) { |
3d459559 | 3127 | mtd->ecc_stats.failed++; |
3f91e94f | 3128 | } else { |
3d459559 | 3129 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
3130 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
3131 | } | |
3d459559 | 3132 | } |
3f91e94f | 3133 | return max_bitflips; |
3d459559 AK |
3134 | } |
3135 | ||
068e3c0a | 3136 | /** |
7854d3f7 | 3137 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
3138 | * @mtd: mtd info structure |
3139 | * @chip: nand chip info structure | |
3140 | * @buf: buffer to store read data | |
1fbb938d | 3141 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 3142 | * @page: page number to read |
068e3c0a | 3143 | * |
7854d3f7 | 3144 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 3145 | */ |
f5bbdacc | 3146 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 3147 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 3148 | { |
846031d3 | 3149 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
3150 | int eccbytes = chip->ecc.bytes; |
3151 | int eccsteps = chip->ecc.steps; | |
3152 | uint8_t *p = buf; | |
c0313b96 MY |
3153 | uint8_t *ecc_calc = chip->ecc.calc_buf; |
3154 | uint8_t *ecc_code = chip->ecc.code_buf; | |
3f91e94f | 3155 | unsigned int max_bitflips = 0; |
f5bbdacc | 3156 | |
25f815f6 BB |
3157 | ret = nand_read_page_op(chip, page, 0, NULL, 0); |
3158 | if (ret) | |
3159 | return ret; | |
3160 | ||
f5bbdacc TG |
3161 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
3162 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
97d90da8 BB |
3163 | |
3164 | ret = nand_read_data_op(chip, p, eccsize, false); | |
3165 | if (ret) | |
3166 | return ret; | |
3167 | ||
f5bbdacc | 3168 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
1da177e4 | 3169 | } |
97d90da8 BB |
3170 | |
3171 | ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false); | |
3172 | if (ret) | |
3173 | return ret; | |
1da177e4 | 3174 | |
846031d3 BB |
3175 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
3176 | chip->ecc.total); | |
3177 | if (ret) | |
3178 | return ret; | |
1da177e4 | 3179 | |
f5bbdacc TG |
3180 | eccsteps = chip->ecc.steps; |
3181 | p = buf; | |
61b03bd7 | 3182 | |
f5bbdacc TG |
3183 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
3184 | int stat; | |
1da177e4 | 3185 | |
f5bbdacc | 3186 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
40cbe6ee BB |
3187 | if (stat == -EBADMSG && |
3188 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
3189 | /* check for empty pages with bitflips */ | |
3190 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
3191 | &ecc_code[i], eccbytes, | |
3192 | NULL, 0, | |
3193 | chip->ecc.strength); | |
3194 | } | |
3195 | ||
3f91e94f | 3196 | if (stat < 0) { |
f5bbdacc | 3197 | mtd->ecc_stats.failed++; |
3f91e94f | 3198 | } else { |
f5bbdacc | 3199 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
3200 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
3201 | } | |
f5bbdacc | 3202 | } |
3f91e94f | 3203 | return max_bitflips; |
f5bbdacc | 3204 | } |
1da177e4 | 3205 | |
6e0cb135 | 3206 | /** |
7854d3f7 | 3207 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
3208 | * @mtd: mtd info structure |
3209 | * @chip: nand chip info structure | |
3210 | * @buf: buffer to store read data | |
1fbb938d | 3211 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 3212 | * @page: page number to read |
6e0cb135 | 3213 | * |
8b6e50c9 BN |
3214 | * Hardware ECC for large page chips, require OOB to be read first. For this |
3215 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
3216 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
3217 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
3218 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
3219 | */ |
3220 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 3221 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 | 3222 | { |
846031d3 | 3223 | int i, eccsize = chip->ecc.size, ret; |
6e0cb135 SN |
3224 | int eccbytes = chip->ecc.bytes; |
3225 | int eccsteps = chip->ecc.steps; | |
3226 | uint8_t *p = buf; | |
c0313b96 MY |
3227 | uint8_t *ecc_code = chip->ecc.code_buf; |
3228 | uint8_t *ecc_calc = chip->ecc.calc_buf; | |
3f91e94f | 3229 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
3230 | |
3231 | /* Read the OOB area first */ | |
97d90da8 BB |
3232 | ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); |
3233 | if (ret) | |
3234 | return ret; | |
3235 | ||
3236 | ret = nand_read_page_op(chip, page, 0, NULL, 0); | |
3237 | if (ret) | |
3238 | return ret; | |
6e0cb135 | 3239 | |
846031d3 BB |
3240 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
3241 | chip->ecc.total); | |
3242 | if (ret) | |
3243 | return ret; | |
6e0cb135 SN |
3244 | |
3245 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
3246 | int stat; | |
3247 | ||
3248 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
97d90da8 BB |
3249 | |
3250 | ret = nand_read_data_op(chip, p, eccsize, false); | |
3251 | if (ret) | |
3252 | return ret; | |
3253 | ||
6e0cb135 SN |
3254 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
3255 | ||
3256 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
40cbe6ee BB |
3257 | if (stat == -EBADMSG && |
3258 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
3259 | /* check for empty pages with bitflips */ | |
3260 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
3261 | &ecc_code[i], eccbytes, | |
3262 | NULL, 0, | |
3263 | chip->ecc.strength); | |
3264 | } | |
3265 | ||
3f91e94f | 3266 | if (stat < 0) { |
6e0cb135 | 3267 | mtd->ecc_stats.failed++; |
3f91e94f | 3268 | } else { |
6e0cb135 | 3269 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
3270 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
3271 | } | |
6e0cb135 | 3272 | } |
3f91e94f | 3273 | return max_bitflips; |
6e0cb135 SN |
3274 | } |
3275 | ||
f5bbdacc | 3276 | /** |
7854d3f7 | 3277 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
3278 | * @mtd: mtd info structure |
3279 | * @chip: nand chip info structure | |
3280 | * @buf: buffer to store read data | |
1fbb938d | 3281 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 3282 | * @page: page number to read |
f5bbdacc | 3283 | * |
8b6e50c9 BN |
3284 | * The hw generator calculates the error syndrome automatically. Therefore we |
3285 | * need a special oob layout and handling. | |
f5bbdacc TG |
3286 | */ |
3287 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 3288 | uint8_t *buf, int oob_required, int page) |
f5bbdacc | 3289 | { |
97d90da8 | 3290 | int ret, i, eccsize = chip->ecc.size; |
f5bbdacc TG |
3291 | int eccbytes = chip->ecc.bytes; |
3292 | int eccsteps = chip->ecc.steps; | |
40cbe6ee | 3293 | int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; |
f5bbdacc | 3294 | uint8_t *p = buf; |
f75e5097 | 3295 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 3296 | unsigned int max_bitflips = 0; |
1da177e4 | 3297 | |
25f815f6 BB |
3298 | ret = nand_read_page_op(chip, page, 0, NULL, 0); |
3299 | if (ret) | |
3300 | return ret; | |
3301 | ||
f5bbdacc TG |
3302 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
3303 | int stat; | |
61b03bd7 | 3304 | |
f5bbdacc | 3305 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
97d90da8 BB |
3306 | |
3307 | ret = nand_read_data_op(chip, p, eccsize, false); | |
3308 | if (ret) | |
3309 | return ret; | |
1da177e4 | 3310 | |
f5bbdacc | 3311 | if (chip->ecc.prepad) { |
97d90da8 BB |
3312 | ret = nand_read_data_op(chip, oob, chip->ecc.prepad, |
3313 | false); | |
3314 | if (ret) | |
3315 | return ret; | |
3316 | ||
f5bbdacc TG |
3317 | oob += chip->ecc.prepad; |
3318 | } | |
1da177e4 | 3319 | |
f5bbdacc | 3320 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
97d90da8 BB |
3321 | |
3322 | ret = nand_read_data_op(chip, oob, eccbytes, false); | |
3323 | if (ret) | |
3324 | return ret; | |
3325 | ||
f5bbdacc | 3326 | stat = chip->ecc.correct(mtd, p, oob, NULL); |
61b03bd7 | 3327 | |
f5bbdacc | 3328 | oob += eccbytes; |
1da177e4 | 3329 | |
f5bbdacc | 3330 | if (chip->ecc.postpad) { |
97d90da8 BB |
3331 | ret = nand_read_data_op(chip, oob, chip->ecc.postpad, |
3332 | false); | |
3333 | if (ret) | |
3334 | return ret; | |
3335 | ||
f5bbdacc | 3336 | oob += chip->ecc.postpad; |
61b03bd7 | 3337 | } |
40cbe6ee BB |
3338 | |
3339 | if (stat == -EBADMSG && | |
3340 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
3341 | /* check for empty pages with bitflips */ | |
3342 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
3343 | oob - eccpadbytes, | |
3344 | eccpadbytes, | |
3345 | NULL, 0, | |
3346 | chip->ecc.strength); | |
3347 | } | |
3348 | ||
3349 | if (stat < 0) { | |
3350 | mtd->ecc_stats.failed++; | |
3351 | } else { | |
3352 | mtd->ecc_stats.corrected += stat; | |
3353 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
3354 | } | |
f5bbdacc | 3355 | } |
1da177e4 | 3356 | |
f5bbdacc | 3357 | /* Calculate remaining oob bytes */ |
7e4178f9 | 3358 | i = mtd->oobsize - (oob - chip->oob_poi); |
97d90da8 BB |
3359 | if (i) { |
3360 | ret = nand_read_data_op(chip, oob, i, false); | |
3361 | if (ret) | |
3362 | return ret; | |
3363 | } | |
61b03bd7 | 3364 | |
3f91e94f | 3365 | return max_bitflips; |
f5bbdacc | 3366 | } |
1da177e4 | 3367 | |
f5bbdacc | 3368 | /** |
7854d3f7 | 3369 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
846031d3 | 3370 | * @mtd: mtd info structure |
8b6e50c9 BN |
3371 | * @oob: oob destination address |
3372 | * @ops: oob ops structure | |
3373 | * @len: size of oob to transfer | |
8593fbc6 | 3374 | */ |
846031d3 | 3375 | static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob, |
7014568b | 3376 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 3377 | { |
846031d3 BB |
3378 | struct nand_chip *chip = mtd_to_nand(mtd); |
3379 | int ret; | |
3380 | ||
f8ac0414 | 3381 | switch (ops->mode) { |
8593fbc6 | 3382 | |
0612b9dd BN |
3383 | case MTD_OPS_PLACE_OOB: |
3384 | case MTD_OPS_RAW: | |
8593fbc6 TG |
3385 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
3386 | return oob + len; | |
3387 | ||
846031d3 BB |
3388 | case MTD_OPS_AUTO_OOB: |
3389 | ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, | |
3390 | ops->ooboffs, len); | |
3391 | BUG_ON(ret); | |
3392 | return oob + len; | |
3393 | ||
8593fbc6 TG |
3394 | default: |
3395 | BUG(); | |
3396 | } | |
3397 | return NULL; | |
3398 | } | |
3399 | ||
ba84fb59 BN |
3400 | /** |
3401 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
3402 | * @mtd: MTD device structure | |
3403 | * @retry_mode: the retry mode to use | |
3404 | * | |
3405 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
3406 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
3407 | * a new threshold, the host should retry reading the page. | |
3408 | */ | |
3409 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
3410 | { | |
862eba51 | 3411 | struct nand_chip *chip = mtd_to_nand(mtd); |
ba84fb59 BN |
3412 | |
3413 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
3414 | ||
3415 | if (retry_mode >= chip->read_retries) | |
3416 | return -EINVAL; | |
3417 | ||
3418 | if (!chip->setup_read_retry) | |
3419 | return -EOPNOTSUPP; | |
3420 | ||
3421 | return chip->setup_read_retry(mtd, retry_mode); | |
3422 | } | |
3423 | ||
8593fbc6 | 3424 | /** |
7854d3f7 | 3425 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
3426 | * @mtd: MTD device structure |
3427 | * @from: offset to read from | |
3428 | * @ops: oob ops structure | |
f5bbdacc TG |
3429 | * |
3430 | * Internal function. Called with chip held. | |
3431 | */ | |
8593fbc6 TG |
3432 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
3433 | struct mtd_oob_ops *ops) | |
f5bbdacc | 3434 | { |
e47f3db4 | 3435 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
862eba51 | 3436 | struct nand_chip *chip = mtd_to_nand(mtd); |
f5bbdacc | 3437 | int ret = 0; |
8593fbc6 | 3438 | uint32_t readlen = ops->len; |
7014568b | 3439 | uint32_t oobreadlen = ops->ooblen; |
29f1058a | 3440 | uint32_t max_oobsize = mtd_oobavail(mtd, ops); |
9aca334e | 3441 | |
8593fbc6 | 3442 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 3443 | int use_bufpoi; |
edbc4540 | 3444 | unsigned int max_bitflips = 0; |
ba84fb59 | 3445 | int retry_mode = 0; |
b72f3dfb | 3446 | bool ecc_fail = false; |
1da177e4 | 3447 | |
f5bbdacc TG |
3448 | chipnr = (int)(from >> chip->chip_shift); |
3449 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 3450 | |
f5bbdacc TG |
3451 | realpage = (int)(from >> chip->page_shift); |
3452 | page = realpage & chip->pagemask; | |
1da177e4 | 3453 | |
f5bbdacc | 3454 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 3455 | |
8593fbc6 TG |
3456 | buf = ops->datbuf; |
3457 | oob = ops->oobbuf; | |
e47f3db4 | 3458 | oob_required = oob ? 1 : 0; |
8593fbc6 | 3459 | |
f8ac0414 | 3460 | while (1) { |
b72f3dfb BN |
3461 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
3462 | ||
f5bbdacc TG |
3463 | bytes = min(mtd->writesize - col, readlen); |
3464 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 3465 | |
66507c7b KD |
3466 | if (!aligned) |
3467 | use_bufpoi = 1; | |
3468 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
3469 | use_bufpoi = !virt_addr_valid(buf) || |
3470 | !IS_ALIGNED((unsigned long)buf, | |
3471 | chip->buf_align); | |
66507c7b KD |
3472 | else |
3473 | use_bufpoi = 0; | |
3474 | ||
8b6e50c9 | 3475 | /* Is the current page in the buffer? */ |
8593fbc6 | 3476 | if (realpage != chip->pagebuf || oob) { |
c0313b96 | 3477 | bufpoi = use_bufpoi ? chip->data_buf : buf; |
66507c7b KD |
3478 | |
3479 | if (use_bufpoi && aligned) | |
3480 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
3481 | __func__, buf); | |
61b03bd7 | 3482 | |
ba84fb59 | 3483 | read_retry: |
edbc4540 MD |
3484 | /* |
3485 | * Now read the page into the buffer. Absent an error, | |
3486 | * the read methods return max bitflips per ecc step. | |
3487 | */ | |
0612b9dd | 3488 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 3489 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
3490 | oob_required, |
3491 | page); | |
a5ff4f10 JW |
3492 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
3493 | !oob) | |
7351d3a5 | 3494 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
3495 | col, bytes, bufpoi, |
3496 | page); | |
956e944c | 3497 | else |
46a8cf2d | 3498 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 3499 | oob_required, page); |
6d77b9d0 | 3500 | if (ret < 0) { |
66507c7b | 3501 | if (use_bufpoi) |
6d77b9d0 BN |
3502 | /* Invalidate page cache */ |
3503 | chip->pagebuf = -1; | |
1da177e4 | 3504 | break; |
6d77b9d0 | 3505 | } |
f5bbdacc TG |
3506 | |
3507 | /* Transfer not aligned data */ | |
66507c7b | 3508 | if (use_bufpoi) { |
a5ff4f10 | 3509 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 3510 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 3511 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 3512 | chip->pagebuf = realpage; |
edbc4540 MD |
3513 | chip->pagebuf_bitflips = ret; |
3514 | } else { | |
6d77b9d0 BN |
3515 | /* Invalidate page cache */ |
3516 | chip->pagebuf = -1; | |
edbc4540 | 3517 | } |
c0313b96 | 3518 | memcpy(buf, chip->data_buf + col, bytes); |
f5bbdacc TG |
3519 | } |
3520 | ||
8593fbc6 | 3521 | if (unlikely(oob)) { |
b64d39d8 ML |
3522 | int toread = min(oobreadlen, max_oobsize); |
3523 | ||
3524 | if (toread) { | |
846031d3 | 3525 | oob = nand_transfer_oob(mtd, |
b64d39d8 ML |
3526 | oob, ops, toread); |
3527 | oobreadlen -= toread; | |
3528 | } | |
8593fbc6 | 3529 | } |
5bc7c33c BN |
3530 | |
3531 | if (chip->options & NAND_NEED_READRDY) { | |
3532 | /* Apply delay or wait for ready/busy pin */ | |
3533 | if (!chip->dev_ready) | |
3534 | udelay(chip->chip_delay); | |
3535 | else | |
3536 | nand_wait_ready(mtd); | |
3537 | } | |
b72f3dfb | 3538 | |
ba84fb59 | 3539 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 3540 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
3541 | retry_mode++; |
3542 | ret = nand_setup_read_retry(mtd, | |
3543 | retry_mode); | |
3544 | if (ret < 0) | |
3545 | break; | |
3546 | ||
3547 | /* Reset failures; retry */ | |
3548 | mtd->ecc_stats.failed = ecc_failures; | |
3549 | goto read_retry; | |
3550 | } else { | |
3551 | /* No more retry modes; real failure */ | |
3552 | ecc_fail = true; | |
3553 | } | |
3554 | } | |
3555 | ||
3556 | buf += bytes; | |
07604686 | 3557 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
8593fbc6 | 3558 | } else { |
c0313b96 | 3559 | memcpy(buf, chip->data_buf + col, bytes); |
8593fbc6 | 3560 | buf += bytes; |
edbc4540 MD |
3561 | max_bitflips = max_t(unsigned int, max_bitflips, |
3562 | chip->pagebuf_bitflips); | |
8593fbc6 | 3563 | } |
1da177e4 | 3564 | |
f5bbdacc | 3565 | readlen -= bytes; |
61b03bd7 | 3566 | |
ba84fb59 BN |
3567 | /* Reset to retry mode 0 */ |
3568 | if (retry_mode) { | |
3569 | ret = nand_setup_read_retry(mtd, 0); | |
3570 | if (ret < 0) | |
3571 | break; | |
3572 | retry_mode = 0; | |
3573 | } | |
3574 | ||
f5bbdacc | 3575 | if (!readlen) |
61b03bd7 | 3576 | break; |
1da177e4 | 3577 | |
8b6e50c9 | 3578 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
3579 | col = 0; |
3580 | /* Increment page address */ | |
3581 | realpage++; | |
3582 | ||
ace4dfee | 3583 | page = realpage & chip->pagemask; |
1da177e4 LT |
3584 | /* Check, if we cross a chip boundary */ |
3585 | if (!page) { | |
3586 | chipnr++; | |
ace4dfee TG |
3587 | chip->select_chip(mtd, -1); |
3588 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 3589 | } |
1da177e4 | 3590 | } |
b0bb6903 | 3591 | chip->select_chip(mtd, -1); |
1da177e4 | 3592 | |
8593fbc6 | 3593 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
3594 | if (oob) |
3595 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 3596 | |
3f91e94f | 3597 | if (ret < 0) |
f5bbdacc TG |
3598 | return ret; |
3599 | ||
b72f3dfb | 3600 | if (ecc_fail) |
9a1fcdfd TG |
3601 | return -EBADMSG; |
3602 | ||
edbc4540 | 3603 | return max_bitflips; |
f5bbdacc TG |
3604 | } |
3605 | ||
3606 | /** | |
25985edc | 3607 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
3608 | * @mtd: MTD device structure |
3609 | * @from: offset to read from | |
3610 | * @len: number of bytes to read | |
3611 | * @retlen: pointer to variable to store the number of read bytes | |
3612 | * @buf: the databuffer to put data | |
f5bbdacc | 3613 | * |
8b6e50c9 | 3614 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
3615 | */ |
3616 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
3617 | size_t *retlen, uint8_t *buf) | |
3618 | { | |
4a89ff88 | 3619 | struct mtd_oob_ops ops; |
f5bbdacc TG |
3620 | int ret; |
3621 | ||
6a8214aa | 3622 | nand_get_device(mtd, FL_READING); |
0ec56dc4 | 3623 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
3624 | ops.len = len; |
3625 | ops.datbuf = buf; | |
11041ae6 | 3626 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 3627 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 3628 | *retlen = ops.retlen; |
f5bbdacc | 3629 | nand_release_device(mtd); |
f5bbdacc | 3630 | return ret; |
1da177e4 LT |
3631 | } |
3632 | ||
7bc3312b | 3633 | /** |
7854d3f7 | 3634 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
3635 | * @mtd: mtd info structure |
3636 | * @chip: nand chip info structure | |
3637 | * @page: page number to read | |
7bc3312b | 3638 | */ |
9d02fc2a | 3639 | int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b | 3640 | { |
97d90da8 | 3641 | return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); |
7bc3312b | 3642 | } |
9d02fc2a | 3643 | EXPORT_SYMBOL(nand_read_oob_std); |
7bc3312b TG |
3644 | |
3645 | /** | |
7854d3f7 | 3646 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 3647 | * with syndromes |
8b6e50c9 BN |
3648 | * @mtd: mtd info structure |
3649 | * @chip: nand chip info structure | |
3650 | * @page: page number to read | |
7bc3312b | 3651 | */ |
9d02fc2a BB |
3652 | int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
3653 | int page) | |
7bc3312b | 3654 | { |
7bc3312b TG |
3655 | int length = mtd->oobsize; |
3656 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
3657 | int eccsize = chip->ecc.size; | |
2ea69d21 | 3658 | uint8_t *bufpoi = chip->oob_poi; |
97d90da8 BB |
3659 | int i, toread, sndrnd = 0, pos, ret; |
3660 | ||
3661 | ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); | |
3662 | if (ret) | |
3663 | return ret; | |
7bc3312b | 3664 | |
7bc3312b TG |
3665 | for (i = 0; i < chip->ecc.steps; i++) { |
3666 | if (sndrnd) { | |
97d90da8 BB |
3667 | int ret; |
3668 | ||
7bc3312b TG |
3669 | pos = eccsize + i * (eccsize + chunk); |
3670 | if (mtd->writesize > 512) | |
97d90da8 BB |
3671 | ret = nand_change_read_column_op(chip, pos, |
3672 | NULL, 0, | |
3673 | false); | |
7bc3312b | 3674 | else |
97d90da8 BB |
3675 | ret = nand_read_page_op(chip, page, pos, NULL, |
3676 | 0); | |
3677 | ||
3678 | if (ret) | |
3679 | return ret; | |
7bc3312b TG |
3680 | } else |
3681 | sndrnd = 1; | |
3682 | toread = min_t(int, length, chunk); | |
97d90da8 BB |
3683 | |
3684 | ret = nand_read_data_op(chip, bufpoi, toread, false); | |
3685 | if (ret) | |
3686 | return ret; | |
3687 | ||
7bc3312b TG |
3688 | bufpoi += toread; |
3689 | length -= toread; | |
3690 | } | |
97d90da8 BB |
3691 | if (length > 0) { |
3692 | ret = nand_read_data_op(chip, bufpoi, length, false); | |
3693 | if (ret) | |
3694 | return ret; | |
3695 | } | |
7bc3312b | 3696 | |
5c2ffb11 | 3697 | return 0; |
7bc3312b | 3698 | } |
9d02fc2a | 3699 | EXPORT_SYMBOL(nand_read_oob_syndrome); |
7bc3312b TG |
3700 | |
3701 | /** | |
7854d3f7 | 3702 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
3703 | * @mtd: mtd info structure |
3704 | * @chip: nand chip info structure | |
3705 | * @page: page number to write | |
7bc3312b | 3706 | */ |
9d02fc2a | 3707 | int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b | 3708 | { |
97d90da8 BB |
3709 | return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, |
3710 | mtd->oobsize); | |
7bc3312b | 3711 | } |
9d02fc2a | 3712 | EXPORT_SYMBOL(nand_write_oob_std); |
7bc3312b TG |
3713 | |
3714 | /** | |
7854d3f7 | 3715 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
3716 | * with syndrome - only for large page flash |
3717 | * @mtd: mtd info structure | |
3718 | * @chip: nand chip info structure | |
3719 | * @page: page number to write | |
7bc3312b | 3720 | */ |
9d02fc2a BB |
3721 | int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
3722 | int page) | |
7bc3312b TG |
3723 | { |
3724 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
3725 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
97d90da8 | 3726 | int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; |
7bc3312b TG |
3727 | const uint8_t *bufpoi = chip->oob_poi; |
3728 | ||
3729 | /* | |
3730 | * data-ecc-data-ecc ... ecc-oob | |
3731 | * or | |
3732 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
3733 | */ | |
3734 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
3735 | pos = steps * (eccsize + chunk); | |
3736 | steps = 0; | |
3737 | } else | |
8b0036ee | 3738 | pos = eccsize; |
7bc3312b | 3739 | |
97d90da8 BB |
3740 | ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0); |
3741 | if (ret) | |
3742 | return ret; | |
3743 | ||
7bc3312b TG |
3744 | for (i = 0; i < steps; i++) { |
3745 | if (sndcmd) { | |
3746 | if (mtd->writesize <= 512) { | |
3747 | uint32_t fill = 0xFFFFFFFF; | |
3748 | ||
3749 | len = eccsize; | |
3750 | while (len > 0) { | |
3751 | int num = min_t(int, len, 4); | |
97d90da8 BB |
3752 | |
3753 | ret = nand_write_data_op(chip, &fill, | |
3754 | num, false); | |
3755 | if (ret) | |
3756 | return ret; | |
3757 | ||
7bc3312b TG |
3758 | len -= num; |
3759 | } | |
3760 | } else { | |
3761 | pos = eccsize + i * (eccsize + chunk); | |
97d90da8 BB |
3762 | ret = nand_change_write_column_op(chip, pos, |
3763 | NULL, 0, | |
3764 | false); | |
3765 | if (ret) | |
3766 | return ret; | |
7bc3312b TG |
3767 | } |
3768 | } else | |
3769 | sndcmd = 1; | |
3770 | len = min_t(int, length, chunk); | |
97d90da8 BB |
3771 | |
3772 | ret = nand_write_data_op(chip, bufpoi, len, false); | |
3773 | if (ret) | |
3774 | return ret; | |
3775 | ||
7bc3312b TG |
3776 | bufpoi += len; |
3777 | length -= len; | |
3778 | } | |
97d90da8 BB |
3779 | if (length > 0) { |
3780 | ret = nand_write_data_op(chip, bufpoi, length, false); | |
3781 | if (ret) | |
3782 | return ret; | |
3783 | } | |
7bc3312b | 3784 | |
97d90da8 | 3785 | return nand_prog_page_end_op(chip); |
7bc3312b | 3786 | } |
9d02fc2a | 3787 | EXPORT_SYMBOL(nand_write_oob_syndrome); |
7bc3312b | 3788 | |
1da177e4 | 3789 | /** |
7854d3f7 | 3790 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
3791 | * @mtd: MTD device structure |
3792 | * @from: offset to read from | |
3793 | * @ops: oob operations description structure | |
1da177e4 | 3794 | * |
8b6e50c9 | 3795 | * NAND read out-of-band data from the spare area. |
1da177e4 | 3796 | */ |
8593fbc6 TG |
3797 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
3798 | struct mtd_oob_ops *ops) | |
1da177e4 | 3799 | { |
c00a0991 | 3800 | int page, realpage, chipnr; |
862eba51 | 3801 | struct nand_chip *chip = mtd_to_nand(mtd); |
041e4575 | 3802 | struct mtd_ecc_stats stats; |
7014568b VW |
3803 | int readlen = ops->ooblen; |
3804 | int len; | |
7bc3312b | 3805 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 3806 | int ret = 0; |
61b03bd7 | 3807 | |
289c0522 | 3808 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 3809 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 3810 | |
041e4575 BN |
3811 | stats = mtd->ecc_stats; |
3812 | ||
29f1058a | 3813 | len = mtd_oobavail(mtd, ops); |
03736155 AH |
3814 | |
3815 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
3816 | pr_debug("%s: attempt to start read outside oob\n", |
3817 | __func__); | |
03736155 AH |
3818 | return -EINVAL; |
3819 | } | |
3820 | ||
3821 | /* Do not allow reads past end of device */ | |
3822 | if (unlikely(from >= mtd->size || | |
3823 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
3824 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
3825 | pr_debug("%s: attempt to read beyond end of device\n", |
3826 | __func__); | |
03736155 AH |
3827 | return -EINVAL; |
3828 | } | |
7014568b | 3829 | |
7314e9e7 | 3830 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 3831 | chip->select_chip(mtd, chipnr); |
1da177e4 | 3832 | |
7314e9e7 TG |
3833 | /* Shift to get page */ |
3834 | realpage = (int)(from >> chip->page_shift); | |
3835 | page = realpage & chip->pagemask; | |
1da177e4 | 3836 | |
f8ac0414 | 3837 | while (1) { |
0612b9dd | 3838 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 3839 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 3840 | else |
1951f2f7 SL |
3841 | ret = chip->ecc.read_oob(mtd, chip, page); |
3842 | ||
3843 | if (ret < 0) | |
3844 | break; | |
7014568b VW |
3845 | |
3846 | len = min(len, readlen); | |
846031d3 | 3847 | buf = nand_transfer_oob(mtd, buf, ops, len); |
8593fbc6 | 3848 | |
5bc7c33c BN |
3849 | if (chip->options & NAND_NEED_READRDY) { |
3850 | /* Apply delay or wait for ready/busy pin */ | |
3851 | if (!chip->dev_ready) | |
3852 | udelay(chip->chip_delay); | |
3853 | else | |
3854 | nand_wait_ready(mtd); | |
3855 | } | |
3856 | ||
7014568b | 3857 | readlen -= len; |
0d420f9d SZ |
3858 | if (!readlen) |
3859 | break; | |
3860 | ||
7314e9e7 TG |
3861 | /* Increment page address */ |
3862 | realpage++; | |
3863 | ||
3864 | page = realpage & chip->pagemask; | |
3865 | /* Check, if we cross a chip boundary */ | |
3866 | if (!page) { | |
3867 | chipnr++; | |
3868 | chip->select_chip(mtd, -1); | |
3869 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
3870 | } |
3871 | } | |
b0bb6903 | 3872 | chip->select_chip(mtd, -1); |
1da177e4 | 3873 | |
1951f2f7 SL |
3874 | ops->oobretlen = ops->ooblen - readlen; |
3875 | ||
3876 | if (ret < 0) | |
3877 | return ret; | |
041e4575 BN |
3878 | |
3879 | if (mtd->ecc_stats.failed - stats.failed) | |
3880 | return -EBADMSG; | |
3881 | ||
3882 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
3883 | } |
3884 | ||
3885 | /** | |
8593fbc6 | 3886 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
3887 | * @mtd: MTD device structure |
3888 | * @from: offset to read from | |
3889 | * @ops: oob operation description structure | |
1da177e4 | 3890 | * |
8b6e50c9 | 3891 | * NAND read data and/or out-of-band data. |
1da177e4 | 3892 | */ |
8593fbc6 TG |
3893 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
3894 | struct mtd_oob_ops *ops) | |
1da177e4 | 3895 | { |
fc6b4d12 | 3896 | int ret; |
8593fbc6 TG |
3897 | |
3898 | ops->retlen = 0; | |
1da177e4 LT |
3899 | |
3900 | /* Do not allow reads past end of device */ | |
7014568b | 3901 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
3902 | pr_debug("%s: attempt to read beyond end of device\n", |
3903 | __func__); | |
1da177e4 LT |
3904 | return -EINVAL; |
3905 | } | |
3906 | ||
fc6b4d12 AS |
3907 | if (ops->mode != MTD_OPS_PLACE_OOB && |
3908 | ops->mode != MTD_OPS_AUTO_OOB && | |
3909 | ops->mode != MTD_OPS_RAW) | |
3910 | return -ENOTSUPP; | |
1da177e4 | 3911 | |
fc6b4d12 | 3912 | nand_get_device(mtd, FL_READING); |
1da177e4 | 3913 | |
8593fbc6 TG |
3914 | if (!ops->datbuf) |
3915 | ret = nand_do_read_oob(mtd, from, ops); | |
3916 | else | |
3917 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 3918 | |
8593fbc6 TG |
3919 | nand_release_device(mtd); |
3920 | return ret; | |
3921 | } | |
61b03bd7 | 3922 | |
1da177e4 | 3923 | |
8593fbc6 | 3924 | /** |
7854d3f7 | 3925 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
3926 | * @mtd: mtd info structure |
3927 | * @chip: nand chip info structure | |
3928 | * @buf: data buffer | |
1fbb938d | 3929 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 3930 | * @page: page number to write |
52ff49df | 3931 | * |
7854d3f7 | 3932 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 3933 | */ |
cc0f51ec TP |
3934 | int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
3935 | const uint8_t *buf, int oob_required, int page) | |
8593fbc6 | 3936 | { |
97d90da8 BB |
3937 | int ret; |
3938 | ||
25f815f6 | 3939 | ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); |
97d90da8 BB |
3940 | if (ret) |
3941 | return ret; | |
3942 | ||
3943 | if (oob_required) { | |
3944 | ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, | |
3945 | false); | |
3946 | if (ret) | |
3947 | return ret; | |
3948 | } | |
fdbad98d | 3949 | |
25f815f6 | 3950 | return nand_prog_page_end_op(chip); |
1da177e4 | 3951 | } |
cc0f51ec | 3952 | EXPORT_SYMBOL(nand_write_page_raw); |
1da177e4 | 3953 | |
52ff49df | 3954 | /** |
7854d3f7 | 3955 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
3956 | * @mtd: mtd info structure |
3957 | * @chip: nand chip info structure | |
3958 | * @buf: data buffer | |
1fbb938d | 3959 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 3960 | * @page: page number to write |
52ff49df DB |
3961 | * |
3962 | * We need a special oob layout and handling even when ECC isn't checked. | |
3963 | */ | |
fdbad98d | 3964 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 3965 | struct nand_chip *chip, |
45aaeff9 BB |
3966 | const uint8_t *buf, int oob_required, |
3967 | int page) | |
52ff49df DB |
3968 | { |
3969 | int eccsize = chip->ecc.size; | |
3970 | int eccbytes = chip->ecc.bytes; | |
3971 | uint8_t *oob = chip->oob_poi; | |
97d90da8 | 3972 | int steps, size, ret; |
52ff49df | 3973 | |
25f815f6 BB |
3974 | ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
3975 | if (ret) | |
3976 | return ret; | |
3977 | ||
52ff49df | 3978 | for (steps = chip->ecc.steps; steps > 0; steps--) { |
97d90da8 BB |
3979 | ret = nand_write_data_op(chip, buf, eccsize, false); |
3980 | if (ret) | |
3981 | return ret; | |
3982 | ||
52ff49df DB |
3983 | buf += eccsize; |
3984 | ||
3985 | if (chip->ecc.prepad) { | |
97d90da8 BB |
3986 | ret = nand_write_data_op(chip, oob, chip->ecc.prepad, |
3987 | false); | |
3988 | if (ret) | |
3989 | return ret; | |
3990 | ||
52ff49df DB |
3991 | oob += chip->ecc.prepad; |
3992 | } | |
3993 | ||
97d90da8 BB |
3994 | ret = nand_write_data_op(chip, oob, eccbytes, false); |
3995 | if (ret) | |
3996 | return ret; | |
3997 | ||
52ff49df DB |
3998 | oob += eccbytes; |
3999 | ||
4000 | if (chip->ecc.postpad) { | |
97d90da8 BB |
4001 | ret = nand_write_data_op(chip, oob, chip->ecc.postpad, |
4002 | false); | |
4003 | if (ret) | |
4004 | return ret; | |
4005 | ||
52ff49df DB |
4006 | oob += chip->ecc.postpad; |
4007 | } | |
4008 | } | |
4009 | ||
4010 | size = mtd->oobsize - (oob - chip->oob_poi); | |
97d90da8 BB |
4011 | if (size) { |
4012 | ret = nand_write_data_op(chip, oob, size, false); | |
4013 | if (ret) | |
4014 | return ret; | |
4015 | } | |
fdbad98d | 4016 | |
25f815f6 | 4017 | return nand_prog_page_end_op(chip); |
52ff49df | 4018 | } |
9223a456 | 4019 | /** |
7854d3f7 | 4020 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
4021 | * @mtd: mtd info structure |
4022 | * @chip: nand chip info structure | |
4023 | * @buf: data buffer | |
1fbb938d | 4024 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 4025 | * @page: page number to write |
9223a456 | 4026 | */ |
fdbad98d | 4027 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
4028 | const uint8_t *buf, int oob_required, |
4029 | int page) | |
9223a456 | 4030 | { |
846031d3 | 4031 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
4032 | int eccbytes = chip->ecc.bytes; |
4033 | int eccsteps = chip->ecc.steps; | |
c0313b96 | 4034 | uint8_t *ecc_calc = chip->ecc.calc_buf; |
f75e5097 | 4035 | const uint8_t *p = buf; |
9223a456 | 4036 | |
7854d3f7 | 4037 | /* Software ECC calculation */ |
8593fbc6 TG |
4038 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
4039 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 4040 | |
846031d3 BB |
4041 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
4042 | chip->ecc.total); | |
4043 | if (ret) | |
4044 | return ret; | |
9223a456 | 4045 | |
45aaeff9 | 4046 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
f75e5097 | 4047 | } |
9223a456 | 4048 | |
f75e5097 | 4049 | /** |
7854d3f7 | 4050 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
4051 | * @mtd: mtd info structure |
4052 | * @chip: nand chip info structure | |
4053 | * @buf: data buffer | |
1fbb938d | 4054 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 4055 | * @page: page number to write |
f75e5097 | 4056 | */ |
fdbad98d | 4057 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
4058 | const uint8_t *buf, int oob_required, |
4059 | int page) | |
f75e5097 | 4060 | { |
846031d3 | 4061 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
4062 | int eccbytes = chip->ecc.bytes; |
4063 | int eccsteps = chip->ecc.steps; | |
c0313b96 | 4064 | uint8_t *ecc_calc = chip->ecc.calc_buf; |
f75e5097 | 4065 | const uint8_t *p = buf; |
9223a456 | 4066 | |
25f815f6 BB |
4067 | ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
4068 | if (ret) | |
4069 | return ret; | |
4070 | ||
f75e5097 TG |
4071 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
4072 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
97d90da8 BB |
4073 | |
4074 | ret = nand_write_data_op(chip, p, eccsize, false); | |
4075 | if (ret) | |
4076 | return ret; | |
4077 | ||
f75e5097 | 4078 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
4079 | } |
4080 | ||
846031d3 BB |
4081 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
4082 | chip->ecc.total); | |
4083 | if (ret) | |
4084 | return ret; | |
f75e5097 | 4085 | |
97d90da8 BB |
4086 | ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); |
4087 | if (ret) | |
4088 | return ret; | |
fdbad98d | 4089 | |
25f815f6 | 4090 | return nand_prog_page_end_op(chip); |
9223a456 TG |
4091 | } |
4092 | ||
837a6ba4 GP |
4093 | |
4094 | /** | |
73c8aaf4 | 4095 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
4096 | * @mtd: mtd info structure |
4097 | * @chip: nand chip info structure | |
d6a95080 | 4098 | * @offset: column address of subpage within the page |
837a6ba4 | 4099 | * @data_len: data length |
d6a95080 | 4100 | * @buf: data buffer |
837a6ba4 | 4101 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 4102 | * @page: page number to write |
837a6ba4 GP |
4103 | */ |
4104 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
4105 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 4106 | uint32_t data_len, const uint8_t *buf, |
45aaeff9 | 4107 | int oob_required, int page) |
837a6ba4 GP |
4108 | { |
4109 | uint8_t *oob_buf = chip->oob_poi; | |
c0313b96 | 4110 | uint8_t *ecc_calc = chip->ecc.calc_buf; |
837a6ba4 GP |
4111 | int ecc_size = chip->ecc.size; |
4112 | int ecc_bytes = chip->ecc.bytes; | |
4113 | int ecc_steps = chip->ecc.steps; | |
837a6ba4 GP |
4114 | uint32_t start_step = offset / ecc_size; |
4115 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
4116 | int oob_bytes = mtd->oobsize / ecc_steps; | |
846031d3 | 4117 | int step, ret; |
837a6ba4 | 4118 | |
25f815f6 BB |
4119 | ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
4120 | if (ret) | |
4121 | return ret; | |
4122 | ||
837a6ba4 GP |
4123 | for (step = 0; step < ecc_steps; step++) { |
4124 | /* configure controller for WRITE access */ | |
4125 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
4126 | ||
4127 | /* write data (untouched subpages already masked by 0xFF) */ | |
97d90da8 BB |
4128 | ret = nand_write_data_op(chip, buf, ecc_size, false); |
4129 | if (ret) | |
4130 | return ret; | |
837a6ba4 GP |
4131 | |
4132 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
4133 | if ((step < start_step) || (step > end_step)) | |
4134 | memset(ecc_calc, 0xff, ecc_bytes); | |
4135 | else | |
d6a95080 | 4136 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
4137 | |
4138 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
4139 | /* if oob_required, preserve OOB metadata of written subpage */ | |
4140 | if (!oob_required || (step < start_step) || (step > end_step)) | |
4141 | memset(oob_buf, 0xff, oob_bytes); | |
4142 | ||
d6a95080 | 4143 | buf += ecc_size; |
837a6ba4 GP |
4144 | ecc_calc += ecc_bytes; |
4145 | oob_buf += oob_bytes; | |
4146 | } | |
4147 | ||
4148 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
4149 | /* this include masked-value(0xFF) for unwritten subpages */ | |
c0313b96 | 4150 | ecc_calc = chip->ecc.calc_buf; |
846031d3 BB |
4151 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
4152 | chip->ecc.total); | |
4153 | if (ret) | |
4154 | return ret; | |
837a6ba4 GP |
4155 | |
4156 | /* write OOB buffer to NAND device */ | |
97d90da8 BB |
4157 | ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); |
4158 | if (ret) | |
4159 | return ret; | |
837a6ba4 | 4160 | |
25f815f6 | 4161 | return nand_prog_page_end_op(chip); |
837a6ba4 GP |
4162 | } |
4163 | ||
4164 | ||
61b03bd7 | 4165 | /** |
7854d3f7 | 4166 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
4167 | * @mtd: mtd info structure |
4168 | * @chip: nand chip info structure | |
4169 | * @buf: data buffer | |
1fbb938d | 4170 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 4171 | * @page: page number to write |
1da177e4 | 4172 | * |
8b6e50c9 BN |
4173 | * The hw generator calculates the error syndrome automatically. Therefore we |
4174 | * need a special oob layout and handling. | |
f75e5097 | 4175 | */ |
fdbad98d | 4176 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d | 4177 | struct nand_chip *chip, |
45aaeff9 BB |
4178 | const uint8_t *buf, int oob_required, |
4179 | int page) | |
1da177e4 | 4180 | { |
f75e5097 TG |
4181 | int i, eccsize = chip->ecc.size; |
4182 | int eccbytes = chip->ecc.bytes; | |
4183 | int eccsteps = chip->ecc.steps; | |
4184 | const uint8_t *p = buf; | |
4185 | uint8_t *oob = chip->oob_poi; | |
97d90da8 | 4186 | int ret; |
1da177e4 | 4187 | |
25f815f6 BB |
4188 | ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
4189 | if (ret) | |
4190 | return ret; | |
4191 | ||
f75e5097 | 4192 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
f75e5097 | 4193 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
97d90da8 BB |
4194 | |
4195 | ret = nand_write_data_op(chip, p, eccsize, false); | |
4196 | if (ret) | |
4197 | return ret; | |
61b03bd7 | 4198 | |
f75e5097 | 4199 | if (chip->ecc.prepad) { |
97d90da8 BB |
4200 | ret = nand_write_data_op(chip, oob, chip->ecc.prepad, |
4201 | false); | |
4202 | if (ret) | |
4203 | return ret; | |
4204 | ||
f75e5097 TG |
4205 | oob += chip->ecc.prepad; |
4206 | } | |
4207 | ||
4208 | chip->ecc.calculate(mtd, p, oob); | |
97d90da8 BB |
4209 | |
4210 | ret = nand_write_data_op(chip, oob, eccbytes, false); | |
4211 | if (ret) | |
4212 | return ret; | |
4213 | ||
f75e5097 TG |
4214 | oob += eccbytes; |
4215 | ||
4216 | if (chip->ecc.postpad) { | |
97d90da8 BB |
4217 | ret = nand_write_data_op(chip, oob, chip->ecc.postpad, |
4218 | false); | |
4219 | if (ret) | |
4220 | return ret; | |
4221 | ||
f75e5097 | 4222 | oob += chip->ecc.postpad; |
1da177e4 | 4223 | } |
1da177e4 | 4224 | } |
f75e5097 TG |
4225 | |
4226 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 4227 | i = mtd->oobsize - (oob - chip->oob_poi); |
97d90da8 BB |
4228 | if (i) { |
4229 | ret = nand_write_data_op(chip, oob, i, false); | |
4230 | if (ret) | |
4231 | return ret; | |
4232 | } | |
fdbad98d | 4233 | |
25f815f6 | 4234 | return nand_prog_page_end_op(chip); |
f75e5097 TG |
4235 | } |
4236 | ||
4237 | /** | |
f107d7a4 | 4238 | * nand_write_page - write one page |
8b6e50c9 BN |
4239 | * @mtd: MTD device structure |
4240 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
4241 | * @offset: address offset within the page |
4242 | * @data_len: length of actual data to be written | |
8b6e50c9 | 4243 | * @buf: the data to write |
1fbb938d | 4244 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 | 4245 | * @page: page number to write |
8b6e50c9 | 4246 | * @raw: use _raw version of write_page |
f75e5097 TG |
4247 | */ |
4248 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 | 4249 | uint32_t offset, int data_len, const uint8_t *buf, |
0b4773fd | 4250 | int oob_required, int page, int raw) |
f75e5097 | 4251 | { |
837a6ba4 GP |
4252 | int status, subpage; |
4253 | ||
4254 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
4255 | chip->ecc.write_subpage) | |
4256 | subpage = offset || (data_len < mtd->writesize); | |
4257 | else | |
4258 | subpage = 0; | |
f75e5097 | 4259 | |
956e944c | 4260 | if (unlikely(raw)) |
837a6ba4 | 4261 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
45aaeff9 | 4262 | oob_required, page); |
837a6ba4 GP |
4263 | else if (subpage) |
4264 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
45aaeff9 | 4265 | buf, oob_required, page); |
956e944c | 4266 | else |
45aaeff9 BB |
4267 | status = chip->ecc.write_page(mtd, chip, buf, oob_required, |
4268 | page); | |
fdbad98d JW |
4269 | |
4270 | if (status < 0) | |
4271 | return status; | |
f75e5097 | 4272 | |
f75e5097 | 4273 | return 0; |
1da177e4 LT |
4274 | } |
4275 | ||
8593fbc6 | 4276 | /** |
7854d3f7 | 4277 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 4278 | * @mtd: MTD device structure |
8b6e50c9 BN |
4279 | * @oob: oob data buffer |
4280 | * @len: oob data write length | |
4281 | * @ops: oob ops structure | |
8593fbc6 | 4282 | */ |
f722013e TAA |
4283 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
4284 | struct mtd_oob_ops *ops) | |
8593fbc6 | 4285 | { |
862eba51 | 4286 | struct nand_chip *chip = mtd_to_nand(mtd); |
846031d3 | 4287 | int ret; |
f722013e TAA |
4288 | |
4289 | /* | |
4290 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
4291 | * data from a previous OOB read. | |
4292 | */ | |
4293 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
4294 | ||
f8ac0414 | 4295 | switch (ops->mode) { |
8593fbc6 | 4296 | |
0612b9dd BN |
4297 | case MTD_OPS_PLACE_OOB: |
4298 | case MTD_OPS_RAW: | |
8593fbc6 TG |
4299 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
4300 | return oob + len; | |
4301 | ||
846031d3 BB |
4302 | case MTD_OPS_AUTO_OOB: |
4303 | ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, | |
4304 | ops->ooboffs, len); | |
4305 | BUG_ON(ret); | |
4306 | return oob + len; | |
4307 | ||
8593fbc6 TG |
4308 | default: |
4309 | BUG(); | |
4310 | } | |
4311 | return NULL; | |
4312 | } | |
4313 | ||
f8ac0414 | 4314 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
4315 | |
4316 | /** | |
7854d3f7 | 4317 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
4318 | * @mtd: MTD device structure |
4319 | * @to: offset to write to | |
4320 | * @ops: oob operations description structure | |
1da177e4 | 4321 | * |
8b6e50c9 | 4322 | * NAND write with ECC. |
1da177e4 | 4323 | */ |
8593fbc6 TG |
4324 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
4325 | struct mtd_oob_ops *ops) | |
1da177e4 | 4326 | { |
73600b61 | 4327 | int chipnr, realpage, page, column; |
862eba51 | 4328 | struct nand_chip *chip = mtd_to_nand(mtd); |
8593fbc6 | 4329 | uint32_t writelen = ops->len; |
782ce79a ML |
4330 | |
4331 | uint32_t oobwritelen = ops->ooblen; | |
29f1058a | 4332 | uint32_t oobmaxlen = mtd_oobavail(mtd, ops); |
782ce79a | 4333 | |
8593fbc6 TG |
4334 | uint8_t *oob = ops->oobbuf; |
4335 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 4336 | int ret; |
e47f3db4 | 4337 | int oob_required = oob ? 1 : 0; |
1da177e4 | 4338 | |
8593fbc6 | 4339 | ops->retlen = 0; |
29072b96 TG |
4340 | if (!writelen) |
4341 | return 0; | |
1da177e4 | 4342 | |
8b6e50c9 | 4343 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 4344 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
4345 | pr_notice("%s: attempt to write non page aligned data\n", |
4346 | __func__); | |
1da177e4 LT |
4347 | return -EINVAL; |
4348 | } | |
4349 | ||
29072b96 | 4350 | column = to & (mtd->writesize - 1); |
1da177e4 | 4351 | |
6a930961 TG |
4352 | chipnr = (int)(to >> chip->chip_shift); |
4353 | chip->select_chip(mtd, chipnr); | |
4354 | ||
1da177e4 | 4355 | /* Check, if it is write protected */ |
b0bb6903 HS |
4356 | if (nand_check_wp(mtd)) { |
4357 | ret = -EIO; | |
4358 | goto err_out; | |
4359 | } | |
1da177e4 | 4360 | |
f75e5097 TG |
4361 | realpage = (int)(to >> chip->page_shift); |
4362 | page = realpage & chip->pagemask; | |
f75e5097 TG |
4363 | |
4364 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
4365 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
4366 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 4367 | chip->pagebuf = -1; |
61b03bd7 | 4368 | |
782ce79a | 4369 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
4370 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
4371 | ret = -EINVAL; | |
4372 | goto err_out; | |
4373 | } | |
782ce79a | 4374 | |
f8ac0414 | 4375 | while (1) { |
29072b96 | 4376 | int bytes = mtd->writesize; |
29072b96 | 4377 | uint8_t *wbuf = buf; |
66507c7b | 4378 | int use_bufpoi; |
144f4c98 | 4379 | int part_pagewr = (column || writelen < mtd->writesize); |
66507c7b KD |
4380 | |
4381 | if (part_pagewr) | |
4382 | use_bufpoi = 1; | |
4383 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
4384 | use_bufpoi = !virt_addr_valid(buf) || |
4385 | !IS_ALIGNED((unsigned long)buf, | |
4386 | chip->buf_align); | |
66507c7b KD |
4387 | else |
4388 | use_bufpoi = 0; | |
29072b96 | 4389 | |
66507c7b KD |
4390 | /* Partial page write?, or need to use bounce buffer */ |
4391 | if (use_bufpoi) { | |
4392 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
4393 | __func__, buf); | |
66507c7b KD |
4394 | if (part_pagewr) |
4395 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 | 4396 | chip->pagebuf = -1; |
c0313b96 MY |
4397 | memset(chip->data_buf, 0xff, mtd->writesize); |
4398 | memcpy(&chip->data_buf[column], buf, bytes); | |
4399 | wbuf = chip->data_buf; | |
29072b96 | 4400 | } |
1da177e4 | 4401 | |
782ce79a ML |
4402 | if (unlikely(oob)) { |
4403 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 4404 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 4405 | oobwritelen -= len; |
f722013e TAA |
4406 | } else { |
4407 | /* We still need to erase leftover OOB data */ | |
4408 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 4409 | } |
f107d7a4 BB |
4410 | |
4411 | ret = nand_write_page(mtd, chip, column, bytes, wbuf, | |
0b4773fd | 4412 | oob_required, page, |
f107d7a4 | 4413 | (ops->mode == MTD_OPS_RAW)); |
f75e5097 TG |
4414 | if (ret) |
4415 | break; | |
4416 | ||
4417 | writelen -= bytes; | |
4418 | if (!writelen) | |
4419 | break; | |
4420 | ||
29072b96 | 4421 | column = 0; |
f75e5097 TG |
4422 | buf += bytes; |
4423 | realpage++; | |
4424 | ||
4425 | page = realpage & chip->pagemask; | |
4426 | /* Check, if we cross a chip boundary */ | |
4427 | if (!page) { | |
4428 | chipnr++; | |
4429 | chip->select_chip(mtd, -1); | |
4430 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
4431 | } |
4432 | } | |
8593fbc6 | 4433 | |
8593fbc6 | 4434 | ops->retlen = ops->len - writelen; |
7014568b VW |
4435 | if (unlikely(oob)) |
4436 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
4437 | |
4438 | err_out: | |
4439 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4440 | return ret; |
4441 | } | |
4442 | ||
2af7c653 SK |
4443 | /** |
4444 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
4445 | * @mtd: MTD device structure |
4446 | * @to: offset to write to | |
4447 | * @len: number of bytes to write | |
4448 | * @retlen: pointer to variable to store the number of written bytes | |
4449 | * @buf: the data to write | |
2af7c653 SK |
4450 | * |
4451 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
4452 | * may for example be called by mtdoops when writing an oops while in panic. | |
4453 | */ | |
4454 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
4455 | size_t *retlen, const uint8_t *buf) | |
4456 | { | |
862eba51 | 4457 | struct nand_chip *chip = mtd_to_nand(mtd); |
30863e38 | 4458 | int chipnr = (int)(to >> chip->chip_shift); |
4a89ff88 | 4459 | struct mtd_oob_ops ops; |
2af7c653 SK |
4460 | int ret; |
4461 | ||
8b6e50c9 | 4462 | /* Grab the device */ |
2af7c653 SK |
4463 | panic_nand_get_device(chip, mtd, FL_WRITING); |
4464 | ||
30863e38 BT |
4465 | chip->select_chip(mtd, chipnr); |
4466 | ||
4467 | /* Wait for the device to get ready */ | |
4468 | panic_nand_wait(mtd, chip, 400); | |
4469 | ||
0ec56dc4 | 4470 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
4471 | ops.len = len; |
4472 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 4473 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 4474 | |
4a89ff88 | 4475 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 4476 | |
4a89ff88 | 4477 | *retlen = ops.retlen; |
2af7c653 SK |
4478 | return ret; |
4479 | } | |
4480 | ||
f75e5097 | 4481 | /** |
8593fbc6 | 4482 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
4483 | * @mtd: MTD device structure |
4484 | * @to: offset to write to | |
4485 | * @len: number of bytes to write | |
4486 | * @retlen: pointer to variable to store the number of written bytes | |
4487 | * @buf: the data to write | |
f75e5097 | 4488 | * |
8b6e50c9 | 4489 | * NAND write with ECC. |
f75e5097 | 4490 | */ |
8593fbc6 TG |
4491 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
4492 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 4493 | { |
4a89ff88 | 4494 | struct mtd_oob_ops ops; |
f75e5097 TG |
4495 | int ret; |
4496 | ||
6a8214aa | 4497 | nand_get_device(mtd, FL_WRITING); |
0ec56dc4 | 4498 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
4499 | ops.len = len; |
4500 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 4501 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 4502 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 4503 | *retlen = ops.retlen; |
f75e5097 | 4504 | nand_release_device(mtd); |
8593fbc6 | 4505 | return ret; |
f75e5097 | 4506 | } |
7314e9e7 | 4507 | |
1da177e4 | 4508 | /** |
8593fbc6 | 4509 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
4510 | * @mtd: MTD device structure |
4511 | * @to: offset to write to | |
4512 | * @ops: oob operation description structure | |
1da177e4 | 4513 | * |
8b6e50c9 | 4514 | * NAND write out-of-band. |
1da177e4 | 4515 | */ |
8593fbc6 TG |
4516 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
4517 | struct mtd_oob_ops *ops) | |
1da177e4 | 4518 | { |
03736155 | 4519 | int chipnr, page, status, len; |
862eba51 | 4520 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 4521 | |
289c0522 | 4522 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 4523 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 4524 | |
29f1058a | 4525 | len = mtd_oobavail(mtd, ops); |
03736155 | 4526 | |
1da177e4 | 4527 | /* Do not allow write past end of page */ |
03736155 | 4528 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
4529 | pr_debug("%s: attempt to write past end of page\n", |
4530 | __func__); | |
1da177e4 LT |
4531 | return -EINVAL; |
4532 | } | |
4533 | ||
03736155 | 4534 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
4535 | pr_debug("%s: attempt to start write outside oob\n", |
4536 | __func__); | |
03736155 AH |
4537 | return -EINVAL; |
4538 | } | |
4539 | ||
775adc3d | 4540 | /* Do not allow write past end of device */ |
03736155 AH |
4541 | if (unlikely(to >= mtd->size || |
4542 | ops->ooboffs + ops->ooblen > | |
4543 | ((mtd->size >> chip->page_shift) - | |
4544 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
4545 | pr_debug("%s: attempt to write beyond end of device\n", |
4546 | __func__); | |
03736155 AH |
4547 | return -EINVAL; |
4548 | } | |
4549 | ||
7314e9e7 | 4550 | chipnr = (int)(to >> chip->chip_shift); |
7314e9e7 TG |
4551 | |
4552 | /* | |
4553 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
4554 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
4555 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
4556 | * it in the doc2000 driver in August 1999. dwmw2. | |
4557 | */ | |
73f907fd BB |
4558 | nand_reset(chip, chipnr); |
4559 | ||
4560 | chip->select_chip(mtd, chipnr); | |
4561 | ||
4562 | /* Shift to get page */ | |
4563 | page = (int)(to >> chip->page_shift); | |
1da177e4 LT |
4564 | |
4565 | /* Check, if it is write protected */ | |
b0bb6903 HS |
4566 | if (nand_check_wp(mtd)) { |
4567 | chip->select_chip(mtd, -1); | |
8593fbc6 | 4568 | return -EROFS; |
b0bb6903 | 4569 | } |
61b03bd7 | 4570 | |
1da177e4 | 4571 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
4572 | if (page == chip->pagebuf) |
4573 | chip->pagebuf = -1; | |
1da177e4 | 4574 | |
f722013e | 4575 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 4576 | |
0612b9dd | 4577 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
4578 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
4579 | else | |
4580 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 4581 | |
b0bb6903 HS |
4582 | chip->select_chip(mtd, -1); |
4583 | ||
7bc3312b TG |
4584 | if (status) |
4585 | return status; | |
1da177e4 | 4586 | |
7014568b | 4587 | ops->oobretlen = ops->ooblen; |
1da177e4 | 4588 | |
7bc3312b | 4589 | return 0; |
8593fbc6 TG |
4590 | } |
4591 | ||
4592 | /** | |
4593 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
4594 | * @mtd: MTD device structure |
4595 | * @to: offset to write to | |
4596 | * @ops: oob operation description structure | |
8593fbc6 TG |
4597 | */ |
4598 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
4599 | struct mtd_oob_ops *ops) | |
4600 | { | |
8593fbc6 TG |
4601 | int ret = -ENOTSUPP; |
4602 | ||
4603 | ops->retlen = 0; | |
4604 | ||
4605 | /* Do not allow writes past end of device */ | |
7014568b | 4606 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
4607 | pr_debug("%s: attempt to write beyond end of device\n", |
4608 | __func__); | |
8593fbc6 TG |
4609 | return -EINVAL; |
4610 | } | |
4611 | ||
6a8214aa | 4612 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 4613 | |
f8ac0414 | 4614 | switch (ops->mode) { |
0612b9dd BN |
4615 | case MTD_OPS_PLACE_OOB: |
4616 | case MTD_OPS_AUTO_OOB: | |
4617 | case MTD_OPS_RAW: | |
8593fbc6 TG |
4618 | break; |
4619 | ||
4620 | default: | |
4621 | goto out; | |
4622 | } | |
4623 | ||
4624 | if (!ops->datbuf) | |
4625 | ret = nand_do_write_oob(mtd, to, ops); | |
4626 | else | |
4627 | ret = nand_do_write_ops(mtd, to, ops); | |
4628 | ||
7351d3a5 | 4629 | out: |
1da177e4 | 4630 | nand_release_device(mtd); |
1da177e4 LT |
4631 | return ret; |
4632 | } | |
4633 | ||
1da177e4 | 4634 | /** |
49c50b97 | 4635 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
4636 | * @mtd: MTD device structure |
4637 | * @page: the page address of the block which will be erased | |
1da177e4 | 4638 | * |
49c50b97 | 4639 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 4640 | */ |
49c50b97 | 4641 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 4642 | { |
862eba51 | 4643 | struct nand_chip *chip = mtd_to_nand(mtd); |
97d90da8 | 4644 | unsigned int eraseblock; |
eb94555e | 4645 | |
1da177e4 | 4646 | /* Send commands to erase a block */ |
97d90da8 | 4647 | eraseblock = page >> (chip->phys_erase_shift - chip->page_shift); |
49c50b97 | 4648 | |
97d90da8 | 4649 | return nand_erase_op(chip, eraseblock); |
1da177e4 LT |
4650 | } |
4651 | ||
1da177e4 LT |
4652 | /** |
4653 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
4654 | * @mtd: MTD device structure |
4655 | * @instr: erase instruction | |
1da177e4 | 4656 | * |
8b6e50c9 | 4657 | * Erase one ore more blocks. |
1da177e4 | 4658 | */ |
e0c7d767 | 4659 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 4660 | { |
e0c7d767 | 4661 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 4662 | } |
61b03bd7 | 4663 | |
1da177e4 | 4664 | /** |
7854d3f7 | 4665 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
4666 | * @mtd: MTD device structure |
4667 | * @instr: erase instruction | |
4668 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 4669 | * |
8b6e50c9 | 4670 | * Erase one ore more blocks. |
1da177e4 | 4671 | */ |
ace4dfee TG |
4672 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
4673 | int allowbbt) | |
1da177e4 | 4674 | { |
69423d99 | 4675 | int page, status, pages_per_block, ret, chipnr; |
862eba51 | 4676 | struct nand_chip *chip = mtd_to_nand(mtd); |
69423d99 | 4677 | loff_t len; |
1da177e4 | 4678 | |
289c0522 BN |
4679 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
4680 | __func__, (unsigned long long)instr->addr, | |
4681 | (unsigned long long)instr->len); | |
1da177e4 | 4682 | |
6fe5a6ac | 4683 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 4684 | return -EINVAL; |
1da177e4 | 4685 | |
1da177e4 | 4686 | /* Grab the lock and see if the device is available */ |
6a8214aa | 4687 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
4688 | |
4689 | /* Shift to get first page */ | |
ace4dfee TG |
4690 | page = (int)(instr->addr >> chip->page_shift); |
4691 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
4692 | |
4693 | /* Calculate pages in each block */ | |
ace4dfee | 4694 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
4695 | |
4696 | /* Select the NAND device */ | |
ace4dfee | 4697 | chip->select_chip(mtd, chipnr); |
1da177e4 | 4698 | |
1da177e4 LT |
4699 | /* Check, if it is write protected */ |
4700 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
4701 | pr_debug("%s: device is write protected!\n", |
4702 | __func__); | |
1da177e4 LT |
4703 | instr->state = MTD_ERASE_FAILED; |
4704 | goto erase_exit; | |
4705 | } | |
4706 | ||
4707 | /* Loop through the pages */ | |
4708 | len = instr->len; | |
4709 | ||
4710 | instr->state = MTD_ERASING; | |
4711 | ||
4712 | while (len) { | |
12183a20 | 4713 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee | 4714 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
9f3e0429 | 4715 | chip->page_shift, allowbbt)) { |
d0370219 BN |
4716 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
4717 | __func__, page); | |
1da177e4 LT |
4718 | instr->state = MTD_ERASE_FAILED; |
4719 | goto erase_exit; | |
4720 | } | |
61b03bd7 | 4721 | |
ace4dfee TG |
4722 | /* |
4723 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 4724 | * contains the current cached page. |
ace4dfee TG |
4725 | */ |
4726 | if (page <= chip->pagebuf && chip->pagebuf < | |
4727 | (page + pages_per_block)) | |
4728 | chip->pagebuf = -1; | |
1da177e4 | 4729 | |
49c50b97 | 4730 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 LT |
4731 | |
4732 | /* See if block erase succeeded */ | |
eb94555e | 4733 | if (status) { |
289c0522 BN |
4734 | pr_debug("%s: failed erase, page 0x%08x\n", |
4735 | __func__, page); | |
1da177e4 | 4736 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
4737 | instr->fail_addr = |
4738 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
4739 | goto erase_exit; |
4740 | } | |
30f464b7 | 4741 | |
1da177e4 | 4742 | /* Increment page address and decrement length */ |
daae74ca | 4743 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
4744 | page += pages_per_block; |
4745 | ||
4746 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 4747 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 4748 | chipnr++; |
ace4dfee TG |
4749 | chip->select_chip(mtd, -1); |
4750 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
4751 | } |
4752 | } | |
4753 | instr->state = MTD_ERASE_DONE; | |
4754 | ||
7351d3a5 | 4755 | erase_exit: |
1da177e4 LT |
4756 | |
4757 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
4758 | |
4759 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 4760 | chip->select_chip(mtd, -1); |
1da177e4 LT |
4761 | nand_release_device(mtd); |
4762 | ||
49defc01 DW |
4763 | /* Do call back function */ |
4764 | if (!ret) | |
4765 | mtd_erase_callback(instr); | |
4766 | ||
1da177e4 LT |
4767 | /* Return more or less happy */ |
4768 | return ret; | |
4769 | } | |
4770 | ||
4771 | /** | |
4772 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 4773 | * @mtd: MTD device structure |
1da177e4 | 4774 | * |
8b6e50c9 | 4775 | * Sync is actually a wait for chip ready function. |
1da177e4 | 4776 | */ |
e0c7d767 | 4777 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 4778 | { |
289c0522 | 4779 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
4780 | |
4781 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 4782 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 4783 | /* Release it and go back */ |
e0c7d767 | 4784 | nand_release_device(mtd); |
1da177e4 LT |
4785 | } |
4786 | ||
1da177e4 | 4787 | /** |
ace4dfee | 4788 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
4789 | * @mtd: MTD device structure |
4790 | * @offs: offset relative to mtd start | |
1da177e4 | 4791 | */ |
ace4dfee | 4792 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 4793 | { |
9f3e0429 AT |
4794 | struct nand_chip *chip = mtd_to_nand(mtd); |
4795 | int chipnr = (int)(offs >> chip->chip_shift); | |
4796 | int ret; | |
4797 | ||
4798 | /* Select the NAND device */ | |
4799 | nand_get_device(mtd, FL_READING); | |
4800 | chip->select_chip(mtd, chipnr); | |
4801 | ||
4802 | ret = nand_block_checkbad(mtd, offs, 0); | |
4803 | ||
4804 | chip->select_chip(mtd, -1); | |
4805 | nand_release_device(mtd); | |
4806 | ||
4807 | return ret; | |
1da177e4 LT |
4808 | } |
4809 | ||
4810 | /** | |
ace4dfee | 4811 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
4812 | * @mtd: MTD device structure |
4813 | * @ofs: offset relative to mtd start | |
1da177e4 | 4814 | */ |
e0c7d767 | 4815 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 4816 | { |
1da177e4 LT |
4817 | int ret; |
4818 | ||
f8ac0414 FF |
4819 | ret = nand_block_isbad(mtd, ofs); |
4820 | if (ret) { | |
8b6e50c9 | 4821 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
4822 | if (ret > 0) |
4823 | return 0; | |
e0c7d767 DW |
4824 | return ret; |
4825 | } | |
1da177e4 | 4826 | |
5a0edb25 | 4827 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
4828 | } |
4829 | ||
5671842f ZB |
4830 | /** |
4831 | * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd | |
4832 | * @mtd: MTD device structure | |
4833 | * @ofs: offset relative to mtd start | |
4834 | * @len: length of mtd | |
4835 | */ | |
4836 | static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len) | |
4837 | { | |
4838 | struct nand_chip *chip = mtd_to_nand(mtd); | |
4839 | u32 part_start_block; | |
4840 | u32 part_end_block; | |
4841 | u32 part_start_die; | |
4842 | u32 part_end_die; | |
4843 | ||
4844 | /* | |
4845 | * max_bb_per_die and blocks_per_die used to determine | |
4846 | * the maximum bad block count. | |
4847 | */ | |
4848 | if (!chip->max_bb_per_die || !chip->blocks_per_die) | |
4849 | return -ENOTSUPP; | |
4850 | ||
4851 | /* Get the start and end of the partition in erase blocks. */ | |
4852 | part_start_block = mtd_div_by_eb(ofs, mtd); | |
4853 | part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1; | |
4854 | ||
4855 | /* Get the start and end LUNs of the partition. */ | |
4856 | part_start_die = part_start_block / chip->blocks_per_die; | |
4857 | part_end_die = part_end_block / chip->blocks_per_die; | |
4858 | ||
4859 | /* | |
4860 | * Look up the bad blocks per unit and multiply by the number of units | |
4861 | * that the partition spans. | |
4862 | */ | |
4863 | return chip->max_bb_per_die * (part_end_die - part_start_die + 1); | |
4864 | } | |
4865 | ||
7db03ecc HS |
4866 | /** |
4867 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
4868 | * @mtd: MTD device structure | |
4869 | * @chip: nand chip info structure | |
4870 | * @addr: feature address. | |
4871 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
4872 | */ | |
4873 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
4874 | int addr, uint8_t *subfeature_param) | |
4875 | { | |
d914c932 DM |
4876 | if (!chip->onfi_version || |
4877 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
4878 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
4879 | return -EINVAL; |
4880 | ||
97d90da8 | 4881 | return nand_set_features_op(chip, addr, subfeature_param); |
7db03ecc HS |
4882 | } |
4883 | ||
4884 | /** | |
4885 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
4886 | * @mtd: MTD device structure | |
4887 | * @chip: nand chip info structure | |
4888 | * @addr: feature address. | |
4889 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
4890 | */ | |
4891 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
4892 | int addr, uint8_t *subfeature_param) | |
4893 | { | |
d914c932 DM |
4894 | if (!chip->onfi_version || |
4895 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
4896 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
4897 | return -EINVAL; |
4898 | ||
97d90da8 | 4899 | return nand_get_features_op(chip, addr, subfeature_param); |
7db03ecc HS |
4900 | } |
4901 | ||
4a78cc64 BB |
4902 | /** |
4903 | * nand_onfi_get_set_features_notsupp - set/get features stub returning | |
4904 | * -ENOTSUPP | |
4905 | * @mtd: MTD device structure | |
4906 | * @chip: nand chip info structure | |
4907 | * @addr: feature address. | |
4908 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
4909 | * | |
4910 | * Should be used by NAND controller drivers that do not support the SET/GET | |
4911 | * FEATURES operations. | |
4912 | */ | |
4913 | int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, | |
4914 | struct nand_chip *chip, int addr, | |
4915 | u8 *subfeature_param) | |
4916 | { | |
4917 | return -ENOTSUPP; | |
4918 | } | |
4919 | EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp); | |
4920 | ||
962034f4 VW |
4921 | /** |
4922 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 4923 | * @mtd: MTD device structure |
962034f4 VW |
4924 | */ |
4925 | static int nand_suspend(struct mtd_info *mtd) | |
4926 | { | |
6a8214aa | 4927 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
4928 | } |
4929 | ||
4930 | /** | |
4931 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 4932 | * @mtd: MTD device structure |
962034f4 VW |
4933 | */ |
4934 | static void nand_resume(struct mtd_info *mtd) | |
4935 | { | |
862eba51 | 4936 | struct nand_chip *chip = mtd_to_nand(mtd); |
962034f4 | 4937 | |
ace4dfee | 4938 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
4939 | nand_release_device(mtd); |
4940 | else | |
d0370219 BN |
4941 | pr_err("%s called for a chip which is not in suspended state\n", |
4942 | __func__); | |
962034f4 VW |
4943 | } |
4944 | ||
72ea4036 SB |
4945 | /** |
4946 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
4947 | * prevent further operations | |
4948 | * @mtd: MTD device structure | |
4949 | */ | |
4950 | static void nand_shutdown(struct mtd_info *mtd) | |
4951 | { | |
9ca641b0 | 4952 | nand_get_device(mtd, FL_PM_SUSPENDED); |
72ea4036 SB |
4953 | } |
4954 | ||
8b6e50c9 | 4955 | /* Set default functions */ |
29a198a1 | 4956 | static void nand_set_defaults(struct nand_chip *chip) |
7aa65bfd | 4957 | { |
29a198a1 BB |
4958 | unsigned int busw = chip->options & NAND_BUSWIDTH_16; |
4959 | ||
1da177e4 | 4960 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
4961 | if (!chip->chip_delay) |
4962 | chip->chip_delay = 20; | |
1da177e4 LT |
4963 | |
4964 | /* check, if a user supplied command function given */ | |
8878b126 | 4965 | if (!chip->cmdfunc && !chip->exec_op) |
ace4dfee | 4966 | chip->cmdfunc = nand_command; |
1da177e4 LT |
4967 | |
4968 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
4969 | if (chip->waitfunc == NULL) |
4970 | chip->waitfunc = nand_wait; | |
4971 | ||
4972 | if (!chip->select_chip) | |
4973 | chip->select_chip = nand_select_chip; | |
68e80780 | 4974 | |
4204cccd HS |
4975 | /* set for ONFI nand */ |
4976 | if (!chip->onfi_set_features) | |
4977 | chip->onfi_set_features = nand_onfi_set_features; | |
4978 | if (!chip->onfi_get_features) | |
4979 | chip->onfi_get_features = nand_onfi_get_features; | |
4980 | ||
68e80780 BN |
4981 | /* If called twice, pointers that depend on busw may need to be reset */ |
4982 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
4983 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
4984 | if (!chip->read_word) | |
4985 | chip->read_word = nand_read_word; | |
4986 | if (!chip->block_bad) | |
4987 | chip->block_bad = nand_block_bad; | |
4988 | if (!chip->block_markbad) | |
4989 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 4990 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 4991 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
4992 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
4993 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 4994 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 4995 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
4996 | if (!chip->scan_bbt) |
4997 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
4998 | |
4999 | if (!chip->controller) { | |
5000 | chip->controller = &chip->hwcontrol; | |
d45bc58d | 5001 | nand_hw_control_init(chip->controller); |
f75e5097 TG |
5002 | } |
5003 | ||
477544c6 MY |
5004 | if (!chip->buf_align) |
5005 | chip->buf_align = 1; | |
7aa65bfd TG |
5006 | } |
5007 | ||
8b6e50c9 | 5008 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
5009 | static void sanitize_string(uint8_t *s, size_t len) |
5010 | { | |
5011 | ssize_t i; | |
5012 | ||
8b6e50c9 | 5013 | /* Null terminate */ |
d1e1f4e4 FF |
5014 | s[len - 1] = 0; |
5015 | ||
8b6e50c9 | 5016 | /* Remove non printable chars */ |
d1e1f4e4 FF |
5017 | for (i = 0; i < len - 1; i++) { |
5018 | if (s[i] < ' ' || s[i] > 127) | |
5019 | s[i] = '?'; | |
5020 | } | |
5021 | ||
8b6e50c9 | 5022 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
5023 | strim(s); |
5024 | } | |
5025 | ||
5026 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
5027 | { | |
5028 | int i; | |
5029 | while (len--) { | |
5030 | crc ^= *p++ << 8; | |
5031 | for (i = 0; i < 8; i++) | |
5032 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
5033 | } | |
5034 | ||
5035 | return crc; | |
5036 | } | |
5037 | ||
6dcbe0cd | 5038 | /* Parse the Extended Parameter Page. */ |
cbe435a1 BB |
5039 | static int nand_flash_detect_ext_param_page(struct nand_chip *chip, |
5040 | struct nand_onfi_params *p) | |
6dcbe0cd HS |
5041 | { |
5042 | struct onfi_ext_param_page *ep; | |
5043 | struct onfi_ext_section *s; | |
5044 | struct onfi_ext_ecc_info *ecc; | |
5045 | uint8_t *cursor; | |
97d90da8 | 5046 | int ret; |
6dcbe0cd HS |
5047 | int len; |
5048 | int i; | |
5049 | ||
5050 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
5051 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
5052 | if (!ep) |
5053 | return -ENOMEM; | |
6dcbe0cd HS |
5054 | |
5055 | /* Send our own NAND_CMD_PARAM. */ | |
97d90da8 BB |
5056 | ret = nand_read_param_page_op(chip, 0, NULL, 0); |
5057 | if (ret) | |
5058 | goto ext_out; | |
6dcbe0cd HS |
5059 | |
5060 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
97d90da8 BB |
5061 | ret = nand_change_read_column_op(chip, |
5062 | sizeof(*p) * p->num_of_param_pages, | |
5063 | ep, len, true); | |
5064 | if (ret) | |
5065 | goto ext_out; | |
6dcbe0cd | 5066 | |
97d90da8 | 5067 | ret = -EINVAL; |
6dcbe0cd HS |
5068 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) |
5069 | != le16_to_cpu(ep->crc))) { | |
5070 | pr_debug("fail in the CRC.\n"); | |
5071 | goto ext_out; | |
5072 | } | |
5073 | ||
5074 | /* | |
5075 | * Check the signature. | |
5076 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
5077 | */ | |
5078 | if (strncmp(ep->sig, "EPPS", 4)) { | |
5079 | pr_debug("The signature is invalid.\n"); | |
5080 | goto ext_out; | |
5081 | } | |
5082 | ||
5083 | /* find the ECC section. */ | |
5084 | cursor = (uint8_t *)(ep + 1); | |
5085 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
5086 | s = ep->sections + i; | |
5087 | if (s->type == ONFI_SECTION_TYPE_2) | |
5088 | break; | |
5089 | cursor += s->length * 16; | |
5090 | } | |
5091 | if (i == ONFI_EXT_SECTION_MAX) { | |
5092 | pr_debug("We can not find the ECC section.\n"); | |
5093 | goto ext_out; | |
5094 | } | |
5095 | ||
5096 | /* get the info we want. */ | |
5097 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
5098 | ||
4ae7d228 BN |
5099 | if (!ecc->codeword_size) { |
5100 | pr_debug("Invalid codeword size\n"); | |
5101 | goto ext_out; | |
6dcbe0cd HS |
5102 | } |
5103 | ||
4ae7d228 BN |
5104 | chip->ecc_strength_ds = ecc->ecc_bits; |
5105 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 5106 | ret = 0; |
6dcbe0cd HS |
5107 | |
5108 | ext_out: | |
5109 | kfree(ep); | |
5110 | return ret; | |
5111 | } | |
5112 | ||
6fb277ba | 5113 | /* |
8b6e50c9 | 5114 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba | 5115 | */ |
29a198a1 | 5116 | static int nand_flash_detect_onfi(struct nand_chip *chip) |
6fb277ba | 5117 | { |
cbe435a1 | 5118 | struct mtd_info *mtd = nand_to_mtd(chip); |
6fb277ba | 5119 | struct nand_onfi_params *p = &chip->onfi_params; |
97d90da8 BB |
5120 | char id[4]; |
5121 | int i, ret, val; | |
6fb277ba | 5122 | |
7854d3f7 | 5123 | /* Try ONFI for unknown chip or LP */ |
97d90da8 BB |
5124 | ret = nand_readid_op(chip, 0x20, id, sizeof(id)); |
5125 | if (ret || strncmp(id, "ONFI", 4)) | |
5126 | return 0; | |
5127 | ||
5128 | ret = nand_read_param_page_op(chip, 0, NULL, 0); | |
5129 | if (ret) | |
6fb277ba FF |
5130 | return 0; |
5131 | ||
6fb277ba | 5132 | for (i = 0; i < 3; i++) { |
97d90da8 BB |
5133 | ret = nand_read_data_op(chip, p, sizeof(*p), true); |
5134 | if (ret) | |
5135 | return 0; | |
5136 | ||
6fb277ba FF |
5137 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
5138 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
5139 | break; |
5140 | } | |
5141 | } | |
5142 | ||
c7f23a70 BN |
5143 | if (i == 3) { |
5144 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 5145 | return 0; |
c7f23a70 | 5146 | } |
6fb277ba | 5147 | |
8b6e50c9 | 5148 | /* Check version */ |
6fb277ba | 5149 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
5150 | if (val & (1 << 5)) |
5151 | chip->onfi_version = 23; | |
5152 | else if (val & (1 << 4)) | |
6fb277ba FF |
5153 | chip->onfi_version = 22; |
5154 | else if (val & (1 << 3)) | |
5155 | chip->onfi_version = 21; | |
5156 | else if (val & (1 << 2)) | |
5157 | chip->onfi_version = 20; | |
b7b1a29d | 5158 | else if (val & (1 << 1)) |
6fb277ba | 5159 | chip->onfi_version = 10; |
b7b1a29d BN |
5160 | |
5161 | if (!chip->onfi_version) { | |
20171642 | 5162 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
5163 | return 0; |
5164 | } | |
6fb277ba FF |
5165 | |
5166 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
5167 | sanitize_string(p->model, sizeof(p->model)); | |
5168 | if (!mtd->name) | |
5169 | mtd->name = p->model; | |
4355b70c | 5170 | |
6fb277ba | 5171 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
5172 | |
5173 | /* | |
5174 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
5175 | * (don't ask me who thought of this...). MTD assumes that these | |
5176 | * dimensions will be power-of-2, so just truncate the remaining area. | |
5177 | */ | |
5178 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
5179 | mtd->erasesize *= mtd->writesize; | |
5180 | ||
6fb277ba | 5181 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
5182 | |
5183 | /* See erasesize comment */ | |
5184 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 5185 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 5186 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 | 5187 | |
34da5f5f ZB |
5188 | chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun); |
5189 | chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun); | |
5190 | ||
e2985fc1 | 5191 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) |
29a198a1 | 5192 | chip->options |= NAND_BUSWIDTH_16; |
6fb277ba | 5193 | |
10c86bab HS |
5194 | if (p->ecc_bits != 0xff) { |
5195 | chip->ecc_strength_ds = p->ecc_bits; | |
5196 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
5197 | } else if (chip->onfi_version >= 21 && |
5198 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
5199 | ||
5200 | /* | |
5201 | * The nand_flash_detect_ext_param_page() uses the | |
5202 | * Change Read Column command which maybe not supported | |
5203 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
5204 | * now. We do not replace user supplied command function. | |
5205 | */ | |
5206 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
5207 | chip->cmdfunc = nand_command_lp; | |
5208 | ||
5209 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
cbe435a1 | 5210 | if (nand_flash_detect_ext_param_page(chip, p)) |
c7f23a70 BN |
5211 | pr_warn("Failed to detect ONFI extended param page\n"); |
5212 | } else { | |
5213 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
5214 | } |
5215 | ||
6fb277ba FF |
5216 | return 1; |
5217 | } | |
5218 | ||
91361818 HS |
5219 | /* |
5220 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
5221 | */ | |
29a198a1 | 5222 | static int nand_flash_detect_jedec(struct nand_chip *chip) |
91361818 | 5223 | { |
cbe435a1 | 5224 | struct mtd_info *mtd = nand_to_mtd(chip); |
91361818 HS |
5225 | struct nand_jedec_params *p = &chip->jedec_params; |
5226 | struct jedec_ecc_info *ecc; | |
97d90da8 BB |
5227 | char id[5]; |
5228 | int i, val, ret; | |
91361818 HS |
5229 | |
5230 | /* Try JEDEC for unknown chip or LP */ | |
97d90da8 BB |
5231 | ret = nand_readid_op(chip, 0x40, id, sizeof(id)); |
5232 | if (ret || strncmp(id, "JEDEC", sizeof(id))) | |
5233 | return 0; | |
5234 | ||
5235 | ret = nand_read_param_page_op(chip, 0x40, NULL, 0); | |
5236 | if (ret) | |
91361818 HS |
5237 | return 0; |
5238 | ||
91361818 | 5239 | for (i = 0; i < 3; i++) { |
97d90da8 BB |
5240 | ret = nand_read_data_op(chip, p, sizeof(*p), true); |
5241 | if (ret) | |
5242 | return 0; | |
91361818 HS |
5243 | |
5244 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
5245 | le16_to_cpu(p->crc)) | |
5246 | break; | |
5247 | } | |
5248 | ||
5249 | if (i == 3) { | |
5250 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
5251 | return 0; | |
5252 | } | |
5253 | ||
5254 | /* Check version */ | |
5255 | val = le16_to_cpu(p->revision); | |
5256 | if (val & (1 << 2)) | |
5257 | chip->jedec_version = 10; | |
5258 | else if (val & (1 << 1)) | |
5259 | chip->jedec_version = 1; /* vendor specific version */ | |
5260 | ||
5261 | if (!chip->jedec_version) { | |
5262 | pr_info("unsupported JEDEC version: %d\n", val); | |
5263 | return 0; | |
5264 | } | |
5265 | ||
5266 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
5267 | sanitize_string(p->model, sizeof(p->model)); | |
5268 | if (!mtd->name) | |
5269 | mtd->name = p->model; | |
5270 | ||
5271 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
5272 | ||
5273 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
5274 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
5275 | mtd->erasesize *= mtd->writesize; | |
5276 | ||
5277 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
5278 | ||
5279 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
5280 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
5281 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
5282 | chip->bits_per_cell = p->bits_per_cell; | |
5283 | ||
5284 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
29a198a1 | 5285 | chip->options |= NAND_BUSWIDTH_16; |
91361818 HS |
5286 | |
5287 | /* ECC info */ | |
5288 | ecc = &p->ecc_info[0]; | |
5289 | ||
5290 | if (ecc->codeword_size >= 9) { | |
5291 | chip->ecc_strength_ds = ecc->ecc_bits; | |
5292 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5293 | } else { | |
5294 | pr_warn("Invalid codeword size\n"); | |
5295 | } | |
5296 | ||
5297 | return 1; | |
5298 | } | |
5299 | ||
e3b88bd6 BN |
5300 | /* |
5301 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
5302 | * @id_data: the ID string | |
5303 | * @arrlen: the length of the @id_data array | |
5304 | * @period: the period of repitition | |
5305 | * | |
5306 | * Check if an ID string is repeated within a given sequence of bytes at | |
5307 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 5308 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
5309 | * if the repetition has a period of @period; otherwise, returns zero. |
5310 | */ | |
5311 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
5312 | { | |
5313 | int i, j; | |
5314 | for (i = 0; i < period; i++) | |
5315 | for (j = i + period; j < arrlen; j += period) | |
5316 | if (id_data[i] != id_data[j]) | |
5317 | return 0; | |
5318 | return 1; | |
5319 | } | |
5320 | ||
5321 | /* | |
5322 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
5323 | * @id_data: the ID string | |
5324 | * @arrlen: the length of the @id_data array | |
5325 | ||
5326 | * Returns the length of the ID string, according to known wraparound/trailing | |
5327 | * zero patterns. If no pattern exists, returns the length of the array. | |
5328 | */ | |
5329 | static int nand_id_len(u8 *id_data, int arrlen) | |
5330 | { | |
5331 | int last_nonzero, period; | |
5332 | ||
5333 | /* Find last non-zero byte */ | |
5334 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
5335 | if (id_data[last_nonzero]) | |
5336 | break; | |
5337 | ||
5338 | /* All zeros */ | |
5339 | if (last_nonzero < 0) | |
5340 | return 0; | |
5341 | ||
5342 | /* Calculate wraparound period */ | |
5343 | for (period = 1; period < arrlen; period++) | |
5344 | if (nand_id_has_period(id_data, arrlen, period)) | |
5345 | break; | |
5346 | ||
5347 | /* There's a repeated pattern */ | |
5348 | if (period < arrlen) | |
5349 | return period; | |
5350 | ||
5351 | /* There are trailing zeros */ | |
5352 | if (last_nonzero < arrlen - 1) | |
5353 | return last_nonzero + 1; | |
5354 | ||
5355 | /* No pattern detected */ | |
5356 | return arrlen; | |
5357 | } | |
5358 | ||
7db906b7 HS |
5359 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
5360 | static int nand_get_bits_per_cell(u8 cellinfo) | |
5361 | { | |
5362 | int bits; | |
5363 | ||
5364 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
5365 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
5366 | return bits + 1; | |
5367 | } | |
5368 | ||
fc09bbc0 BN |
5369 | /* |
5370 | * Many new NAND share similar device ID codes, which represent the size of the | |
5371 | * chip. The rest of the parameters must be decoded according to generic or | |
5372 | * manufacturer-specific "extended ID" decoding patterns. | |
5373 | */ | |
abbe26d1 | 5374 | void nand_decode_ext_id(struct nand_chip *chip) |
fc09bbc0 | 5375 | { |
cbe435a1 | 5376 | struct mtd_info *mtd = nand_to_mtd(chip); |
9b2d61f8 | 5377 | int extid; |
7f501f0a | 5378 | u8 *id_data = chip->id.data; |
fc09bbc0 | 5379 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 5380 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
5381 | /* The 4th id byte is the important one */ |
5382 | extid = id_data[3]; | |
5383 | ||
01389b6b BB |
5384 | /* Calc pagesize */ |
5385 | mtd->writesize = 1024 << (extid & 0x03); | |
5386 | extid >>= 2; | |
5387 | /* Calc oobsize */ | |
5388 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); | |
5389 | extid >>= 2; | |
5390 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
5391 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
5392 | extid >>= 2; | |
5393 | /* Get buswidth information */ | |
5394 | if (extid & 0x1) | |
5395 | chip->options |= NAND_BUSWIDTH_16; | |
fc09bbc0 | 5396 | } |
abbe26d1 | 5397 | EXPORT_SYMBOL_GPL(nand_decode_ext_id); |
fc09bbc0 | 5398 | |
f23a481c BN |
5399 | /* |
5400 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
5401 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
5402 | * the chip. | |
5403 | */ | |
29a198a1 | 5404 | static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) |
f23a481c | 5405 | { |
cbe435a1 | 5406 | struct mtd_info *mtd = nand_to_mtd(chip); |
f23a481c BN |
5407 | |
5408 | mtd->erasesize = type->erasesize; | |
5409 | mtd->writesize = type->pagesize; | |
5410 | mtd->oobsize = mtd->writesize / 32; | |
f23a481c | 5411 | |
1c195e90 HS |
5412 | /* All legacy ID NAND are small-page, SLC */ |
5413 | chip->bits_per_cell = 1; | |
f23a481c BN |
5414 | } |
5415 | ||
7e74c2d7 BN |
5416 | /* |
5417 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
5418 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
5419 | * page size, cell-type information). | |
5420 | */ | |
7f501f0a | 5421 | static void nand_decode_bbm_options(struct nand_chip *chip) |
7e74c2d7 | 5422 | { |
cbe435a1 | 5423 | struct mtd_info *mtd = nand_to_mtd(chip); |
7e74c2d7 BN |
5424 | |
5425 | /* Set the bad block position */ | |
5426 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
5427 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
5428 | else | |
5429 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
7e74c2d7 BN |
5430 | } |
5431 | ||
ec6e87e3 HS |
5432 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
5433 | { | |
5434 | return type->id_len; | |
5435 | } | |
5436 | ||
cbe435a1 | 5437 | static bool find_full_id_nand(struct nand_chip *chip, |
29a198a1 | 5438 | struct nand_flash_dev *type) |
ec6e87e3 | 5439 | { |
cbe435a1 | 5440 | struct mtd_info *mtd = nand_to_mtd(chip); |
7f501f0a | 5441 | u8 *id_data = chip->id.data; |
cbe435a1 | 5442 | |
ec6e87e3 HS |
5443 | if (!strncmp(type->id, id_data, type->id_len)) { |
5444 | mtd->writesize = type->pagesize; | |
5445 | mtd->erasesize = type->erasesize; | |
5446 | mtd->oobsize = type->oobsize; | |
5447 | ||
7db906b7 | 5448 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
5449 | chip->chipsize = (uint64_t)type->chipsize << 20; |
5450 | chip->options |= type->options; | |
57219342 HS |
5451 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
5452 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
5453 | chip->onfi_timing_mode_default = |
5454 | type->onfi_timing_mode_default; | |
ec6e87e3 | 5455 | |
092b6a1d CZ |
5456 | if (!mtd->name) |
5457 | mtd->name = type->name; | |
5458 | ||
ec6e87e3 HS |
5459 | return true; |
5460 | } | |
5461 | return false; | |
5462 | } | |
5463 | ||
abbe26d1 BB |
5464 | /* |
5465 | * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC | |
5466 | * compliant and does not have a full-id or legacy-id entry in the nand_ids | |
5467 | * table. | |
5468 | */ | |
5469 | static void nand_manufacturer_detect(struct nand_chip *chip) | |
5470 | { | |
5471 | /* | |
5472 | * Try manufacturer detection if available and use | |
5473 | * nand_decode_ext_id() otherwise. | |
5474 | */ | |
5475 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
69fc0129 LW |
5476 | chip->manufacturer.desc->ops->detect) { |
5477 | /* The 3rd id byte holds MLC / multichip data */ | |
5478 | chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); | |
abbe26d1 | 5479 | chip->manufacturer.desc->ops->detect(chip); |
69fc0129 | 5480 | } else { |
abbe26d1 | 5481 | nand_decode_ext_id(chip); |
69fc0129 | 5482 | } |
abbe26d1 BB |
5483 | } |
5484 | ||
5485 | /* | |
5486 | * Manufacturer initialization. This function is called for all NANDs including | |
5487 | * ONFI and JEDEC compliant ones. | |
5488 | * Manufacturer drivers should put all their specific initialization code in | |
5489 | * their ->init() hook. | |
5490 | */ | |
5491 | static int nand_manufacturer_init(struct nand_chip *chip) | |
5492 | { | |
5493 | if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || | |
5494 | !chip->manufacturer.desc->ops->init) | |
5495 | return 0; | |
5496 | ||
5497 | return chip->manufacturer.desc->ops->init(chip); | |
5498 | } | |
5499 | ||
5500 | /* | |
5501 | * Manufacturer cleanup. This function is called for all NANDs including | |
5502 | * ONFI and JEDEC compliant ones. | |
5503 | * Manufacturer drivers should put all their specific cleanup code in their | |
5504 | * ->cleanup() hook. | |
5505 | */ | |
5506 | static void nand_manufacturer_cleanup(struct nand_chip *chip) | |
5507 | { | |
5508 | /* Release manufacturer private data */ | |
5509 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
5510 | chip->manufacturer.desc->ops->cleanup) | |
5511 | chip->manufacturer.desc->ops->cleanup(chip); | |
5512 | } | |
5513 | ||
7aa65bfd | 5514 | /* |
8b6e50c9 | 5515 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd | 5516 | */ |
7bb42799 | 5517 | static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) |
7aa65bfd | 5518 | { |
bcc678c2 | 5519 | const struct nand_manufacturer *manufacturer; |
cbe435a1 | 5520 | struct mtd_info *mtd = nand_to_mtd(chip); |
97d90da8 | 5521 | int busw, ret; |
7f501f0a BB |
5522 | u8 *id_data = chip->id.data; |
5523 | u8 maf_id, dev_id; | |
1da177e4 | 5524 | |
ef89a880 KB |
5525 | /* |
5526 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 5527 | * after power-up. |
ef89a880 | 5528 | */ |
97d90da8 BB |
5529 | ret = nand_reset(chip, 0); |
5530 | if (ret) | |
5531 | return ret; | |
73f907fd BB |
5532 | |
5533 | /* Select the device */ | |
5534 | chip->select_chip(mtd, 0); | |
ef89a880 | 5535 | |
1da177e4 | 5536 | /* Send the command for reading device ID */ |
97d90da8 BB |
5537 | ret = nand_readid_op(chip, 0, id_data, 2); |
5538 | if (ret) | |
5539 | return ret; | |
1da177e4 LT |
5540 | |
5541 | /* Read manufacturer and device IDs */ | |
97d90da8 BB |
5542 | maf_id = id_data[0]; |
5543 | dev_id = id_data[1]; | |
1da177e4 | 5544 | |
8b6e50c9 BN |
5545 | /* |
5546 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
5547 | * interface concerns can cause random data which looks like a |
5548 | * possibly credible NAND flash to appear. If the two results do | |
5549 | * not match, ignore the device completely. | |
5550 | */ | |
5551 | ||
4aef9b78 | 5552 | /* Read entire ID string */ |
97d90da8 BB |
5553 | ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data)); |
5554 | if (ret) | |
5555 | return ret; | |
ed8165c7 | 5556 | |
7f501f0a | 5557 | if (id_data[0] != maf_id || id_data[1] != dev_id) { |
20171642 | 5558 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
7f501f0a | 5559 | maf_id, dev_id, id_data[0], id_data[1]); |
4722c0e9 | 5560 | return -ENODEV; |
ed8165c7 BD |
5561 | } |
5562 | ||
5158bd55 | 5563 | chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); |
7f501f0a | 5564 | |
abbe26d1 BB |
5565 | /* Try to identify manufacturer */ |
5566 | manufacturer = nand_get_manufacturer(maf_id); | |
5567 | chip->manufacturer.desc = manufacturer; | |
5568 | ||
7aa65bfd | 5569 | if (!type) |
5e81e88a DW |
5570 | type = nand_flash_ids; |
5571 | ||
29a198a1 BB |
5572 | /* |
5573 | * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic | |
5574 | * override it. | |
5575 | * This is required to make sure initial NAND bus width set by the | |
5576 | * NAND controller driver is coherent with the real NAND bus width | |
5577 | * (extracted by auto-detection code). | |
5578 | */ | |
5579 | busw = chip->options & NAND_BUSWIDTH_16; | |
5580 | ||
5581 | /* | |
5582 | * The flag is only set (never cleared), reset it to its default value | |
5583 | * before starting auto-detection. | |
5584 | */ | |
5585 | chip->options &= ~NAND_BUSWIDTH_16; | |
5586 | ||
ec6e87e3 HS |
5587 | for (; type->name != NULL; type++) { |
5588 | if (is_full_id_nand(type)) { | |
29a198a1 | 5589 | if (find_full_id_nand(chip, type)) |
ec6e87e3 | 5590 | goto ident_done; |
7f501f0a | 5591 | } else if (dev_id == type->dev_id) { |
db5b09f6 | 5592 | break; |
ec6e87e3 HS |
5593 | } |
5594 | } | |
5e81e88a | 5595 | |
d1e1f4e4 FF |
5596 | chip->onfi_version = 0; |
5597 | if (!type->name || !type->pagesize) { | |
35fc5195 | 5598 | /* Check if the chip is ONFI compliant */ |
29a198a1 | 5599 | if (nand_flash_detect_onfi(chip)) |
6fb277ba | 5600 | goto ident_done; |
91361818 HS |
5601 | |
5602 | /* Check if the chip is JEDEC compliant */ | |
29a198a1 | 5603 | if (nand_flash_detect_jedec(chip)) |
91361818 | 5604 | goto ident_done; |
d1e1f4e4 FF |
5605 | } |
5606 | ||
5e81e88a | 5607 | if (!type->name) |
4722c0e9 | 5608 | return -ENODEV; |
7aa65bfd | 5609 | |
ba0251fe TG |
5610 | if (!mtd->name) |
5611 | mtd->name = type->name; | |
5612 | ||
69423d99 | 5613 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 5614 | |
abbe26d1 BB |
5615 | if (!type->pagesize) |
5616 | nand_manufacturer_detect(chip); | |
5617 | else | |
29a198a1 | 5618 | nand_decode_id(chip, type); |
abbe26d1 | 5619 | |
bf7a01bf BN |
5620 | /* Get chip options */ |
5621 | chip->options |= type->options; | |
d1e1f4e4 | 5622 | |
d1e1f4e4 FF |
5623 | ident_done: |
5624 | ||
64b37b2a | 5625 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
29a198a1 BB |
5626 | WARN_ON(busw & NAND_BUSWIDTH_16); |
5627 | nand_set_defaults(chip); | |
64b37b2a MC |
5628 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
5629 | /* | |
5630 | * Check, if buswidth is correct. Hardware drivers should set | |
5631 | * chip correct! | |
5632 | */ | |
20171642 | 5633 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 5634 | maf_id, dev_id); |
bcc678c2 BB |
5635 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
5636 | mtd->name); | |
29a198a1 BB |
5637 | pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, |
5638 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); | |
4722c0e9 | 5639 | return -EINVAL; |
7aa65bfd | 5640 | } |
61b03bd7 | 5641 | |
7f501f0a | 5642 | nand_decode_bbm_options(chip); |
7e74c2d7 | 5643 | |
7aa65bfd | 5644 | /* Calculate the address shift from the page size */ |
ace4dfee | 5645 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 5646 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 5647 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 5648 | |
ace4dfee | 5649 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 5650 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
5651 | if (chip->chipsize & 0xffffffff) |
5652 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
5653 | else { |
5654 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
5655 | chip->chip_shift += 32 - 1; | |
5656 | } | |
1da177e4 | 5657 | |
14157f86 MY |
5658 | if (chip->chip_shift - chip->page_shift > 16) |
5659 | chip->options |= NAND_ROW_ADDR_3; | |
5660 | ||
26d9be11 | 5661 | chip->badblockbits = 8; |
49c50b97 | 5662 | chip->erase = single_erase; |
7aa65bfd | 5663 | |
8b6e50c9 | 5664 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
5665 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
5666 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 5667 | |
20171642 | 5668 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 5669 | maf_id, dev_id); |
ffdac6cd HS |
5670 | |
5671 | if (chip->onfi_version) | |
bcc678c2 BB |
5672 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
5673 | chip->onfi_params.model); | |
ffdac6cd | 5674 | else if (chip->jedec_version) |
bcc678c2 BB |
5675 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
5676 | chip->jedec_params.model); | |
ffdac6cd | 5677 | else |
bcc678c2 BB |
5678 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
5679 | type->name); | |
ffdac6cd | 5680 | |
3755a991 | 5681 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 5682 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 5683 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
4722c0e9 | 5684 | return 0; |
7aa65bfd TG |
5685 | } |
5686 | ||
d48f62b9 BB |
5687 | static const char * const nand_ecc_modes[] = { |
5688 | [NAND_ECC_NONE] = "none", | |
5689 | [NAND_ECC_SOFT] = "soft", | |
5690 | [NAND_ECC_HW] = "hw", | |
5691 | [NAND_ECC_HW_SYNDROME] = "hw_syndrome", | |
5692 | [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first", | |
785818fa | 5693 | [NAND_ECC_ON_DIE] = "on-die", |
d48f62b9 BB |
5694 | }; |
5695 | ||
5696 | static int of_get_nand_ecc_mode(struct device_node *np) | |
5697 | { | |
5698 | const char *pm; | |
5699 | int err, i; | |
5700 | ||
5701 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
5702 | if (err < 0) | |
5703 | return err; | |
5704 | ||
5705 | for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++) | |
5706 | if (!strcasecmp(pm, nand_ecc_modes[i])) | |
5707 | return i; | |
5708 | ||
ae211bcf RM |
5709 | /* |
5710 | * For backward compatibility we support few obsoleted values that don't | |
5711 | * have their mappings into nand_ecc_modes_t anymore (they were merged | |
5712 | * with other enums). | |
5713 | */ | |
5714 | if (!strcasecmp(pm, "soft_bch")) | |
5715 | return NAND_ECC_SOFT; | |
5716 | ||
d48f62b9 BB |
5717 | return -ENODEV; |
5718 | } | |
5719 | ||
ba4f46b2 RM |
5720 | static const char * const nand_ecc_algos[] = { |
5721 | [NAND_ECC_HAMMING] = "hamming", | |
5722 | [NAND_ECC_BCH] = "bch", | |
5723 | }; | |
5724 | ||
d48f62b9 BB |
5725 | static int of_get_nand_ecc_algo(struct device_node *np) |
5726 | { | |
5727 | const char *pm; | |
ba4f46b2 | 5728 | int err, i; |
d48f62b9 | 5729 | |
ba4f46b2 RM |
5730 | err = of_property_read_string(np, "nand-ecc-algo", &pm); |
5731 | if (!err) { | |
5732 | for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++) | |
5733 | if (!strcasecmp(pm, nand_ecc_algos[i])) | |
5734 | return i; | |
5735 | return -ENODEV; | |
5736 | } | |
d48f62b9 BB |
5737 | |
5738 | /* | |
5739 | * For backward compatibility we also read "nand-ecc-mode" checking | |
5740 | * for some obsoleted values that were specifying ECC algorithm. | |
5741 | */ | |
5742 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
5743 | if (err < 0) | |
5744 | return err; | |
5745 | ||
5746 | if (!strcasecmp(pm, "soft")) | |
5747 | return NAND_ECC_HAMMING; | |
5748 | else if (!strcasecmp(pm, "soft_bch")) | |
5749 | return NAND_ECC_BCH; | |
5750 | ||
5751 | return -ENODEV; | |
5752 | } | |
5753 | ||
5754 | static int of_get_nand_ecc_step_size(struct device_node *np) | |
5755 | { | |
5756 | int ret; | |
5757 | u32 val; | |
5758 | ||
5759 | ret = of_property_read_u32(np, "nand-ecc-step-size", &val); | |
5760 | return ret ? ret : val; | |
5761 | } | |
5762 | ||
5763 | static int of_get_nand_ecc_strength(struct device_node *np) | |
5764 | { | |
5765 | int ret; | |
5766 | u32 val; | |
5767 | ||
5768 | ret = of_property_read_u32(np, "nand-ecc-strength", &val); | |
5769 | return ret ? ret : val; | |
5770 | } | |
5771 | ||
5772 | static int of_get_nand_bus_width(struct device_node *np) | |
5773 | { | |
5774 | u32 val; | |
5775 | ||
5776 | if (of_property_read_u32(np, "nand-bus-width", &val)) | |
5777 | return 8; | |
5778 | ||
5779 | switch (val) { | |
5780 | case 8: | |
5781 | case 16: | |
5782 | return val; | |
5783 | default: | |
5784 | return -EIO; | |
5785 | } | |
5786 | } | |
5787 | ||
5788 | static bool of_get_nand_on_flash_bbt(struct device_node *np) | |
5789 | { | |
5790 | return of_property_read_bool(np, "nand-on-flash-bbt"); | |
5791 | } | |
5792 | ||
7194a29a | 5793 | static int nand_dt_init(struct nand_chip *chip) |
5844feea | 5794 | { |
7194a29a | 5795 | struct device_node *dn = nand_get_flash_node(chip); |
79082457 | 5796 | int ecc_mode, ecc_algo, ecc_strength, ecc_step; |
5844feea | 5797 | |
7194a29a BB |
5798 | if (!dn) |
5799 | return 0; | |
5800 | ||
5844feea BN |
5801 | if (of_get_nand_bus_width(dn) == 16) |
5802 | chip->options |= NAND_BUSWIDTH_16; | |
5803 | ||
5804 | if (of_get_nand_on_flash_bbt(dn)) | |
5805 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
5806 | ||
5807 | ecc_mode = of_get_nand_ecc_mode(dn); | |
79082457 | 5808 | ecc_algo = of_get_nand_ecc_algo(dn); |
5844feea BN |
5809 | ecc_strength = of_get_nand_ecc_strength(dn); |
5810 | ecc_step = of_get_nand_ecc_step_size(dn); | |
5811 | ||
5844feea BN |
5812 | if (ecc_mode >= 0) |
5813 | chip->ecc.mode = ecc_mode; | |
5814 | ||
79082457 RM |
5815 | if (ecc_algo >= 0) |
5816 | chip->ecc.algo = ecc_algo; | |
5817 | ||
5844feea BN |
5818 | if (ecc_strength >= 0) |
5819 | chip->ecc.strength = ecc_strength; | |
5820 | ||
5821 | if (ecc_step > 0) | |
5822 | chip->ecc.size = ecc_step; | |
5823 | ||
ba78ee00 BB |
5824 | if (of_property_read_bool(dn, "nand-ecc-maximize")) |
5825 | chip->ecc.options |= NAND_ECC_MAXIMIZE; | |
5826 | ||
5844feea BN |
5827 | return 0; |
5828 | } | |
5829 | ||
7aa65bfd | 5830 | /** |
3b85c321 | 5831 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
5832 | * @mtd: MTD device structure |
5833 | * @maxchips: number of chips to scan for | |
5834 | * @table: alternative NAND ID table | |
7aa65bfd | 5835 | * |
8b6e50c9 BN |
5836 | * This is the first phase of the normal nand_scan() function. It reads the |
5837 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd TG |
5838 | * |
5839 | */ | |
5e81e88a DW |
5840 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
5841 | struct nand_flash_dev *table) | |
7aa65bfd | 5842 | { |
bb77082f | 5843 | int i, nand_maf_id, nand_dev_id; |
862eba51 | 5844 | struct nand_chip *chip = mtd_to_nand(mtd); |
5844feea BN |
5845 | int ret; |
5846 | ||
17fa8044 MR |
5847 | /* Enforce the right timings for reset/detection */ |
5848 | onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0); | |
5849 | ||
7194a29a BB |
5850 | ret = nand_dt_init(chip); |
5851 | if (ret) | |
5852 | return ret; | |
7aa65bfd | 5853 | |
f7a8e38f BN |
5854 | if (!mtd->name && mtd->dev.parent) |
5855 | mtd->name = dev_name(mtd->dev.parent); | |
5856 | ||
8878b126 MR |
5857 | /* |
5858 | * ->cmdfunc() is legacy and will only be used if ->exec_op() is not | |
5859 | * populated. | |
5860 | */ | |
5861 | if (!chip->exec_op) { | |
76fe334f | 5862 | /* |
8878b126 MR |
5863 | * Default functions assigned for ->cmdfunc() and |
5864 | * ->select_chip() both expect ->cmd_ctrl() to be populated. | |
76fe334f | 5865 | */ |
8878b126 MR |
5866 | if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) { |
5867 | pr_err("->cmd_ctrl() should be provided\n"); | |
5868 | return -EINVAL; | |
5869 | } | |
76fe334f | 5870 | } |
8878b126 | 5871 | |
7aa65bfd | 5872 | /* Set the default functions */ |
29a198a1 | 5873 | nand_set_defaults(chip); |
7aa65bfd TG |
5874 | |
5875 | /* Read the flash type */ | |
7bb42799 | 5876 | ret = nand_detect(chip, table); |
4722c0e9 | 5877 | if (ret) { |
b1c6e6db | 5878 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 5879 | pr_warn("No NAND device found\n"); |
ace4dfee | 5880 | chip->select_chip(mtd, -1); |
4722c0e9 | 5881 | return ret; |
1da177e4 LT |
5882 | } |
5883 | ||
7f501f0a BB |
5884 | nand_maf_id = chip->id.data[0]; |
5885 | nand_dev_id = chip->id.data[1]; | |
5886 | ||
07300164 HS |
5887 | chip->select_chip(mtd, -1); |
5888 | ||
7aa65bfd | 5889 | /* Check for a chip array */ |
e0c7d767 | 5890 | for (i = 1; i < maxchips; i++) { |
97d90da8 BB |
5891 | u8 id[2]; |
5892 | ||
ef89a880 | 5893 | /* See comment in nand_get_flash_type for reset */ |
73f907fd BB |
5894 | nand_reset(chip, i); |
5895 | ||
5896 | chip->select_chip(mtd, i); | |
1da177e4 | 5897 | /* Send the command for reading device ID */ |
97d90da8 | 5898 | nand_readid_op(chip, 0, id, sizeof(id)); |
1da177e4 | 5899 | /* Read manufacturer and device IDs */ |
97d90da8 | 5900 | if (nand_maf_id != id[0] || nand_dev_id != id[1]) { |
07300164 | 5901 | chip->select_chip(mtd, -1); |
1da177e4 | 5902 | break; |
07300164 HS |
5903 | } |
5904 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
5905 | } |
5906 | if (i > 1) | |
20171642 | 5907 | pr_info("%d chips detected\n", i); |
61b03bd7 | 5908 | |
1da177e4 | 5909 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
5910 | chip->numchips = i; |
5911 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 5912 | |
3b85c321 DW |
5913 | return 0; |
5914 | } | |
7351d3a5 | 5915 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 5916 | |
06f384c9 RM |
5917 | static int nand_set_ecc_soft_ops(struct mtd_info *mtd) |
5918 | { | |
5919 | struct nand_chip *chip = mtd_to_nand(mtd); | |
5920 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
5921 | ||
e4225ae8 | 5922 | if (WARN_ON(ecc->mode != NAND_ECC_SOFT)) |
06f384c9 RM |
5923 | return -EINVAL; |
5924 | ||
5925 | switch (ecc->algo) { | |
5926 | case NAND_ECC_HAMMING: | |
5927 | ecc->calculate = nand_calculate_ecc; | |
5928 | ecc->correct = nand_correct_data; | |
5929 | ecc->read_page = nand_read_page_swecc; | |
5930 | ecc->read_subpage = nand_read_subpage; | |
5931 | ecc->write_page = nand_write_page_swecc; | |
5932 | ecc->read_page_raw = nand_read_page_raw; | |
5933 | ecc->write_page_raw = nand_write_page_raw; | |
5934 | ecc->read_oob = nand_read_oob_std; | |
5935 | ecc->write_oob = nand_write_oob_std; | |
5936 | if (!ecc->size) | |
5937 | ecc->size = 256; | |
5938 | ecc->bytes = 3; | |
5939 | ecc->strength = 1; | |
5940 | return 0; | |
5941 | case NAND_ECC_BCH: | |
5942 | if (!mtd_nand_has_bch()) { | |
5943 | WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
5944 | return -EINVAL; | |
5945 | } | |
5946 | ecc->calculate = nand_bch_calculate_ecc; | |
5947 | ecc->correct = nand_bch_correct_data; | |
5948 | ecc->read_page = nand_read_page_swecc; | |
5949 | ecc->read_subpage = nand_read_subpage; | |
5950 | ecc->write_page = nand_write_page_swecc; | |
5951 | ecc->read_page_raw = nand_read_page_raw; | |
5952 | ecc->write_page_raw = nand_write_page_raw; | |
5953 | ecc->read_oob = nand_read_oob_std; | |
5954 | ecc->write_oob = nand_write_oob_std; | |
8bbba481 | 5955 | |
06f384c9 RM |
5956 | /* |
5957 | * Board driver should supply ecc.size and ecc.strength | |
5958 | * values to select how many bits are correctable. | |
5959 | * Otherwise, default to 4 bits for large page devices. | |
5960 | */ | |
5961 | if (!ecc->size && (mtd->oobsize >= 64)) { | |
5962 | ecc->size = 512; | |
5963 | ecc->strength = 4; | |
5964 | } | |
5965 | ||
5966 | /* | |
5967 | * if no ecc placement scheme was provided pickup the default | |
5968 | * large page one. | |
5969 | */ | |
5970 | if (!mtd->ooblayout) { | |
5971 | /* handle large page devices only */ | |
5972 | if (mtd->oobsize < 64) { | |
5973 | WARN(1, "OOB layout is required when using software BCH on small pages\n"); | |
5974 | return -EINVAL; | |
5975 | } | |
5976 | ||
5977 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); | |
8bbba481 BB |
5978 | |
5979 | } | |
5980 | ||
5981 | /* | |
5982 | * We can only maximize ECC config when the default layout is | |
5983 | * used, otherwise we don't know how many bytes can really be | |
5984 | * used. | |
5985 | */ | |
5986 | if (mtd->ooblayout == &nand_ooblayout_lp_ops && | |
5987 | ecc->options & NAND_ECC_MAXIMIZE) { | |
5988 | int steps, bytes; | |
5989 | ||
5990 | /* Always prefer 1k blocks over 512bytes ones */ | |
5991 | ecc->size = 1024; | |
5992 | steps = mtd->writesize / ecc->size; | |
5993 | ||
5994 | /* Reserve 2 bytes for the BBM */ | |
5995 | bytes = (mtd->oobsize - 2) / steps; | |
5996 | ecc->strength = bytes * 8 / fls(8 * ecc->size); | |
06f384c9 RM |
5997 | } |
5998 | ||
5999 | /* See nand_bch_init() for details. */ | |
6000 | ecc->bytes = 0; | |
6001 | ecc->priv = nand_bch_init(mtd); | |
6002 | if (!ecc->priv) { | |
6003 | WARN(1, "BCH ECC initialization failed!\n"); | |
6004 | return -EINVAL; | |
6005 | } | |
6006 | return 0; | |
6007 | default: | |
6008 | WARN(1, "Unsupported ECC algorithm!\n"); | |
6009 | return -EINVAL; | |
6010 | } | |
6011 | } | |
6012 | ||
2c8f8afa MY |
6013 | /** |
6014 | * nand_check_ecc_caps - check the sanity of preset ECC settings | |
6015 | * @chip: nand chip info structure | |
6016 | * @caps: ECC caps info structure | |
6017 | * @oobavail: OOB size that the ECC engine can use | |
6018 | * | |
6019 | * When ECC step size and strength are already set, check if they are supported | |
6020 | * by the controller and the calculated ECC bytes fit within the chip's OOB. | |
6021 | * On success, the calculated ECC bytes is set. | |
6022 | */ | |
6023 | int nand_check_ecc_caps(struct nand_chip *chip, | |
6024 | const struct nand_ecc_caps *caps, int oobavail) | |
6025 | { | |
6026 | struct mtd_info *mtd = nand_to_mtd(chip); | |
6027 | const struct nand_ecc_step_info *stepinfo; | |
6028 | int preset_step = chip->ecc.size; | |
6029 | int preset_strength = chip->ecc.strength; | |
6030 | int nsteps, ecc_bytes; | |
6031 | int i, j; | |
6032 | ||
6033 | if (WARN_ON(oobavail < 0)) | |
6034 | return -EINVAL; | |
6035 | ||
6036 | if (!preset_step || !preset_strength) | |
6037 | return -ENODATA; | |
6038 | ||
6039 | nsteps = mtd->writesize / preset_step; | |
6040 | ||
6041 | for (i = 0; i < caps->nstepinfos; i++) { | |
6042 | stepinfo = &caps->stepinfos[i]; | |
6043 | ||
6044 | if (stepinfo->stepsize != preset_step) | |
6045 | continue; | |
6046 | ||
6047 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
6048 | if (stepinfo->strengths[j] != preset_strength) | |
6049 | continue; | |
6050 | ||
6051 | ecc_bytes = caps->calc_ecc_bytes(preset_step, | |
6052 | preset_strength); | |
6053 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
6054 | return ecc_bytes; | |
6055 | ||
6056 | if (ecc_bytes * nsteps > oobavail) { | |
6057 | pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", | |
6058 | preset_step, preset_strength); | |
6059 | return -ENOSPC; | |
6060 | } | |
6061 | ||
6062 | chip->ecc.bytes = ecc_bytes; | |
6063 | ||
6064 | return 0; | |
6065 | } | |
6066 | } | |
6067 | ||
6068 | pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", | |
6069 | preset_step, preset_strength); | |
6070 | ||
6071 | return -ENOTSUPP; | |
6072 | } | |
6073 | EXPORT_SYMBOL_GPL(nand_check_ecc_caps); | |
6074 | ||
6075 | /** | |
6076 | * nand_match_ecc_req - meet the chip's requirement with least ECC bytes | |
6077 | * @chip: nand chip info structure | |
6078 | * @caps: ECC engine caps info structure | |
6079 | * @oobavail: OOB size that the ECC engine can use | |
6080 | * | |
6081 | * If a chip's ECC requirement is provided, try to meet it with the least | |
6082 | * number of ECC bytes (i.e. with the largest number of OOB-free bytes). | |
6083 | * On success, the chosen ECC settings are set. | |
6084 | */ | |
6085 | int nand_match_ecc_req(struct nand_chip *chip, | |
6086 | const struct nand_ecc_caps *caps, int oobavail) | |
6087 | { | |
6088 | struct mtd_info *mtd = nand_to_mtd(chip); | |
6089 | const struct nand_ecc_step_info *stepinfo; | |
6090 | int req_step = chip->ecc_step_ds; | |
6091 | int req_strength = chip->ecc_strength_ds; | |
6092 | int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; | |
6093 | int best_step, best_strength, best_ecc_bytes; | |
6094 | int best_ecc_bytes_total = INT_MAX; | |
6095 | int i, j; | |
6096 | ||
6097 | if (WARN_ON(oobavail < 0)) | |
6098 | return -EINVAL; | |
6099 | ||
6100 | /* No information provided by the NAND chip */ | |
6101 | if (!req_step || !req_strength) | |
6102 | return -ENOTSUPP; | |
6103 | ||
6104 | /* number of correctable bits the chip requires in a page */ | |
6105 | req_corr = mtd->writesize / req_step * req_strength; | |
6106 | ||
6107 | for (i = 0; i < caps->nstepinfos; i++) { | |
6108 | stepinfo = &caps->stepinfos[i]; | |
6109 | step_size = stepinfo->stepsize; | |
6110 | ||
6111 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
6112 | strength = stepinfo->strengths[j]; | |
6113 | ||
6114 | /* | |
6115 | * If both step size and strength are smaller than the | |
6116 | * chip's requirement, it is not easy to compare the | |
6117 | * resulted reliability. | |
6118 | */ | |
6119 | if (step_size < req_step && strength < req_strength) | |
6120 | continue; | |
6121 | ||
6122 | if (mtd->writesize % step_size) | |
6123 | continue; | |
6124 | ||
6125 | nsteps = mtd->writesize / step_size; | |
6126 | ||
6127 | ecc_bytes = caps->calc_ecc_bytes(step_size, strength); | |
6128 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
6129 | continue; | |
6130 | ecc_bytes_total = ecc_bytes * nsteps; | |
6131 | ||
6132 | if (ecc_bytes_total > oobavail || | |
6133 | strength * nsteps < req_corr) | |
6134 | continue; | |
6135 | ||
6136 | /* | |
6137 | * We assume the best is to meet the chip's requrement | |
6138 | * with the least number of ECC bytes. | |
6139 | */ | |
6140 | if (ecc_bytes_total < best_ecc_bytes_total) { | |
6141 | best_ecc_bytes_total = ecc_bytes_total; | |
6142 | best_step = step_size; | |
6143 | best_strength = strength; | |
6144 | best_ecc_bytes = ecc_bytes; | |
6145 | } | |
6146 | } | |
6147 | } | |
6148 | ||
6149 | if (best_ecc_bytes_total == INT_MAX) | |
6150 | return -ENOTSUPP; | |
6151 | ||
6152 | chip->ecc.size = best_step; | |
6153 | chip->ecc.strength = best_strength; | |
6154 | chip->ecc.bytes = best_ecc_bytes; | |
6155 | ||
6156 | return 0; | |
6157 | } | |
6158 | EXPORT_SYMBOL_GPL(nand_match_ecc_req); | |
6159 | ||
6160 | /** | |
6161 | * nand_maximize_ecc - choose the max ECC strength available | |
6162 | * @chip: nand chip info structure | |
6163 | * @caps: ECC engine caps info structure | |
6164 | * @oobavail: OOB size that the ECC engine can use | |
6165 | * | |
6166 | * Choose the max ECC strength that is supported on the controller, and can fit | |
6167 | * within the chip's OOB. On success, the chosen ECC settings are set. | |
6168 | */ | |
6169 | int nand_maximize_ecc(struct nand_chip *chip, | |
6170 | const struct nand_ecc_caps *caps, int oobavail) | |
6171 | { | |
6172 | struct mtd_info *mtd = nand_to_mtd(chip); | |
6173 | const struct nand_ecc_step_info *stepinfo; | |
6174 | int step_size, strength, nsteps, ecc_bytes, corr; | |
6175 | int best_corr = 0; | |
6176 | int best_step = 0; | |
6177 | int best_strength, best_ecc_bytes; | |
6178 | int i, j; | |
6179 | ||
6180 | if (WARN_ON(oobavail < 0)) | |
6181 | return -EINVAL; | |
6182 | ||
6183 | for (i = 0; i < caps->nstepinfos; i++) { | |
6184 | stepinfo = &caps->stepinfos[i]; | |
6185 | step_size = stepinfo->stepsize; | |
6186 | ||
6187 | /* If chip->ecc.size is already set, respect it */ | |
6188 | if (chip->ecc.size && step_size != chip->ecc.size) | |
6189 | continue; | |
6190 | ||
6191 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
6192 | strength = stepinfo->strengths[j]; | |
6193 | ||
6194 | if (mtd->writesize % step_size) | |
6195 | continue; | |
6196 | ||
6197 | nsteps = mtd->writesize / step_size; | |
6198 | ||
6199 | ecc_bytes = caps->calc_ecc_bytes(step_size, strength); | |
6200 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
6201 | continue; | |
6202 | ||
6203 | if (ecc_bytes * nsteps > oobavail) | |
6204 | continue; | |
6205 | ||
6206 | corr = strength * nsteps; | |
6207 | ||
6208 | /* | |
6209 | * If the number of correctable bits is the same, | |
6210 | * bigger step_size has more reliability. | |
6211 | */ | |
6212 | if (corr > best_corr || | |
6213 | (corr == best_corr && step_size > best_step)) { | |
6214 | best_corr = corr; | |
6215 | best_step = step_size; | |
6216 | best_strength = strength; | |
6217 | best_ecc_bytes = ecc_bytes; | |
6218 | } | |
6219 | } | |
6220 | } | |
6221 | ||
6222 | if (!best_corr) | |
6223 | return -ENOTSUPP; | |
6224 | ||
6225 | chip->ecc.size = best_step; | |
6226 | chip->ecc.strength = best_strength; | |
6227 | chip->ecc.bytes = best_ecc_bytes; | |
6228 | ||
6229 | return 0; | |
6230 | } | |
6231 | EXPORT_SYMBOL_GPL(nand_maximize_ecc); | |
6232 | ||
67a9ad9b EG |
6233 | /* |
6234 | * Check if the chip configuration meet the datasheet requirements. | |
6235 | ||
6236 | * If our configuration corrects A bits per B bytes and the minimum | |
6237 | * required correction level is X bits per Y bytes, then we must ensure | |
6238 | * both of the following are true: | |
6239 | * | |
6240 | * (1) A / B >= X / Y | |
6241 | * (2) A >= X | |
6242 | * | |
6243 | * Requirement (1) ensures we can correct for the required bitflip density. | |
6244 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
6245 | * in the same sector. | |
6246 | */ | |
6247 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
6248 | { | |
862eba51 | 6249 | struct nand_chip *chip = mtd_to_nand(mtd); |
67a9ad9b EG |
6250 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
6251 | int corr, ds_corr; | |
6252 | ||
6253 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
6254 | /* Not enough information */ | |
6255 | return true; | |
6256 | ||
6257 | /* | |
6258 | * We get the number of corrected bits per page to compare | |
6259 | * the correction density. | |
6260 | */ | |
6261 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
6262 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
6263 | ||
6264 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
6265 | } | |
3b85c321 DW |
6266 | |
6267 | /** | |
6268 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 6269 | * @mtd: MTD device structure |
3b85c321 | 6270 | * |
8b6e50c9 BN |
6271 | * This is the second phase of the normal nand_scan() function. It fills out |
6272 | * all the uninitialized function pointers with the defaults and scans for a | |
6273 | * bad block table if appropriate. | |
3b85c321 DW |
6274 | */ |
6275 | int nand_scan_tail(struct mtd_info *mtd) | |
6276 | { | |
862eba51 | 6277 | struct nand_chip *chip = mtd_to_nand(mtd); |
97de79e0 | 6278 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f84674b8 | 6279 | int ret, i; |
3b85c321 | 6280 | |
e2414f4c | 6281 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
11eaf6df | 6282 | if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && |
78771049 | 6283 | !(chip->bbt_options & NAND_BBT_USE_FLASH))) { |
f84674b8 | 6284 | return -EINVAL; |
78771049 | 6285 | } |
e2414f4c | 6286 | |
c0313b96 | 6287 | chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); |
aeb93af9 BB |
6288 | if (!chip->data_buf) |
6289 | return -ENOMEM; | |
f02ea4e6 | 6290 | |
f84674b8 BB |
6291 | /* |
6292 | * FIXME: some NAND manufacturer drivers expect the first die to be | |
6293 | * selected when manufacturer->init() is called. They should be fixed | |
6294 | * to explictly select the relevant die when interacting with the NAND | |
6295 | * chip. | |
6296 | */ | |
6297 | chip->select_chip(mtd, 0); | |
6298 | ret = nand_manufacturer_init(chip); | |
6299 | chip->select_chip(mtd, -1); | |
6300 | if (ret) | |
c0313b96 | 6301 | goto err_free_buf; |
f84674b8 | 6302 | |
7dcdcbef | 6303 | /* Set the internal oob buffer location, just after the page data */ |
c0313b96 | 6304 | chip->oob_poi = chip->data_buf + mtd->writesize; |
1da177e4 | 6305 | |
7aa65bfd | 6306 | /* |
8b6e50c9 | 6307 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 6308 | */ |
06f384c9 | 6309 | if (!mtd->ooblayout && |
e4225ae8 | 6310 | !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) { |
61b03bd7 | 6311 | switch (mtd->oobsize) { |
1da177e4 | 6312 | case 8: |
1da177e4 | 6313 | case 16: |
41b207a7 | 6314 | mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); |
1da177e4 LT |
6315 | break; |
6316 | case 64: | |
81ec5364 | 6317 | case 128: |
6a623e07 | 6318 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops); |
81ec5364 | 6319 | break; |
1da177e4 | 6320 | default: |
882fd157 MR |
6321 | /* |
6322 | * Expose the whole OOB area to users if ECC_NONE | |
6323 | * is passed. We could do that for all kind of | |
6324 | * ->oobsize, but we must keep the old large/small | |
6325 | * page with ECC layout when ->oobsize <= 128 for | |
6326 | * compatibility reasons. | |
6327 | */ | |
6328 | if (ecc->mode == NAND_ECC_NONE) { | |
6329 | mtd_set_ooblayout(mtd, | |
6330 | &nand_ooblayout_lp_ops); | |
6331 | break; | |
6332 | } | |
6333 | ||
11eaf6df EG |
6334 | WARN(1, "No oob scheme defined for oobsize %d\n", |
6335 | mtd->oobsize); | |
6336 | ret = -EINVAL; | |
f84674b8 | 6337 | goto err_nand_manuf_cleanup; |
1da177e4 LT |
6338 | } |
6339 | } | |
61b03bd7 | 6340 | |
61b03bd7 | 6341 | /* |
8b6e50c9 | 6342 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 6343 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 6344 | */ |
956e944c | 6345 | |
97de79e0 | 6346 | switch (ecc->mode) { |
6e0cb135 SN |
6347 | case NAND_ECC_HW_OOB_FIRST: |
6348 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 6349 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
11eaf6df EG |
6350 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
6351 | ret = -EINVAL; | |
f84674b8 | 6352 | goto err_nand_manuf_cleanup; |
6e0cb135 | 6353 | } |
97de79e0 HS |
6354 | if (!ecc->read_page) |
6355 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 6356 | |
6dfc6d25 | 6357 | case NAND_ECC_HW: |
8b6e50c9 | 6358 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
6359 | if (!ecc->read_page) |
6360 | ecc->read_page = nand_read_page_hwecc; | |
6361 | if (!ecc->write_page) | |
6362 | ecc->write_page = nand_write_page_hwecc; | |
6363 | if (!ecc->read_page_raw) | |
6364 | ecc->read_page_raw = nand_read_page_raw; | |
6365 | if (!ecc->write_page_raw) | |
6366 | ecc->write_page_raw = nand_write_page_raw; | |
6367 | if (!ecc->read_oob) | |
6368 | ecc->read_oob = nand_read_oob_std; | |
6369 | if (!ecc->write_oob) | |
6370 | ecc->write_oob = nand_write_oob_std; | |
6371 | if (!ecc->read_subpage) | |
6372 | ecc->read_subpage = nand_read_subpage; | |
44991b3d | 6373 | if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) |
97de79e0 | 6374 | ecc->write_subpage = nand_write_subpage_hwecc; |
f5bbdacc | 6375 | |
6dfc6d25 | 6376 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
6377 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
6378 | (!ecc->read_page || | |
6379 | ecc->read_page == nand_read_page_hwecc || | |
6380 | !ecc->write_page || | |
6381 | ecc->write_page == nand_write_page_hwecc)) { | |
11eaf6df EG |
6382 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
6383 | ret = -EINVAL; | |
f84674b8 | 6384 | goto err_nand_manuf_cleanup; |
6dfc6d25 | 6385 | } |
8b6e50c9 | 6386 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
6387 | if (!ecc->read_page) |
6388 | ecc->read_page = nand_read_page_syndrome; | |
6389 | if (!ecc->write_page) | |
6390 | ecc->write_page = nand_write_page_syndrome; | |
6391 | if (!ecc->read_page_raw) | |
6392 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
6393 | if (!ecc->write_page_raw) | |
6394 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
6395 | if (!ecc->read_oob) | |
6396 | ecc->read_oob = nand_read_oob_syndrome; | |
6397 | if (!ecc->write_oob) | |
6398 | ecc->write_oob = nand_write_oob_syndrome; | |
6399 | ||
6400 | if (mtd->writesize >= ecc->size) { | |
6401 | if (!ecc->strength) { | |
11eaf6df EG |
6402 | WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); |
6403 | ret = -EINVAL; | |
f84674b8 | 6404 | goto err_nand_manuf_cleanup; |
e2788c98 | 6405 | } |
6dfc6d25 | 6406 | break; |
e2788c98 | 6407 | } |
2ac63d90 RM |
6408 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
6409 | ecc->size, mtd->writesize); | |
97de79e0 | 6410 | ecc->mode = NAND_ECC_SOFT; |
e9d4faed | 6411 | ecc->algo = NAND_ECC_HAMMING; |
61b03bd7 | 6412 | |
6dfc6d25 | 6413 | case NAND_ECC_SOFT: |
06f384c9 RM |
6414 | ret = nand_set_ecc_soft_ops(mtd); |
6415 | if (ret) { | |
11eaf6df | 6416 | ret = -EINVAL; |
f84674b8 | 6417 | goto err_nand_manuf_cleanup; |
193bd400 ID |
6418 | } |
6419 | break; | |
6420 | ||
785818fa TP |
6421 | case NAND_ECC_ON_DIE: |
6422 | if (!ecc->read_page || !ecc->write_page) { | |
6423 | WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); | |
6424 | ret = -EINVAL; | |
f84674b8 | 6425 | goto err_nand_manuf_cleanup; |
785818fa TP |
6426 | } |
6427 | if (!ecc->read_oob) | |
6428 | ecc->read_oob = nand_read_oob_std; | |
6429 | if (!ecc->write_oob) | |
6430 | ecc->write_oob = nand_write_oob_std; | |
6431 | break; | |
6432 | ||
61b03bd7 | 6433 | case NAND_ECC_NONE: |
2ac63d90 | 6434 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
6435 | ecc->read_page = nand_read_page_raw; |
6436 | ecc->write_page = nand_write_page_raw; | |
6437 | ecc->read_oob = nand_read_oob_std; | |
6438 | ecc->read_page_raw = nand_read_page_raw; | |
6439 | ecc->write_page_raw = nand_write_page_raw; | |
6440 | ecc->write_oob = nand_write_oob_std; | |
6441 | ecc->size = mtd->writesize; | |
6442 | ecc->bytes = 0; | |
6443 | ecc->strength = 0; | |
1da177e4 | 6444 | break; |
956e944c | 6445 | |
1da177e4 | 6446 | default: |
11eaf6df EG |
6447 | WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode); |
6448 | ret = -EINVAL; | |
f84674b8 | 6449 | goto err_nand_manuf_cleanup; |
1da177e4 | 6450 | } |
61b03bd7 | 6451 | |
aeb93af9 BB |
6452 | if (ecc->correct || ecc->calculate) { |
6453 | ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); | |
6454 | ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); | |
6455 | if (!ecc->calc_buf || !ecc->code_buf) { | |
6456 | ret = -ENOMEM; | |
6457 | goto err_nand_manuf_cleanup; | |
6458 | } | |
6459 | } | |
6460 | ||
9ce244b3 | 6461 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
6462 | if (!ecc->read_oob_raw) |
6463 | ecc->read_oob_raw = ecc->read_oob; | |
6464 | if (!ecc->write_oob_raw) | |
6465 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 6466 | |
846031d3 | 6467 | /* propagate ecc info to mtd_info */ |
846031d3 BB |
6468 | mtd->ecc_strength = ecc->strength; |
6469 | mtd->ecc_step_size = ecc->size; | |
67a9ad9b | 6470 | |
7aa65bfd TG |
6471 | /* |
6472 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 6473 | * mode. |
7aa65bfd | 6474 | */ |
97de79e0 HS |
6475 | ecc->steps = mtd->writesize / ecc->size; |
6476 | if (ecc->steps * ecc->size != mtd->writesize) { | |
11eaf6df EG |
6477 | WARN(1, "Invalid ECC parameters\n"); |
6478 | ret = -EINVAL; | |
f84674b8 | 6479 | goto err_nand_manuf_cleanup; |
1da177e4 | 6480 | } |
97de79e0 | 6481 | ecc->total = ecc->steps * ecc->bytes; |
79e0348c MY |
6482 | if (ecc->total > mtd->oobsize) { |
6483 | WARN(1, "Total number of ECC bytes exceeded oobsize\n"); | |
6484 | ret = -EINVAL; | |
f84674b8 | 6485 | goto err_nand_manuf_cleanup; |
79e0348c | 6486 | } |
61b03bd7 | 6487 | |
846031d3 BB |
6488 | /* |
6489 | * The number of bytes available for a client to place data into | |
6490 | * the out of band area. | |
6491 | */ | |
6492 | ret = mtd_ooblayout_count_freebytes(mtd); | |
6493 | if (ret < 0) | |
6494 | ret = 0; | |
6495 | ||
6496 | mtd->oobavail = ret; | |
6497 | ||
6498 | /* ECC sanity check: warn if it's too weak */ | |
6499 | if (!nand_ecc_strength_good(mtd)) | |
6500 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
6501 | mtd->name); | |
6502 | ||
8b6e50c9 | 6503 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 6504 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 6505 | switch (ecc->steps) { |
29072b96 TG |
6506 | case 2: |
6507 | mtd->subpage_sft = 1; | |
6508 | break; | |
6509 | case 4: | |
6510 | case 8: | |
81ec5364 | 6511 | case 16: |
29072b96 TG |
6512 | mtd->subpage_sft = 2; |
6513 | break; | |
6514 | } | |
6515 | } | |
6516 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
6517 | ||
04bbd0ea | 6518 | /* Initialize state */ |
ace4dfee | 6519 | chip->state = FL_READY; |
1da177e4 | 6520 | |
1da177e4 | 6521 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 6522 | chip->pagebuf = -1; |
1da177e4 | 6523 | |
a5ff4f10 | 6524 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
6525 | switch (ecc->mode) { |
6526 | case NAND_ECC_SOFT: | |
4007e2d1 RL |
6527 | if (chip->page_shift > 9) |
6528 | chip->options |= NAND_SUBPAGE_READ; | |
6529 | break; | |
6530 | ||
6531 | default: | |
6532 | break; | |
6533 | } | |
a5ff4f10 | 6534 | |
1da177e4 | 6535 | /* Fill in remaining MTD driver data */ |
963d1c28 | 6536 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
6537 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
6538 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
6539 | mtd->_erase = nand_erase; |
6540 | mtd->_point = NULL; | |
6541 | mtd->_unpoint = NULL; | |
6542 | mtd->_read = nand_read; | |
6543 | mtd->_write = nand_write; | |
6544 | mtd->_panic_write = panic_nand_write; | |
6545 | mtd->_read_oob = nand_read_oob; | |
6546 | mtd->_write_oob = nand_write_oob; | |
6547 | mtd->_sync = nand_sync; | |
6548 | mtd->_lock = NULL; | |
6549 | mtd->_unlock = NULL; | |
6550 | mtd->_suspend = nand_suspend; | |
6551 | mtd->_resume = nand_resume; | |
72ea4036 | 6552 | mtd->_reboot = nand_shutdown; |
8471bb73 | 6553 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
6554 | mtd->_block_isbad = nand_block_isbad; |
6555 | mtd->_block_markbad = nand_block_markbad; | |
5671842f | 6556 | mtd->_max_bad_blocks = nand_max_bad_blocks; |
cbcab65a | 6557 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 6558 | |
ea3b2ea2 SL |
6559 | /* |
6560 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
6561 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
6562 | * properly set. | |
6563 | */ | |
6564 | if (!mtd->bitflip_threshold) | |
240181fd | 6565 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 6566 | |
f84674b8 BB |
6567 | /* Initialize the ->data_interface field. */ |
6568 | ret = nand_init_data_interface(chip); | |
6569 | if (ret) | |
6570 | goto err_nand_manuf_cleanup; | |
6571 | ||
6572 | /* Enter fastest possible mode on all dies. */ | |
6573 | for (i = 0; i < chip->numchips; i++) { | |
6574 | chip->select_chip(mtd, i); | |
6575 | ret = nand_setup_data_interface(chip, i); | |
6576 | chip->select_chip(mtd, -1); | |
6577 | ||
6578 | if (ret) | |
17fa8044 | 6579 | goto err_nand_manuf_cleanup; |
f84674b8 BB |
6580 | } |
6581 | ||
0040bf38 | 6582 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 6583 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 6584 | return 0; |
1da177e4 LT |
6585 | |
6586 | /* Build bad block table */ | |
44d4182e BN |
6587 | ret = chip->scan_bbt(mtd); |
6588 | if (ret) | |
17fa8044 | 6589 | goto err_nand_manuf_cleanup; |
f84674b8 | 6590 | |
44d4182e BN |
6591 | return 0; |
6592 | ||
f84674b8 BB |
6593 | |
6594 | err_nand_manuf_cleanup: | |
6595 | nand_manufacturer_cleanup(chip); | |
6596 | ||
c0313b96 MY |
6597 | err_free_buf: |
6598 | kfree(chip->data_buf); | |
6599 | kfree(ecc->code_buf); | |
6600 | kfree(ecc->calc_buf); | |
78771049 | 6601 | |
11eaf6df | 6602 | return ret; |
1da177e4 | 6603 | } |
7351d3a5 | 6604 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 6605 | |
8b6e50c9 BN |
6606 | /* |
6607 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 6608 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
6609 | * to call us from in-kernel code if the core NAND support is modular. |
6610 | */ | |
3b85c321 DW |
6611 | #ifdef MODULE |
6612 | #define caller_is_module() (1) | |
6613 | #else | |
6614 | #define caller_is_module() \ | |
a6e6abd5 | 6615 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
6616 | #endif |
6617 | ||
6618 | /** | |
6619 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
6620 | * @mtd: MTD device structure |
6621 | * @maxchips: number of chips to scan for | |
3b85c321 | 6622 | * |
8b6e50c9 BN |
6623 | * This fills out all the uninitialized function pointers with the defaults. |
6624 | * The flash ID is read and the mtd/chip structures are filled with the | |
20c07a5b | 6625 | * appropriate values. |
3b85c321 DW |
6626 | */ |
6627 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
6628 | { | |
6629 | int ret; | |
6630 | ||
5e81e88a | 6631 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
6632 | if (!ret) |
6633 | ret = nand_scan_tail(mtd); | |
6634 | return ret; | |
6635 | } | |
7351d3a5 | 6636 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 6637 | |
1da177e4 | 6638 | /** |
d44154f9 RW |
6639 | * nand_cleanup - [NAND Interface] Free resources held by the NAND device |
6640 | * @chip: NAND chip object | |
8b6e50c9 | 6641 | */ |
d44154f9 | 6642 | void nand_cleanup(struct nand_chip *chip) |
1da177e4 | 6643 | { |
e4225ae8 | 6644 | if (chip->ecc.mode == NAND_ECC_SOFT && |
06f384c9 | 6645 | chip->ecc.algo == NAND_ECC_BCH) |
193bd400 ID |
6646 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); |
6647 | ||
fa671646 | 6648 | /* Free bad block table memory */ |
ace4dfee | 6649 | kfree(chip->bbt); |
c0313b96 MY |
6650 | kfree(chip->data_buf); |
6651 | kfree(chip->ecc.code_buf); | |
6652 | kfree(chip->ecc.calc_buf); | |
58373ff0 BN |
6653 | |
6654 | /* Free bad block descriptor memory */ | |
6655 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
6656 | & NAND_BBT_DYNAMICSTRUCT) | |
6657 | kfree(chip->badblock_pattern); | |
abbe26d1 BB |
6658 | |
6659 | /* Free manufacturer priv data. */ | |
6660 | nand_manufacturer_cleanup(chip); | |
1da177e4 | 6661 | } |
d44154f9 RW |
6662 | EXPORT_SYMBOL_GPL(nand_cleanup); |
6663 | ||
6664 | /** | |
6665 | * nand_release - [NAND Interface] Unregister the MTD device and free resources | |
6666 | * held by the NAND device | |
6667 | * @mtd: MTD device structure | |
6668 | */ | |
6669 | void nand_release(struct mtd_info *mtd) | |
6670 | { | |
6671 | mtd_device_unregister(mtd); | |
6672 | nand_cleanup(mtd_to_nand(mtd)); | |
6673 | } | |
e0c7d767 | 6674 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 | 6675 | |
e0c7d767 | 6676 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
6677 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
6678 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 6679 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |