Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/mtd/mtd.h> | |
41 | #include <linux/mtd/nand.h> | |
42 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 43 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
44 | #include <linux/interrupt.h> |
45 | #include <linux/bitops.h> | |
7351d3a5 | 46 | #include <linux/io.h> |
1da177e4 | 47 | #include <linux/mtd/partitions.h> |
5844feea | 48 | #include <linux/of_mtd.h> |
1da177e4 LT |
49 | |
50 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 51 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
52 | .eccbytes = 3, |
53 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
54 | .oobfree = { |
55 | {.offset = 3, | |
56 | .length = 2}, | |
57 | {.offset = 6, | |
f8ac0414 | 58 | .length = 2} } |
1da177e4 LT |
59 | }; |
60 | ||
5bd34c09 | 61 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
62 | .eccbytes = 6, |
63 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
64 | .oobfree = { |
65 | {.offset = 8, | |
f8ac0414 | 66 | . length = 8} } |
1da177e4 LT |
67 | }; |
68 | ||
5bd34c09 | 69 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
70 | .eccbytes = 24, |
71 | .eccpos = { | |
e0c7d767 DW |
72 | 40, 41, 42, 43, 44, 45, 46, 47, |
73 | 48, 49, 50, 51, 52, 53, 54, 55, | |
74 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
75 | .oobfree = { |
76 | {.offset = 2, | |
f8ac0414 | 77 | .length = 38} } |
1da177e4 LT |
78 | }; |
79 | ||
81ec5364 TG |
80 | static struct nand_ecclayout nand_oob_128 = { |
81 | .eccbytes = 48, | |
82 | .eccpos = { | |
83 | 80, 81, 82, 83, 84, 85, 86, 87, | |
84 | 88, 89, 90, 91, 92, 93, 94, 95, | |
85 | 96, 97, 98, 99, 100, 101, 102, 103, | |
86 | 104, 105, 106, 107, 108, 109, 110, 111, | |
87 | 112, 113, 114, 115, 116, 117, 118, 119, | |
88 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
89 | .oobfree = { | |
90 | {.offset = 2, | |
f8ac0414 | 91 | .length = 78} } |
81ec5364 TG |
92 | }; |
93 | ||
6a8214aa | 94 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 95 | |
8593fbc6 TG |
96 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
97 | struct mtd_oob_ops *ops); | |
98 | ||
6fe5a6ac VS |
99 | static int check_offs_len(struct mtd_info *mtd, |
100 | loff_t ofs, uint64_t len) | |
101 | { | |
862eba51 | 102 | struct nand_chip *chip = mtd_to_nand(mtd); |
6fe5a6ac VS |
103 | int ret = 0; |
104 | ||
105 | /* Start address must align on block boundary */ | |
daae74ca | 106 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 107 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
108 | ret = -EINVAL; |
109 | } | |
110 | ||
111 | /* Length must align on block boundary */ | |
daae74ca | 112 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 113 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
114 | ret = -EINVAL; |
115 | } | |
116 | ||
6fe5a6ac VS |
117 | return ret; |
118 | } | |
119 | ||
1da177e4 LT |
120 | /** |
121 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 122 | * @mtd: MTD device structure |
61b03bd7 | 123 | * |
b0bb6903 | 124 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 125 | */ |
e0c7d767 | 126 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 127 | { |
862eba51 | 128 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 129 | |
a36ed299 | 130 | /* Release the controller and the chip */ |
ace4dfee TG |
131 | spin_lock(&chip->controller->lock); |
132 | chip->controller->active = NULL; | |
133 | chip->state = FL_READY; | |
134 | wake_up(&chip->controller->wq); | |
135 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
136 | } |
137 | ||
138 | /** | |
139 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 140 | * @mtd: MTD device structure |
1da177e4 | 141 | * |
7854d3f7 | 142 | * Default read function for 8bit buswidth |
1da177e4 | 143 | */ |
58dd8f2b | 144 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 145 | { |
862eba51 | 146 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 147 | return readb(chip->IO_ADDR_R); |
1da177e4 LT |
148 | } |
149 | ||
1da177e4 | 150 | /** |
7854d3f7 | 151 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 152 | * @mtd: MTD device structure |
1da177e4 | 153 | * |
7854d3f7 BN |
154 | * Default read function for 16bit buswidth with endianness conversion. |
155 | * | |
1da177e4 | 156 | */ |
58dd8f2b | 157 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 158 | { |
862eba51 | 159 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 160 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
1da177e4 LT |
161 | } |
162 | ||
1da177e4 LT |
163 | /** |
164 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 165 | * @mtd: MTD device structure |
1da177e4 | 166 | * |
7854d3f7 | 167 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
168 | */ |
169 | static u16 nand_read_word(struct mtd_info *mtd) | |
170 | { | |
862eba51 | 171 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 172 | return readw(chip->IO_ADDR_R); |
1da177e4 LT |
173 | } |
174 | ||
1da177e4 LT |
175 | /** |
176 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
177 | * @mtd: MTD device structure |
178 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
179 | * |
180 | * Default select function for 1 chip devices. | |
181 | */ | |
ace4dfee | 182 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 183 | { |
862eba51 | 184 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
185 | |
186 | switch (chipnr) { | |
1da177e4 | 187 | case -1: |
ace4dfee | 188 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
189 | break; |
190 | case 0: | |
1da177e4 LT |
191 | break; |
192 | ||
193 | default: | |
194 | BUG(); | |
195 | } | |
196 | } | |
197 | ||
05f78359 UKK |
198 | /** |
199 | * nand_write_byte - [DEFAULT] write single byte to chip | |
200 | * @mtd: MTD device structure | |
201 | * @byte: value to write | |
202 | * | |
203 | * Default function to write a byte to I/O[7:0] | |
204 | */ | |
205 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
206 | { | |
862eba51 | 207 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
208 | |
209 | chip->write_buf(mtd, &byte, 1); | |
210 | } | |
211 | ||
212 | /** | |
213 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
214 | * @mtd: MTD device structure | |
215 | * @byte: value to write | |
216 | * | |
217 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
218 | */ | |
219 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
220 | { | |
862eba51 | 221 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
222 | uint16_t word = byte; |
223 | ||
224 | /* | |
225 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
226 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
227 | * | |
228 | * When the host supports a 16-bit bus width, only data is | |
229 | * transferred at the 16-bit width. All address and command line | |
230 | * transfers shall use only the lower 8-bits of the data bus. During | |
231 | * command transfers, the host may place any value on the upper | |
232 | * 8-bits of the data bus. During address transfers, the host shall | |
233 | * set the upper 8-bits of the data bus to 00h. | |
234 | * | |
235 | * One user of the write_byte callback is nand_onfi_set_features. The | |
236 | * four parameters are specified to be written to I/O[7:0], but this is | |
237 | * neither an address nor a command transfer. Let's assume a 0 on the | |
238 | * upper I/O lines is OK. | |
239 | */ | |
240 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
241 | } | |
242 | ||
1da177e4 LT |
243 | /** |
244 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
245 | * @mtd: MTD device structure |
246 | * @buf: data buffer | |
247 | * @len: number of bytes to write | |
1da177e4 | 248 | * |
7854d3f7 | 249 | * Default write function for 8bit buswidth. |
1da177e4 | 250 | */ |
58dd8f2b | 251 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 252 | { |
862eba51 | 253 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 254 | |
76413839 | 255 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
256 | } |
257 | ||
258 | /** | |
61b03bd7 | 259 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
260 | * @mtd: MTD device structure |
261 | * @buf: buffer to store date | |
262 | * @len: number of bytes to read | |
1da177e4 | 263 | * |
7854d3f7 | 264 | * Default read function for 8bit buswidth. |
1da177e4 | 265 | */ |
58dd8f2b | 266 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 267 | { |
862eba51 | 268 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 269 | |
76413839 | 270 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
271 | } |
272 | ||
1da177e4 LT |
273 | /** |
274 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
275 | * @mtd: MTD device structure |
276 | * @buf: data buffer | |
277 | * @len: number of bytes to write | |
1da177e4 | 278 | * |
7854d3f7 | 279 | * Default write function for 16bit buswidth. |
1da177e4 | 280 | */ |
58dd8f2b | 281 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 282 | { |
862eba51 | 283 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 284 | u16 *p = (u16 *) buf; |
61b03bd7 | 285 | |
76413839 | 286 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
287 | } |
288 | ||
289 | /** | |
61b03bd7 | 290 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
291 | * @mtd: MTD device structure |
292 | * @buf: buffer to store date | |
293 | * @len: number of bytes to read | |
1da177e4 | 294 | * |
7854d3f7 | 295 | * Default read function for 16bit buswidth. |
1da177e4 | 296 | */ |
58dd8f2b | 297 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 298 | { |
862eba51 | 299 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 300 | u16 *p = (u16 *) buf; |
1da177e4 | 301 | |
76413839 | 302 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
303 | } |
304 | ||
1da177e4 LT |
305 | /** |
306 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
307 | * @mtd: MTD device structure |
308 | * @ofs: offset from device start | |
1da177e4 | 309 | * |
61b03bd7 | 310 | * Check, if the block is bad. |
1da177e4 | 311 | */ |
9f3e0429 | 312 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 313 | { |
9f3e0429 | 314 | int page, res = 0, i = 0; |
862eba51 | 315 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
316 | u16 bad; |
317 | ||
5fb1549d | 318 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
319 | ofs += mtd->erasesize - mtd->writesize; |
320 | ||
1a12f46a TK |
321 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
322 | ||
cdbec050 BN |
323 | do { |
324 | if (chip->options & NAND_BUSWIDTH_16) { | |
325 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
326 | chip->badblockpos & 0xFE, page); | |
327 | bad = cpu_to_le16(chip->read_word(mtd)); | |
328 | if (chip->badblockpos & 0x1) | |
329 | bad >>= 8; | |
330 | else | |
331 | bad &= 0xFF; | |
332 | } else { | |
333 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
334 | page); | |
335 | bad = chip->read_byte(mtd); | |
336 | } | |
337 | ||
338 | if (likely(chip->badblockbits == 8)) | |
339 | res = bad != 0xFF; | |
e0b58d0a | 340 | else |
cdbec050 BN |
341 | res = hweight8(bad) < chip->badblockbits; |
342 | ofs += mtd->writesize; | |
343 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
344 | i++; | |
345 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 346 | |
1da177e4 LT |
347 | return res; |
348 | } | |
349 | ||
350 | /** | |
5a0edb25 | 351 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
352 | * @mtd: MTD device structure |
353 | * @ofs: offset from device start | |
1da177e4 | 354 | * |
8b6e50c9 | 355 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
356 | * specific driver. It provides the details for writing a bad block marker to a |
357 | * block. | |
358 | */ | |
359 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
360 | { | |
862eba51 | 361 | struct nand_chip *chip = mtd_to_nand(mtd); |
5a0edb25 BN |
362 | struct mtd_oob_ops ops; |
363 | uint8_t buf[2] = { 0, 0 }; | |
364 | int ret = 0, res, i = 0; | |
365 | ||
0ec56dc4 | 366 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
367 | ops.oobbuf = buf; |
368 | ops.ooboffs = chip->badblockpos; | |
369 | if (chip->options & NAND_BUSWIDTH_16) { | |
370 | ops.ooboffs &= ~0x01; | |
371 | ops.len = ops.ooblen = 2; | |
372 | } else { | |
373 | ops.len = ops.ooblen = 1; | |
374 | } | |
375 | ops.mode = MTD_OPS_PLACE_OOB; | |
376 | ||
377 | /* Write to first/last page(s) if necessary */ | |
378 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
379 | ofs += mtd->erasesize - mtd->writesize; | |
380 | do { | |
381 | res = nand_do_write_oob(mtd, ofs, &ops); | |
382 | if (!ret) | |
383 | ret = res; | |
384 | ||
385 | i++; | |
386 | ofs += mtd->writesize; | |
387 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | /** | |
393 | * nand_block_markbad_lowlevel - mark a block bad | |
394 | * @mtd: MTD device structure | |
395 | * @ofs: offset from device start | |
396 | * | |
397 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
398 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
399 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
400 | * | |
b32843b7 | 401 | * We try operations in the following order: |
e2414f4c | 402 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
403 | * (2) write bad block marker to OOB area of affected block (unless flag |
404 | * NAND_BBT_NO_OOB_BBM is present) | |
405 | * (3) update the BBT | |
406 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 407 | * procedures, and dump the error in the end. |
1da177e4 | 408 | */ |
5a0edb25 | 409 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 410 | { |
862eba51 | 411 | struct nand_chip *chip = mtd_to_nand(mtd); |
b32843b7 | 412 | int res, ret = 0; |
61b03bd7 | 413 | |
b32843b7 | 414 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
415 | struct erase_info einfo; |
416 | ||
417 | /* Attempt erase before marking OOB */ | |
418 | memset(&einfo, 0, sizeof(einfo)); | |
419 | einfo.mtd = mtd; | |
420 | einfo.addr = ofs; | |
daae74ca | 421 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 422 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 423 | |
b32843b7 | 424 | /* Write bad block marker to OOB */ |
6a8214aa | 425 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 426 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 427 | nand_release_device(mtd); |
f1a28c02 | 428 | } |
e2414f4c | 429 | |
b32843b7 BN |
430 | /* Mark block bad in BBT */ |
431 | if (chip->bbt) { | |
432 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
433 | if (!ret) |
434 | ret = res; | |
435 | } | |
436 | ||
f1a28c02 TG |
437 | if (!ret) |
438 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 439 | |
f1a28c02 | 440 | return ret; |
1da177e4 LT |
441 | } |
442 | ||
61b03bd7 | 443 | /** |
1da177e4 | 444 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 445 | * @mtd: MTD device structure |
1da177e4 | 446 | * |
8b6e50c9 BN |
447 | * Check, if the device is write protected. The function expects, that the |
448 | * device is already selected. | |
1da177e4 | 449 | */ |
e0c7d767 | 450 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 451 | { |
862eba51 | 452 | struct nand_chip *chip = mtd_to_nand(mtd); |
93edbad6 | 453 | |
8b6e50c9 | 454 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
455 | if (chip->options & NAND_BROKEN_XD) |
456 | return 0; | |
457 | ||
1da177e4 | 458 | /* Check the WP bit */ |
ace4dfee TG |
459 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
460 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
461 | } |
462 | ||
8471bb73 | 463 | /** |
c30e1f79 | 464 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
465 | * @mtd: MTD device structure |
466 | * @ofs: offset from device start | |
467 | * | |
c30e1f79 | 468 | * Check if the block is marked as reserved. |
8471bb73 EG |
469 | */ |
470 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
471 | { | |
862eba51 | 472 | struct nand_chip *chip = mtd_to_nand(mtd); |
8471bb73 EG |
473 | |
474 | if (!chip->bbt) | |
475 | return 0; | |
476 | /* Return info from the table */ | |
477 | return nand_isreserved_bbt(mtd, ofs); | |
478 | } | |
479 | ||
1da177e4 LT |
480 | /** |
481 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
482 | * @mtd: MTD device structure |
483 | * @ofs: offset from device start | |
8b6e50c9 | 484 | * @allowbbt: 1, if its allowed to access the bbt area |
1da177e4 LT |
485 | * |
486 | * Check, if the block is bad. Either by reading the bad block table or | |
487 | * calling of the scan function. | |
488 | */ | |
9f3e0429 | 489 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) |
1da177e4 | 490 | { |
862eba51 | 491 | struct nand_chip *chip = mtd_to_nand(mtd); |
61b03bd7 | 492 | |
ace4dfee | 493 | if (!chip->bbt) |
9f3e0429 | 494 | return chip->block_bad(mtd, ofs); |
61b03bd7 | 495 | |
1da177e4 | 496 | /* Return info from the table */ |
e0c7d767 | 497 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
498 | } |
499 | ||
2af7c653 SK |
500 | /** |
501 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
502 | * @mtd: MTD device structure |
503 | * @timeo: Timeout | |
2af7c653 SK |
504 | * |
505 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
506 | * context. | |
507 | */ | |
508 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
509 | { | |
862eba51 | 510 | struct nand_chip *chip = mtd_to_nand(mtd); |
2af7c653 SK |
511 | int i; |
512 | ||
513 | /* Wait for the device to get ready */ | |
514 | for (i = 0; i < timeo; i++) { | |
515 | if (chip->dev_ready(mtd)) | |
516 | break; | |
517 | touch_softlockup_watchdog(); | |
518 | mdelay(1); | |
519 | } | |
520 | } | |
521 | ||
b70af9be AS |
522 | /** |
523 | * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
524 | * @mtd: MTD device structure | |
525 | * | |
526 | * Wait for the ready pin after a command, and warn if a timeout occurs. | |
527 | */ | |
4b648b02 | 528 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 529 | { |
862eba51 | 530 | struct nand_chip *chip = mtd_to_nand(mtd); |
b70af9be | 531 | unsigned long timeo = 400; |
3b88775c | 532 | |
2af7c653 | 533 | if (in_interrupt() || oops_in_progress) |
b70af9be | 534 | return panic_nand_wait_ready(mtd, timeo); |
2af7c653 | 535 | |
7854d3f7 | 536 | /* Wait until command is processed or timeout occurs */ |
b70af9be | 537 | timeo = jiffies + msecs_to_jiffies(timeo); |
3b88775c | 538 | do { |
ace4dfee | 539 | if (chip->dev_ready(mtd)) |
4c7e054f | 540 | return; |
b70af9be | 541 | cond_resched(); |
61b03bd7 | 542 | } while (time_before(jiffies, timeo)); |
b70af9be | 543 | |
9ebfdf5b BN |
544 | if (!chip->dev_ready(mtd)) |
545 | pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); | |
3b88775c | 546 | } |
4b648b02 | 547 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 548 | |
60c70d66 RQ |
549 | /** |
550 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
551 | * @mtd: MTD device structure | |
552 | * @timeo: Timeout in ms | |
553 | * | |
554 | * Wait for status ready (i.e. command done) or timeout. | |
555 | */ | |
556 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
557 | { | |
862eba51 | 558 | register struct nand_chip *chip = mtd_to_nand(mtd); |
60c70d66 RQ |
559 | |
560 | timeo = jiffies + msecs_to_jiffies(timeo); | |
561 | do { | |
562 | if ((chip->read_byte(mtd) & NAND_STATUS_READY)) | |
563 | break; | |
564 | touch_softlockup_watchdog(); | |
565 | } while (time_before(jiffies, timeo)); | |
566 | }; | |
567 | ||
1da177e4 LT |
568 | /** |
569 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
570 | * @mtd: MTD device structure |
571 | * @command: the command to be sent | |
572 | * @column: the column address for this command, -1 if none | |
573 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 574 | * |
8b6e50c9 | 575 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 576 | * (512 Bytes per page). |
1da177e4 | 577 | */ |
7abd3ef9 TG |
578 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
579 | int column, int page_addr) | |
1da177e4 | 580 | { |
862eba51 | 581 | register struct nand_chip *chip = mtd_to_nand(mtd); |
7abd3ef9 | 582 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 583 | |
8b6e50c9 | 584 | /* Write out the command to the device */ |
1da177e4 LT |
585 | if (command == NAND_CMD_SEQIN) { |
586 | int readcmd; | |
587 | ||
28318776 | 588 | if (column >= mtd->writesize) { |
1da177e4 | 589 | /* OOB area */ |
28318776 | 590 | column -= mtd->writesize; |
1da177e4 LT |
591 | readcmd = NAND_CMD_READOOB; |
592 | } else if (column < 256) { | |
593 | /* First 256 bytes --> READ0 */ | |
594 | readcmd = NAND_CMD_READ0; | |
595 | } else { | |
596 | column -= 256; | |
597 | readcmd = NAND_CMD_READ1; | |
598 | } | |
ace4dfee | 599 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 600 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 601 | } |
ace4dfee | 602 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 603 | |
8b6e50c9 | 604 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
605 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
606 | /* Serially input address */ | |
607 | if (column != -1) { | |
608 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
609 | if (chip->options & NAND_BUSWIDTH_16 && |
610 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 611 | column >>= 1; |
ace4dfee | 612 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
613 | ctrl &= ~NAND_CTRL_CHANGE; |
614 | } | |
615 | if (page_addr != -1) { | |
ace4dfee | 616 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 617 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 618 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 619 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
620 | if (chip->chipsize > (32 << 20)) |
621 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 622 | } |
ace4dfee | 623 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
624 | |
625 | /* | |
8b6e50c9 BN |
626 | * Program and erase have their own busy handlers status and sequential |
627 | * in needs no delay | |
e0c7d767 | 628 | */ |
1da177e4 | 629 | switch (command) { |
61b03bd7 | 630 | |
1da177e4 LT |
631 | case NAND_CMD_PAGEPROG: |
632 | case NAND_CMD_ERASE1: | |
633 | case NAND_CMD_ERASE2: | |
634 | case NAND_CMD_SEQIN: | |
635 | case NAND_CMD_STATUS: | |
636 | return; | |
637 | ||
638 | case NAND_CMD_RESET: | |
ace4dfee | 639 | if (chip->dev_ready) |
1da177e4 | 640 | break; |
ace4dfee TG |
641 | udelay(chip->chip_delay); |
642 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 643 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
644 | chip->cmd_ctrl(mtd, |
645 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
646 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
647 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
648 | return; |
649 | ||
e0c7d767 | 650 | /* This applies to read commands */ |
1da177e4 | 651 | default: |
61b03bd7 | 652 | /* |
1da177e4 LT |
653 | * If we don't have access to the busy pin, we apply the given |
654 | * command delay | |
e0c7d767 | 655 | */ |
ace4dfee TG |
656 | if (!chip->dev_ready) { |
657 | udelay(chip->chip_delay); | |
1da177e4 | 658 | return; |
61b03bd7 | 659 | } |
1da177e4 | 660 | } |
8b6e50c9 BN |
661 | /* |
662 | * Apply this short delay always to ensure that we do wait tWB in | |
663 | * any case on any machine. | |
664 | */ | |
e0c7d767 | 665 | ndelay(100); |
3b88775c TG |
666 | |
667 | nand_wait_ready(mtd); | |
1da177e4 LT |
668 | } |
669 | ||
670 | /** | |
671 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
672 | * @mtd: MTD device structure |
673 | * @command: the command to be sent | |
674 | * @column: the column address for this command, -1 if none | |
675 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 676 | * |
7abd3ef9 | 677 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
678 | * devices. We don't have the separate regions as we have in the small page |
679 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 680 | */ |
7abd3ef9 TG |
681 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
682 | int column, int page_addr) | |
1da177e4 | 683 | { |
862eba51 | 684 | register struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
685 | |
686 | /* Emulate NAND_CMD_READOOB */ | |
687 | if (command == NAND_CMD_READOOB) { | |
28318776 | 688 | column += mtd->writesize; |
1da177e4 LT |
689 | command = NAND_CMD_READ0; |
690 | } | |
61b03bd7 | 691 | |
7abd3ef9 | 692 | /* Command latch cycle */ |
fb066ada | 693 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
694 | |
695 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 696 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
697 | |
698 | /* Serially input address */ | |
699 | if (column != -1) { | |
700 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
701 | if (chip->options & NAND_BUSWIDTH_16 && |
702 | !nand_opcode_8bits(command)) | |
1da177e4 | 703 | column >>= 1; |
ace4dfee | 704 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 705 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 706 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 707 | } |
1da177e4 | 708 | if (page_addr != -1) { |
ace4dfee TG |
709 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
710 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 711 | NAND_NCE | NAND_ALE); |
1da177e4 | 712 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
713 | if (chip->chipsize > (128 << 20)) |
714 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 715 | NAND_NCE | NAND_ALE); |
1da177e4 | 716 | } |
1da177e4 | 717 | } |
ace4dfee | 718 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
719 | |
720 | /* | |
8b6e50c9 | 721 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 722 | * in and status need no delay. |
30f464b7 | 723 | */ |
1da177e4 | 724 | switch (command) { |
61b03bd7 | 725 | |
1da177e4 LT |
726 | case NAND_CMD_CACHEDPROG: |
727 | case NAND_CMD_PAGEPROG: | |
728 | case NAND_CMD_ERASE1: | |
729 | case NAND_CMD_ERASE2: | |
730 | case NAND_CMD_SEQIN: | |
7bc3312b | 731 | case NAND_CMD_RNDIN: |
1da177e4 | 732 | case NAND_CMD_STATUS: |
30f464b7 | 733 | return; |
1da177e4 LT |
734 | |
735 | case NAND_CMD_RESET: | |
ace4dfee | 736 | if (chip->dev_ready) |
1da177e4 | 737 | break; |
ace4dfee | 738 | udelay(chip->chip_delay); |
12efdde3 TG |
739 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
740 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
741 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
742 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
743 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
744 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
745 | return; |
746 | ||
7bc3312b TG |
747 | case NAND_CMD_RNDOUT: |
748 | /* No ready / busy check necessary */ | |
749 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
750 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
751 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
752 | NAND_NCE | NAND_CTRL_CHANGE); | |
753 | return; | |
754 | ||
1da177e4 | 755 | case NAND_CMD_READ0: |
12efdde3 TG |
756 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
757 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
758 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
759 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 760 | |
e0c7d767 | 761 | /* This applies to read commands */ |
1da177e4 | 762 | default: |
61b03bd7 | 763 | /* |
1da177e4 | 764 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 765 | * command delay. |
e0c7d767 | 766 | */ |
ace4dfee TG |
767 | if (!chip->dev_ready) { |
768 | udelay(chip->chip_delay); | |
1da177e4 | 769 | return; |
61b03bd7 | 770 | } |
1da177e4 | 771 | } |
3b88775c | 772 | |
8b6e50c9 BN |
773 | /* |
774 | * Apply this short delay always to ensure that we do wait tWB in | |
775 | * any case on any machine. | |
776 | */ | |
e0c7d767 | 777 | ndelay(100); |
3b88775c TG |
778 | |
779 | nand_wait_ready(mtd); | |
1da177e4 LT |
780 | } |
781 | ||
2af7c653 SK |
782 | /** |
783 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
784 | * @chip: the nand chip descriptor |
785 | * @mtd: MTD device structure | |
786 | * @new_state: the state which is requested | |
2af7c653 SK |
787 | * |
788 | * Used when in panic, no locks are taken. | |
789 | */ | |
790 | static void panic_nand_get_device(struct nand_chip *chip, | |
791 | struct mtd_info *mtd, int new_state) | |
792 | { | |
7854d3f7 | 793 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
794 | chip->controller->active = chip; |
795 | chip->state = new_state; | |
796 | } | |
797 | ||
1da177e4 LT |
798 | /** |
799 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
800 | * @mtd: MTD device structure |
801 | * @new_state: the state which is requested | |
1da177e4 LT |
802 | * |
803 | * Get the device and lock it for exclusive access | |
804 | */ | |
2c0a2bed | 805 | static int |
6a8214aa | 806 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 807 | { |
862eba51 | 808 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
809 | spinlock_t *lock = &chip->controller->lock; |
810 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 811 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 812 | retry: |
0dfc6246 TG |
813 | spin_lock(lock); |
814 | ||
b8b3ee9a | 815 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
816 | if (!chip->controller->active) |
817 | chip->controller->active = chip; | |
a36ed299 | 818 | |
ace4dfee TG |
819 | if (chip->controller->active == chip && chip->state == FL_READY) { |
820 | chip->state = new_state; | |
0dfc6246 | 821 | spin_unlock(lock); |
962034f4 VW |
822 | return 0; |
823 | } | |
824 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
825 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
826 | chip->state = FL_PM_SUSPENDED; | |
827 | spin_unlock(lock); | |
828 | return 0; | |
6b0d9a84 | 829 | } |
0dfc6246 TG |
830 | } |
831 | set_current_state(TASK_UNINTERRUPTIBLE); | |
832 | add_wait_queue(wq, &wait); | |
833 | spin_unlock(lock); | |
834 | schedule(); | |
835 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
836 | goto retry; |
837 | } | |
838 | ||
2af7c653 | 839 | /** |
8b6e50c9 BN |
840 | * panic_nand_wait - [GENERIC] wait until the command is done |
841 | * @mtd: MTD device structure | |
842 | * @chip: NAND chip structure | |
843 | * @timeo: timeout | |
2af7c653 SK |
844 | * |
845 | * Wait for command done. This is a helper function for nand_wait used when | |
846 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 847 | * an oops through mtdoops. |
2af7c653 SK |
848 | */ |
849 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
850 | unsigned long timeo) | |
851 | { | |
852 | int i; | |
853 | for (i = 0; i < timeo; i++) { | |
854 | if (chip->dev_ready) { | |
855 | if (chip->dev_ready(mtd)) | |
856 | break; | |
857 | } else { | |
858 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
859 | break; | |
860 | } | |
861 | mdelay(1); | |
f8ac0414 | 862 | } |
2af7c653 SK |
863 | } |
864 | ||
1da177e4 | 865 | /** |
8b6e50c9 BN |
866 | * nand_wait - [DEFAULT] wait until the command is done |
867 | * @mtd: MTD device structure | |
868 | * @chip: NAND chip structure | |
1da177e4 | 869 | * |
b70af9be | 870 | * Wait for command done. This applies to erase and program only. |
844d3b42 | 871 | */ |
7bc3312b | 872 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
873 | { |
874 | ||
b70af9be AS |
875 | int status; |
876 | unsigned long timeo = 400; | |
1da177e4 | 877 | |
8b6e50c9 BN |
878 | /* |
879 | * Apply this short delay always to ensure that we do wait tWB in any | |
880 | * case on any machine. | |
881 | */ | |
e0c7d767 | 882 | ndelay(100); |
1da177e4 | 883 | |
14c65786 | 884 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 885 | |
2af7c653 SK |
886 | if (in_interrupt() || oops_in_progress) |
887 | panic_nand_wait(mtd, chip, timeo); | |
888 | else { | |
6d2559f8 | 889 | timeo = jiffies + msecs_to_jiffies(timeo); |
b70af9be | 890 | do { |
2af7c653 SK |
891 | if (chip->dev_ready) { |
892 | if (chip->dev_ready(mtd)) | |
893 | break; | |
894 | } else { | |
895 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
896 | break; | |
897 | } | |
898 | cond_resched(); | |
b70af9be | 899 | } while (time_before(jiffies, timeo)); |
1da177e4 | 900 | } |
8fe833c1 | 901 | |
ace4dfee | 902 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
903 | /* This can happen if in case of timeout or buggy dev_ready */ |
904 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
905 | return status; |
906 | } | |
907 | ||
7d70f334 | 908 | /** |
b6d676db | 909 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
910 | * @mtd: mtd info |
911 | * @ofs: offset to start unlock from | |
912 | * @len: length to unlock | |
8b6e50c9 BN |
913 | * @invert: when = 0, unlock the range of blocks within the lower and |
914 | * upper boundary address | |
915 | * when = 1, unlock the range of blocks outside the boundaries | |
916 | * of the lower and upper boundary address | |
7d70f334 | 917 | * |
8b6e50c9 | 918 | * Returs unlock status. |
7d70f334 VS |
919 | */ |
920 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
921 | uint64_t len, int invert) | |
922 | { | |
923 | int ret = 0; | |
924 | int status, page; | |
862eba51 | 925 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 VS |
926 | |
927 | /* Submit address of first page to unlock */ | |
928 | page = ofs >> chip->page_shift; | |
929 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
930 | ||
931 | /* Submit address of last page to unlock */ | |
932 | page = (ofs + len) >> chip->page_shift; | |
933 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
934 | (page | invert) & chip->pagemask); | |
935 | ||
936 | /* Call wait ready function */ | |
937 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 938 | /* See if device thinks it succeeded */ |
74830966 | 939 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 940 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
941 | __func__, status); |
942 | ret = -EIO; | |
943 | } | |
944 | ||
945 | return ret; | |
946 | } | |
947 | ||
948 | /** | |
b6d676db | 949 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
950 | * @mtd: mtd info |
951 | * @ofs: offset to start unlock from | |
952 | * @len: length to unlock | |
7d70f334 | 953 | * |
8b6e50c9 | 954 | * Returns unlock status. |
7d70f334 VS |
955 | */ |
956 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
957 | { | |
958 | int ret = 0; | |
959 | int chipnr; | |
862eba51 | 960 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 961 | |
289c0522 | 962 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
963 | __func__, (unsigned long long)ofs, len); |
964 | ||
965 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 966 | return -EINVAL; |
7d70f334 VS |
967 | |
968 | /* Align to last block address if size addresses end of the device */ | |
969 | if (ofs + len == mtd->size) | |
970 | len -= mtd->erasesize; | |
971 | ||
6a8214aa | 972 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
973 | |
974 | /* Shift to get chip number */ | |
975 | chipnr = ofs >> chip->chip_shift; | |
976 | ||
977 | chip->select_chip(mtd, chipnr); | |
978 | ||
57d3a9a8 WD |
979 | /* |
980 | * Reset the chip. | |
981 | * If we want to check the WP through READ STATUS and check the bit 7 | |
982 | * we must reset the chip | |
983 | * some operation can also clear the bit 7 of status register | |
984 | * eg. erase/program a locked block | |
985 | */ | |
986 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
987 | ||
7d70f334 VS |
988 | /* Check, if it is write protected */ |
989 | if (nand_check_wp(mtd)) { | |
289c0522 | 990 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
991 | __func__); |
992 | ret = -EIO; | |
993 | goto out; | |
994 | } | |
995 | ||
996 | ret = __nand_unlock(mtd, ofs, len, 0); | |
997 | ||
998 | out: | |
b0bb6903 | 999 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1000 | nand_release_device(mtd); |
1001 | ||
1002 | return ret; | |
1003 | } | |
7351d3a5 | 1004 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1005 | |
1006 | /** | |
b6d676db | 1007 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1008 | * @mtd: mtd info |
1009 | * @ofs: offset to start unlock from | |
1010 | * @len: length to unlock | |
7d70f334 | 1011 | * |
8b6e50c9 BN |
1012 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1013 | * have this feature, but it allows only to lock all blocks, not for specified | |
1014 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1015 | * now. | |
7d70f334 | 1016 | * |
8b6e50c9 | 1017 | * Returns lock status. |
7d70f334 VS |
1018 | */ |
1019 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1020 | { | |
1021 | int ret = 0; | |
1022 | int chipnr, status, page; | |
862eba51 | 1023 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 1024 | |
289c0522 | 1025 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1026 | __func__, (unsigned long long)ofs, len); |
1027 | ||
1028 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1029 | return -EINVAL; |
7d70f334 | 1030 | |
6a8214aa | 1031 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1032 | |
1033 | /* Shift to get chip number */ | |
1034 | chipnr = ofs >> chip->chip_shift; | |
1035 | ||
1036 | chip->select_chip(mtd, chipnr); | |
1037 | ||
57d3a9a8 WD |
1038 | /* |
1039 | * Reset the chip. | |
1040 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1041 | * we must reset the chip | |
1042 | * some operation can also clear the bit 7 of status register | |
1043 | * eg. erase/program a locked block | |
1044 | */ | |
1045 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1046 | ||
7d70f334 VS |
1047 | /* Check, if it is write protected */ |
1048 | if (nand_check_wp(mtd)) { | |
289c0522 | 1049 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1050 | __func__); |
1051 | status = MTD_ERASE_FAILED; | |
1052 | ret = -EIO; | |
1053 | goto out; | |
1054 | } | |
1055 | ||
1056 | /* Submit address of first page to lock */ | |
1057 | page = ofs >> chip->page_shift; | |
1058 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1059 | ||
1060 | /* Call wait ready function */ | |
1061 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1062 | /* See if device thinks it succeeded */ |
74830966 | 1063 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1064 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1065 | __func__, status); |
1066 | ret = -EIO; | |
1067 | goto out; | |
1068 | } | |
1069 | ||
1070 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1071 | ||
1072 | out: | |
b0bb6903 | 1073 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1074 | nand_release_device(mtd); |
1075 | ||
1076 | return ret; | |
1077 | } | |
7351d3a5 | 1078 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1079 | |
730a43fb BB |
1080 | /** |
1081 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
1082 | * @buf: buffer to test | |
1083 | * @len: buffer length | |
1084 | * @bitflips_threshold: maximum number of bitflips | |
1085 | * | |
1086 | * Check if a buffer contains only 0xff, which means the underlying region | |
1087 | * has been erased and is ready to be programmed. | |
1088 | * The bitflips_threshold specify the maximum number of bitflips before | |
1089 | * considering the region is not erased. | |
1090 | * Note: The logic of this function has been extracted from the memweight | |
1091 | * implementation, except that nand_check_erased_buf function exit before | |
1092 | * testing the whole buffer if the number of bitflips exceed the | |
1093 | * bitflips_threshold value. | |
1094 | * | |
1095 | * Returns a positive number of bitflips less than or equal to | |
1096 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1097 | * threshold. | |
1098 | */ | |
1099 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
1100 | { | |
1101 | const unsigned char *bitmap = buf; | |
1102 | int bitflips = 0; | |
1103 | int weight; | |
1104 | ||
1105 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
1106 | len--, bitmap++) { | |
1107 | weight = hweight8(*bitmap); | |
1108 | bitflips += BITS_PER_BYTE - weight; | |
1109 | if (unlikely(bitflips > bitflips_threshold)) | |
1110 | return -EBADMSG; | |
1111 | } | |
1112 | ||
1113 | for (; len >= sizeof(long); | |
1114 | len -= sizeof(long), bitmap += sizeof(long)) { | |
1115 | weight = hweight_long(*((unsigned long *)bitmap)); | |
1116 | bitflips += BITS_PER_LONG - weight; | |
1117 | if (unlikely(bitflips > bitflips_threshold)) | |
1118 | return -EBADMSG; | |
1119 | } | |
1120 | ||
1121 | for (; len > 0; len--, bitmap++) { | |
1122 | weight = hweight8(*bitmap); | |
1123 | bitflips += BITS_PER_BYTE - weight; | |
1124 | if (unlikely(bitflips > bitflips_threshold)) | |
1125 | return -EBADMSG; | |
1126 | } | |
1127 | ||
1128 | return bitflips; | |
1129 | } | |
1130 | ||
1131 | /** | |
1132 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
1133 | * 0xff data | |
1134 | * @data: data buffer to test | |
1135 | * @datalen: data length | |
1136 | * @ecc: ECC buffer | |
1137 | * @ecclen: ECC length | |
1138 | * @extraoob: extra OOB buffer | |
1139 | * @extraooblen: extra OOB length | |
1140 | * @bitflips_threshold: maximum number of bitflips | |
1141 | * | |
1142 | * Check if a data buffer and its associated ECC and OOB data contains only | |
1143 | * 0xff pattern, which means the underlying region has been erased and is | |
1144 | * ready to be programmed. | |
1145 | * The bitflips_threshold specify the maximum number of bitflips before | |
1146 | * considering the region as not erased. | |
1147 | * | |
1148 | * Note: | |
1149 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
1150 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
1151 | * report the number of errors per chunk, and the NAND core infrastructure | |
1152 | * expect you to return the maximum number of bitflips for the whole page. | |
1153 | * This is why you should always use this function on a single chunk and | |
1154 | * not on the whole page. After checking each chunk you should update your | |
1155 | * max_bitflips value accordingly. | |
1156 | * 2/ When checking for bitflips in erased pages you should not only check | |
1157 | * the payload data but also their associated ECC data, because a user might | |
1158 | * have programmed almost all bits to 1 but a few. In this case, we | |
1159 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
1160 | * this case. | |
1161 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
1162 | * data are protected by the ECC engine. | |
1163 | * It could also be used if you support subpages and want to attach some | |
1164 | * extra OOB data to an ECC chunk. | |
1165 | * | |
1166 | * Returns a positive number of bitflips less than or equal to | |
1167 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1168 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
1169 | */ | |
1170 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1171 | void *ecc, int ecclen, | |
1172 | void *extraoob, int extraooblen, | |
1173 | int bitflips_threshold) | |
1174 | { | |
1175 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
1176 | ||
1177 | data_bitflips = nand_check_erased_buf(data, datalen, | |
1178 | bitflips_threshold); | |
1179 | if (data_bitflips < 0) | |
1180 | return data_bitflips; | |
1181 | ||
1182 | bitflips_threshold -= data_bitflips; | |
1183 | ||
1184 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
1185 | if (ecc_bitflips < 0) | |
1186 | return ecc_bitflips; | |
1187 | ||
1188 | bitflips_threshold -= ecc_bitflips; | |
1189 | ||
1190 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
1191 | bitflips_threshold); | |
1192 | if (extraoob_bitflips < 0) | |
1193 | return extraoob_bitflips; | |
1194 | ||
1195 | if (data_bitflips) | |
1196 | memset(data, 0xff, datalen); | |
1197 | ||
1198 | if (ecc_bitflips) | |
1199 | memset(ecc, 0xff, ecclen); | |
1200 | ||
1201 | if (extraoob_bitflips) | |
1202 | memset(extraoob, 0xff, extraooblen); | |
1203 | ||
1204 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
1205 | } | |
1206 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
1207 | ||
8593fbc6 | 1208 | /** |
7854d3f7 | 1209 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1210 | * @mtd: mtd info structure |
1211 | * @chip: nand chip info structure | |
1212 | * @buf: buffer to store read data | |
1fbb938d | 1213 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1214 | * @page: page number to read |
52ff49df | 1215 | * |
7854d3f7 | 1216 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1217 | */ |
1218 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1219 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1220 | { |
1221 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1222 | if (oob_required) |
1223 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1224 | return 0; |
1225 | } | |
1226 | ||
52ff49df | 1227 | /** |
7854d3f7 | 1228 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1229 | * @mtd: mtd info structure |
1230 | * @chip: nand chip info structure | |
1231 | * @buf: buffer to store read data | |
1fbb938d | 1232 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1233 | * @page: page number to read |
52ff49df DB |
1234 | * |
1235 | * We need a special oob layout and handling even when OOB isn't used. | |
1236 | */ | |
7351d3a5 | 1237 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1238 | struct nand_chip *chip, uint8_t *buf, |
1239 | int oob_required, int page) | |
52ff49df DB |
1240 | { |
1241 | int eccsize = chip->ecc.size; | |
1242 | int eccbytes = chip->ecc.bytes; | |
1243 | uint8_t *oob = chip->oob_poi; | |
1244 | int steps, size; | |
1245 | ||
1246 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1247 | chip->read_buf(mtd, buf, eccsize); | |
1248 | buf += eccsize; | |
1249 | ||
1250 | if (chip->ecc.prepad) { | |
1251 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1252 | oob += chip->ecc.prepad; | |
1253 | } | |
1254 | ||
1255 | chip->read_buf(mtd, oob, eccbytes); | |
1256 | oob += eccbytes; | |
1257 | ||
1258 | if (chip->ecc.postpad) { | |
1259 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1260 | oob += chip->ecc.postpad; | |
1261 | } | |
1262 | } | |
1263 | ||
1264 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1265 | if (size) | |
1266 | chip->read_buf(mtd, oob, size); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
1da177e4 | 1271 | /** |
7854d3f7 | 1272 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1273 | * @mtd: mtd info structure |
1274 | * @chip: nand chip info structure | |
1275 | * @buf: buffer to store read data | |
1fbb938d | 1276 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1277 | * @page: page number to read |
068e3c0a | 1278 | */ |
f5bbdacc | 1279 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1280 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1281 | { |
f5bbdacc TG |
1282 | int i, eccsize = chip->ecc.size; |
1283 | int eccbytes = chip->ecc.bytes; | |
1284 | int eccsteps = chip->ecc.steps; | |
1285 | uint8_t *p = buf; | |
4bf63fcb DW |
1286 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1287 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1288 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1289 | unsigned int max_bitflips = 0; |
f5bbdacc | 1290 | |
1fbb938d | 1291 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1292 | |
1293 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1294 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1295 | ||
1296 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1297 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1298 | |
1299 | eccsteps = chip->ecc.steps; | |
1300 | p = buf; | |
1301 | ||
1302 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1303 | int stat; | |
1304 | ||
1305 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1306 | if (stat < 0) { |
f5bbdacc | 1307 | mtd->ecc_stats.failed++; |
3f91e94f | 1308 | } else { |
f5bbdacc | 1309 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1310 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1311 | } | |
f5bbdacc | 1312 | } |
3f91e94f | 1313 | return max_bitflips; |
22c60f5f | 1314 | } |
1da177e4 | 1315 | |
3d459559 | 1316 | /** |
837a6ba4 | 1317 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1318 | * @mtd: mtd info structure |
1319 | * @chip: nand chip info structure | |
1320 | * @data_offs: offset of requested data within the page | |
1321 | * @readlen: data length | |
1322 | * @bufpoi: buffer to store read data | |
e004debd | 1323 | * @page: page number to read |
3d459559 | 1324 | */ |
7351d3a5 | 1325 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1326 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1327 | int page) | |
3d459559 AK |
1328 | { |
1329 | int start_step, end_step, num_steps; | |
1330 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1331 | uint8_t *p; | |
1332 | int data_col_addr, i, gaps = 0; | |
1333 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1334 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1335 | int index; |
3f91e94f | 1336 | unsigned int max_bitflips = 0; |
3d459559 | 1337 | |
7854d3f7 | 1338 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1339 | start_step = data_offs / chip->ecc.size; |
1340 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1341 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1342 | index = start_step * chip->ecc.bytes; |
3d459559 | 1343 | |
8b6e50c9 | 1344 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1345 | datafrag_len = num_steps * chip->ecc.size; |
1346 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1347 | ||
1348 | data_col_addr = start_step * chip->ecc.size; | |
1349 | /* If we read not a page aligned data */ | |
1350 | if (data_col_addr != 0) | |
1351 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1352 | ||
1353 | p = bufpoi + data_col_addr; | |
1354 | chip->read_buf(mtd, p, datafrag_len); | |
1355 | ||
8b6e50c9 | 1356 | /* Calculate ECC */ |
3d459559 AK |
1357 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1358 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1359 | ||
8b6e50c9 BN |
1360 | /* |
1361 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1362 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1363 | */ |
3d459559 | 1364 | for (i = 0; i < eccfrag_len - 1; i++) { |
47570bb1 | 1365 | if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { |
3d459559 AK |
1366 | gaps = 1; |
1367 | break; | |
1368 | } | |
1369 | } | |
1370 | if (gaps) { | |
1371 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1372 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1373 | } else { | |
8b6e50c9 | 1374 | /* |
7854d3f7 | 1375 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1376 | * about buswidth alignment in read_buf. |
1377 | */ | |
7351d3a5 | 1378 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1379 | aligned_len = eccfrag_len; |
7351d3a5 | 1380 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1381 | aligned_len++; |
7351d3a5 | 1382 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1383 | aligned_len++; |
1384 | ||
7351d3a5 FF |
1385 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1386 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1387 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1388 | } | |
1389 | ||
1390 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1391 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1392 | |
1393 | p = bufpoi + data_col_addr; | |
1394 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1395 | int stat; | |
1396 | ||
7351d3a5 FF |
1397 | stat = chip->ecc.correct(mtd, p, |
1398 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
40cbe6ee BB |
1399 | if (stat == -EBADMSG && |
1400 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1401 | /* check for empty pages with bitflips */ | |
1402 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1403 | &chip->buffers->ecccode[i], | |
1404 | chip->ecc.bytes, | |
1405 | NULL, 0, | |
1406 | chip->ecc.strength); | |
1407 | } | |
1408 | ||
3f91e94f | 1409 | if (stat < 0) { |
3d459559 | 1410 | mtd->ecc_stats.failed++; |
3f91e94f | 1411 | } else { |
3d459559 | 1412 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1413 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1414 | } | |
3d459559 | 1415 | } |
3f91e94f | 1416 | return max_bitflips; |
3d459559 AK |
1417 | } |
1418 | ||
068e3c0a | 1419 | /** |
7854d3f7 | 1420 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1421 | * @mtd: mtd info structure |
1422 | * @chip: nand chip info structure | |
1423 | * @buf: buffer to store read data | |
1fbb938d | 1424 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1425 | * @page: page number to read |
068e3c0a | 1426 | * |
7854d3f7 | 1427 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1428 | */ |
f5bbdacc | 1429 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1430 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1431 | { |
f5bbdacc TG |
1432 | int i, eccsize = chip->ecc.size; |
1433 | int eccbytes = chip->ecc.bytes; | |
1434 | int eccsteps = chip->ecc.steps; | |
1435 | uint8_t *p = buf; | |
4bf63fcb DW |
1436 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1437 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1438 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1439 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1440 | |
1441 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1442 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1443 | chip->read_buf(mtd, p, eccsize); | |
1444 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1445 | } |
f75e5097 | 1446 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1447 | |
f5bbdacc | 1448 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1449 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1450 | |
f5bbdacc TG |
1451 | eccsteps = chip->ecc.steps; |
1452 | p = buf; | |
61b03bd7 | 1453 | |
f5bbdacc TG |
1454 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1455 | int stat; | |
1da177e4 | 1456 | |
f5bbdacc | 1457 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
40cbe6ee BB |
1458 | if (stat == -EBADMSG && |
1459 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1460 | /* check for empty pages with bitflips */ | |
1461 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1462 | &ecc_code[i], eccbytes, | |
1463 | NULL, 0, | |
1464 | chip->ecc.strength); | |
1465 | } | |
1466 | ||
3f91e94f | 1467 | if (stat < 0) { |
f5bbdacc | 1468 | mtd->ecc_stats.failed++; |
3f91e94f | 1469 | } else { |
f5bbdacc | 1470 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1471 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1472 | } | |
f5bbdacc | 1473 | } |
3f91e94f | 1474 | return max_bitflips; |
f5bbdacc | 1475 | } |
1da177e4 | 1476 | |
6e0cb135 | 1477 | /** |
7854d3f7 | 1478 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1479 | * @mtd: mtd info structure |
1480 | * @chip: nand chip info structure | |
1481 | * @buf: buffer to store read data | |
1fbb938d | 1482 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1483 | * @page: page number to read |
6e0cb135 | 1484 | * |
8b6e50c9 BN |
1485 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1486 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1487 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1488 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1489 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1490 | */ |
1491 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1492 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1493 | { |
1494 | int i, eccsize = chip->ecc.size; | |
1495 | int eccbytes = chip->ecc.bytes; | |
1496 | int eccsteps = chip->ecc.steps; | |
1497 | uint8_t *p = buf; | |
1498 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1499 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1500 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1501 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1502 | |
1503 | /* Read the OOB area first */ | |
1504 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1505 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1506 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1507 | ||
1508 | for (i = 0; i < chip->ecc.total; i++) | |
1509 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1510 | ||
1511 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1512 | int stat; | |
1513 | ||
1514 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1515 | chip->read_buf(mtd, p, eccsize); | |
1516 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1517 | ||
1518 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
40cbe6ee BB |
1519 | if (stat == -EBADMSG && |
1520 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1521 | /* check for empty pages with bitflips */ | |
1522 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1523 | &ecc_code[i], eccbytes, | |
1524 | NULL, 0, | |
1525 | chip->ecc.strength); | |
1526 | } | |
1527 | ||
3f91e94f | 1528 | if (stat < 0) { |
6e0cb135 | 1529 | mtd->ecc_stats.failed++; |
3f91e94f | 1530 | } else { |
6e0cb135 | 1531 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1532 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1533 | } | |
6e0cb135 | 1534 | } |
3f91e94f | 1535 | return max_bitflips; |
6e0cb135 SN |
1536 | } |
1537 | ||
f5bbdacc | 1538 | /** |
7854d3f7 | 1539 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1540 | * @mtd: mtd info structure |
1541 | * @chip: nand chip info structure | |
1542 | * @buf: buffer to store read data | |
1fbb938d | 1543 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1544 | * @page: page number to read |
f5bbdacc | 1545 | * |
8b6e50c9 BN |
1546 | * The hw generator calculates the error syndrome automatically. Therefore we |
1547 | * need a special oob layout and handling. | |
f5bbdacc TG |
1548 | */ |
1549 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1550 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1551 | { |
1552 | int i, eccsize = chip->ecc.size; | |
1553 | int eccbytes = chip->ecc.bytes; | |
1554 | int eccsteps = chip->ecc.steps; | |
40cbe6ee | 1555 | int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; |
f5bbdacc | 1556 | uint8_t *p = buf; |
f75e5097 | 1557 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1558 | unsigned int max_bitflips = 0; |
1da177e4 | 1559 | |
f5bbdacc TG |
1560 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1561 | int stat; | |
61b03bd7 | 1562 | |
f5bbdacc TG |
1563 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1564 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1565 | |
f5bbdacc TG |
1566 | if (chip->ecc.prepad) { |
1567 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1568 | oob += chip->ecc.prepad; | |
1569 | } | |
1da177e4 | 1570 | |
f5bbdacc TG |
1571 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1572 | chip->read_buf(mtd, oob, eccbytes); | |
1573 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1574 | |
f5bbdacc | 1575 | oob += eccbytes; |
1da177e4 | 1576 | |
f5bbdacc TG |
1577 | if (chip->ecc.postpad) { |
1578 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1579 | oob += chip->ecc.postpad; | |
61b03bd7 | 1580 | } |
40cbe6ee BB |
1581 | |
1582 | if (stat == -EBADMSG && | |
1583 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1584 | /* check for empty pages with bitflips */ | |
1585 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1586 | oob - eccpadbytes, | |
1587 | eccpadbytes, | |
1588 | NULL, 0, | |
1589 | chip->ecc.strength); | |
1590 | } | |
1591 | ||
1592 | if (stat < 0) { | |
1593 | mtd->ecc_stats.failed++; | |
1594 | } else { | |
1595 | mtd->ecc_stats.corrected += stat; | |
1596 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1597 | } | |
f5bbdacc | 1598 | } |
1da177e4 | 1599 | |
f5bbdacc | 1600 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1601 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1602 | if (i) |
1603 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1604 | |
3f91e94f | 1605 | return max_bitflips; |
f5bbdacc | 1606 | } |
1da177e4 | 1607 | |
f5bbdacc | 1608 | /** |
7854d3f7 | 1609 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1610 | * @chip: nand chip structure |
1611 | * @oob: oob destination address | |
1612 | * @ops: oob ops structure | |
1613 | * @len: size of oob to transfer | |
8593fbc6 TG |
1614 | */ |
1615 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1616 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1617 | { |
f8ac0414 | 1618 | switch (ops->mode) { |
8593fbc6 | 1619 | |
0612b9dd BN |
1620 | case MTD_OPS_PLACE_OOB: |
1621 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1622 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1623 | return oob + len; | |
1624 | ||
0612b9dd | 1625 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1626 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1627 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1628 | size_t bytes = 0; | |
8593fbc6 | 1629 | |
f8ac0414 | 1630 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1631 | /* Read request not from offset 0? */ |
7bc3312b TG |
1632 | if (unlikely(roffs)) { |
1633 | if (roffs >= free->length) { | |
1634 | roffs -= free->length; | |
1635 | continue; | |
1636 | } | |
1637 | boffs = free->offset + roffs; | |
1638 | bytes = min_t(size_t, len, | |
1639 | (free->length - roffs)); | |
1640 | roffs = 0; | |
1641 | } else { | |
1642 | bytes = min_t(size_t, len, free->length); | |
1643 | boffs = free->offset; | |
1644 | } | |
1645 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1646 | oob += bytes; |
1647 | } | |
1648 | return oob; | |
1649 | } | |
1650 | default: | |
1651 | BUG(); | |
1652 | } | |
1653 | return NULL; | |
1654 | } | |
1655 | ||
ba84fb59 BN |
1656 | /** |
1657 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1658 | * @mtd: MTD device structure | |
1659 | * @retry_mode: the retry mode to use | |
1660 | * | |
1661 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1662 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1663 | * a new threshold, the host should retry reading the page. | |
1664 | */ | |
1665 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1666 | { | |
862eba51 | 1667 | struct nand_chip *chip = mtd_to_nand(mtd); |
ba84fb59 BN |
1668 | |
1669 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1670 | ||
1671 | if (retry_mode >= chip->read_retries) | |
1672 | return -EINVAL; | |
1673 | ||
1674 | if (!chip->setup_read_retry) | |
1675 | return -EOPNOTSUPP; | |
1676 | ||
1677 | return chip->setup_read_retry(mtd, retry_mode); | |
1678 | } | |
1679 | ||
8593fbc6 | 1680 | /** |
7854d3f7 | 1681 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1682 | * @mtd: MTD device structure |
1683 | * @from: offset to read from | |
1684 | * @ops: oob ops structure | |
f5bbdacc TG |
1685 | * |
1686 | * Internal function. Called with chip held. | |
1687 | */ | |
8593fbc6 TG |
1688 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1689 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1690 | { |
e47f3db4 | 1691 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
862eba51 | 1692 | struct nand_chip *chip = mtd_to_nand(mtd); |
f5bbdacc | 1693 | int ret = 0; |
8593fbc6 | 1694 | uint32_t readlen = ops->len; |
7014568b | 1695 | uint32_t oobreadlen = ops->ooblen; |
29f1058a | 1696 | uint32_t max_oobsize = mtd_oobavail(mtd, ops); |
9aca334e | 1697 | |
8593fbc6 | 1698 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1699 | int use_bufpoi; |
edbc4540 | 1700 | unsigned int max_bitflips = 0; |
ba84fb59 | 1701 | int retry_mode = 0; |
b72f3dfb | 1702 | bool ecc_fail = false; |
1da177e4 | 1703 | |
f5bbdacc TG |
1704 | chipnr = (int)(from >> chip->chip_shift); |
1705 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1706 | |
f5bbdacc TG |
1707 | realpage = (int)(from >> chip->page_shift); |
1708 | page = realpage & chip->pagemask; | |
1da177e4 | 1709 | |
f5bbdacc | 1710 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1711 | |
8593fbc6 TG |
1712 | buf = ops->datbuf; |
1713 | oob = ops->oobbuf; | |
e47f3db4 | 1714 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1715 | |
f8ac0414 | 1716 | while (1) { |
b72f3dfb BN |
1717 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1718 | ||
f5bbdacc TG |
1719 | bytes = min(mtd->writesize - col, readlen); |
1720 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1721 | |
66507c7b KD |
1722 | if (!aligned) |
1723 | use_bufpoi = 1; | |
1724 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
1725 | use_bufpoi = !virt_addr_valid(buf); | |
1726 | else | |
1727 | use_bufpoi = 0; | |
1728 | ||
8b6e50c9 | 1729 | /* Is the current page in the buffer? */ |
8593fbc6 | 1730 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1731 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1732 | ||
1733 | if (use_bufpoi && aligned) | |
1734 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1735 | __func__, buf); | |
61b03bd7 | 1736 | |
ba84fb59 | 1737 | read_retry: |
c00a0991 | 1738 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1739 | |
edbc4540 MD |
1740 | /* |
1741 | * Now read the page into the buffer. Absent an error, | |
1742 | * the read methods return max bitflips per ecc step. | |
1743 | */ | |
0612b9dd | 1744 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1745 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1746 | oob_required, |
1747 | page); | |
a5ff4f10 JW |
1748 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1749 | !oob) | |
7351d3a5 | 1750 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1751 | col, bytes, bufpoi, |
1752 | page); | |
956e944c | 1753 | else |
46a8cf2d | 1754 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1755 | oob_required, page); |
6d77b9d0 | 1756 | if (ret < 0) { |
66507c7b | 1757 | if (use_bufpoi) |
6d77b9d0 BN |
1758 | /* Invalidate page cache */ |
1759 | chip->pagebuf = -1; | |
1da177e4 | 1760 | break; |
6d77b9d0 | 1761 | } |
f5bbdacc | 1762 | |
edbc4540 MD |
1763 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1764 | ||
f5bbdacc | 1765 | /* Transfer not aligned data */ |
66507c7b | 1766 | if (use_bufpoi) { |
a5ff4f10 | 1767 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1768 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1769 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1770 | chip->pagebuf = realpage; |
edbc4540 MD |
1771 | chip->pagebuf_bitflips = ret; |
1772 | } else { | |
6d77b9d0 BN |
1773 | /* Invalidate page cache */ |
1774 | chip->pagebuf = -1; | |
edbc4540 | 1775 | } |
4bf63fcb | 1776 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1777 | } |
1778 | ||
8593fbc6 | 1779 | if (unlikely(oob)) { |
b64d39d8 ML |
1780 | int toread = min(oobreadlen, max_oobsize); |
1781 | ||
1782 | if (toread) { | |
1783 | oob = nand_transfer_oob(chip, | |
1784 | oob, ops, toread); | |
1785 | oobreadlen -= toread; | |
1786 | } | |
8593fbc6 | 1787 | } |
5bc7c33c BN |
1788 | |
1789 | if (chip->options & NAND_NEED_READRDY) { | |
1790 | /* Apply delay or wait for ready/busy pin */ | |
1791 | if (!chip->dev_ready) | |
1792 | udelay(chip->chip_delay); | |
1793 | else | |
1794 | nand_wait_ready(mtd); | |
1795 | } | |
b72f3dfb | 1796 | |
ba84fb59 | 1797 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1798 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1799 | retry_mode++; |
1800 | ret = nand_setup_read_retry(mtd, | |
1801 | retry_mode); | |
1802 | if (ret < 0) | |
1803 | break; | |
1804 | ||
1805 | /* Reset failures; retry */ | |
1806 | mtd->ecc_stats.failed = ecc_failures; | |
1807 | goto read_retry; | |
1808 | } else { | |
1809 | /* No more retry modes; real failure */ | |
1810 | ecc_fail = true; | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | buf += bytes; | |
8593fbc6 | 1815 | } else { |
4bf63fcb | 1816 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1817 | buf += bytes; |
edbc4540 MD |
1818 | max_bitflips = max_t(unsigned int, max_bitflips, |
1819 | chip->pagebuf_bitflips); | |
8593fbc6 | 1820 | } |
1da177e4 | 1821 | |
f5bbdacc | 1822 | readlen -= bytes; |
61b03bd7 | 1823 | |
ba84fb59 BN |
1824 | /* Reset to retry mode 0 */ |
1825 | if (retry_mode) { | |
1826 | ret = nand_setup_read_retry(mtd, 0); | |
1827 | if (ret < 0) | |
1828 | break; | |
1829 | retry_mode = 0; | |
1830 | } | |
1831 | ||
f5bbdacc | 1832 | if (!readlen) |
61b03bd7 | 1833 | break; |
1da177e4 | 1834 | |
8b6e50c9 | 1835 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1836 | col = 0; |
1837 | /* Increment page address */ | |
1838 | realpage++; | |
1839 | ||
ace4dfee | 1840 | page = realpage & chip->pagemask; |
1da177e4 LT |
1841 | /* Check, if we cross a chip boundary */ |
1842 | if (!page) { | |
1843 | chipnr++; | |
ace4dfee TG |
1844 | chip->select_chip(mtd, -1); |
1845 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1846 | } |
1da177e4 | 1847 | } |
b0bb6903 | 1848 | chip->select_chip(mtd, -1); |
1da177e4 | 1849 | |
8593fbc6 | 1850 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1851 | if (oob) |
1852 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1853 | |
3f91e94f | 1854 | if (ret < 0) |
f5bbdacc TG |
1855 | return ret; |
1856 | ||
b72f3dfb | 1857 | if (ecc_fail) |
9a1fcdfd TG |
1858 | return -EBADMSG; |
1859 | ||
edbc4540 | 1860 | return max_bitflips; |
f5bbdacc TG |
1861 | } |
1862 | ||
1863 | /** | |
25985edc | 1864 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1865 | * @mtd: MTD device structure |
1866 | * @from: offset to read from | |
1867 | * @len: number of bytes to read | |
1868 | * @retlen: pointer to variable to store the number of read bytes | |
1869 | * @buf: the databuffer to put data | |
f5bbdacc | 1870 | * |
8b6e50c9 | 1871 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1872 | */ |
1873 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1874 | size_t *retlen, uint8_t *buf) | |
1875 | { | |
4a89ff88 | 1876 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1877 | int ret; |
1878 | ||
6a8214aa | 1879 | nand_get_device(mtd, FL_READING); |
0ec56dc4 | 1880 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
1881 | ops.len = len; |
1882 | ops.datbuf = buf; | |
11041ae6 | 1883 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1884 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1885 | *retlen = ops.retlen; |
f5bbdacc | 1886 | nand_release_device(mtd); |
f5bbdacc | 1887 | return ret; |
1da177e4 LT |
1888 | } |
1889 | ||
7bc3312b | 1890 | /** |
7854d3f7 | 1891 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1892 | * @mtd: mtd info structure |
1893 | * @chip: nand chip info structure | |
1894 | * @page: page number to read | |
7bc3312b TG |
1895 | */ |
1896 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1897 | int page) |
7bc3312b | 1898 | { |
5c2ffb11 | 1899 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1900 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1901 | return 0; |
7bc3312b TG |
1902 | } |
1903 | ||
1904 | /** | |
7854d3f7 | 1905 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1906 | * with syndromes |
8b6e50c9 BN |
1907 | * @mtd: mtd info structure |
1908 | * @chip: nand chip info structure | |
1909 | * @page: page number to read | |
7bc3312b TG |
1910 | */ |
1911 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1912 | int page) |
7bc3312b | 1913 | { |
7bc3312b TG |
1914 | int length = mtd->oobsize; |
1915 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1916 | int eccsize = chip->ecc.size; | |
2ea69d21 | 1917 | uint8_t *bufpoi = chip->oob_poi; |
7bc3312b TG |
1918 | int i, toread, sndrnd = 0, pos; |
1919 | ||
1920 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1921 | for (i = 0; i < chip->ecc.steps; i++) { | |
1922 | if (sndrnd) { | |
1923 | pos = eccsize + i * (eccsize + chunk); | |
1924 | if (mtd->writesize > 512) | |
1925 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1926 | else | |
1927 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1928 | } else | |
1929 | sndrnd = 1; | |
1930 | toread = min_t(int, length, chunk); | |
1931 | chip->read_buf(mtd, bufpoi, toread); | |
1932 | bufpoi += toread; | |
1933 | length -= toread; | |
1934 | } | |
1935 | if (length > 0) | |
1936 | chip->read_buf(mtd, bufpoi, length); | |
1937 | ||
5c2ffb11 | 1938 | return 0; |
7bc3312b TG |
1939 | } |
1940 | ||
1941 | /** | |
7854d3f7 | 1942 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1943 | * @mtd: mtd info structure |
1944 | * @chip: nand chip info structure | |
1945 | * @page: page number to write | |
7bc3312b TG |
1946 | */ |
1947 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1948 | int page) | |
1949 | { | |
1950 | int status = 0; | |
1951 | const uint8_t *buf = chip->oob_poi; | |
1952 | int length = mtd->oobsize; | |
1953 | ||
1954 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1955 | chip->write_buf(mtd, buf, length); | |
1956 | /* Send command to program the OOB data */ | |
1957 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1958 | ||
1959 | status = chip->waitfunc(mtd, chip); | |
1960 | ||
0d420f9d | 1961 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1962 | } |
1963 | ||
1964 | /** | |
7854d3f7 | 1965 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1966 | * with syndrome - only for large page flash |
1967 | * @mtd: mtd info structure | |
1968 | * @chip: nand chip info structure | |
1969 | * @page: page number to write | |
7bc3312b TG |
1970 | */ |
1971 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1972 | struct nand_chip *chip, int page) | |
1973 | { | |
1974 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1975 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1976 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1977 | const uint8_t *bufpoi = chip->oob_poi; | |
1978 | ||
1979 | /* | |
1980 | * data-ecc-data-ecc ... ecc-oob | |
1981 | * or | |
1982 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1983 | */ | |
1984 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1985 | pos = steps * (eccsize + chunk); | |
1986 | steps = 0; | |
1987 | } else | |
8b0036ee | 1988 | pos = eccsize; |
7bc3312b TG |
1989 | |
1990 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1991 | for (i = 0; i < steps; i++) { | |
1992 | if (sndcmd) { | |
1993 | if (mtd->writesize <= 512) { | |
1994 | uint32_t fill = 0xFFFFFFFF; | |
1995 | ||
1996 | len = eccsize; | |
1997 | while (len > 0) { | |
1998 | int num = min_t(int, len, 4); | |
1999 | chip->write_buf(mtd, (uint8_t *)&fill, | |
2000 | num); | |
2001 | len -= num; | |
2002 | } | |
2003 | } else { | |
2004 | pos = eccsize + i * (eccsize + chunk); | |
2005 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
2006 | } | |
2007 | } else | |
2008 | sndcmd = 1; | |
2009 | len = min_t(int, length, chunk); | |
2010 | chip->write_buf(mtd, bufpoi, len); | |
2011 | bufpoi += len; | |
2012 | length -= len; | |
2013 | } | |
2014 | if (length > 0) | |
2015 | chip->write_buf(mtd, bufpoi, length); | |
2016 | ||
2017 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2018 | status = chip->waitfunc(mtd, chip); | |
2019 | ||
2020 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
2021 | } | |
2022 | ||
1da177e4 | 2023 | /** |
7854d3f7 | 2024 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
2025 | * @mtd: MTD device structure |
2026 | * @from: offset to read from | |
2027 | * @ops: oob operations description structure | |
1da177e4 | 2028 | * |
8b6e50c9 | 2029 | * NAND read out-of-band data from the spare area. |
1da177e4 | 2030 | */ |
8593fbc6 TG |
2031 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
2032 | struct mtd_oob_ops *ops) | |
1da177e4 | 2033 | { |
c00a0991 | 2034 | int page, realpage, chipnr; |
862eba51 | 2035 | struct nand_chip *chip = mtd_to_nand(mtd); |
041e4575 | 2036 | struct mtd_ecc_stats stats; |
7014568b VW |
2037 | int readlen = ops->ooblen; |
2038 | int len; | |
7bc3312b | 2039 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 2040 | int ret = 0; |
61b03bd7 | 2041 | |
289c0522 | 2042 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 2043 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 2044 | |
041e4575 BN |
2045 | stats = mtd->ecc_stats; |
2046 | ||
29f1058a | 2047 | len = mtd_oobavail(mtd, ops); |
03736155 AH |
2048 | |
2049 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
2050 | pr_debug("%s: attempt to start read outside oob\n", |
2051 | __func__); | |
03736155 AH |
2052 | return -EINVAL; |
2053 | } | |
2054 | ||
2055 | /* Do not allow reads past end of device */ | |
2056 | if (unlikely(from >= mtd->size || | |
2057 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
2058 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
2059 | pr_debug("%s: attempt to read beyond end of device\n", |
2060 | __func__); | |
03736155 AH |
2061 | return -EINVAL; |
2062 | } | |
7014568b | 2063 | |
7314e9e7 | 2064 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 2065 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2066 | |
7314e9e7 TG |
2067 | /* Shift to get page */ |
2068 | realpage = (int)(from >> chip->page_shift); | |
2069 | page = realpage & chip->pagemask; | |
1da177e4 | 2070 | |
f8ac0414 | 2071 | while (1) { |
0612b9dd | 2072 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 2073 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 2074 | else |
1951f2f7 SL |
2075 | ret = chip->ecc.read_oob(mtd, chip, page); |
2076 | ||
2077 | if (ret < 0) | |
2078 | break; | |
7014568b VW |
2079 | |
2080 | len = min(len, readlen); | |
2081 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 2082 | |
5bc7c33c BN |
2083 | if (chip->options & NAND_NEED_READRDY) { |
2084 | /* Apply delay or wait for ready/busy pin */ | |
2085 | if (!chip->dev_ready) | |
2086 | udelay(chip->chip_delay); | |
2087 | else | |
2088 | nand_wait_ready(mtd); | |
2089 | } | |
2090 | ||
7014568b | 2091 | readlen -= len; |
0d420f9d SZ |
2092 | if (!readlen) |
2093 | break; | |
2094 | ||
7314e9e7 TG |
2095 | /* Increment page address */ |
2096 | realpage++; | |
2097 | ||
2098 | page = realpage & chip->pagemask; | |
2099 | /* Check, if we cross a chip boundary */ | |
2100 | if (!page) { | |
2101 | chipnr++; | |
2102 | chip->select_chip(mtd, -1); | |
2103 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2104 | } |
2105 | } | |
b0bb6903 | 2106 | chip->select_chip(mtd, -1); |
1da177e4 | 2107 | |
1951f2f7 SL |
2108 | ops->oobretlen = ops->ooblen - readlen; |
2109 | ||
2110 | if (ret < 0) | |
2111 | return ret; | |
041e4575 BN |
2112 | |
2113 | if (mtd->ecc_stats.failed - stats.failed) | |
2114 | return -EBADMSG; | |
2115 | ||
2116 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
2117 | } |
2118 | ||
2119 | /** | |
8593fbc6 | 2120 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
2121 | * @mtd: MTD device structure |
2122 | * @from: offset to read from | |
2123 | * @ops: oob operation description structure | |
1da177e4 | 2124 | * |
8b6e50c9 | 2125 | * NAND read data and/or out-of-band data. |
1da177e4 | 2126 | */ |
8593fbc6 TG |
2127 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
2128 | struct mtd_oob_ops *ops) | |
1da177e4 | 2129 | { |
8593fbc6 TG |
2130 | int ret = -ENOTSUPP; |
2131 | ||
2132 | ops->retlen = 0; | |
1da177e4 LT |
2133 | |
2134 | /* Do not allow reads past end of device */ | |
7014568b | 2135 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
2136 | pr_debug("%s: attempt to read beyond end of device\n", |
2137 | __func__); | |
1da177e4 LT |
2138 | return -EINVAL; |
2139 | } | |
2140 | ||
6a8214aa | 2141 | nand_get_device(mtd, FL_READING); |
1da177e4 | 2142 | |
f8ac0414 | 2143 | switch (ops->mode) { |
0612b9dd BN |
2144 | case MTD_OPS_PLACE_OOB: |
2145 | case MTD_OPS_AUTO_OOB: | |
2146 | case MTD_OPS_RAW: | |
8593fbc6 | 2147 | break; |
1da177e4 | 2148 | |
8593fbc6 TG |
2149 | default: |
2150 | goto out; | |
2151 | } | |
1da177e4 | 2152 | |
8593fbc6 TG |
2153 | if (!ops->datbuf) |
2154 | ret = nand_do_read_oob(mtd, from, ops); | |
2155 | else | |
2156 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2157 | |
7351d3a5 | 2158 | out: |
8593fbc6 TG |
2159 | nand_release_device(mtd); |
2160 | return ret; | |
2161 | } | |
61b03bd7 | 2162 | |
1da177e4 | 2163 | |
8593fbc6 | 2164 | /** |
7854d3f7 | 2165 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2166 | * @mtd: mtd info structure |
2167 | * @chip: nand chip info structure | |
2168 | * @buf: data buffer | |
1fbb938d | 2169 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2170 | * @page: page number to write |
52ff49df | 2171 | * |
7854d3f7 | 2172 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2173 | */ |
fdbad98d | 2174 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 2175 | const uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
2176 | { |
2177 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2178 | if (oob_required) |
2179 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2180 | |
2181 | return 0; | |
1da177e4 LT |
2182 | } |
2183 | ||
52ff49df | 2184 | /** |
7854d3f7 | 2185 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2186 | * @mtd: mtd info structure |
2187 | * @chip: nand chip info structure | |
2188 | * @buf: data buffer | |
1fbb938d | 2189 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2190 | * @page: page number to write |
52ff49df DB |
2191 | * |
2192 | * We need a special oob layout and handling even when ECC isn't checked. | |
2193 | */ | |
fdbad98d | 2194 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2195 | struct nand_chip *chip, |
45aaeff9 BB |
2196 | const uint8_t *buf, int oob_required, |
2197 | int page) | |
52ff49df DB |
2198 | { |
2199 | int eccsize = chip->ecc.size; | |
2200 | int eccbytes = chip->ecc.bytes; | |
2201 | uint8_t *oob = chip->oob_poi; | |
2202 | int steps, size; | |
2203 | ||
2204 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2205 | chip->write_buf(mtd, buf, eccsize); | |
2206 | buf += eccsize; | |
2207 | ||
2208 | if (chip->ecc.prepad) { | |
2209 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2210 | oob += chip->ecc.prepad; | |
2211 | } | |
2212 | ||
60c3bc1f | 2213 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2214 | oob += eccbytes; |
2215 | ||
2216 | if (chip->ecc.postpad) { | |
2217 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2218 | oob += chip->ecc.postpad; | |
2219 | } | |
2220 | } | |
2221 | ||
2222 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2223 | if (size) | |
2224 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2225 | |
2226 | return 0; | |
52ff49df | 2227 | } |
9223a456 | 2228 | /** |
7854d3f7 | 2229 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2230 | * @mtd: mtd info structure |
2231 | * @chip: nand chip info structure | |
2232 | * @buf: data buffer | |
1fbb938d | 2233 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2234 | * @page: page number to write |
9223a456 | 2235 | */ |
fdbad98d | 2236 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2237 | const uint8_t *buf, int oob_required, |
2238 | int page) | |
9223a456 | 2239 | { |
f75e5097 TG |
2240 | int i, eccsize = chip->ecc.size; |
2241 | int eccbytes = chip->ecc.bytes; | |
2242 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2243 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2244 | const uint8_t *p = buf; |
8b099a39 | 2245 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2246 | |
7854d3f7 | 2247 | /* Software ECC calculation */ |
8593fbc6 TG |
2248 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2249 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2250 | |
8593fbc6 TG |
2251 | for (i = 0; i < chip->ecc.total; i++) |
2252 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2253 | |
45aaeff9 | 2254 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
f75e5097 | 2255 | } |
9223a456 | 2256 | |
f75e5097 | 2257 | /** |
7854d3f7 | 2258 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2259 | * @mtd: mtd info structure |
2260 | * @chip: nand chip info structure | |
2261 | * @buf: data buffer | |
1fbb938d | 2262 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2263 | * @page: page number to write |
f75e5097 | 2264 | */ |
fdbad98d | 2265 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2266 | const uint8_t *buf, int oob_required, |
2267 | int page) | |
f75e5097 TG |
2268 | { |
2269 | int i, eccsize = chip->ecc.size; | |
2270 | int eccbytes = chip->ecc.bytes; | |
2271 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2272 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2273 | const uint8_t *p = buf; |
8b099a39 | 2274 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2275 | |
f75e5097 TG |
2276 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2277 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2278 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2279 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2280 | } |
2281 | ||
f75e5097 TG |
2282 | for (i = 0; i < chip->ecc.total; i++) |
2283 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2284 | ||
2285 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2286 | |
2287 | return 0; | |
9223a456 TG |
2288 | } |
2289 | ||
837a6ba4 GP |
2290 | |
2291 | /** | |
73c8aaf4 | 2292 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
2293 | * @mtd: mtd info structure |
2294 | * @chip: nand chip info structure | |
d6a95080 | 2295 | * @offset: column address of subpage within the page |
837a6ba4 | 2296 | * @data_len: data length |
d6a95080 | 2297 | * @buf: data buffer |
837a6ba4 | 2298 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2299 | * @page: page number to write |
837a6ba4 GP |
2300 | */ |
2301 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2302 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2303 | uint32_t data_len, const uint8_t *buf, |
45aaeff9 | 2304 | int oob_required, int page) |
837a6ba4 GP |
2305 | { |
2306 | uint8_t *oob_buf = chip->oob_poi; | |
2307 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2308 | int ecc_size = chip->ecc.size; | |
2309 | int ecc_bytes = chip->ecc.bytes; | |
2310 | int ecc_steps = chip->ecc.steps; | |
2311 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2312 | uint32_t start_step = offset / ecc_size; | |
2313 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2314 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2315 | int step, i; | |
2316 | ||
2317 | for (step = 0; step < ecc_steps; step++) { | |
2318 | /* configure controller for WRITE access */ | |
2319 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2320 | ||
2321 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2322 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2323 | |
2324 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2325 | if ((step < start_step) || (step > end_step)) | |
2326 | memset(ecc_calc, 0xff, ecc_bytes); | |
2327 | else | |
d6a95080 | 2328 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2329 | |
2330 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2331 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2332 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2333 | memset(oob_buf, 0xff, oob_bytes); | |
2334 | ||
d6a95080 | 2335 | buf += ecc_size; |
837a6ba4 GP |
2336 | ecc_calc += ecc_bytes; |
2337 | oob_buf += oob_bytes; | |
2338 | } | |
2339 | ||
2340 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2341 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2342 | ecc_calc = chip->buffers->ecccalc; | |
2343 | for (i = 0; i < chip->ecc.total; i++) | |
2344 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2345 | ||
2346 | /* write OOB buffer to NAND device */ | |
2347 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2348 | ||
2349 | return 0; | |
2350 | } | |
2351 | ||
2352 | ||
61b03bd7 | 2353 | /** |
7854d3f7 | 2354 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2355 | * @mtd: mtd info structure |
2356 | * @chip: nand chip info structure | |
2357 | * @buf: data buffer | |
1fbb938d | 2358 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2359 | * @page: page number to write |
1da177e4 | 2360 | * |
8b6e50c9 BN |
2361 | * The hw generator calculates the error syndrome automatically. Therefore we |
2362 | * need a special oob layout and handling. | |
f75e5097 | 2363 | */ |
fdbad98d | 2364 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d | 2365 | struct nand_chip *chip, |
45aaeff9 BB |
2366 | const uint8_t *buf, int oob_required, |
2367 | int page) | |
1da177e4 | 2368 | { |
f75e5097 TG |
2369 | int i, eccsize = chip->ecc.size; |
2370 | int eccbytes = chip->ecc.bytes; | |
2371 | int eccsteps = chip->ecc.steps; | |
2372 | const uint8_t *p = buf; | |
2373 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2374 | |
f75e5097 | 2375 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2376 | |
f75e5097 TG |
2377 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2378 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2379 | |
f75e5097 TG |
2380 | if (chip->ecc.prepad) { |
2381 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2382 | oob += chip->ecc.prepad; | |
2383 | } | |
2384 | ||
2385 | chip->ecc.calculate(mtd, p, oob); | |
2386 | chip->write_buf(mtd, oob, eccbytes); | |
2387 | oob += eccbytes; | |
2388 | ||
2389 | if (chip->ecc.postpad) { | |
2390 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2391 | oob += chip->ecc.postpad; | |
1da177e4 | 2392 | } |
1da177e4 | 2393 | } |
f75e5097 TG |
2394 | |
2395 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2396 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2397 | if (i) |
2398 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2399 | |
2400 | return 0; | |
f75e5097 TG |
2401 | } |
2402 | ||
2403 | /** | |
956e944c | 2404 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2405 | * @mtd: MTD device structure |
2406 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2407 | * @offset: address offset within the page |
2408 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2409 | * @buf: the data to write |
1fbb938d | 2410 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2411 | * @page: page number to write |
2412 | * @cached: cached programming | |
2413 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2414 | */ |
2415 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2416 | uint32_t offset, int data_len, const uint8_t *buf, |
2417 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2418 | { |
837a6ba4 GP |
2419 | int status, subpage; |
2420 | ||
2421 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2422 | chip->ecc.write_subpage) | |
2423 | subpage = offset || (data_len < mtd->writesize); | |
2424 | else | |
2425 | subpage = 0; | |
f75e5097 TG |
2426 | |
2427 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2428 | ||
956e944c | 2429 | if (unlikely(raw)) |
837a6ba4 | 2430 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
45aaeff9 | 2431 | oob_required, page); |
837a6ba4 GP |
2432 | else if (subpage) |
2433 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
45aaeff9 | 2434 | buf, oob_required, page); |
956e944c | 2435 | else |
45aaeff9 BB |
2436 | status = chip->ecc.write_page(mtd, chip, buf, oob_required, |
2437 | page); | |
fdbad98d JW |
2438 | |
2439 | if (status < 0) | |
2440 | return status; | |
f75e5097 TG |
2441 | |
2442 | /* | |
7854d3f7 | 2443 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2444 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2445 | */ |
2446 | cached = 0; | |
2447 | ||
3239a6cd | 2448 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2449 | |
2450 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2451 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2452 | /* |
2453 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2454 | * available. |
f75e5097 TG |
2455 | */ |
2456 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2457 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2458 | page); | |
2459 | ||
2460 | if (status & NAND_STATUS_FAIL) | |
2461 | return -EIO; | |
2462 | } else { | |
2463 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2464 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2465 | } |
2466 | ||
f75e5097 | 2467 | return 0; |
1da177e4 LT |
2468 | } |
2469 | ||
8593fbc6 | 2470 | /** |
7854d3f7 | 2471 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2472 | * @mtd: MTD device structure |
8b6e50c9 BN |
2473 | * @oob: oob data buffer |
2474 | * @len: oob data write length | |
2475 | * @ops: oob ops structure | |
8593fbc6 | 2476 | */ |
f722013e TAA |
2477 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2478 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2479 | { |
862eba51 | 2480 | struct nand_chip *chip = mtd_to_nand(mtd); |
f722013e TAA |
2481 | |
2482 | /* | |
2483 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2484 | * data from a previous OOB read. | |
2485 | */ | |
2486 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2487 | ||
f8ac0414 | 2488 | switch (ops->mode) { |
8593fbc6 | 2489 | |
0612b9dd BN |
2490 | case MTD_OPS_PLACE_OOB: |
2491 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2492 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2493 | return oob + len; | |
2494 | ||
0612b9dd | 2495 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2496 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2497 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2498 | size_t bytes = 0; | |
8593fbc6 | 2499 | |
f8ac0414 | 2500 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2501 | /* Write request not from offset 0? */ |
7bc3312b TG |
2502 | if (unlikely(woffs)) { |
2503 | if (woffs >= free->length) { | |
2504 | woffs -= free->length; | |
2505 | continue; | |
2506 | } | |
2507 | boffs = free->offset + woffs; | |
2508 | bytes = min_t(size_t, len, | |
2509 | (free->length - woffs)); | |
2510 | woffs = 0; | |
2511 | } else { | |
2512 | bytes = min_t(size_t, len, free->length); | |
2513 | boffs = free->offset; | |
2514 | } | |
8b0036ee | 2515 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2516 | oob += bytes; |
2517 | } | |
2518 | return oob; | |
2519 | } | |
2520 | default: | |
2521 | BUG(); | |
2522 | } | |
2523 | return NULL; | |
2524 | } | |
2525 | ||
f8ac0414 | 2526 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2527 | |
2528 | /** | |
7854d3f7 | 2529 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2530 | * @mtd: MTD device structure |
2531 | * @to: offset to write to | |
2532 | * @ops: oob operations description structure | |
1da177e4 | 2533 | * |
8b6e50c9 | 2534 | * NAND write with ECC. |
1da177e4 | 2535 | */ |
8593fbc6 TG |
2536 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2537 | struct mtd_oob_ops *ops) | |
1da177e4 | 2538 | { |
29072b96 | 2539 | int chipnr, realpage, page, blockmask, column; |
862eba51 | 2540 | struct nand_chip *chip = mtd_to_nand(mtd); |
8593fbc6 | 2541 | uint32_t writelen = ops->len; |
782ce79a ML |
2542 | |
2543 | uint32_t oobwritelen = ops->ooblen; | |
29f1058a | 2544 | uint32_t oobmaxlen = mtd_oobavail(mtd, ops); |
782ce79a | 2545 | |
8593fbc6 TG |
2546 | uint8_t *oob = ops->oobbuf; |
2547 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2548 | int ret; |
e47f3db4 | 2549 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2550 | |
8593fbc6 | 2551 | ops->retlen = 0; |
29072b96 TG |
2552 | if (!writelen) |
2553 | return 0; | |
1da177e4 | 2554 | |
8b6e50c9 | 2555 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2556 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2557 | pr_notice("%s: attempt to write non page aligned data\n", |
2558 | __func__); | |
1da177e4 LT |
2559 | return -EINVAL; |
2560 | } | |
2561 | ||
29072b96 | 2562 | column = to & (mtd->writesize - 1); |
1da177e4 | 2563 | |
6a930961 TG |
2564 | chipnr = (int)(to >> chip->chip_shift); |
2565 | chip->select_chip(mtd, chipnr); | |
2566 | ||
1da177e4 | 2567 | /* Check, if it is write protected */ |
b0bb6903 HS |
2568 | if (nand_check_wp(mtd)) { |
2569 | ret = -EIO; | |
2570 | goto err_out; | |
2571 | } | |
1da177e4 | 2572 | |
f75e5097 TG |
2573 | realpage = (int)(to >> chip->page_shift); |
2574 | page = realpage & chip->pagemask; | |
2575 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2576 | ||
2577 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2578 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2579 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2580 | chip->pagebuf = -1; |
61b03bd7 | 2581 | |
782ce79a | 2582 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2583 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2584 | ret = -EINVAL; | |
2585 | goto err_out; | |
2586 | } | |
782ce79a | 2587 | |
f8ac0414 | 2588 | while (1) { |
29072b96 | 2589 | int bytes = mtd->writesize; |
f75e5097 | 2590 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2591 | uint8_t *wbuf = buf; |
66507c7b KD |
2592 | int use_bufpoi; |
2593 | int part_pagewr = (column || writelen < (mtd->writesize - 1)); | |
2594 | ||
2595 | if (part_pagewr) | |
2596 | use_bufpoi = 1; | |
2597 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
2598 | use_bufpoi = !virt_addr_valid(buf); | |
2599 | else | |
2600 | use_bufpoi = 0; | |
29072b96 | 2601 | |
66507c7b KD |
2602 | /* Partial page write?, or need to use bounce buffer */ |
2603 | if (use_bufpoi) { | |
2604 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2605 | __func__, buf); | |
29072b96 | 2606 | cached = 0; |
66507c7b KD |
2607 | if (part_pagewr) |
2608 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2609 | chip->pagebuf = -1; |
2610 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2611 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2612 | wbuf = chip->buffers->databuf; | |
2613 | } | |
1da177e4 | 2614 | |
782ce79a ML |
2615 | if (unlikely(oob)) { |
2616 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2617 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2618 | oobwritelen -= len; |
f722013e TAA |
2619 | } else { |
2620 | /* We still need to erase leftover OOB data */ | |
2621 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2622 | } |
837a6ba4 GP |
2623 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2624 | oob_required, page, cached, | |
2625 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2626 | if (ret) |
2627 | break; | |
2628 | ||
2629 | writelen -= bytes; | |
2630 | if (!writelen) | |
2631 | break; | |
2632 | ||
29072b96 | 2633 | column = 0; |
f75e5097 TG |
2634 | buf += bytes; |
2635 | realpage++; | |
2636 | ||
2637 | page = realpage & chip->pagemask; | |
2638 | /* Check, if we cross a chip boundary */ | |
2639 | if (!page) { | |
2640 | chipnr++; | |
2641 | chip->select_chip(mtd, -1); | |
2642 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2643 | } |
2644 | } | |
8593fbc6 | 2645 | |
8593fbc6 | 2646 | ops->retlen = ops->len - writelen; |
7014568b VW |
2647 | if (unlikely(oob)) |
2648 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2649 | |
2650 | err_out: | |
2651 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2652 | return ret; |
2653 | } | |
2654 | ||
2af7c653 SK |
2655 | /** |
2656 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2657 | * @mtd: MTD device structure |
2658 | * @to: offset to write to | |
2659 | * @len: number of bytes to write | |
2660 | * @retlen: pointer to variable to store the number of written bytes | |
2661 | * @buf: the data to write | |
2af7c653 SK |
2662 | * |
2663 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2664 | * may for example be called by mtdoops when writing an oops while in panic. | |
2665 | */ | |
2666 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2667 | size_t *retlen, const uint8_t *buf) | |
2668 | { | |
862eba51 | 2669 | struct nand_chip *chip = mtd_to_nand(mtd); |
4a89ff88 | 2670 | struct mtd_oob_ops ops; |
2af7c653 SK |
2671 | int ret; |
2672 | ||
8b6e50c9 | 2673 | /* Wait for the device to get ready */ |
2af7c653 SK |
2674 | panic_nand_wait(mtd, chip, 400); |
2675 | ||
8b6e50c9 | 2676 | /* Grab the device */ |
2af7c653 SK |
2677 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2678 | ||
0ec56dc4 | 2679 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2680 | ops.len = len; |
2681 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2682 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2683 | |
4a89ff88 | 2684 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2685 | |
4a89ff88 | 2686 | *retlen = ops.retlen; |
2af7c653 SK |
2687 | return ret; |
2688 | } | |
2689 | ||
f75e5097 | 2690 | /** |
8593fbc6 | 2691 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2692 | * @mtd: MTD device structure |
2693 | * @to: offset to write to | |
2694 | * @len: number of bytes to write | |
2695 | * @retlen: pointer to variable to store the number of written bytes | |
2696 | * @buf: the data to write | |
f75e5097 | 2697 | * |
8b6e50c9 | 2698 | * NAND write with ECC. |
f75e5097 | 2699 | */ |
8593fbc6 TG |
2700 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2701 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2702 | { |
4a89ff88 | 2703 | struct mtd_oob_ops ops; |
f75e5097 TG |
2704 | int ret; |
2705 | ||
6a8214aa | 2706 | nand_get_device(mtd, FL_WRITING); |
0ec56dc4 | 2707 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2708 | ops.len = len; |
2709 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2710 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2711 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2712 | *retlen = ops.retlen; |
f75e5097 | 2713 | nand_release_device(mtd); |
8593fbc6 | 2714 | return ret; |
f75e5097 | 2715 | } |
7314e9e7 | 2716 | |
1da177e4 | 2717 | /** |
8593fbc6 | 2718 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2719 | * @mtd: MTD device structure |
2720 | * @to: offset to write to | |
2721 | * @ops: oob operation description structure | |
1da177e4 | 2722 | * |
8b6e50c9 | 2723 | * NAND write out-of-band. |
1da177e4 | 2724 | */ |
8593fbc6 TG |
2725 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2726 | struct mtd_oob_ops *ops) | |
1da177e4 | 2727 | { |
03736155 | 2728 | int chipnr, page, status, len; |
862eba51 | 2729 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 2730 | |
289c0522 | 2731 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2732 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2733 | |
29f1058a | 2734 | len = mtd_oobavail(mtd, ops); |
03736155 | 2735 | |
1da177e4 | 2736 | /* Do not allow write past end of page */ |
03736155 | 2737 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2738 | pr_debug("%s: attempt to write past end of page\n", |
2739 | __func__); | |
1da177e4 LT |
2740 | return -EINVAL; |
2741 | } | |
2742 | ||
03736155 | 2743 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2744 | pr_debug("%s: attempt to start write outside oob\n", |
2745 | __func__); | |
03736155 AH |
2746 | return -EINVAL; |
2747 | } | |
2748 | ||
775adc3d | 2749 | /* Do not allow write past end of device */ |
03736155 AH |
2750 | if (unlikely(to >= mtd->size || |
2751 | ops->ooboffs + ops->ooblen > | |
2752 | ((mtd->size >> chip->page_shift) - | |
2753 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2754 | pr_debug("%s: attempt to write beyond end of device\n", |
2755 | __func__); | |
03736155 AH |
2756 | return -EINVAL; |
2757 | } | |
2758 | ||
7314e9e7 | 2759 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2760 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2761 | |
7314e9e7 TG |
2762 | /* Shift to get page */ |
2763 | page = (int)(to >> chip->page_shift); | |
2764 | ||
2765 | /* | |
2766 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2767 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2768 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2769 | * it in the doc2000 driver in August 1999. dwmw2. | |
2770 | */ | |
ace4dfee | 2771 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2772 | |
2773 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2774 | if (nand_check_wp(mtd)) { |
2775 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2776 | return -EROFS; |
b0bb6903 | 2777 | } |
61b03bd7 | 2778 | |
1da177e4 | 2779 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2780 | if (page == chip->pagebuf) |
2781 | chip->pagebuf = -1; | |
1da177e4 | 2782 | |
f722013e | 2783 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2784 | |
0612b9dd | 2785 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2786 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2787 | else | |
2788 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2789 | |
b0bb6903 HS |
2790 | chip->select_chip(mtd, -1); |
2791 | ||
7bc3312b TG |
2792 | if (status) |
2793 | return status; | |
1da177e4 | 2794 | |
7014568b | 2795 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2796 | |
7bc3312b | 2797 | return 0; |
8593fbc6 TG |
2798 | } |
2799 | ||
2800 | /** | |
2801 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2802 | * @mtd: MTD device structure |
2803 | * @to: offset to write to | |
2804 | * @ops: oob operation description structure | |
8593fbc6 TG |
2805 | */ |
2806 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2807 | struct mtd_oob_ops *ops) | |
2808 | { | |
8593fbc6 TG |
2809 | int ret = -ENOTSUPP; |
2810 | ||
2811 | ops->retlen = 0; | |
2812 | ||
2813 | /* Do not allow writes past end of device */ | |
7014568b | 2814 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2815 | pr_debug("%s: attempt to write beyond end of device\n", |
2816 | __func__); | |
8593fbc6 TG |
2817 | return -EINVAL; |
2818 | } | |
2819 | ||
6a8214aa | 2820 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2821 | |
f8ac0414 | 2822 | switch (ops->mode) { |
0612b9dd BN |
2823 | case MTD_OPS_PLACE_OOB: |
2824 | case MTD_OPS_AUTO_OOB: | |
2825 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2826 | break; |
2827 | ||
2828 | default: | |
2829 | goto out; | |
2830 | } | |
2831 | ||
2832 | if (!ops->datbuf) | |
2833 | ret = nand_do_write_oob(mtd, to, ops); | |
2834 | else | |
2835 | ret = nand_do_write_ops(mtd, to, ops); | |
2836 | ||
7351d3a5 | 2837 | out: |
1da177e4 | 2838 | nand_release_device(mtd); |
1da177e4 LT |
2839 | return ret; |
2840 | } | |
2841 | ||
1da177e4 | 2842 | /** |
49c50b97 | 2843 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2844 | * @mtd: MTD device structure |
2845 | * @page: the page address of the block which will be erased | |
1da177e4 | 2846 | * |
49c50b97 | 2847 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2848 | */ |
49c50b97 | 2849 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2850 | { |
862eba51 | 2851 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 2852 | /* Send commands to erase a block */ |
ace4dfee TG |
2853 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2854 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2855 | |
2856 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2857 | } |
2858 | ||
1da177e4 LT |
2859 | /** |
2860 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2861 | * @mtd: MTD device structure |
2862 | * @instr: erase instruction | |
1da177e4 | 2863 | * |
8b6e50c9 | 2864 | * Erase one ore more blocks. |
1da177e4 | 2865 | */ |
e0c7d767 | 2866 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2867 | { |
e0c7d767 | 2868 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2869 | } |
61b03bd7 | 2870 | |
1da177e4 | 2871 | /** |
7854d3f7 | 2872 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2873 | * @mtd: MTD device structure |
2874 | * @instr: erase instruction | |
2875 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2876 | * |
8b6e50c9 | 2877 | * Erase one ore more blocks. |
1da177e4 | 2878 | */ |
ace4dfee TG |
2879 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2880 | int allowbbt) | |
1da177e4 | 2881 | { |
69423d99 | 2882 | int page, status, pages_per_block, ret, chipnr; |
862eba51 | 2883 | struct nand_chip *chip = mtd_to_nand(mtd); |
69423d99 | 2884 | loff_t len; |
1da177e4 | 2885 | |
289c0522 BN |
2886 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2887 | __func__, (unsigned long long)instr->addr, | |
2888 | (unsigned long long)instr->len); | |
1da177e4 | 2889 | |
6fe5a6ac | 2890 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2891 | return -EINVAL; |
1da177e4 | 2892 | |
1da177e4 | 2893 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2894 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2895 | |
2896 | /* Shift to get first page */ | |
ace4dfee TG |
2897 | page = (int)(instr->addr >> chip->page_shift); |
2898 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2899 | |
2900 | /* Calculate pages in each block */ | |
ace4dfee | 2901 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2902 | |
2903 | /* Select the NAND device */ | |
ace4dfee | 2904 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2905 | |
1da177e4 LT |
2906 | /* Check, if it is write protected */ |
2907 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2908 | pr_debug("%s: device is write protected!\n", |
2909 | __func__); | |
1da177e4 LT |
2910 | instr->state = MTD_ERASE_FAILED; |
2911 | goto erase_exit; | |
2912 | } | |
2913 | ||
2914 | /* Loop through the pages */ | |
2915 | len = instr->len; | |
2916 | ||
2917 | instr->state = MTD_ERASING; | |
2918 | ||
2919 | while (len) { | |
12183a20 | 2920 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee | 2921 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
9f3e0429 | 2922 | chip->page_shift, allowbbt)) { |
d0370219 BN |
2923 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2924 | __func__, page); | |
1da177e4 LT |
2925 | instr->state = MTD_ERASE_FAILED; |
2926 | goto erase_exit; | |
2927 | } | |
61b03bd7 | 2928 | |
ace4dfee TG |
2929 | /* |
2930 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2931 | * contains the current cached page. |
ace4dfee TG |
2932 | */ |
2933 | if (page <= chip->pagebuf && chip->pagebuf < | |
2934 | (page + pages_per_block)) | |
2935 | chip->pagebuf = -1; | |
1da177e4 | 2936 | |
49c50b97 | 2937 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 2938 | |
ace4dfee TG |
2939 | /* |
2940 | * See if operation failed and additional status checks are | |
2941 | * available | |
2942 | */ | |
2943 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2944 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2945 | status, page); | |
068e3c0a | 2946 | |
1da177e4 | 2947 | /* See if block erase succeeded */ |
a4ab4c5d | 2948 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2949 | pr_debug("%s: failed erase, page 0x%08x\n", |
2950 | __func__, page); | |
1da177e4 | 2951 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2952 | instr->fail_addr = |
2953 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2954 | goto erase_exit; |
2955 | } | |
30f464b7 | 2956 | |
1da177e4 | 2957 | /* Increment page address and decrement length */ |
daae74ca | 2958 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2959 | page += pages_per_block; |
2960 | ||
2961 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2962 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2963 | chipnr++; |
ace4dfee TG |
2964 | chip->select_chip(mtd, -1); |
2965 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2966 | } |
2967 | } | |
2968 | instr->state = MTD_ERASE_DONE; | |
2969 | ||
7351d3a5 | 2970 | erase_exit: |
1da177e4 LT |
2971 | |
2972 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2973 | |
2974 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2975 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2976 | nand_release_device(mtd); |
2977 | ||
49defc01 DW |
2978 | /* Do call back function */ |
2979 | if (!ret) | |
2980 | mtd_erase_callback(instr); | |
2981 | ||
1da177e4 LT |
2982 | /* Return more or less happy */ |
2983 | return ret; | |
2984 | } | |
2985 | ||
2986 | /** | |
2987 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2988 | * @mtd: MTD device structure |
1da177e4 | 2989 | * |
8b6e50c9 | 2990 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2991 | */ |
e0c7d767 | 2992 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2993 | { |
289c0522 | 2994 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2995 | |
2996 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2997 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2998 | /* Release it and go back */ |
e0c7d767 | 2999 | nand_release_device(mtd); |
1da177e4 LT |
3000 | } |
3001 | ||
1da177e4 | 3002 | /** |
ace4dfee | 3003 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
3004 | * @mtd: MTD device structure |
3005 | * @offs: offset relative to mtd start | |
1da177e4 | 3006 | */ |
ace4dfee | 3007 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 3008 | { |
9f3e0429 AT |
3009 | struct nand_chip *chip = mtd_to_nand(mtd); |
3010 | int chipnr = (int)(offs >> chip->chip_shift); | |
3011 | int ret; | |
3012 | ||
3013 | /* Select the NAND device */ | |
3014 | nand_get_device(mtd, FL_READING); | |
3015 | chip->select_chip(mtd, chipnr); | |
3016 | ||
3017 | ret = nand_block_checkbad(mtd, offs, 0); | |
3018 | ||
3019 | chip->select_chip(mtd, -1); | |
3020 | nand_release_device(mtd); | |
3021 | ||
3022 | return ret; | |
1da177e4 LT |
3023 | } |
3024 | ||
3025 | /** | |
ace4dfee | 3026 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
3027 | * @mtd: MTD device structure |
3028 | * @ofs: offset relative to mtd start | |
1da177e4 | 3029 | */ |
e0c7d767 | 3030 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 3031 | { |
1da177e4 LT |
3032 | int ret; |
3033 | ||
f8ac0414 FF |
3034 | ret = nand_block_isbad(mtd, ofs); |
3035 | if (ret) { | |
8b6e50c9 | 3036 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
3037 | if (ret > 0) |
3038 | return 0; | |
e0c7d767 DW |
3039 | return ret; |
3040 | } | |
1da177e4 | 3041 | |
5a0edb25 | 3042 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
3043 | } |
3044 | ||
7db03ecc HS |
3045 | /** |
3046 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
3047 | * @mtd: MTD device structure | |
3048 | * @chip: nand chip info structure | |
3049 | * @addr: feature address. | |
3050 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3051 | */ | |
3052 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3053 | int addr, uint8_t *subfeature_param) | |
3054 | { | |
3055 | int status; | |
05f78359 | 3056 | int i; |
7db03ecc | 3057 | |
d914c932 DM |
3058 | if (!chip->onfi_version || |
3059 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3060 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3061 | return -EINVAL; |
3062 | ||
3063 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
3064 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3065 | chip->write_byte(mtd, subfeature_param[i]); | |
3066 | ||
7db03ecc HS |
3067 | status = chip->waitfunc(mtd, chip); |
3068 | if (status & NAND_STATUS_FAIL) | |
3069 | return -EIO; | |
3070 | return 0; | |
3071 | } | |
3072 | ||
3073 | /** | |
3074 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
3075 | * @mtd: MTD device structure | |
3076 | * @chip: nand chip info structure | |
3077 | * @addr: feature address. | |
3078 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3079 | */ | |
3080 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3081 | int addr, uint8_t *subfeature_param) | |
3082 | { | |
05f78359 UKK |
3083 | int i; |
3084 | ||
d914c932 DM |
3085 | if (!chip->onfi_version || |
3086 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3087 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3088 | return -EINVAL; |
3089 | ||
7db03ecc | 3090 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); |
05f78359 UKK |
3091 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3092 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
3093 | return 0; |
3094 | } | |
3095 | ||
962034f4 VW |
3096 | /** |
3097 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 3098 | * @mtd: MTD device structure |
962034f4 VW |
3099 | */ |
3100 | static int nand_suspend(struct mtd_info *mtd) | |
3101 | { | |
6a8214aa | 3102 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
3103 | } |
3104 | ||
3105 | /** | |
3106 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 3107 | * @mtd: MTD device structure |
962034f4 VW |
3108 | */ |
3109 | static void nand_resume(struct mtd_info *mtd) | |
3110 | { | |
862eba51 | 3111 | struct nand_chip *chip = mtd_to_nand(mtd); |
962034f4 | 3112 | |
ace4dfee | 3113 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
3114 | nand_release_device(mtd); |
3115 | else | |
d0370219 BN |
3116 | pr_err("%s called for a chip which is not in suspended state\n", |
3117 | __func__); | |
962034f4 VW |
3118 | } |
3119 | ||
72ea4036 SB |
3120 | /** |
3121 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
3122 | * prevent further operations | |
3123 | * @mtd: MTD device structure | |
3124 | */ | |
3125 | static void nand_shutdown(struct mtd_info *mtd) | |
3126 | { | |
9ca641b0 | 3127 | nand_get_device(mtd, FL_PM_SUSPENDED); |
72ea4036 SB |
3128 | } |
3129 | ||
8b6e50c9 | 3130 | /* Set default functions */ |
ace4dfee | 3131 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 3132 | { |
1da177e4 | 3133 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
3134 | if (!chip->chip_delay) |
3135 | chip->chip_delay = 20; | |
1da177e4 LT |
3136 | |
3137 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
3138 | if (chip->cmdfunc == NULL) |
3139 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
3140 | |
3141 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
3142 | if (chip->waitfunc == NULL) |
3143 | chip->waitfunc = nand_wait; | |
3144 | ||
3145 | if (!chip->select_chip) | |
3146 | chip->select_chip = nand_select_chip; | |
68e80780 | 3147 | |
4204cccd HS |
3148 | /* set for ONFI nand */ |
3149 | if (!chip->onfi_set_features) | |
3150 | chip->onfi_set_features = nand_onfi_set_features; | |
3151 | if (!chip->onfi_get_features) | |
3152 | chip->onfi_get_features = nand_onfi_get_features; | |
3153 | ||
68e80780 BN |
3154 | /* If called twice, pointers that depend on busw may need to be reset */ |
3155 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
3156 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
3157 | if (!chip->read_word) | |
3158 | chip->read_word = nand_read_word; | |
3159 | if (!chip->block_bad) | |
3160 | chip->block_bad = nand_block_bad; | |
3161 | if (!chip->block_markbad) | |
3162 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 3163 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 3164 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
3165 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
3166 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 3167 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 3168 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
3169 | if (!chip->scan_bbt) |
3170 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
3171 | |
3172 | if (!chip->controller) { | |
3173 | chip->controller = &chip->hwcontrol; | |
3174 | spin_lock_init(&chip->controller->lock); | |
3175 | init_waitqueue_head(&chip->controller->wq); | |
3176 | } | |
3177 | ||
7aa65bfd TG |
3178 | } |
3179 | ||
8b6e50c9 | 3180 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3181 | static void sanitize_string(uint8_t *s, size_t len) |
3182 | { | |
3183 | ssize_t i; | |
3184 | ||
8b6e50c9 | 3185 | /* Null terminate */ |
d1e1f4e4 FF |
3186 | s[len - 1] = 0; |
3187 | ||
8b6e50c9 | 3188 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3189 | for (i = 0; i < len - 1; i++) { |
3190 | if (s[i] < ' ' || s[i] > 127) | |
3191 | s[i] = '?'; | |
3192 | } | |
3193 | ||
8b6e50c9 | 3194 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3195 | strim(s); |
3196 | } | |
3197 | ||
3198 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3199 | { | |
3200 | int i; | |
3201 | while (len--) { | |
3202 | crc ^= *p++ << 8; | |
3203 | for (i = 0; i < 8; i++) | |
3204 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3205 | } | |
3206 | ||
3207 | return crc; | |
3208 | } | |
3209 | ||
6dcbe0cd HS |
3210 | /* Parse the Extended Parameter Page. */ |
3211 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
3212 | struct nand_chip *chip, struct nand_onfi_params *p) | |
3213 | { | |
3214 | struct onfi_ext_param_page *ep; | |
3215 | struct onfi_ext_section *s; | |
3216 | struct onfi_ext_ecc_info *ecc; | |
3217 | uint8_t *cursor; | |
3218 | int ret = -EINVAL; | |
3219 | int len; | |
3220 | int i; | |
3221 | ||
3222 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3223 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3224 | if (!ep) |
3225 | return -ENOMEM; | |
6dcbe0cd HS |
3226 | |
3227 | /* Send our own NAND_CMD_PARAM. */ | |
3228 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3229 | ||
3230 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3231 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3232 | sizeof(*p) * p->num_of_param_pages , -1); | |
3233 | ||
3234 | /* Read out the Extended Parameter Page. */ | |
3235 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3236 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3237 | != le16_to_cpu(ep->crc))) { | |
3238 | pr_debug("fail in the CRC.\n"); | |
3239 | goto ext_out; | |
3240 | } | |
3241 | ||
3242 | /* | |
3243 | * Check the signature. | |
3244 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3245 | */ | |
3246 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3247 | pr_debug("The signature is invalid.\n"); | |
3248 | goto ext_out; | |
3249 | } | |
3250 | ||
3251 | /* find the ECC section. */ | |
3252 | cursor = (uint8_t *)(ep + 1); | |
3253 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3254 | s = ep->sections + i; | |
3255 | if (s->type == ONFI_SECTION_TYPE_2) | |
3256 | break; | |
3257 | cursor += s->length * 16; | |
3258 | } | |
3259 | if (i == ONFI_EXT_SECTION_MAX) { | |
3260 | pr_debug("We can not find the ECC section.\n"); | |
3261 | goto ext_out; | |
3262 | } | |
3263 | ||
3264 | /* get the info we want. */ | |
3265 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3266 | ||
4ae7d228 BN |
3267 | if (!ecc->codeword_size) { |
3268 | pr_debug("Invalid codeword size\n"); | |
3269 | goto ext_out; | |
6dcbe0cd HS |
3270 | } |
3271 | ||
4ae7d228 BN |
3272 | chip->ecc_strength_ds = ecc->ecc_bits; |
3273 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3274 | ret = 0; |
6dcbe0cd HS |
3275 | |
3276 | ext_out: | |
3277 | kfree(ep); | |
3278 | return ret; | |
3279 | } | |
3280 | ||
8429bb39 BN |
3281 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3282 | { | |
862eba51 | 3283 | struct nand_chip *chip = mtd_to_nand(mtd); |
8429bb39 BN |
3284 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; |
3285 | ||
3286 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3287 | feature); | |
3288 | } | |
3289 | ||
3290 | /* | |
3291 | * Configure chip properties from Micron vendor-specific ONFI table | |
3292 | */ | |
3293 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3294 | struct nand_onfi_params *p) | |
3295 | { | |
3296 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3297 | ||
3298 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3299 | return; | |
3300 | ||
3301 | chip->read_retries = micron->read_retry_options; | |
3302 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3303 | } | |
3304 | ||
6fb277ba | 3305 | /* |
8b6e50c9 | 3306 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3307 | */ |
3308 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3309 | int *busw) |
6fb277ba FF |
3310 | { |
3311 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3312 | int i, j; |
6fb277ba FF |
3313 | int val; |
3314 | ||
7854d3f7 | 3315 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3316 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3317 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3318 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3319 | return 0; | |
3320 | ||
6fb277ba FF |
3321 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3322 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3323 | for (j = 0; j < sizeof(*p); j++) |
3324 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3325 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3326 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3327 | break; |
3328 | } | |
3329 | } | |
3330 | ||
c7f23a70 BN |
3331 | if (i == 3) { |
3332 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3333 | return 0; |
c7f23a70 | 3334 | } |
6fb277ba | 3335 | |
8b6e50c9 | 3336 | /* Check version */ |
6fb277ba | 3337 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3338 | if (val & (1 << 5)) |
3339 | chip->onfi_version = 23; | |
3340 | else if (val & (1 << 4)) | |
6fb277ba FF |
3341 | chip->onfi_version = 22; |
3342 | else if (val & (1 << 3)) | |
3343 | chip->onfi_version = 21; | |
3344 | else if (val & (1 << 2)) | |
3345 | chip->onfi_version = 20; | |
b7b1a29d | 3346 | else if (val & (1 << 1)) |
6fb277ba | 3347 | chip->onfi_version = 10; |
b7b1a29d BN |
3348 | |
3349 | if (!chip->onfi_version) { | |
20171642 | 3350 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3351 | return 0; |
3352 | } | |
6fb277ba FF |
3353 | |
3354 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3355 | sanitize_string(p->model, sizeof(p->model)); | |
3356 | if (!mtd->name) | |
3357 | mtd->name = p->model; | |
4355b70c | 3358 | |
6fb277ba | 3359 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3360 | |
3361 | /* | |
3362 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3363 | * (don't ask me who thought of this...). MTD assumes that these | |
3364 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3365 | */ | |
3366 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3367 | mtd->erasesize *= mtd->writesize; | |
3368 | ||
6fb277ba | 3369 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3370 | |
3371 | /* See erasesize comment */ | |
3372 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3373 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3374 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3375 | |
3376 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3377 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3378 | else |
3379 | *busw = 0; | |
6fb277ba | 3380 | |
10c86bab HS |
3381 | if (p->ecc_bits != 0xff) { |
3382 | chip->ecc_strength_ds = p->ecc_bits; | |
3383 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3384 | } else if (chip->onfi_version >= 21 && |
3385 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3386 | ||
3387 | /* | |
3388 | * The nand_flash_detect_ext_param_page() uses the | |
3389 | * Change Read Column command which maybe not supported | |
3390 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3391 | * now. We do not replace user supplied command function. | |
3392 | */ | |
3393 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3394 | chip->cmdfunc = nand_command_lp; | |
3395 | ||
3396 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3397 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3398 | pr_warn("Failed to detect ONFI extended param page\n"); |
3399 | } else { | |
3400 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3401 | } |
3402 | ||
8429bb39 BN |
3403 | if (p->jedec_id == NAND_MFR_MICRON) |
3404 | nand_onfi_detect_micron(chip, p); | |
3405 | ||
6fb277ba FF |
3406 | return 1; |
3407 | } | |
3408 | ||
91361818 HS |
3409 | /* |
3410 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3411 | */ | |
3412 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3413 | int *busw) | |
3414 | { | |
3415 | struct nand_jedec_params *p = &chip->jedec_params; | |
3416 | struct jedec_ecc_info *ecc; | |
3417 | int val; | |
3418 | int i, j; | |
3419 | ||
3420 | /* Try JEDEC for unknown chip or LP */ | |
3421 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3422 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3423 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3424 | chip->read_byte(mtd) != 'C') | |
3425 | return 0; | |
3426 | ||
3427 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3428 | for (i = 0; i < 3; i++) { | |
3429 | for (j = 0; j < sizeof(*p); j++) | |
3430 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3431 | ||
3432 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3433 | le16_to_cpu(p->crc)) | |
3434 | break; | |
3435 | } | |
3436 | ||
3437 | if (i == 3) { | |
3438 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3439 | return 0; | |
3440 | } | |
3441 | ||
3442 | /* Check version */ | |
3443 | val = le16_to_cpu(p->revision); | |
3444 | if (val & (1 << 2)) | |
3445 | chip->jedec_version = 10; | |
3446 | else if (val & (1 << 1)) | |
3447 | chip->jedec_version = 1; /* vendor specific version */ | |
3448 | ||
3449 | if (!chip->jedec_version) { | |
3450 | pr_info("unsupported JEDEC version: %d\n", val); | |
3451 | return 0; | |
3452 | } | |
3453 | ||
3454 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3455 | sanitize_string(p->model, sizeof(p->model)); | |
3456 | if (!mtd->name) | |
3457 | mtd->name = p->model; | |
3458 | ||
3459 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3460 | ||
3461 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3462 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3463 | mtd->erasesize *= mtd->writesize; | |
3464 | ||
3465 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3466 | ||
3467 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3468 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3469 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3470 | chip->bits_per_cell = p->bits_per_cell; | |
3471 | ||
3472 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3473 | *busw = NAND_BUSWIDTH_16; | |
3474 | else | |
3475 | *busw = 0; | |
3476 | ||
3477 | /* ECC info */ | |
3478 | ecc = &p->ecc_info[0]; | |
3479 | ||
3480 | if (ecc->codeword_size >= 9) { | |
3481 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3482 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3483 | } else { | |
3484 | pr_warn("Invalid codeword size\n"); | |
3485 | } | |
3486 | ||
3487 | return 1; | |
3488 | } | |
3489 | ||
e3b88bd6 BN |
3490 | /* |
3491 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3492 | * @id_data: the ID string | |
3493 | * @arrlen: the length of the @id_data array | |
3494 | * @period: the period of repitition | |
3495 | * | |
3496 | * Check if an ID string is repeated within a given sequence of bytes at | |
3497 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3498 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3499 | * if the repetition has a period of @period; otherwise, returns zero. |
3500 | */ | |
3501 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3502 | { | |
3503 | int i, j; | |
3504 | for (i = 0; i < period; i++) | |
3505 | for (j = i + period; j < arrlen; j += period) | |
3506 | if (id_data[i] != id_data[j]) | |
3507 | return 0; | |
3508 | return 1; | |
3509 | } | |
3510 | ||
3511 | /* | |
3512 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3513 | * @id_data: the ID string | |
3514 | * @arrlen: the length of the @id_data array | |
3515 | ||
3516 | * Returns the length of the ID string, according to known wraparound/trailing | |
3517 | * zero patterns. If no pattern exists, returns the length of the array. | |
3518 | */ | |
3519 | static int nand_id_len(u8 *id_data, int arrlen) | |
3520 | { | |
3521 | int last_nonzero, period; | |
3522 | ||
3523 | /* Find last non-zero byte */ | |
3524 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3525 | if (id_data[last_nonzero]) | |
3526 | break; | |
3527 | ||
3528 | /* All zeros */ | |
3529 | if (last_nonzero < 0) | |
3530 | return 0; | |
3531 | ||
3532 | /* Calculate wraparound period */ | |
3533 | for (period = 1; period < arrlen; period++) | |
3534 | if (nand_id_has_period(id_data, arrlen, period)) | |
3535 | break; | |
3536 | ||
3537 | /* There's a repeated pattern */ | |
3538 | if (period < arrlen) | |
3539 | return period; | |
3540 | ||
3541 | /* There are trailing zeros */ | |
3542 | if (last_nonzero < arrlen - 1) | |
3543 | return last_nonzero + 1; | |
3544 | ||
3545 | /* No pattern detected */ | |
3546 | return arrlen; | |
3547 | } | |
3548 | ||
7db906b7 HS |
3549 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3550 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3551 | { | |
3552 | int bits; | |
3553 | ||
3554 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3555 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3556 | return bits + 1; | |
3557 | } | |
3558 | ||
fc09bbc0 BN |
3559 | /* |
3560 | * Many new NAND share similar device ID codes, which represent the size of the | |
3561 | * chip. The rest of the parameters must be decoded according to generic or | |
3562 | * manufacturer-specific "extended ID" decoding patterns. | |
3563 | */ | |
3564 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3565 | u8 id_data[8], int *busw) | |
3566 | { | |
e3b88bd6 | 3567 | int extid, id_len; |
fc09bbc0 | 3568 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3569 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3570 | /* The 4th id byte is the important one */ |
3571 | extid = id_data[3]; | |
3572 | ||
e3b88bd6 BN |
3573 | id_len = nand_id_len(id_data, 8); |
3574 | ||
fc09bbc0 BN |
3575 | /* |
3576 | * Field definitions are in the following datasheets: | |
3577 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3578 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3579 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3580 | * |
af451af4 BN |
3581 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3582 | * ID to decide what to do. | |
fc09bbc0 | 3583 | */ |
af451af4 | 3584 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3585 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3586 | /* Calc pagesize */ |
3587 | mtd->writesize = 2048 << (extid & 0x03); | |
3588 | extid >>= 2; | |
3589 | /* Calc oobsize */ | |
e2d3a35e | 3590 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3591 | case 1: |
3592 | mtd->oobsize = 128; | |
3593 | break; | |
3594 | case 2: | |
3595 | mtd->oobsize = 218; | |
3596 | break; | |
3597 | case 3: | |
3598 | mtd->oobsize = 400; | |
3599 | break; | |
e2d3a35e | 3600 | case 4: |
fc09bbc0 BN |
3601 | mtd->oobsize = 436; |
3602 | break; | |
e2d3a35e BN |
3603 | case 5: |
3604 | mtd->oobsize = 512; | |
3605 | break; | |
3606 | case 6: | |
e2d3a35e BN |
3607 | mtd->oobsize = 640; |
3608 | break; | |
94d04e82 HS |
3609 | case 7: |
3610 | default: /* Other cases are "reserved" (unknown) */ | |
3611 | mtd->oobsize = 1024; | |
3612 | break; | |
fc09bbc0 BN |
3613 | } |
3614 | extid >>= 2; | |
3615 | /* Calc blocksize */ | |
3616 | mtd->erasesize = (128 * 1024) << | |
3617 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3618 | *busw = 0; | |
73ca392f | 3619 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3620 | !nand_is_slc(chip)) { |
73ca392f BN |
3621 | unsigned int tmp; |
3622 | ||
3623 | /* Calc pagesize */ | |
3624 | mtd->writesize = 2048 << (extid & 0x03); | |
3625 | extid >>= 2; | |
3626 | /* Calc oobsize */ | |
3627 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3628 | case 0: | |
3629 | mtd->oobsize = 128; | |
3630 | break; | |
3631 | case 1: | |
3632 | mtd->oobsize = 224; | |
3633 | break; | |
3634 | case 2: | |
3635 | mtd->oobsize = 448; | |
3636 | break; | |
3637 | case 3: | |
3638 | mtd->oobsize = 64; | |
3639 | break; | |
3640 | case 4: | |
3641 | mtd->oobsize = 32; | |
3642 | break; | |
3643 | case 5: | |
3644 | mtd->oobsize = 16; | |
3645 | break; | |
3646 | default: | |
3647 | mtd->oobsize = 640; | |
3648 | break; | |
3649 | } | |
3650 | extid >>= 2; | |
3651 | /* Calc blocksize */ | |
3652 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3653 | if (tmp < 0x03) | |
3654 | mtd->erasesize = (128 * 1024) << tmp; | |
3655 | else if (tmp == 0x03) | |
3656 | mtd->erasesize = 768 * 1024; | |
3657 | else | |
3658 | mtd->erasesize = (64 * 1024) << tmp; | |
3659 | *busw = 0; | |
fc09bbc0 BN |
3660 | } else { |
3661 | /* Calc pagesize */ | |
3662 | mtd->writesize = 1024 << (extid & 0x03); | |
3663 | extid >>= 2; | |
3664 | /* Calc oobsize */ | |
3665 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3666 | (mtd->writesize >> 9); | |
3667 | extid >>= 2; | |
3668 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3669 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3670 | extid >>= 2; | |
3671 | /* Get buswidth information */ | |
3672 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3673 | |
3674 | /* | |
3675 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3676 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3677 | * follows: | |
3678 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3679 | * 110b -> 24nm | |
3680 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3681 | */ | |
3682 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3683 | nand_is_slc(chip) && |
60c67382 BN |
3684 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3685 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3686 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3687 | } | |
3688 | ||
fc09bbc0 BN |
3689 | } |
3690 | } | |
3691 | ||
f23a481c BN |
3692 | /* |
3693 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3694 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3695 | * the chip. | |
3696 | */ | |
3697 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3698 | struct nand_flash_dev *type, u8 id_data[8], | |
3699 | int *busw) | |
3700 | { | |
3701 | int maf_id = id_data[0]; | |
3702 | ||
3703 | mtd->erasesize = type->erasesize; | |
3704 | mtd->writesize = type->pagesize; | |
3705 | mtd->oobsize = mtd->writesize / 32; | |
3706 | *busw = type->options & NAND_BUSWIDTH_16; | |
3707 | ||
1c195e90 HS |
3708 | /* All legacy ID NAND are small-page, SLC */ |
3709 | chip->bits_per_cell = 1; | |
3710 | ||
f23a481c BN |
3711 | /* |
3712 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3713 | * some Spansion chips have erasesize that conflicts with size | |
3714 | * listed in nand_ids table. | |
3715 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3716 | */ | |
3717 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3718 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3719 | && mtd->writesize == 512) { | |
3720 | mtd->erasesize = 128 * 1024; | |
3721 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3722 | } | |
3723 | } | |
3724 | ||
7e74c2d7 BN |
3725 | /* |
3726 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3727 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3728 | * page size, cell-type information). | |
3729 | */ | |
3730 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3731 | struct nand_chip *chip, u8 id_data[8]) | |
3732 | { | |
3733 | int maf_id = id_data[0]; | |
3734 | ||
3735 | /* Set the bad block position */ | |
3736 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3737 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3738 | else | |
3739 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3740 | ||
3741 | /* | |
3742 | * Bad block marker is stored in the last page of each block on Samsung | |
3743 | * and Hynix MLC devices; stored in first two pages of each block on | |
3744 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3745 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3746 | */ | |
1d0ed69d | 3747 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3748 | (maf_id == NAND_MFR_SAMSUNG || |
3749 | maf_id == NAND_MFR_HYNIX)) | |
3750 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3751 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3752 | (maf_id == NAND_MFR_SAMSUNG || |
3753 | maf_id == NAND_MFR_HYNIX || | |
3754 | maf_id == NAND_MFR_TOSHIBA || | |
3755 | maf_id == NAND_MFR_AMD || | |
3756 | maf_id == NAND_MFR_MACRONIX)) || | |
3757 | (mtd->writesize == 2048 && | |
3758 | maf_id == NAND_MFR_MICRON)) | |
3759 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3760 | } | |
3761 | ||
ec6e87e3 HS |
3762 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3763 | { | |
3764 | return type->id_len; | |
3765 | } | |
3766 | ||
3767 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3768 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3769 | { | |
3770 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3771 | mtd->writesize = type->pagesize; | |
3772 | mtd->erasesize = type->erasesize; | |
3773 | mtd->oobsize = type->oobsize; | |
3774 | ||
7db906b7 | 3775 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3776 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3777 | chip->options |= type->options; | |
57219342 HS |
3778 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3779 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3780 | chip->onfi_timing_mode_default = |
3781 | type->onfi_timing_mode_default; | |
ec6e87e3 HS |
3782 | |
3783 | *busw = type->options & NAND_BUSWIDTH_16; | |
3784 | ||
092b6a1d CZ |
3785 | if (!mtd->name) |
3786 | mtd->name = type->name; | |
3787 | ||
ec6e87e3 HS |
3788 | return true; |
3789 | } | |
3790 | return false; | |
3791 | } | |
3792 | ||
7aa65bfd | 3793 | /* |
8b6e50c9 | 3794 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3795 | */ |
3796 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3797 | struct nand_chip *chip, |
7351d3a5 | 3798 | int *maf_id, int *dev_id, |
5e81e88a | 3799 | struct nand_flash_dev *type) |
7aa65bfd | 3800 | { |
bb77082f | 3801 | int busw; |
d1e1f4e4 | 3802 | int i, maf_idx; |
426c457a | 3803 | u8 id_data[8]; |
1da177e4 LT |
3804 | |
3805 | /* Select the device */ | |
ace4dfee | 3806 | chip->select_chip(mtd, 0); |
1da177e4 | 3807 | |
ef89a880 KB |
3808 | /* |
3809 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3810 | * after power-up. |
ef89a880 KB |
3811 | */ |
3812 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3813 | ||
1da177e4 | 3814 | /* Send the command for reading device ID */ |
ace4dfee | 3815 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3816 | |
3817 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3818 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3819 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3820 | |
8b6e50c9 BN |
3821 | /* |
3822 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3823 | * interface concerns can cause random data which looks like a |
3824 | * possibly credible NAND flash to appear. If the two results do | |
3825 | * not match, ignore the device completely. | |
3826 | */ | |
3827 | ||
3828 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3829 | ||
4aef9b78 BN |
3830 | /* Read entire ID string */ |
3831 | for (i = 0; i < 8; i++) | |
426c457a | 3832 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3833 | |
d1e1f4e4 | 3834 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3835 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3836 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3837 | return ERR_PTR(-ENODEV); |
3838 | } | |
3839 | ||
7aa65bfd | 3840 | if (!type) |
5e81e88a DW |
3841 | type = nand_flash_ids; |
3842 | ||
ec6e87e3 HS |
3843 | for (; type->name != NULL; type++) { |
3844 | if (is_full_id_nand(type)) { | |
3845 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3846 | goto ident_done; | |
3847 | } else if (*dev_id == type->dev_id) { | |
db5b09f6 | 3848 | break; |
ec6e87e3 HS |
3849 | } |
3850 | } | |
5e81e88a | 3851 | |
d1e1f4e4 FF |
3852 | chip->onfi_version = 0; |
3853 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3854 | /* Check if the chip is ONFI compliant */ |
47450b35 | 3855 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3856 | goto ident_done; |
91361818 HS |
3857 | |
3858 | /* Check if the chip is JEDEC compliant */ | |
3859 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3860 | goto ident_done; | |
d1e1f4e4 FF |
3861 | } |
3862 | ||
5e81e88a | 3863 | if (!type->name) |
7aa65bfd TG |
3864 | return ERR_PTR(-ENODEV); |
3865 | ||
ba0251fe TG |
3866 | if (!mtd->name) |
3867 | mtd->name = type->name; | |
3868 | ||
69423d99 | 3869 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3870 | |
a7f5ba40 | 3871 | if (!type->pagesize) { |
fc09bbc0 BN |
3872 | /* Decode parameters from extended ID */ |
3873 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3874 | } else { |
f23a481c | 3875 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3876 | } |
bf7a01bf BN |
3877 | /* Get chip options */ |
3878 | chip->options |= type->options; | |
d1e1f4e4 | 3879 | |
8b6e50c9 BN |
3880 | /* |
3881 | * Check if chip is not a Samsung device. Do not clear the | |
3882 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3883 | */ |
3884 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3885 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3886 | ident_done: | |
3887 | ||
7aa65bfd | 3888 | /* Try to identify manufacturer */ |
9a909867 | 3889 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3890 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3891 | break; | |
3892 | } | |
0ea4a755 | 3893 | |
64b37b2a MC |
3894 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3895 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3896 | chip->options |= busw; | |
3897 | nand_set_defaults(chip, busw); | |
3898 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3899 | /* | |
3900 | * Check, if buswidth is correct. Hardware drivers should set | |
3901 | * chip correct! | |
3902 | */ | |
20171642 EG |
3903 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3904 | *maf_id, *dev_id); | |
3905 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3906 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3907 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3908 | busw ? 16 : 8); | |
7aa65bfd TG |
3909 | return ERR_PTR(-EINVAL); |
3910 | } | |
61b03bd7 | 3911 | |
7e74c2d7 BN |
3912 | nand_decode_bbm_options(mtd, chip, id_data); |
3913 | ||
7aa65bfd | 3914 | /* Calculate the address shift from the page size */ |
ace4dfee | 3915 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3916 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3917 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3918 | |
ace4dfee | 3919 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3920 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3921 | if (chip->chipsize & 0xffffffff) |
3922 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3923 | else { |
3924 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3925 | chip->chip_shift += 32 - 1; | |
3926 | } | |
1da177e4 | 3927 | |
26d9be11 | 3928 | chip->badblockbits = 8; |
49c50b97 | 3929 | chip->erase = single_erase; |
7aa65bfd | 3930 | |
8b6e50c9 | 3931 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3932 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3933 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3934 | |
20171642 EG |
3935 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3936 | *maf_id, *dev_id); | |
ffdac6cd HS |
3937 | |
3938 | if (chip->onfi_version) | |
3939 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3940 | chip->onfi_params.model); | |
3941 | else if (chip->jedec_version) | |
3942 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3943 | chip->jedec_params.model); | |
3944 | else | |
3945 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3946 | type->name); | |
3947 | ||
3755a991 | 3948 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 3949 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 3950 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
7aa65bfd TG |
3951 | return type; |
3952 | } | |
3953 | ||
7194a29a | 3954 | static int nand_dt_init(struct nand_chip *chip) |
5844feea | 3955 | { |
7194a29a | 3956 | struct device_node *dn = nand_get_flash_node(chip); |
5844feea BN |
3957 | int ecc_mode, ecc_strength, ecc_step; |
3958 | ||
7194a29a BB |
3959 | if (!dn) |
3960 | return 0; | |
3961 | ||
5844feea BN |
3962 | if (of_get_nand_bus_width(dn) == 16) |
3963 | chip->options |= NAND_BUSWIDTH_16; | |
3964 | ||
3965 | if (of_get_nand_on_flash_bbt(dn)) | |
3966 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
3967 | ||
3968 | ecc_mode = of_get_nand_ecc_mode(dn); | |
3969 | ecc_strength = of_get_nand_ecc_strength(dn); | |
3970 | ecc_step = of_get_nand_ecc_step_size(dn); | |
3971 | ||
3972 | if ((ecc_step >= 0 && !(ecc_strength >= 0)) || | |
3973 | (!(ecc_step >= 0) && ecc_strength >= 0)) { | |
3974 | pr_err("must set both strength and step size in DT\n"); | |
3975 | return -EINVAL; | |
3976 | } | |
3977 | ||
3978 | if (ecc_mode >= 0) | |
3979 | chip->ecc.mode = ecc_mode; | |
3980 | ||
3981 | if (ecc_strength >= 0) | |
3982 | chip->ecc.strength = ecc_strength; | |
3983 | ||
3984 | if (ecc_step > 0) | |
3985 | chip->ecc.size = ecc_step; | |
3986 | ||
3987 | return 0; | |
3988 | } | |
3989 | ||
7aa65bfd | 3990 | /** |
3b85c321 | 3991 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3992 | * @mtd: MTD device structure |
3993 | * @maxchips: number of chips to scan for | |
3994 | * @table: alternative NAND ID table | |
7aa65bfd | 3995 | * |
8b6e50c9 BN |
3996 | * This is the first phase of the normal nand_scan() function. It reads the |
3997 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd TG |
3998 | * |
3999 | */ | |
5e81e88a DW |
4000 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
4001 | struct nand_flash_dev *table) | |
7aa65bfd | 4002 | { |
bb77082f | 4003 | int i, nand_maf_id, nand_dev_id; |
862eba51 | 4004 | struct nand_chip *chip = mtd_to_nand(mtd); |
7aa65bfd | 4005 | struct nand_flash_dev *type; |
5844feea BN |
4006 | int ret; |
4007 | ||
7194a29a BB |
4008 | ret = nand_dt_init(chip); |
4009 | if (ret) | |
4010 | return ret; | |
7aa65bfd | 4011 | |
f7a8e38f BN |
4012 | if (!mtd->name && mtd->dev.parent) |
4013 | mtd->name = dev_name(mtd->dev.parent); | |
4014 | ||
7aa65bfd | 4015 | /* Set the default functions */ |
bb77082f | 4016 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
4017 | |
4018 | /* Read the flash type */ | |
bb77082f CZ |
4019 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
4020 | &nand_dev_id, table); | |
7aa65bfd TG |
4021 | |
4022 | if (IS_ERR(type)) { | |
b1c6e6db | 4023 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 4024 | pr_warn("No NAND device found\n"); |
ace4dfee | 4025 | chip->select_chip(mtd, -1); |
7aa65bfd | 4026 | return PTR_ERR(type); |
1da177e4 LT |
4027 | } |
4028 | ||
07300164 HS |
4029 | chip->select_chip(mtd, -1); |
4030 | ||
7aa65bfd | 4031 | /* Check for a chip array */ |
e0c7d767 | 4032 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 4033 | chip->select_chip(mtd, i); |
ef89a880 KB |
4034 | /* See comment in nand_get_flash_type for reset */ |
4035 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 4036 | /* Send the command for reading device ID */ |
ace4dfee | 4037 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 4038 | /* Read manufacturer and device IDs */ |
ace4dfee | 4039 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
4040 | nand_dev_id != chip->read_byte(mtd)) { |
4041 | chip->select_chip(mtd, -1); | |
1da177e4 | 4042 | break; |
07300164 HS |
4043 | } |
4044 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4045 | } |
4046 | if (i > 1) | |
20171642 | 4047 | pr_info("%d chips detected\n", i); |
61b03bd7 | 4048 | |
1da177e4 | 4049 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
4050 | chip->numchips = i; |
4051 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 4052 | |
3b85c321 DW |
4053 | return 0; |
4054 | } | |
7351d3a5 | 4055 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 4056 | |
67a9ad9b EG |
4057 | /* |
4058 | * Check if the chip configuration meet the datasheet requirements. | |
4059 | ||
4060 | * If our configuration corrects A bits per B bytes and the minimum | |
4061 | * required correction level is X bits per Y bytes, then we must ensure | |
4062 | * both of the following are true: | |
4063 | * | |
4064 | * (1) A / B >= X / Y | |
4065 | * (2) A >= X | |
4066 | * | |
4067 | * Requirement (1) ensures we can correct for the required bitflip density. | |
4068 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
4069 | * in the same sector. | |
4070 | */ | |
4071 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
4072 | { | |
862eba51 | 4073 | struct nand_chip *chip = mtd_to_nand(mtd); |
67a9ad9b EG |
4074 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
4075 | int corr, ds_corr; | |
4076 | ||
4077 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
4078 | /* Not enough information */ | |
4079 | return true; | |
4080 | ||
4081 | /* | |
4082 | * We get the number of corrected bits per page to compare | |
4083 | * the correction density. | |
4084 | */ | |
4085 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
4086 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
4087 | ||
4088 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
4089 | } | |
3b85c321 DW |
4090 | |
4091 | /** | |
4092 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 4093 | * @mtd: MTD device structure |
3b85c321 | 4094 | * |
8b6e50c9 BN |
4095 | * This is the second phase of the normal nand_scan() function. It fills out |
4096 | * all the uninitialized function pointers with the defaults and scans for a | |
4097 | * bad block table if appropriate. | |
3b85c321 DW |
4098 | */ |
4099 | int nand_scan_tail(struct mtd_info *mtd) | |
4100 | { | |
4101 | int i; | |
862eba51 | 4102 | struct nand_chip *chip = mtd_to_nand(mtd); |
97de79e0 | 4103 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 4104 | struct nand_buffers *nbuf; |
3b85c321 | 4105 | |
e2414f4c BN |
4106 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
4107 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
4108 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
4109 | ||
f02ea4e6 HS |
4110 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
4111 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
4112 | + mtd->oobsize * 3, GFP_KERNEL); | |
4113 | if (!nbuf) | |
4114 | return -ENOMEM; | |
4115 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
4116 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
4117 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
4118 | ||
4119 | chip->buffers = nbuf; | |
4120 | } else { | |
4121 | if (!chip->buffers) | |
4122 | return -ENOMEM; | |
4123 | } | |
4bf63fcb | 4124 | |
7dcdcbef | 4125 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 4126 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 4127 | |
7aa65bfd | 4128 | /* |
8b6e50c9 | 4129 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 4130 | */ |
97de79e0 | 4131 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 4132 | switch (mtd->oobsize) { |
1da177e4 | 4133 | case 8: |
97de79e0 | 4134 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
4135 | break; |
4136 | case 16: | |
97de79e0 | 4137 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
4138 | break; |
4139 | case 64: | |
97de79e0 | 4140 | ecc->layout = &nand_oob_64; |
1da177e4 | 4141 | break; |
81ec5364 | 4142 | case 128: |
97de79e0 | 4143 | ecc->layout = &nand_oob_128; |
81ec5364 | 4144 | break; |
1da177e4 | 4145 | default: |
d0370219 BN |
4146 | pr_warn("No oob scheme defined for oobsize %d\n", |
4147 | mtd->oobsize); | |
1da177e4 LT |
4148 | BUG(); |
4149 | } | |
4150 | } | |
61b03bd7 | 4151 | |
956e944c DW |
4152 | if (!chip->write_page) |
4153 | chip->write_page = nand_write_page; | |
4154 | ||
61b03bd7 | 4155 | /* |
8b6e50c9 | 4156 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 4157 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 4158 | */ |
956e944c | 4159 | |
97de79e0 | 4160 | switch (ecc->mode) { |
6e0cb135 SN |
4161 | case NAND_ECC_HW_OOB_FIRST: |
4162 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 4163 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
2ac63d90 | 4164 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6e0cb135 SN |
4165 | BUG(); |
4166 | } | |
97de79e0 HS |
4167 | if (!ecc->read_page) |
4168 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 4169 | |
6dfc6d25 | 4170 | case NAND_ECC_HW: |
8b6e50c9 | 4171 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
4172 | if (!ecc->read_page) |
4173 | ecc->read_page = nand_read_page_hwecc; | |
4174 | if (!ecc->write_page) | |
4175 | ecc->write_page = nand_write_page_hwecc; | |
4176 | if (!ecc->read_page_raw) | |
4177 | ecc->read_page_raw = nand_read_page_raw; | |
4178 | if (!ecc->write_page_raw) | |
4179 | ecc->write_page_raw = nand_write_page_raw; | |
4180 | if (!ecc->read_oob) | |
4181 | ecc->read_oob = nand_read_oob_std; | |
4182 | if (!ecc->write_oob) | |
4183 | ecc->write_oob = nand_write_oob_std; | |
4184 | if (!ecc->read_subpage) | |
4185 | ecc->read_subpage = nand_read_subpage; | |
44991b3d | 4186 | if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) |
97de79e0 | 4187 | ecc->write_subpage = nand_write_subpage_hwecc; |
f5bbdacc | 4188 | |
6dfc6d25 | 4189 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
4190 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
4191 | (!ecc->read_page || | |
4192 | ecc->read_page == nand_read_page_hwecc || | |
4193 | !ecc->write_page || | |
4194 | ecc->write_page == nand_write_page_hwecc)) { | |
2ac63d90 | 4195 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6dfc6d25 TG |
4196 | BUG(); |
4197 | } | |
8b6e50c9 | 4198 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
4199 | if (!ecc->read_page) |
4200 | ecc->read_page = nand_read_page_syndrome; | |
4201 | if (!ecc->write_page) | |
4202 | ecc->write_page = nand_write_page_syndrome; | |
4203 | if (!ecc->read_page_raw) | |
4204 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
4205 | if (!ecc->write_page_raw) | |
4206 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
4207 | if (!ecc->read_oob) | |
4208 | ecc->read_oob = nand_read_oob_syndrome; | |
4209 | if (!ecc->write_oob) | |
4210 | ecc->write_oob = nand_write_oob_syndrome; | |
4211 | ||
4212 | if (mtd->writesize >= ecc->size) { | |
4213 | if (!ecc->strength) { | |
e2788c98 MD |
4214 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
4215 | BUG(); | |
4216 | } | |
6dfc6d25 | 4217 | break; |
e2788c98 | 4218 | } |
2ac63d90 RM |
4219 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4220 | ecc->size, mtd->writesize); | |
97de79e0 | 4221 | ecc->mode = NAND_ECC_SOFT; |
61b03bd7 | 4222 | |
6dfc6d25 | 4223 | case NAND_ECC_SOFT: |
97de79e0 HS |
4224 | ecc->calculate = nand_calculate_ecc; |
4225 | ecc->correct = nand_correct_data; | |
4226 | ecc->read_page = nand_read_page_swecc; | |
4227 | ecc->read_subpage = nand_read_subpage; | |
4228 | ecc->write_page = nand_write_page_swecc; | |
4229 | ecc->read_page_raw = nand_read_page_raw; | |
4230 | ecc->write_page_raw = nand_write_page_raw; | |
4231 | ecc->read_oob = nand_read_oob_std; | |
4232 | ecc->write_oob = nand_write_oob_std; | |
4233 | if (!ecc->size) | |
4234 | ecc->size = 256; | |
4235 | ecc->bytes = 3; | |
4236 | ecc->strength = 1; | |
1da177e4 | 4237 | break; |
61b03bd7 | 4238 | |
193bd400 ID |
4239 | case NAND_ECC_SOFT_BCH: |
4240 | if (!mtd_nand_has_bch()) { | |
148256fa | 4241 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
4242 | BUG(); |
4243 | } | |
97de79e0 HS |
4244 | ecc->calculate = nand_bch_calculate_ecc; |
4245 | ecc->correct = nand_bch_correct_data; | |
4246 | ecc->read_page = nand_read_page_swecc; | |
4247 | ecc->read_subpage = nand_read_subpage; | |
4248 | ecc->write_page = nand_write_page_swecc; | |
4249 | ecc->read_page_raw = nand_read_page_raw; | |
4250 | ecc->write_page_raw = nand_write_page_raw; | |
4251 | ecc->read_oob = nand_read_oob_std; | |
4252 | ecc->write_oob = nand_write_oob_std; | |
193bd400 | 4253 | /* |
e0377cde AS |
4254 | * Board driver should supply ecc.size and ecc.strength values |
4255 | * to select how many bits are correctable. Otherwise, default | |
4256 | * to 4 bits for large page devices. | |
193bd400 | 4257 | */ |
97de79e0 HS |
4258 | if (!ecc->size && (mtd->oobsize >= 64)) { |
4259 | ecc->size = 512; | |
e0377cde | 4260 | ecc->strength = 4; |
193bd400 | 4261 | } |
e0377cde AS |
4262 | |
4263 | /* See nand_bch_init() for details. */ | |
a8c65d50 BB |
4264 | ecc->bytes = 0; |
4265 | ecc->priv = nand_bch_init(mtd); | |
97de79e0 | 4266 | if (!ecc->priv) { |
9a4d4d69 | 4267 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
4268 | BUG(); |
4269 | } | |
4270 | break; | |
4271 | ||
61b03bd7 | 4272 | case NAND_ECC_NONE: |
2ac63d90 | 4273 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4274 | ecc->read_page = nand_read_page_raw; |
4275 | ecc->write_page = nand_write_page_raw; | |
4276 | ecc->read_oob = nand_read_oob_std; | |
4277 | ecc->read_page_raw = nand_read_page_raw; | |
4278 | ecc->write_page_raw = nand_write_page_raw; | |
4279 | ecc->write_oob = nand_write_oob_std; | |
4280 | ecc->size = mtd->writesize; | |
4281 | ecc->bytes = 0; | |
4282 | ecc->strength = 0; | |
1da177e4 | 4283 | break; |
956e944c | 4284 | |
1da177e4 | 4285 | default: |
97de79e0 | 4286 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 4287 | BUG(); |
1da177e4 | 4288 | } |
61b03bd7 | 4289 | |
9ce244b3 | 4290 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4291 | if (!ecc->read_oob_raw) |
4292 | ecc->read_oob_raw = ecc->read_oob; | |
4293 | if (!ecc->write_oob_raw) | |
4294 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4295 | |
5bd34c09 TG |
4296 | /* |
4297 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 4298 | * the out of band area. |
5bd34c09 | 4299 | */ |
f5b8aa78 BB |
4300 | mtd->oobavail = 0; |
4301 | if (ecc->layout) { | |
4302 | for (i = 0; ecc->layout->oobfree[i].length; i++) | |
4303 | mtd->oobavail += ecc->layout->oobfree[i].length; | |
4304 | } | |
5bd34c09 | 4305 | |
54c39e9b TP |
4306 | /* ECC sanity check: warn if it's too weak */ |
4307 | if (!nand_ecc_strength_good(mtd)) | |
4308 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
4309 | mtd->name); | |
67a9ad9b | 4310 | |
7aa65bfd TG |
4311 | /* |
4312 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4313 | * mode. |
7aa65bfd | 4314 | */ |
97de79e0 HS |
4315 | ecc->steps = mtd->writesize / ecc->size; |
4316 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 4317 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4318 | BUG(); |
1da177e4 | 4319 | } |
97de79e0 | 4320 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4321 | |
8b6e50c9 | 4322 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4323 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4324 | switch (ecc->steps) { |
29072b96 TG |
4325 | case 2: |
4326 | mtd->subpage_sft = 1; | |
4327 | break; | |
4328 | case 4: | |
4329 | case 8: | |
81ec5364 | 4330 | case 16: |
29072b96 TG |
4331 | mtd->subpage_sft = 2; |
4332 | break; | |
4333 | } | |
4334 | } | |
4335 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4336 | ||
04bbd0ea | 4337 | /* Initialize state */ |
ace4dfee | 4338 | chip->state = FL_READY; |
1da177e4 | 4339 | |
1da177e4 | 4340 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4341 | chip->pagebuf = -1; |
1da177e4 | 4342 | |
a5ff4f10 | 4343 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4344 | switch (ecc->mode) { |
4345 | case NAND_ECC_SOFT: | |
4346 | case NAND_ECC_SOFT_BCH: | |
4347 | if (chip->page_shift > 9) | |
4348 | chip->options |= NAND_SUBPAGE_READ; | |
4349 | break; | |
4350 | ||
4351 | default: | |
4352 | break; | |
4353 | } | |
a5ff4f10 | 4354 | |
1da177e4 | 4355 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4356 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4357 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4358 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4359 | mtd->_erase = nand_erase; |
4360 | mtd->_point = NULL; | |
4361 | mtd->_unpoint = NULL; | |
4362 | mtd->_read = nand_read; | |
4363 | mtd->_write = nand_write; | |
4364 | mtd->_panic_write = panic_nand_write; | |
4365 | mtd->_read_oob = nand_read_oob; | |
4366 | mtd->_write_oob = nand_write_oob; | |
4367 | mtd->_sync = nand_sync; | |
4368 | mtd->_lock = NULL; | |
4369 | mtd->_unlock = NULL; | |
4370 | mtd->_suspend = nand_suspend; | |
4371 | mtd->_resume = nand_resume; | |
72ea4036 | 4372 | mtd->_reboot = nand_shutdown; |
8471bb73 | 4373 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4374 | mtd->_block_isbad = nand_block_isbad; |
4375 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4376 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4377 | |
6a918bad | 4378 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4379 | mtd->ecclayout = ecc->layout; |
4380 | mtd->ecc_strength = ecc->strength; | |
4381 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4382 | /* |
4383 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4384 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4385 | * properly set. | |
4386 | */ | |
4387 | if (!mtd->bitflip_threshold) | |
240181fd | 4388 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 4389 | |
0040bf38 | 4390 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4391 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4392 | return 0; |
1da177e4 LT |
4393 | |
4394 | /* Build bad block table */ | |
ace4dfee | 4395 | return chip->scan_bbt(mtd); |
1da177e4 | 4396 | } |
7351d3a5 | 4397 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4398 | |
8b6e50c9 BN |
4399 | /* |
4400 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4401 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4402 | * to call us from in-kernel code if the core NAND support is modular. |
4403 | */ | |
3b85c321 DW |
4404 | #ifdef MODULE |
4405 | #define caller_is_module() (1) | |
4406 | #else | |
4407 | #define caller_is_module() \ | |
a6e6abd5 | 4408 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4409 | #endif |
4410 | ||
4411 | /** | |
4412 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4413 | * @mtd: MTD device structure |
4414 | * @maxchips: number of chips to scan for | |
3b85c321 | 4415 | * |
8b6e50c9 BN |
4416 | * This fills out all the uninitialized function pointers with the defaults. |
4417 | * The flash ID is read and the mtd/chip structures are filled with the | |
20c07a5b | 4418 | * appropriate values. |
3b85c321 DW |
4419 | */ |
4420 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4421 | { | |
4422 | int ret; | |
4423 | ||
5e81e88a | 4424 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4425 | if (!ret) |
4426 | ret = nand_scan_tail(mtd); | |
4427 | return ret; | |
4428 | } | |
7351d3a5 | 4429 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4430 | |
1da177e4 | 4431 | /** |
61b03bd7 | 4432 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4433 | * @mtd: MTD device structure |
4434 | */ | |
e0c7d767 | 4435 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4436 | { |
862eba51 | 4437 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 4438 | |
193bd400 ID |
4439 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4440 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4441 | ||
5ffcaf3d | 4442 | mtd_device_unregister(mtd); |
1da177e4 | 4443 | |
fa671646 | 4444 | /* Free bad block table memory */ |
ace4dfee | 4445 | kfree(chip->bbt); |
4bf63fcb DW |
4446 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4447 | kfree(chip->buffers); | |
58373ff0 BN |
4448 | |
4449 | /* Free bad block descriptor memory */ | |
4450 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4451 | & NAND_BBT_DYNAMICSTRUCT) | |
4452 | kfree(chip->badblock_pattern); | |
1da177e4 | 4453 | } |
e0c7d767 | 4454 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 | 4455 | |
e0c7d767 | 4456 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4457 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4458 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4459 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |