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mtd: nand: remove deprecated IRQF_DISABLED
[linux-2.6-block.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
38#include <linux/types.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/nand_ecc.h>
193bd400 42#include <linux/mtd/nand_bch.h>
1da177e4
LT		 43#include <linux/interrupt.h>
44#include <linux/bitops.h>
8fe833c1 45#include <linux/leds.h>
7351d3a5 46#include <linux/io.h>
1da177e4 47#include <linux/mtd/partitions.h>
1da177e4
LT		 48
49/* Define default oob placement schemes for large and small page devices */
5bd34c09 50static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 51 .eccbytes = 3,
52 .eccpos = {0, 1, 2},
5bd34c09
TG		 53 .oobfree = {
54 {.offset = 3,
55 .length = 2},
56 {.offset = 6,
f8ac0414 57 .length = 2} }
1da177e4
LT		 58};
59
5bd34c09 60static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 61 .eccbytes = 6,
62 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 63 .oobfree = {
64 {.offset = 8,
f8ac0414 65 . length = 8} }
1da177e4
LT		 66};
67
5bd34c09 68static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 69 .eccbytes = 24,
70 .eccpos = {
e0c7d767
DW		 71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 74 .oobfree = {
75 {.offset = 2,
f8ac0414 76 .length = 38} }
1da177e4
LT		 77};
78
81ec5364
TG		 79static struct nand_ecclayout nand_oob_128 = {
80 .eccbytes = 48,
81 .eccpos = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
88 .oobfree = {
89 {.offset = 2,
f8ac0414 90 .length = 78} }
81ec5364
TG		 91};
92
6a8214aa 93static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 94
8593fbc6
TG		 95static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
97
d470a97c 98/*
8e87d782 99 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 100 * compiled away when LED support is disabled.
101 */
102DEFINE_LED_TRIGGER(nand_led_trigger);
103
6fe5a6ac
VS		 104static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
106{
107 struct nand_chip *chip = mtd->priv;
108 int ret = 0;
109
110 /* Start address must align on block boundary */
daae74ca 111 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 112 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 113 ret = -EINVAL;
114 }
115
116 /* Length must align on block boundary */
daae74ca 117 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 118 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 119 ret = -EINVAL;
120 }
121
6fe5a6ac
VS		 122 return ret;
123}
124
1da177e4
LT		 125/**
126 * nand_release_device - [GENERIC] release chip
8b6e50c9 127 * @mtd: MTD device structure
61b03bd7 128 *
b0bb6903 129 * Release chip lock and wake up anyone waiting on the device.
1da177e4 130 */
e0c7d767 131static void nand_release_device(struct mtd_info *mtd)
1da177e4 132{
ace4dfee 133 struct nand_chip *chip = mtd->priv;
1da177e4 134
a36ed299 135 /* Release the controller and the chip */
ace4dfee
TG		 136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
1da177e4
LT		 141}
142
143/**
144 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 145 * @mtd: MTD device structure
1da177e4 146 *
7854d3f7 147 * Default read function for 8bit buswidth
1da177e4 148 */
58dd8f2b 149static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 150{
ace4dfee
TG		 151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
1da177e4
LT		 153}
154
1da177e4 155/**
064a7694 156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
7854d3f7 157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 158 * @mtd: MTD device structure
1da177e4 159 *
7854d3f7
BN		 160 * Default read function for 16bit buswidth with endianness conversion.
161 *
1da177e4 162 */
58dd8f2b 163static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 164{
ace4dfee
TG		 165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 167}
168
1da177e4
LT		 169/**
170 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 171 * @mtd: MTD device structure
1da177e4 172 *
7854d3f7 173 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 174 */
175static u16 nand_read_word(struct mtd_info *mtd)
176{
ace4dfee
TG		 177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
1da177e4
LT		 179}
180
1da177e4
LT		 181/**
182 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 185 *
186 * Default select function for 1 chip devices.
187 */
ace4dfee 188static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 189{
ace4dfee
TG		 190 struct nand_chip *chip = mtd->priv;
191
192 switch (chipnr) {
1da177e4 193 case -1:
ace4dfee 194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 195 break;
196 case 0:
1da177e4
LT		 197 break;
198
199 default:
200 BUG();
201 }
202}
203
204/**
205 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 206 * @mtd: MTD device structure
207 * @buf: data buffer
208 * @len: number of bytes to write
1da177e4 209 *
7854d3f7 210 * Default write function for 8bit buswidth.
1da177e4 211 */
58dd8f2b 212static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 213{
ace4dfee 214 struct nand_chip *chip = mtd->priv;
1da177e4 215
76413839 216 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 217}
218
219/**
61b03bd7 220 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 221 * @mtd: MTD device structure
222 * @buf: buffer to store date
223 * @len: number of bytes to read
1da177e4 224 *
7854d3f7 225 * Default read function for 8bit buswidth.
1da177e4 226 */
58dd8f2b 227static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 228{
ace4dfee 229 struct nand_chip *chip = mtd->priv;
1da177e4 230
76413839 231 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 232}
233
1da177e4
LT		 234/**
235 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 236 * @mtd: MTD device structure
237 * @buf: data buffer
238 * @len: number of bytes to write
1da177e4 239 *
7854d3f7 240 * Default write function for 16bit buswidth.
1da177e4 241 */
58dd8f2b 242static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 243{
ace4dfee 244 struct nand_chip *chip = mtd->priv;
1da177e4 245 u16 *p = (u16 *) buf;
61b03bd7 246
76413839 247 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 248}
249
250/**
61b03bd7 251 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 252 * @mtd: MTD device structure
253 * @buf: buffer to store date
254 * @len: number of bytes to read
1da177e4 255 *
7854d3f7 256 * Default read function for 16bit buswidth.
1da177e4 257 */
58dd8f2b 258static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 259{
ace4dfee 260 struct nand_chip *chip = mtd->priv;
1da177e4 261 u16 *p = (u16 *) buf;
1da177e4 262
76413839 263 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 264}
265
1da177e4
LT		 266/**
267 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 268 * @mtd: MTD device structure
269 * @ofs: offset from device start
270 * @getchip: 0, if the chip is already selected
1da177e4 271 *
61b03bd7 272 * Check, if the block is bad.
1da177e4
LT		 273 */
274static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
275{
cdbec050 276 int page, chipnr, res = 0, i = 0;
ace4dfee 277 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 278 u16 bad;
279
5fb1549d 280 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 281 ofs += mtd->erasesize - mtd->writesize;
282
1a12f46a
TK		 283 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
284
1da177e4 285 if (getchip) {
ace4dfee 286 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 287
6a8214aa 288 nand_get_device(mtd, FL_READING);
1da177e4
LT		 289
290 /* Select the NAND device */
ace4dfee 291 chip->select_chip(mtd, chipnr);
1a12f46a 292 }
1da177e4 293
cdbec050
BN		 294 do {
295 if (chip->options & NAND_BUSWIDTH_16) {
296 chip->cmdfunc(mtd, NAND_CMD_READOOB,
297 chip->badblockpos & 0xFE, page);
298 bad = cpu_to_le16(chip->read_word(mtd));
299 if (chip->badblockpos & 0x1)
300 bad >>= 8;
301 else
302 bad &= 0xFF;
303 } else {
304 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
305 page);
306 bad = chip->read_byte(mtd);
307 }
308
309 if (likely(chip->badblockbits == 8))
310 res = bad != 0xFF;
e0b58d0a 311 else
cdbec050
BN		 312 res = hweight8(bad) < chip->badblockbits;
313 ofs += mtd->writesize;
314 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
315 i++;
316 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 317
b0bb6903
HS		 318 if (getchip) {
319 chip->select_chip(mtd, -1);
1da177e4 320 nand_release_device(mtd);
b0bb6903 321 }
61b03bd7 322
1da177e4
LT		 323 return res;
324}
325
326/**
5a0edb25 327 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 328 * @mtd: MTD device structure
329 * @ofs: offset from device start
1da177e4 330 *
8b6e50c9 331 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 332 * specific driver. It provides the details for writing a bad block marker to a
333 * block.
334 */
335static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
336{
337 struct nand_chip *chip = mtd->priv;
338 struct mtd_oob_ops ops;
339 uint8_t buf[2] = { 0, 0 };
340 int ret = 0, res, i = 0;
341
342 ops.datbuf = NULL;
343 ops.oobbuf = buf;
344 ops.ooboffs = chip->badblockpos;
345 if (chip->options & NAND_BUSWIDTH_16) {
346 ops.ooboffs &= ~0x01;
347 ops.len = ops.ooblen = 2;
348 } else {
349 ops.len = ops.ooblen = 1;
350 }
351 ops.mode = MTD_OPS_PLACE_OOB;
352
353 /* Write to first/last page(s) if necessary */
354 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
355 ofs += mtd->erasesize - mtd->writesize;
356 do {
357 res = nand_do_write_oob(mtd, ofs, &ops);
358 if (!ret)
359 ret = res;
360
361 i++;
362 ofs += mtd->writesize;
363 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
364
365 return ret;
366}
367
368/**
369 * nand_block_markbad_lowlevel - mark a block bad
370 * @mtd: MTD device structure
371 * @ofs: offset from device start
372 *
373 * This function performs the generic NAND bad block marking steps (i.e., bad
374 * block table(s) and/or marker(s)). We only allow the hardware driver to
375 * specify how to write bad block markers to OOB (chip->block_markbad).
376 *
b32843b7 377 * We try operations in the following order:
e2414f4c 378 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 379 * (2) write bad block marker to OOB area of affected block (unless flag
380 * NAND_BBT_NO_OOB_BBM is present)
381 * (3) update the BBT
382 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 383 * procedures, and dump the error in the end.
1da177e4 384*/
5a0edb25 385static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 386{
ace4dfee 387 struct nand_chip *chip = mtd->priv;
b32843b7 388 int res, ret = 0;
61b03bd7 389
b32843b7 390 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 391 struct erase_info einfo;
392
393 /* Attempt erase before marking OOB */
394 memset(&einfo, 0, sizeof(einfo));
395 einfo.mtd = mtd;
396 einfo.addr = ofs;
daae74ca 397 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 398 nand_erase_nand(mtd, &einfo, 0);
1da177e4 399
b32843b7 400 /* Write bad block marker to OOB */
6a8214aa 401 nand_get_device(mtd, FL_WRITING);
5a0edb25 402 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 403 nand_release_device(mtd);
f1a28c02 404 }
e2414f4c 405
b32843b7
BN		 406 /* Mark block bad in BBT */
407 if (chip->bbt) {
408 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 409 if (!ret)
410 ret = res;
411 }
412
f1a28c02
TG		 413 if (!ret)
414 mtd->ecc_stats.badblocks++;
c0b8ba7b 415
f1a28c02 416 return ret;
1da177e4
LT		 417}
418
61b03bd7 419/**
1da177e4 420 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 421 * @mtd: MTD device structure
1da177e4 422 *
8b6e50c9
BN		 423 * Check, if the device is write protected. The function expects, that the
424 * device is already selected.
1da177e4 425 */
e0c7d767 426static int nand_check_wp(struct mtd_info *mtd)
1da177e4 427{
ace4dfee 428 struct nand_chip *chip = mtd->priv;
93edbad6 429
8b6e50c9 430 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 431 if (chip->options & NAND_BROKEN_XD)
432 return 0;
433
1da177e4 434 /* Check the WP bit */
ace4dfee
TG		 435 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
436 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 437}
438
439/**
440 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 441 * @mtd: MTD device structure
442 * @ofs: offset from device start
443 * @getchip: 0, if the chip is already selected
444 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 445 *
446 * Check, if the block is bad. Either by reading the bad block table or
447 * calling of the scan function.
448 */
2c0a2bed
TG		 449static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
450 int allowbbt)
1da177e4 451{
ace4dfee 452 struct nand_chip *chip = mtd->priv;
61b03bd7 453
ace4dfee
TG		 454 if (!chip->bbt)
455 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 456
1da177e4 457 /* Return info from the table */
e0c7d767 458 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 459}
460
2af7c653
SK		 461/**
462 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 463 * @mtd: MTD device structure
464 * @timeo: Timeout
2af7c653
SK		 465 *
466 * Helper function for nand_wait_ready used when needing to wait in interrupt
467 * context.
468 */
469static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
470{
471 struct nand_chip *chip = mtd->priv;
472 int i;
473
474 /* Wait for the device to get ready */
475 for (i = 0; i < timeo; i++) {
476 if (chip->dev_ready(mtd))
477 break;
478 touch_softlockup_watchdog();
479 mdelay(1);
480 }
481}
482
7854d3f7 483/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 484void nand_wait_ready(struct mtd_info *mtd)
3b88775c 485{
ace4dfee 486 struct nand_chip *chip = mtd->priv;
ca6a2489 487 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 488
2af7c653
SK		 489 /* 400ms timeout */
490 if (in_interrupt() || oops_in_progress)
491 return panic_nand_wait_ready(mtd, 400);
492
8fe833c1 493 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 494 /* Wait until command is processed or timeout occurs */
3b88775c 495 do {
ace4dfee 496 if (chip->dev_ready(mtd))
8fe833c1 497 break;
8446f1d3 498 touch_softlockup_watchdog();
61b03bd7 499 } while (time_before(jiffies, timeo));
8fe833c1 500 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 501}
4b648b02 502EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 503
1da177e4
LT		 504/**
505 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 506 * @mtd: MTD device structure
507 * @command: the command to be sent
508 * @column: the column address for this command, -1 if none
509 * @page_addr: the page address for this command, -1 if none
1da177e4 510 *
8b6e50c9 511 * Send command to NAND device. This function is used for small page devices
51148f1f 512 * (512 Bytes per page).
1da177e4 513 */
7abd3ef9
TG		 514static void nand_command(struct mtd_info *mtd, unsigned int command,
515 int column, int page_addr)
1da177e4 516{
ace4dfee 517 register struct nand_chip *chip = mtd->priv;
7abd3ef9 518 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 519
8b6e50c9 520 /* Write out the command to the device */
1da177e4
LT		 521 if (command == NAND_CMD_SEQIN) {
522 int readcmd;
523
28318776 524 if (column >= mtd->writesize) {
1da177e4 525 /* OOB area */
28318776 526 column -= mtd->writesize;
1da177e4
LT		 527 readcmd = NAND_CMD_READOOB;
528 } else if (column < 256) {
529 /* First 256 bytes --> READ0 */
530 readcmd = NAND_CMD_READ0;
531 } else {
532 column -= 256;
533 readcmd = NAND_CMD_READ1;
534 }
ace4dfee 535 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 536 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 537 }
ace4dfee 538 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 539
8b6e50c9 540 /* Address cycle, when necessary */
7abd3ef9
TG		 541 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
542 /* Serially input address */
543 if (column != -1) {
544 /* Adjust columns for 16 bit buswidth */
ace4dfee 545 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 546 column >>= 1;
ace4dfee 547 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 548 ctrl &= ~NAND_CTRL_CHANGE;
549 }
550 if (page_addr != -1) {
ace4dfee 551 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 552 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 553 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 554 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 555 if (chip->chipsize > (32 << 20))
556 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 557 }
ace4dfee 558 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 559
560 /*
8b6e50c9
BN		 561 * Program and erase have their own busy handlers status and sequential
562 * in needs no delay
e0c7d767 563 */
1da177e4 564 switch (command) {
61b03bd7 565
1da177e4
LT		 566 case NAND_CMD_PAGEPROG:
567 case NAND_CMD_ERASE1:
568 case NAND_CMD_ERASE2:
569 case NAND_CMD_SEQIN:
570 case NAND_CMD_STATUS:
571 return;
572
573 case NAND_CMD_RESET:
ace4dfee 574 if (chip->dev_ready)
1da177e4 575 break;
ace4dfee
TG		 576 udelay(chip->chip_delay);
577 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 578 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 579 chip->cmd_ctrl(mtd,
580 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 581 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
582 ;
1da177e4
LT		 583 return;
584
e0c7d767 585 /* This applies to read commands */
1da177e4 586 default:
61b03bd7 587 /*
1da177e4
LT		 588 * If we don't have access to the busy pin, we apply the given
589 * command delay
e0c7d767 590 */
ace4dfee
TG		 591 if (!chip->dev_ready) {
592 udelay(chip->chip_delay);
1da177e4 593 return;
61b03bd7 594 }
1da177e4 595 }
8b6e50c9
BN		 596 /*
597 * Apply this short delay always to ensure that we do wait tWB in
598 * any case on any machine.
599 */
e0c7d767 600 ndelay(100);
3b88775c
TG		 601
602 nand_wait_ready(mtd);
1da177e4
LT		 603}
604
605/**
606 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 607 * @mtd: MTD device structure
608 * @command: the command to be sent
609 * @column: the column address for this command, -1 if none
610 * @page_addr: the page address for this command, -1 if none
1da177e4 611 *
7abd3ef9 612 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 613 * devices. We don't have the separate regions as we have in the small page
614 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 615 */
7abd3ef9
TG		 616static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
617 int column, int page_addr)
1da177e4 618{
ace4dfee 619 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 620
621 /* Emulate NAND_CMD_READOOB */
622 if (command == NAND_CMD_READOOB) {
28318776 623 column += mtd->writesize;
1da177e4
LT		 624 command = NAND_CMD_READ0;
625 }
61b03bd7 626
7abd3ef9 627 /* Command latch cycle */
fb066ada 628 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 629
630 if (column != -1 || page_addr != -1) {
7abd3ef9 631 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 632
633 /* Serially input address */
634 if (column != -1) {
635 /* Adjust columns for 16 bit buswidth */
ace4dfee 636 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 637 column >>= 1;
ace4dfee 638 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 639 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 640 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 641 }
1da177e4 642 if (page_addr != -1) {
ace4dfee
TG		 643 chip->cmd_ctrl(mtd, page_addr, ctrl);
644 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 645 NAND_NCE | NAND_ALE);
1da177e4 646 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 647 if (chip->chipsize > (128 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 649 NAND_NCE | NAND_ALE);
1da177e4 650 }
1da177e4 651 }
ace4dfee 652 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 653
654 /*
8b6e50c9
BN		 655 * Program and erase have their own busy handlers status, sequential
656 * in, and deplete1 need no delay.
30f464b7 657 */
1da177e4 658 switch (command) {
61b03bd7 659
1da177e4
LT		 660 case NAND_CMD_CACHEDPROG:
661 case NAND_CMD_PAGEPROG:
662 case NAND_CMD_ERASE1:
663 case NAND_CMD_ERASE2:
664 case NAND_CMD_SEQIN:
7bc3312b 665 case NAND_CMD_RNDIN:
1da177e4 666 case NAND_CMD_STATUS:
30f464b7 667 return;
1da177e4
LT		 668
669 case NAND_CMD_RESET:
ace4dfee 670 if (chip->dev_ready)
1da177e4 671 break;
ace4dfee 672 udelay(chip->chip_delay);
12efdde3
TG		 673 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
674 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
675 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
676 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 677 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
678 ;
1da177e4
LT		 679 return;
680
7bc3312b
TG		 681 case NAND_CMD_RNDOUT:
682 /* No ready / busy check necessary */
683 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
684 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
685 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
686 NAND_NCE | NAND_CTRL_CHANGE);
687 return;
688
1da177e4 689 case NAND_CMD_READ0:
12efdde3
TG		 690 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
691 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
692 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
693 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 694
e0c7d767 695 /* This applies to read commands */
1da177e4 696 default:
61b03bd7 697 /*
1da177e4 698 * If we don't have access to the busy pin, we apply the given
8b6e50c9 699 * command delay.
e0c7d767 700 */
ace4dfee
TG		 701 if (!chip->dev_ready) {
702 udelay(chip->chip_delay);
1da177e4 703 return;
61b03bd7 704 }
1da177e4 705 }
3b88775c 706
8b6e50c9
BN		 707 /*
708 * Apply this short delay always to ensure that we do wait tWB in
709 * any case on any machine.
710 */
e0c7d767 711 ndelay(100);
3b88775c
TG		 712
713 nand_wait_ready(mtd);
1da177e4
LT		 714}
715
2af7c653
SK		 716/**
717 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 718 * @chip: the nand chip descriptor
719 * @mtd: MTD device structure
720 * @new_state: the state which is requested
2af7c653
SK		 721 *
722 * Used when in panic, no locks are taken.
723 */
724static void panic_nand_get_device(struct nand_chip *chip,
725 struct mtd_info *mtd, int new_state)
726{
7854d3f7 727 /* Hardware controller shared among independent devices */
2af7c653
SK		 728 chip->controller->active = chip;
729 chip->state = new_state;
730}
731
1da177e4
LT		 732/**
733 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 734 * @mtd: MTD device structure
735 * @new_state: the state which is requested
1da177e4
LT		 736 *
737 * Get the device and lock it for exclusive access
738 */
2c0a2bed 739static int
6a8214aa 740nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 741{
6a8214aa 742 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 743 spinlock_t *lock = &chip->controller->lock;
744 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 745 DECLARE_WAITQUEUE(wait, current);
7351d3a5 746retry:
0dfc6246
TG		 747 spin_lock(lock);
748
b8b3ee9a 749 /* Hardware controller shared among independent devices */
ace4dfee
TG		 750 if (!chip->controller->active)
751 chip->controller->active = chip;
a36ed299 752
ace4dfee
TG		 753 if (chip->controller->active == chip && chip->state == FL_READY) {
754 chip->state = new_state;
0dfc6246 755 spin_unlock(lock);
962034f4
VW		 756 return 0;
757 }
758 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 759 if (chip->controller->active->state == FL_PM_SUSPENDED) {
760 chip->state = FL_PM_SUSPENDED;
761 spin_unlock(lock);
762 return 0;
6b0d9a84 763 }
0dfc6246
TG		 764 }
765 set_current_state(TASK_UNINTERRUPTIBLE);
766 add_wait_queue(wq, &wait);
767 spin_unlock(lock);
768 schedule();
769 remove_wait_queue(wq, &wait);
1da177e4
LT		 770 goto retry;
771}
772
2af7c653 773/**
8b6e50c9
BN		 774 * panic_nand_wait - [GENERIC] wait until the command is done
775 * @mtd: MTD device structure
776 * @chip: NAND chip structure
777 * @timeo: timeout
2af7c653
SK		 778 *
779 * Wait for command done. This is a helper function for nand_wait used when
780 * we are in interrupt context. May happen when in panic and trying to write
b595076a 781 * an oops through mtdoops.
2af7c653
SK		 782 */
783static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
784 unsigned long timeo)
785{
786 int i;
787 for (i = 0; i < timeo; i++) {
788 if (chip->dev_ready) {
789 if (chip->dev_ready(mtd))
790 break;
791 } else {
792 if (chip->read_byte(mtd) & NAND_STATUS_READY)
793 break;
794 }
795 mdelay(1);
f8ac0414 796 }
2af7c653
SK		 797}
798
1da177e4 799/**
8b6e50c9
BN		 800 * nand_wait - [DEFAULT] wait until the command is done
801 * @mtd: MTD device structure
802 * @chip: NAND chip structure
1da177e4 803 *
8b6e50c9
BN		 804 * Wait for command done. This applies to erase and program only. Erase can
805 * take up to 400ms and program up to 20ms according to general NAND and
806 * SmartMedia specs.
844d3b42 807 */
7bc3312b 808static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 809{
810
7bc3312b 811 int status, state = chip->state;
6d2559f8 812 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 813
8fe833c1
RP		 814 led_trigger_event(nand_led_trigger, LED_FULL);
815
8b6e50c9
BN		 816 /*
817 * Apply this short delay always to ensure that we do wait tWB in any
818 * case on any machine.
819 */
e0c7d767 820 ndelay(100);
1da177e4 821
14c65786 822 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 823
2af7c653
SK		 824 if (in_interrupt() || oops_in_progress)
825 panic_nand_wait(mtd, chip, timeo);
826 else {
6d2559f8 827 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 828 while (time_before(jiffies, timeo)) {
829 if (chip->dev_ready) {
830 if (chip->dev_ready(mtd))
831 break;
832 } else {
833 if (chip->read_byte(mtd) & NAND_STATUS_READY)
834 break;
835 }
836 cond_resched();
1da177e4 837 }
1da177e4 838 }
8fe833c1
RP		 839 led_trigger_event(nand_led_trigger, LED_OFF);
840
ace4dfee 841 status = (int)chip->read_byte(mtd);
f251b8df
MC		 842 /* This can happen if in case of timeout or buggy dev_ready */
843 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 844 return status;
845}
846
7d70f334 847/**
b6d676db 848 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 849 * @mtd: mtd info
850 * @ofs: offset to start unlock from
851 * @len: length to unlock
8b6e50c9
BN		 852 * @invert: when = 0, unlock the range of blocks within the lower and
853 * upper boundary address
854 * when = 1, unlock the range of blocks outside the boundaries
855 * of the lower and upper boundary address
7d70f334 856 *
8b6e50c9 857 * Returs unlock status.
7d70f334
VS		 858 */
859static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
860 uint64_t len, int invert)
861{
862 int ret = 0;
863 int status, page;
864 struct nand_chip *chip = mtd->priv;
865
866 /* Submit address of first page to unlock */
867 page = ofs >> chip->page_shift;
868 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
869
870 /* Submit address of last page to unlock */
871 page = (ofs + len) >> chip->page_shift;
872 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
873 (page | invert) & chip->pagemask);
874
875 /* Call wait ready function */
876 status = chip->waitfunc(mtd, chip);
7d70f334 877 /* See if device thinks it succeeded */
74830966 878 if (status & NAND_STATUS_FAIL) {
289c0522 879 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 880 __func__, status);
881 ret = -EIO;
882 }
883
884 return ret;
885}
886
887/**
b6d676db 888 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 889 * @mtd: mtd info
890 * @ofs: offset to start unlock from
891 * @len: length to unlock
7d70f334 892 *
8b6e50c9 893 * Returns unlock status.
7d70f334
VS		 894 */
895int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
896{
897 int ret = 0;
898 int chipnr;
899 struct nand_chip *chip = mtd->priv;
900
289c0522 901 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 902 __func__, (unsigned long long)ofs, len);
903
904 if (check_offs_len(mtd, ofs, len))
905 ret = -EINVAL;
906
907 /* Align to last block address if size addresses end of the device */
908 if (ofs + len == mtd->size)
909 len -= mtd->erasesize;
910
6a8214aa 911 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 912
913 /* Shift to get chip number */
914 chipnr = ofs >> chip->chip_shift;
915
916 chip->select_chip(mtd, chipnr);
917
918 /* Check, if it is write protected */
919 if (nand_check_wp(mtd)) {
289c0522 920 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 921 __func__);
922 ret = -EIO;
923 goto out;
924 }
925
926 ret = __nand_unlock(mtd, ofs, len, 0);
927
928out:
b0bb6903 929 chip->select_chip(mtd, -1);
7d70f334
VS		 930 nand_release_device(mtd);
931
932 return ret;
933}
7351d3a5 934EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 935
936/**
b6d676db 937 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 938 * @mtd: mtd info
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
7d70f334 941 *
8b6e50c9
BN		 942 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
943 * have this feature, but it allows only to lock all blocks, not for specified
944 * range for block. Implementing 'lock' feature by making use of 'unlock', for
945 * now.
7d70f334 946 *
8b6e50c9 947 * Returns lock status.
7d70f334
VS		 948 */
949int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
950{
951 int ret = 0;
952 int chipnr, status, page;
953 struct nand_chip *chip = mtd->priv;
954
289c0522 955 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 956 __func__, (unsigned long long)ofs, len);
957
958 if (check_offs_len(mtd, ofs, len))
959 ret = -EINVAL;
960
6a8214aa 961 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 962
963 /* Shift to get chip number */
964 chipnr = ofs >> chip->chip_shift;
965
966 chip->select_chip(mtd, chipnr);
967
968 /* Check, if it is write protected */
969 if (nand_check_wp(mtd)) {
289c0522 970 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 971 __func__);
972 status = MTD_ERASE_FAILED;
973 ret = -EIO;
974 goto out;
975 }
976
977 /* Submit address of first page to lock */
978 page = ofs >> chip->page_shift;
979 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
980
981 /* Call wait ready function */
982 status = chip->waitfunc(mtd, chip);
7d70f334 983 /* See if device thinks it succeeded */
74830966 984 if (status & NAND_STATUS_FAIL) {
289c0522 985 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 986 __func__, status);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0x1);
992
993out:
b0bb6903 994 chip->select_chip(mtd, -1);
7d70f334
VS		 995 nand_release_device(mtd);
996
997 return ret;
998}
7351d3a5 999EXPORT_SYMBOL(nand_lock);
7d70f334 1000
8593fbc6 1001/**
7854d3f7 1002 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1003 * @mtd: mtd info structure
1004 * @chip: nand chip info structure
1005 * @buf: buffer to store read data
1fbb938d 1006 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1007 * @page: page number to read
52ff49df 1008 *
7854d3f7 1009 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1010 */
1011static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1012 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1013{
1014 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1015 if (oob_required)
1016 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1017 return 0;
1018}
1019
52ff49df 1020/**
7854d3f7 1021 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1022 * @mtd: mtd info structure
1023 * @chip: nand chip info structure
1024 * @buf: buffer to store read data
1fbb938d 1025 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1026 * @page: page number to read
52ff49df
DB		 1027 *
1028 * We need a special oob layout and handling even when OOB isn't used.
1029 */
7351d3a5 1030static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1031 struct nand_chip *chip, uint8_t *buf,
1032 int oob_required, int page)
52ff49df
DB		 1033{
1034 int eccsize = chip->ecc.size;
1035 int eccbytes = chip->ecc.bytes;
1036 uint8_t *oob = chip->oob_poi;
1037 int steps, size;
1038
1039 for (steps = chip->ecc.steps; steps > 0; steps--) {
1040 chip->read_buf(mtd, buf, eccsize);
1041 buf += eccsize;
1042
1043 if (chip->ecc.prepad) {
1044 chip->read_buf(mtd, oob, chip->ecc.prepad);
1045 oob += chip->ecc.prepad;
1046 }
1047
1048 chip->read_buf(mtd, oob, eccbytes);
1049 oob += eccbytes;
1050
1051 if (chip->ecc.postpad) {
1052 chip->read_buf(mtd, oob, chip->ecc.postpad);
1053 oob += chip->ecc.postpad;
1054 }
1055 }
1056
1057 size = mtd->oobsize - (oob - chip->oob_poi);
1058 if (size)
1059 chip->read_buf(mtd, oob, size);
1060
1061 return 0;
1062}
1063
1da177e4 1064/**
7854d3f7 1065 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1fbb938d 1069 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1070 * @page: page number to read
068e3c0a 1071 */
f5bbdacc 1072static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1073 uint8_t *buf, int oob_required, int page)
1da177e4 1074{
f5bbdacc
TG		 1075 int i, eccsize = chip->ecc.size;
1076 int eccbytes = chip->ecc.bytes;
1077 int eccsteps = chip->ecc.steps;
1078 uint8_t *p = buf;
4bf63fcb
DW		 1079 uint8_t *ecc_calc = chip->buffers->ecccalc;
1080 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1081 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1082 unsigned int max_bitflips = 0;
f5bbdacc 1083
1fbb938d 1084 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1085
1086 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1087 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1088
1089 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1090 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1091
1092 eccsteps = chip->ecc.steps;
1093 p = buf;
1094
1095 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1096 int stat;
1097
1098 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1099 if (stat < 0) {
f5bbdacc 1100 mtd->ecc_stats.failed++;
3f91e94f 1101 } else {
f5bbdacc 1102 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1103 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1104 }
f5bbdacc 1105 }
3f91e94f 1106 return max_bitflips;
22c60f5f 1107}
1da177e4 1108
3d459559 1109/**
837a6ba4 1110 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1111 * @mtd: mtd info structure
1112 * @chip: nand chip info structure
1113 * @data_offs: offset of requested data within the page
1114 * @readlen: data length
1115 * @bufpoi: buffer to store read data
3d459559 1116 */
7351d3a5
FF		 1117static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1118 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1119{
1120 int start_step, end_step, num_steps;
1121 uint32_t *eccpos = chip->ecc.layout->eccpos;
1122 uint8_t *p;
1123 int data_col_addr, i, gaps = 0;
1124 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1125 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1126 int index = 0;
3f91e94f 1127 unsigned int max_bitflips = 0;
3d459559 1128
7854d3f7 1129 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1130 start_step = data_offs / chip->ecc.size;
1131 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1132 num_steps = end_step - start_step + 1;
1133
8b6e50c9 1134 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1135 datafrag_len = num_steps * chip->ecc.size;
1136 eccfrag_len = num_steps * chip->ecc.bytes;
1137
1138 data_col_addr = start_step * chip->ecc.size;
1139 /* If we read not a page aligned data */
1140 if (data_col_addr != 0)
1141 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1142
1143 p = bufpoi + data_col_addr;
1144 chip->read_buf(mtd, p, datafrag_len);
1145
8b6e50c9 1146 /* Calculate ECC */
3d459559
AK		 1147 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1148 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1149
8b6e50c9
BN		 1150 /*
1151 * The performance is faster if we position offsets according to
7854d3f7 1152 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1153 */
3d459559
AK		 1154 for (i = 0; i < eccfrag_len - 1; i++) {
1155 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1156 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1157 gaps = 1;
1158 break;
1159 }
1160 }
1161 if (gaps) {
1162 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1163 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1164 } else {
8b6e50c9 1165 /*
7854d3f7 1166 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1167 * about buswidth alignment in read_buf.
1168 */
7351d3a5
FF		 1169 index = start_step * chip->ecc.bytes;
1170
1171 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1172 aligned_len = eccfrag_len;
7351d3a5 1173 if (eccpos[index] & (busw - 1))
3d459559 1174 aligned_len++;
7351d3a5 1175 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1176 aligned_len++;
1177
7351d3a5
FF		 1178 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1179 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1180 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1181 }
1182
1183 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1184 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1185
1186 p = bufpoi + data_col_addr;
1187 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1188 int stat;
1189
7351d3a5
FF		 1190 stat = chip->ecc.correct(mtd, p,
1191 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1192 if (stat < 0) {
3d459559 1193 mtd->ecc_stats.failed++;
3f91e94f 1194 } else {
3d459559 1195 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1196 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1197 }
3d459559 1198 }
3f91e94f 1199 return max_bitflips;
3d459559
AK		 1200}
1201
068e3c0a 1202/**
7854d3f7 1203 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1204 * @mtd: mtd info structure
1205 * @chip: nand chip info structure
1206 * @buf: buffer to store read data
1fbb938d 1207 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1208 * @page: page number to read
068e3c0a 1209 *
7854d3f7 1210 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1211 */
f5bbdacc 1212static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1213 uint8_t *buf, int oob_required, int page)
1da177e4 1214{
f5bbdacc
TG		 1215 int i, eccsize = chip->ecc.size;
1216 int eccbytes = chip->ecc.bytes;
1217 int eccsteps = chip->ecc.steps;
1218 uint8_t *p = buf;
4bf63fcb
DW		 1219 uint8_t *ecc_calc = chip->buffers->ecccalc;
1220 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1221 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1222 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1223
1224 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1225 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1226 chip->read_buf(mtd, p, eccsize);
1227 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1228 }
f75e5097 1229 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1230
f5bbdacc 1231 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1232 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1233
f5bbdacc
TG		 1234 eccsteps = chip->ecc.steps;
1235 p = buf;
61b03bd7 1236
f5bbdacc
TG		 1237 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1238 int stat;
1da177e4 1239
f5bbdacc 1240 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1241 if (stat < 0) {
f5bbdacc 1242 mtd->ecc_stats.failed++;
3f91e94f 1243 } else {
f5bbdacc 1244 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1245 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1246 }
f5bbdacc 1247 }
3f91e94f 1248 return max_bitflips;
f5bbdacc 1249}
1da177e4 1250
6e0cb135 1251/**
7854d3f7 1252 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1253 * @mtd: mtd info structure
1254 * @chip: nand chip info structure
1255 * @buf: buffer to store read data
1fbb938d 1256 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1257 * @page: page number to read
6e0cb135 1258 *
8b6e50c9
BN		 1259 * Hardware ECC for large page chips, require OOB to be read first. For this
1260 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1261 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1262 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1263 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1264 */
1265static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1266 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1267{
1268 int i, eccsize = chip->ecc.size;
1269 int eccbytes = chip->ecc.bytes;
1270 int eccsteps = chip->ecc.steps;
1271 uint8_t *p = buf;
1272 uint8_t *ecc_code = chip->buffers->ecccode;
1273 uint32_t *eccpos = chip->ecc.layout->eccpos;
1274 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1275 unsigned int max_bitflips = 0;
6e0cb135
SN		 1276
1277 /* Read the OOB area first */
1278 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1279 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1280 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1281
1282 for (i = 0; i < chip->ecc.total; i++)
1283 ecc_code[i] = chip->oob_poi[eccpos[i]];
1284
1285 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1286 int stat;
1287
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1291
1292 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1293 if (stat < 0) {
6e0cb135 1294 mtd->ecc_stats.failed++;
3f91e94f 1295 } else {
6e0cb135 1296 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1297 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1298 }
6e0cb135 1299 }
3f91e94f 1300 return max_bitflips;
6e0cb135
SN		 1301}
1302
f5bbdacc 1303/**
7854d3f7 1304 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1305 * @mtd: mtd info structure
1306 * @chip: nand chip info structure
1307 * @buf: buffer to store read data
1fbb938d 1308 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1309 * @page: page number to read
f5bbdacc 1310 *
8b6e50c9
BN		 1311 * The hw generator calculates the error syndrome automatically. Therefore we
1312 * need a special oob layout and handling.
f5bbdacc
TG		 1313 */
1314static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1315 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1316{
1317 int i, eccsize = chip->ecc.size;
1318 int eccbytes = chip->ecc.bytes;
1319 int eccsteps = chip->ecc.steps;
1320 uint8_t *p = buf;
f75e5097 1321 uint8_t *oob = chip->oob_poi;
3f91e94f 1322 unsigned int max_bitflips = 0;
1da177e4 1323
f5bbdacc
TG		 1324 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1325 int stat;
61b03bd7 1326
f5bbdacc
TG		 1327 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1328 chip->read_buf(mtd, p, eccsize);
1da177e4 1329
f5bbdacc
TG		 1330 if (chip->ecc.prepad) {
1331 chip->read_buf(mtd, oob, chip->ecc.prepad);
1332 oob += chip->ecc.prepad;
1333 }
1da177e4 1334
f5bbdacc
TG		 1335 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1336 chip->read_buf(mtd, oob, eccbytes);
1337 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1338
3f91e94f 1339 if (stat < 0) {
f5bbdacc 1340 mtd->ecc_stats.failed++;
3f91e94f 1341 } else {
f5bbdacc 1342 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1343 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1344 }
61b03bd7 1345
f5bbdacc 1346 oob += eccbytes;
1da177e4 1347
f5bbdacc
TG		 1348 if (chip->ecc.postpad) {
1349 chip->read_buf(mtd, oob, chip->ecc.postpad);
1350 oob += chip->ecc.postpad;
61b03bd7 1351 }
f5bbdacc 1352 }
1da177e4 1353
f5bbdacc 1354 /* Calculate remaining oob bytes */
7e4178f9 1355 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1356 if (i)
1357 chip->read_buf(mtd, oob, i);
61b03bd7 1358
3f91e94f 1359 return max_bitflips;
f5bbdacc 1360}
1da177e4 1361
f5bbdacc 1362/**
7854d3f7 1363 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1364 * @chip: nand chip structure
1365 * @oob: oob destination address
1366 * @ops: oob ops structure
1367 * @len: size of oob to transfer
8593fbc6
TG		 1368 */
1369static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1370 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1371{
f8ac0414 1372 switch (ops->mode) {
8593fbc6 1373
0612b9dd
BN		 1374 case MTD_OPS_PLACE_OOB:
1375 case MTD_OPS_RAW:
8593fbc6
TG		 1376 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1377 return oob + len;
1378
0612b9dd 1379 case MTD_OPS_AUTO_OOB: {
8593fbc6 1380 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1381 uint32_t boffs = 0, roffs = ops->ooboffs;
1382 size_t bytes = 0;
8593fbc6 1383
f8ac0414 1384 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1385 /* Read request not from offset 0? */
7bc3312b
TG		 1386 if (unlikely(roffs)) {
1387 if (roffs >= free->length) {
1388 roffs -= free->length;
1389 continue;
1390 }
1391 boffs = free->offset + roffs;
1392 bytes = min_t(size_t, len,
1393 (free->length - roffs));
1394 roffs = 0;
1395 } else {
1396 bytes = min_t(size_t, len, free->length);
1397 boffs = free->offset;
1398 }
1399 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1400 oob += bytes;
1401 }
1402 return oob;
1403 }
1404 default:
1405 BUG();
1406 }
1407 return NULL;
1408}
1409
1410/**
7854d3f7 1411 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1412 * @mtd: MTD device structure
1413 * @from: offset to read from
1414 * @ops: oob ops structure
f5bbdacc
TG		 1415 *
1416 * Internal function. Called with chip held.
1417 */
8593fbc6
TG		 1418static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1419 struct mtd_oob_ops *ops)
f5bbdacc 1420{
e47f3db4 1421 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1422 struct nand_chip *chip = mtd->priv;
1423 struct mtd_ecc_stats stats;
f5bbdacc 1424 int ret = 0;
8593fbc6 1425 uint32_t readlen = ops->len;
7014568b 1426 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1427 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1428 mtd->oobavail : mtd->oobsize;
1429
8593fbc6 1430 uint8_t *bufpoi, *oob, *buf;
edbc4540 1431 unsigned int max_bitflips = 0;
1da177e4 1432
f5bbdacc 1433 stats = mtd->ecc_stats;
1da177e4 1434
f5bbdacc
TG		 1435 chipnr = (int)(from >> chip->chip_shift);
1436 chip->select_chip(mtd, chipnr);
61b03bd7 1437
f5bbdacc
TG		 1438 realpage = (int)(from >> chip->page_shift);
1439 page = realpage & chip->pagemask;
1da177e4 1440
f5bbdacc 1441 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1442
8593fbc6
TG		 1443 buf = ops->datbuf;
1444 oob = ops->oobbuf;
e47f3db4 1445 oob_required = oob ? 1 : 0;
8593fbc6 1446
f8ac0414 1447 while (1) {
f5bbdacc
TG		 1448 bytes = min(mtd->writesize - col, readlen);
1449 aligned = (bytes == mtd->writesize);
61b03bd7 1450
8b6e50c9 1451 /* Is the current page in the buffer? */
8593fbc6 1452 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1453 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1454
c00a0991 1455 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1456
edbc4540
MD		 1457 /*
1458 * Now read the page into the buffer. Absent an error,
1459 * the read methods return max bitflips per ecc step.
1460 */
0612b9dd 1461 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1462 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1463 oob_required,
1464 page);
a5ff4f10
JW		 1465 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1466 !oob)
7351d3a5
FF		 1467 ret = chip->ecc.read_subpage(mtd, chip,
1468 col, bytes, bufpoi);
956e944c 1469 else
46a8cf2d 1470 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1471 oob_required, page);
6d77b9d0
BN		 1472 if (ret < 0) {
1473 if (!aligned)
1474 /* Invalidate page cache */
1475 chip->pagebuf = -1;
1da177e4 1476 break;
6d77b9d0 1477 }
f5bbdacc 1478
edbc4540
MD		 1479 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1480
f5bbdacc
TG		 1481 /* Transfer not aligned data */
1482 if (!aligned) {
a5ff4f10 1483 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1484 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1485 (ops->mode != MTD_OPS_RAW)) {
3d459559 1486 chip->pagebuf = realpage;
edbc4540
MD		 1487 chip->pagebuf_bitflips = ret;
1488 } else {
6d77b9d0
BN		 1489 /* Invalidate page cache */
1490 chip->pagebuf = -1;
edbc4540 1491 }
4bf63fcb 1492 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1493 }
1494
8593fbc6
TG		 1495 buf += bytes;
1496
1497 if (unlikely(oob)) {
b64d39d8
ML		 1498 int toread = min(oobreadlen, max_oobsize);
1499
1500 if (toread) {
1501 oob = nand_transfer_oob(chip,
1502 oob, ops, toread);
1503 oobreadlen -= toread;
1504 }
8593fbc6 1505 }
5bc7c33c
BN		 1506
1507 if (chip->options & NAND_NEED_READRDY) {
1508 /* Apply delay or wait for ready/busy pin */
1509 if (!chip->dev_ready)
1510 udelay(chip->chip_delay);
1511 else
1512 nand_wait_ready(mtd);
1513 }
8593fbc6 1514 } else {
4bf63fcb 1515 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1516 buf += bytes;
edbc4540
MD		 1517 max_bitflips = max_t(unsigned int, max_bitflips,
1518 chip->pagebuf_bitflips);
8593fbc6 1519 }
1da177e4 1520
f5bbdacc 1521 readlen -= bytes;
61b03bd7 1522
f5bbdacc 1523 if (!readlen)
61b03bd7 1524 break;
1da177e4 1525
8b6e50c9 1526 /* For subsequent reads align to page boundary */
1da177e4
LT		 1527 col = 0;
1528 /* Increment page address */
1529 realpage++;
1530
ace4dfee 1531 page = realpage & chip->pagemask;
1da177e4
LT		 1532 /* Check, if we cross a chip boundary */
1533 if (!page) {
1534 chipnr++;
ace4dfee
TG		 1535 chip->select_chip(mtd, -1);
1536 chip->select_chip(mtd, chipnr);
1da177e4 1537 }
1da177e4 1538 }
b0bb6903 1539 chip->select_chip(mtd, -1);
1da177e4 1540
8593fbc6 1541 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1542 if (oob)
1543 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1544
3f91e94f 1545 if (ret < 0)
f5bbdacc
TG		 1546 return ret;
1547
9a1fcdfd
TG		 1548 if (mtd->ecc_stats.failed - stats.failed)
1549 return -EBADMSG;
1550
edbc4540 1551 return max_bitflips;
f5bbdacc
TG		 1552}
1553
1554/**
25985edc 1555 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1556 * @mtd: MTD device structure
1557 * @from: offset to read from
1558 * @len: number of bytes to read
1559 * @retlen: pointer to variable to store the number of read bytes
1560 * @buf: the databuffer to put data
f5bbdacc 1561 *
8b6e50c9 1562 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1563 */
1564static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1565 size_t *retlen, uint8_t *buf)
1566{
4a89ff88 1567 struct mtd_oob_ops ops;
f5bbdacc
TG		 1568 int ret;
1569
6a8214aa 1570 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 1571 ops.len = len;
1572 ops.datbuf = buf;
1573 ops.oobbuf = NULL;
11041ae6 1574 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1575 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1576 *retlen = ops.retlen;
f5bbdacc 1577 nand_release_device(mtd);
f5bbdacc 1578 return ret;
1da177e4
LT		 1579}
1580
7bc3312b 1581/**
7854d3f7 1582 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1583 * @mtd: mtd info structure
1584 * @chip: nand chip info structure
1585 * @page: page number to read
7bc3312b
TG		 1586 */
1587static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1588 int page)
7bc3312b 1589{
5c2ffb11 1590 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1591 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1592 return 0;
7bc3312b
TG		 1593}
1594
1595/**
7854d3f7 1596 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1597 * with syndromes
8b6e50c9
BN		 1598 * @mtd: mtd info structure
1599 * @chip: nand chip info structure
1600 * @page: page number to read
7bc3312b
TG		 1601 */
1602static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1603 int page)
7bc3312b
TG		 1604{
1605 uint8_t *buf = chip->oob_poi;
1606 int length = mtd->oobsize;
1607 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1608 int eccsize = chip->ecc.size;
1609 uint8_t *bufpoi = buf;
1610 int i, toread, sndrnd = 0, pos;
1611
1612 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1613 for (i = 0; i < chip->ecc.steps; i++) {
1614 if (sndrnd) {
1615 pos = eccsize + i * (eccsize + chunk);
1616 if (mtd->writesize > 512)
1617 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1618 else
1619 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1620 } else
1621 sndrnd = 1;
1622 toread = min_t(int, length, chunk);
1623 chip->read_buf(mtd, bufpoi, toread);
1624 bufpoi += toread;
1625 length -= toread;
1626 }
1627 if (length > 0)
1628 chip->read_buf(mtd, bufpoi, length);
1629
5c2ffb11 1630 return 0;
7bc3312b
TG		 1631}
1632
1633/**
7854d3f7 1634 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to write
7bc3312b
TG		 1638 */
1639static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1640 int page)
1641{
1642 int status = 0;
1643 const uint8_t *buf = chip->oob_poi;
1644 int length = mtd->oobsize;
1645
1646 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1647 chip->write_buf(mtd, buf, length);
1648 /* Send command to program the OOB data */
1649 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1650
1651 status = chip->waitfunc(mtd, chip);
1652
0d420f9d 1653 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1654}
1655
1656/**
7854d3f7 1657 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1658 * with syndrome - only for large page flash
1659 * @mtd: mtd info structure
1660 * @chip: nand chip info structure
1661 * @page: page number to write
7bc3312b
TG		 1662 */
1663static int nand_write_oob_syndrome(struct mtd_info *mtd,
1664 struct nand_chip *chip, int page)
1665{
1666 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1667 int eccsize = chip->ecc.size, length = mtd->oobsize;
1668 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1669 const uint8_t *bufpoi = chip->oob_poi;
1670
1671 /*
1672 * data-ecc-data-ecc ... ecc-oob
1673 * or
1674 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1675 */
1676 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1677 pos = steps * (eccsize + chunk);
1678 steps = 0;
1679 } else
8b0036ee 1680 pos = eccsize;
7bc3312b
TG		 1681
1682 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1683 for (i = 0; i < steps; i++) {
1684 if (sndcmd) {
1685 if (mtd->writesize <= 512) {
1686 uint32_t fill = 0xFFFFFFFF;
1687
1688 len = eccsize;
1689 while (len > 0) {
1690 int num = min_t(int, len, 4);
1691 chip->write_buf(mtd, (uint8_t *)&fill,
1692 num);
1693 len -= num;
1694 }
1695 } else {
1696 pos = eccsize + i * (eccsize + chunk);
1697 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1698 }
1699 } else
1700 sndcmd = 1;
1701 len = min_t(int, length, chunk);
1702 chip->write_buf(mtd, bufpoi, len);
1703 bufpoi += len;
1704 length -= len;
1705 }
1706 if (length > 0)
1707 chip->write_buf(mtd, bufpoi, length);
1708
1709 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1710 status = chip->waitfunc(mtd, chip);
1711
1712 return status & NAND_STATUS_FAIL ? -EIO : 0;
1713}
1714
1da177e4 1715/**
7854d3f7 1716 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1717 * @mtd: MTD device structure
1718 * @from: offset to read from
1719 * @ops: oob operations description structure
1da177e4 1720 *
8b6e50c9 1721 * NAND read out-of-band data from the spare area.
1da177e4 1722 */
8593fbc6
TG		 1723static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1724 struct mtd_oob_ops *ops)
1da177e4 1725{
c00a0991 1726 int page, realpage, chipnr;
ace4dfee 1727 struct nand_chip *chip = mtd->priv;
041e4575 1728 struct mtd_ecc_stats stats;
7014568b
VW		 1729 int readlen = ops->ooblen;
1730 int len;
7bc3312b 1731 uint8_t *buf = ops->oobbuf;
1951f2f7 1732 int ret = 0;
61b03bd7 1733
289c0522 1734 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1735 __func__, (unsigned long long)from, readlen);
1da177e4 1736
041e4575
BN		 1737 stats = mtd->ecc_stats;
1738
0612b9dd 1739 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1740 len = chip->ecc.layout->oobavail;
03736155
AH		 1741 else
1742 len = mtd->oobsize;
1743
1744 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1745 pr_debug("%s: attempt to start read outside oob\n",
1746 __func__);
03736155
AH		 1747 return -EINVAL;
1748 }
1749
1750 /* Do not allow reads past end of device */
1751 if (unlikely(from >= mtd->size ||
1752 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1753 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1754 pr_debug("%s: attempt to read beyond end of device\n",
1755 __func__);
03736155
AH		 1756 return -EINVAL;
1757 }
7014568b 1758
7314e9e7 1759 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1760 chip->select_chip(mtd, chipnr);
1da177e4 1761
7314e9e7
TG		 1762 /* Shift to get page */
1763 realpage = (int)(from >> chip->page_shift);
1764 page = realpage & chip->pagemask;
1da177e4 1765
f8ac0414 1766 while (1) {
0612b9dd 1767 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1768 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1769 else
1951f2f7
SL		 1770 ret = chip->ecc.read_oob(mtd, chip, page);
1771
1772 if (ret < 0)
1773 break;
7014568b
VW		 1774
1775 len = min(len, readlen);
1776 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1777
5bc7c33c
BN		 1778 if (chip->options & NAND_NEED_READRDY) {
1779 /* Apply delay or wait for ready/busy pin */
1780 if (!chip->dev_ready)
1781 udelay(chip->chip_delay);
1782 else
1783 nand_wait_ready(mtd);
1784 }
1785
7014568b 1786 readlen -= len;
0d420f9d
SZ		 1787 if (!readlen)
1788 break;
1789
7314e9e7
TG		 1790 /* Increment page address */
1791 realpage++;
1792
1793 page = realpage & chip->pagemask;
1794 /* Check, if we cross a chip boundary */
1795 if (!page) {
1796 chipnr++;
1797 chip->select_chip(mtd, -1);
1798 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1799 }
1800 }
b0bb6903 1801 chip->select_chip(mtd, -1);
1da177e4 1802
1951f2f7
SL		 1803 ops->oobretlen = ops->ooblen - readlen;
1804
1805 if (ret < 0)
1806 return ret;
041e4575
BN		 1807
1808 if (mtd->ecc_stats.failed - stats.failed)
1809 return -EBADMSG;
1810
1811 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1812}
1813
1814/**
8593fbc6 1815 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1816 * @mtd: MTD device structure
1817 * @from: offset to read from
1818 * @ops: oob operation description structure
1da177e4 1819 *
8b6e50c9 1820 * NAND read data and/or out-of-band data.
1da177e4 1821 */
8593fbc6
TG		 1822static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1823 struct mtd_oob_ops *ops)
1da177e4 1824{
8593fbc6
TG		 1825 int ret = -ENOTSUPP;
1826
1827 ops->retlen = 0;
1da177e4
LT		 1828
1829 /* Do not allow reads past end of device */
7014568b 1830 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1831 pr_debug("%s: attempt to read beyond end of device\n",
1832 __func__);
1da177e4
LT		 1833 return -EINVAL;
1834 }
1835
6a8214aa 1836 nand_get_device(mtd, FL_READING);
1da177e4 1837
f8ac0414 1838 switch (ops->mode) {
0612b9dd
BN		 1839 case MTD_OPS_PLACE_OOB:
1840 case MTD_OPS_AUTO_OOB:
1841 case MTD_OPS_RAW:
8593fbc6 1842 break;
1da177e4 1843
8593fbc6
TG		 1844 default:
1845 goto out;
1846 }
1da177e4 1847
8593fbc6
TG		 1848 if (!ops->datbuf)
1849 ret = nand_do_read_oob(mtd, from, ops);
1850 else
1851 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1852
7351d3a5 1853out:
8593fbc6
TG		 1854 nand_release_device(mtd);
1855 return ret;
1856}
61b03bd7 1857
1da177e4 1858
8593fbc6 1859/**
7854d3f7 1860 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1861 * @mtd: mtd info structure
1862 * @chip: nand chip info structure
1863 * @buf: data buffer
1fbb938d 1864 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1865 *
7854d3f7 1866 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1867 */
fdbad98d 1868static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1869 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1870{
1871 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1872 if (oob_required)
1873 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1874
1875 return 0;
1da177e4
LT		 1876}
1877
52ff49df 1878/**
7854d3f7 1879 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1880 * @mtd: mtd info structure
1881 * @chip: nand chip info structure
1882 * @buf: data buffer
1fbb938d 1883 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1884 *
1885 * We need a special oob layout and handling even when ECC isn't checked.
1886 */
fdbad98d 1887static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1888 struct nand_chip *chip,
1fbb938d 1889 const uint8_t *buf, int oob_required)
52ff49df
DB		 1890{
1891 int eccsize = chip->ecc.size;
1892 int eccbytes = chip->ecc.bytes;
1893 uint8_t *oob = chip->oob_poi;
1894 int steps, size;
1895
1896 for (steps = chip->ecc.steps; steps > 0; steps--) {
1897 chip->write_buf(mtd, buf, eccsize);
1898 buf += eccsize;
1899
1900 if (chip->ecc.prepad) {
1901 chip->write_buf(mtd, oob, chip->ecc.prepad);
1902 oob += chip->ecc.prepad;
1903 }
1904
1905 chip->read_buf(mtd, oob, eccbytes);
1906 oob += eccbytes;
1907
1908 if (chip->ecc.postpad) {
1909 chip->write_buf(mtd, oob, chip->ecc.postpad);
1910 oob += chip->ecc.postpad;
1911 }
1912 }
1913
1914 size = mtd->oobsize - (oob - chip->oob_poi);
1915 if (size)
1916 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 1917
1918 return 0;
52ff49df 1919}
9223a456 1920/**
7854d3f7 1921 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1922 * @mtd: mtd info structure
1923 * @chip: nand chip info structure
1924 * @buf: data buffer
1fbb938d 1925 * @oob_required: must write chip->oob_poi to OOB
9223a456 1926 */
fdbad98d 1927static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1928 const uint8_t *buf, int oob_required)
9223a456 1929{
f75e5097
TG		 1930 int i, eccsize = chip->ecc.size;
1931 int eccbytes = chip->ecc.bytes;
1932 int eccsteps = chip->ecc.steps;
4bf63fcb 1933 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1934 const uint8_t *p = buf;
8b099a39 1935 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1936
7854d3f7 1937 /* Software ECC calculation */
8593fbc6
TG		 1938 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1939 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1940
8593fbc6
TG		 1941 for (i = 0; i < chip->ecc.total; i++)
1942 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1943
fdbad98d 1944 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1945}
9223a456 1946
f75e5097 1947/**
7854d3f7 1948 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1949 * @mtd: mtd info structure
1950 * @chip: nand chip info structure
1951 * @buf: data buffer
1fbb938d 1952 * @oob_required: must write chip->oob_poi to OOB
f75e5097 1953 */
fdbad98d 1954static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1955 const uint8_t *buf, int oob_required)
f75e5097
TG		 1956{
1957 int i, eccsize = chip->ecc.size;
1958 int eccbytes = chip->ecc.bytes;
1959 int eccsteps = chip->ecc.steps;
4bf63fcb 1960 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1961 const uint8_t *p = buf;
8b099a39 1962 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1963
f75e5097
TG		 1964 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1965 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1966 chip->write_buf(mtd, p, eccsize);
f75e5097 1967 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1968 }
1969
f75e5097
TG		 1970 for (i = 0; i < chip->ecc.total; i++)
1971 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1972
1973 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1974
1975 return 0;
9223a456
TG		 1976}
1977
837a6ba4
GP		 1978
1979/**
1980 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1981 * @mtd: mtd info structure
1982 * @chip: nand chip info structure
d6a95080 1983 * @offset: column address of subpage within the page
837a6ba4 1984 * @data_len: data length
d6a95080 1985 * @buf: data buffer
837a6ba4
GP		 1986 * @oob_required: must write chip->oob_poi to OOB
1987 */
1988static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1989 struct nand_chip *chip, uint32_t offset,
d6a95080 1990 uint32_t data_len, const uint8_t *buf,
837a6ba4
GP		 1991 int oob_required)
1992{
1993 uint8_t *oob_buf = chip->oob_poi;
1994 uint8_t *ecc_calc = chip->buffers->ecccalc;
1995 int ecc_size = chip->ecc.size;
1996 int ecc_bytes = chip->ecc.bytes;
1997 int ecc_steps = chip->ecc.steps;
1998 uint32_t *eccpos = chip->ecc.layout->eccpos;
1999 uint32_t start_step = offset / ecc_size;
2000 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2001 int oob_bytes = mtd->oobsize / ecc_steps;
2002 int step, i;
2003
2004 for (step = 0; step < ecc_steps; step++) {
2005 /* configure controller for WRITE access */
2006 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2007
2008 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2009 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2010
2011 /* mask ECC of un-touched subpages by padding 0xFF */
2012 if ((step < start_step) || (step > end_step))
2013 memset(ecc_calc, 0xff, ecc_bytes);
2014 else
d6a95080 2015 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2016
2017 /* mask OOB of un-touched subpages by padding 0xFF */
2018 /* if oob_required, preserve OOB metadata of written subpage */
2019 if (!oob_required || (step < start_step) || (step > end_step))
2020 memset(oob_buf, 0xff, oob_bytes);
2021
d6a95080 2022 buf += ecc_size;
837a6ba4
GP		 2023 ecc_calc += ecc_bytes;
2024 oob_buf += oob_bytes;
2025 }
2026
2027 /* copy calculated ECC for whole page to chip->buffer->oob */
2028 /* this include masked-value(0xFF) for unwritten subpages */
2029 ecc_calc = chip->buffers->ecccalc;
2030 for (i = 0; i < chip->ecc.total; i++)
2031 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2032
2033 /* write OOB buffer to NAND device */
2034 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2035
2036 return 0;
2037}
2038
2039
61b03bd7 2040/**
7854d3f7 2041 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2042 * @mtd: mtd info structure
2043 * @chip: nand chip info structure
2044 * @buf: data buffer
1fbb938d 2045 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2046 *
8b6e50c9
BN		 2047 * The hw generator calculates the error syndrome automatically. Therefore we
2048 * need a special oob layout and handling.
f75e5097 2049 */
fdbad98d 2050static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2051 struct nand_chip *chip,
2052 const uint8_t *buf, int oob_required)
1da177e4 2053{
f75e5097
TG		 2054 int i, eccsize = chip->ecc.size;
2055 int eccbytes = chip->ecc.bytes;
2056 int eccsteps = chip->ecc.steps;
2057 const uint8_t *p = buf;
2058 uint8_t *oob = chip->oob_poi;
1da177e4 2059
f75e5097 2060 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2061
f75e5097
TG		 2062 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2063 chip->write_buf(mtd, p, eccsize);
61b03bd7 2064
f75e5097
TG		 2065 if (chip->ecc.prepad) {
2066 chip->write_buf(mtd, oob, chip->ecc.prepad);
2067 oob += chip->ecc.prepad;
2068 }
2069
2070 chip->ecc.calculate(mtd, p, oob);
2071 chip->write_buf(mtd, oob, eccbytes);
2072 oob += eccbytes;
2073
2074 if (chip->ecc.postpad) {
2075 chip->write_buf(mtd, oob, chip->ecc.postpad);
2076 oob += chip->ecc.postpad;
1da177e4 2077 }
1da177e4 2078 }
f75e5097
TG		 2079
2080 /* Calculate remaining oob bytes */
7e4178f9 2081 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2082 if (i)
2083 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2084
2085 return 0;
f75e5097
TG		 2086}
2087
2088/**
956e944c 2089 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2090 * @mtd: MTD device structure
2091 * @chip: NAND chip descriptor
837a6ba4
GP		 2092 * @offset: address offset within the page
2093 * @data_len: length of actual data to be written
8b6e50c9 2094 * @buf: the data to write
1fbb938d 2095 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2096 * @page: page number to write
2097 * @cached: cached programming
2098 * @raw: use _raw version of write_page
f75e5097
TG		 2099 */
2100static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2101 uint32_t offset, int data_len, const uint8_t *buf,
2102 int oob_required, int page, int cached, int raw)
f75e5097 2103{
837a6ba4
GP		 2104 int status, subpage;
2105
2106 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2107 chip->ecc.write_subpage)
2108 subpage = offset || (data_len < mtd->writesize);
2109 else
2110 subpage = 0;
f75e5097
TG		 2111
2112 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2113
956e944c 2114 if (unlikely(raw))
837a6ba4
GP		 2115 status = chip->ecc.write_page_raw(mtd, chip, buf,
2116 oob_required);
2117 else if (subpage)
2118 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2119 buf, oob_required);
956e944c 2120 else
fdbad98d
JW		 2121 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2122
2123 if (status < 0)
2124 return status;
f75e5097
TG		 2125
2126 /*
7854d3f7 2127 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2128 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2129 */
2130 cached = 0;
2131
3239a6cd 2132 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2133
2134 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2135 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2136 /*
2137 * See if operation failed and additional status checks are
8b6e50c9 2138 * available.
f75e5097
TG		 2139 */
2140 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2141 status = chip->errstat(mtd, chip, FL_WRITING, status,
2142 page);
2143
2144 if (status & NAND_STATUS_FAIL)
2145 return -EIO;
2146 } else {
2147 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2148 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2149 }
2150
f75e5097 2151 return 0;
1da177e4
LT		 2152}
2153
8593fbc6 2154/**
7854d3f7 2155 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2156 * @mtd: MTD device structure
8b6e50c9
BN		 2157 * @oob: oob data buffer
2158 * @len: oob data write length
2159 * @ops: oob ops structure
8593fbc6 2160 */
f722013e
TAA		 2161static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2162 struct mtd_oob_ops *ops)
8593fbc6 2163{
f722013e
TAA		 2164 struct nand_chip *chip = mtd->priv;
2165
2166 /*
2167 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2168 * data from a previous OOB read.
2169 */
2170 memset(chip->oob_poi, 0xff, mtd->oobsize);
2171
f8ac0414 2172 switch (ops->mode) {
8593fbc6 2173
0612b9dd
BN		 2174 case MTD_OPS_PLACE_OOB:
2175 case MTD_OPS_RAW:
8593fbc6
TG		 2176 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2177 return oob + len;
2178
0612b9dd 2179 case MTD_OPS_AUTO_OOB: {
8593fbc6 2180 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2181 uint32_t boffs = 0, woffs = ops->ooboffs;
2182 size_t bytes = 0;
8593fbc6 2183
f8ac0414 2184 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2185 /* Write request not from offset 0? */
7bc3312b
TG		 2186 if (unlikely(woffs)) {
2187 if (woffs >= free->length) {
2188 woffs -= free->length;
2189 continue;
2190 }
2191 boffs = free->offset + woffs;
2192 bytes = min_t(size_t, len,
2193 (free->length - woffs));
2194 woffs = 0;
2195 } else {
2196 bytes = min_t(size_t, len, free->length);
2197 boffs = free->offset;
2198 }
8b0036ee 2199 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2200 oob += bytes;
2201 }
2202 return oob;
2203 }
2204 default:
2205 BUG();
2206 }
2207 return NULL;
2208}
2209
f8ac0414 2210#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2211
2212/**
7854d3f7 2213 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2214 * @mtd: MTD device structure
2215 * @to: offset to write to
2216 * @ops: oob operations description structure
1da177e4 2217 *
8b6e50c9 2218 * NAND write with ECC.
1da177e4 2219 */
8593fbc6
TG		 2220static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2221 struct mtd_oob_ops *ops)
1da177e4 2222{
29072b96 2223 int chipnr, realpage, page, blockmask, column;
ace4dfee 2224 struct nand_chip *chip = mtd->priv;
8593fbc6 2225 uint32_t writelen = ops->len;
782ce79a
ML		 2226
2227 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2228 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2229 mtd->oobavail : mtd->oobsize;
2230
8593fbc6
TG		 2231 uint8_t *oob = ops->oobbuf;
2232 uint8_t *buf = ops->datbuf;
837a6ba4 2233 int ret;
e47f3db4 2234 int oob_required = oob ? 1 : 0;
1da177e4 2235
8593fbc6 2236 ops->retlen = 0;
29072b96
TG		 2237 if (!writelen)
2238 return 0;
1da177e4 2239
8b6e50c9 2240 /* Reject writes, which are not page aligned */
8593fbc6 2241 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2242 pr_notice("%s: attempt to write non page aligned data\n",
2243 __func__);
1da177e4
LT		 2244 return -EINVAL;
2245 }
2246
29072b96 2247 column = to & (mtd->writesize - 1);
1da177e4 2248
6a930961
TG		 2249 chipnr = (int)(to >> chip->chip_shift);
2250 chip->select_chip(mtd, chipnr);
2251
1da177e4 2252 /* Check, if it is write protected */
b0bb6903
HS		 2253 if (nand_check_wp(mtd)) {
2254 ret = -EIO;
2255 goto err_out;
2256 }
1da177e4 2257
f75e5097
TG		 2258 realpage = (int)(to >> chip->page_shift);
2259 page = realpage & chip->pagemask;
2260 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2261
2262 /* Invalidate the page cache, when we write to the cached page */
2263 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2264 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2265 chip->pagebuf = -1;
61b03bd7 2266
782ce79a 2267 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2268 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2269 ret = -EINVAL;
2270 goto err_out;
2271 }
782ce79a 2272
f8ac0414 2273 while (1) {
29072b96 2274 int bytes = mtd->writesize;
f75e5097 2275 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2276 uint8_t *wbuf = buf;
2277
8b6e50c9 2278 /* Partial page write? */
29072b96
TG		 2279 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2280 cached = 0;
2281 bytes = min_t(int, bytes - column, (int) writelen);
2282 chip->pagebuf = -1;
2283 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2284 memcpy(&chip->buffers->databuf[column], buf, bytes);
2285 wbuf = chip->buffers->databuf;
2286 }
1da177e4 2287
782ce79a
ML		 2288 if (unlikely(oob)) {
2289 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2290 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2291 oobwritelen -= len;
f722013e
TAA		 2292 } else {
2293 /* We still need to erase leftover OOB data */
2294 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2295 }
837a6ba4
GP		 2296 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2297 oob_required, page, cached,
2298 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2299 if (ret)
2300 break;
2301
2302 writelen -= bytes;
2303 if (!writelen)
2304 break;
2305
29072b96 2306 column = 0;
f75e5097
TG		 2307 buf += bytes;
2308 realpage++;
2309
2310 page = realpage & chip->pagemask;
2311 /* Check, if we cross a chip boundary */
2312 if (!page) {
2313 chipnr++;
2314 chip->select_chip(mtd, -1);
2315 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2316 }
2317 }
8593fbc6 2318
8593fbc6 2319 ops->retlen = ops->len - writelen;
7014568b
VW		 2320 if (unlikely(oob))
2321 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2322
2323err_out:
2324 chip->select_chip(mtd, -1);
1da177e4
LT		 2325 return ret;
2326}
2327
2af7c653
SK		 2328/**
2329 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2330 * @mtd: MTD device structure
2331 * @to: offset to write to
2332 * @len: number of bytes to write
2333 * @retlen: pointer to variable to store the number of written bytes
2334 * @buf: the data to write
2af7c653
SK		 2335 *
2336 * NAND write with ECC. Used when performing writes in interrupt context, this
2337 * may for example be called by mtdoops when writing an oops while in panic.
2338 */
2339static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2340 size_t *retlen, const uint8_t *buf)
2341{
2342 struct nand_chip *chip = mtd->priv;
4a89ff88 2343 struct mtd_oob_ops ops;
2af7c653
SK		 2344 int ret;
2345
8b6e50c9 2346 /* Wait for the device to get ready */
2af7c653
SK		 2347 panic_nand_wait(mtd, chip, 400);
2348
8b6e50c9 2349 /* Grab the device */
2af7c653
SK		 2350 panic_nand_get_device(chip, mtd, FL_WRITING);
2351
4a89ff88
BN		 2352 ops.len = len;
2353 ops.datbuf = (uint8_t *)buf;
2354 ops.oobbuf = NULL;
11041ae6 2355 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2356
4a89ff88 2357 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2358
4a89ff88 2359 *retlen = ops.retlen;
2af7c653
SK		 2360 return ret;
2361}
2362
f75e5097 2363/**
8593fbc6 2364 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2365 * @mtd: MTD device structure
2366 * @to: offset to write to
2367 * @len: number of bytes to write
2368 * @retlen: pointer to variable to store the number of written bytes
2369 * @buf: the data to write
f75e5097 2370 *
8b6e50c9 2371 * NAND write with ECC.
f75e5097 2372 */
8593fbc6
TG		 2373static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2374 size_t *retlen, const uint8_t *buf)
f75e5097 2375{
4a89ff88 2376 struct mtd_oob_ops ops;
f75e5097
TG		 2377 int ret;
2378
6a8214aa 2379 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 2380 ops.len = len;
2381 ops.datbuf = (uint8_t *)buf;
2382 ops.oobbuf = NULL;
11041ae6 2383 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2384 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2385 *retlen = ops.retlen;
f75e5097 2386 nand_release_device(mtd);
8593fbc6 2387 return ret;
f75e5097 2388}
7314e9e7 2389
1da177e4 2390/**
8593fbc6 2391 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2392 * @mtd: MTD device structure
2393 * @to: offset to write to
2394 * @ops: oob operation description structure
1da177e4 2395 *
8b6e50c9 2396 * NAND write out-of-band.
1da177e4 2397 */
8593fbc6
TG		 2398static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2399 struct mtd_oob_ops *ops)
1da177e4 2400{
03736155 2401 int chipnr, page, status, len;
ace4dfee 2402 struct nand_chip *chip = mtd->priv;
1da177e4 2403
289c0522 2404 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2405 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2406
0612b9dd 2407 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2408 len = chip->ecc.layout->oobavail;
2409 else
2410 len = mtd->oobsize;
2411
1da177e4 2412 /* Do not allow write past end of page */
03736155 2413 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2414 pr_debug("%s: attempt to write past end of page\n",
2415 __func__);
1da177e4
LT		 2416 return -EINVAL;
2417 }
2418
03736155 2419 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2420 pr_debug("%s: attempt to start write outside oob\n",
2421 __func__);
03736155
AH		 2422 return -EINVAL;
2423 }
2424
775adc3d 2425 /* Do not allow write past end of device */
03736155
AH		 2426 if (unlikely(to >= mtd->size ||
2427 ops->ooboffs + ops->ooblen >
2428 ((mtd->size >> chip->page_shift) -
2429 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2430 pr_debug("%s: attempt to write beyond end of device\n",
2431 __func__);
03736155
AH		 2432 return -EINVAL;
2433 }
2434
7314e9e7 2435 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2436 chip->select_chip(mtd, chipnr);
1da177e4 2437
7314e9e7
TG		 2438 /* Shift to get page */
2439 page = (int)(to >> chip->page_shift);
2440
2441 /*
2442 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2443 * of my DiskOnChip 2000 test units) will clear the whole data page too
2444 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2445 * it in the doc2000 driver in August 1999. dwmw2.
2446 */
ace4dfee 2447 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2448
2449 /* Check, if it is write protected */
b0bb6903
HS		 2450 if (nand_check_wp(mtd)) {
2451 chip->select_chip(mtd, -1);
8593fbc6 2452 return -EROFS;
b0bb6903 2453 }
61b03bd7 2454
1da177e4 2455 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2456 if (page == chip->pagebuf)
2457 chip->pagebuf = -1;
1da177e4 2458
f722013e 2459 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2460
0612b9dd 2461 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2462 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2463 else
2464 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2465
b0bb6903
HS		 2466 chip->select_chip(mtd, -1);
2467
7bc3312b
TG		 2468 if (status)
2469 return status;
1da177e4 2470
7014568b 2471 ops->oobretlen = ops->ooblen;
1da177e4 2472
7bc3312b 2473 return 0;
8593fbc6
TG		 2474}
2475
2476/**
2477 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2478 * @mtd: MTD device structure
2479 * @to: offset to write to
2480 * @ops: oob operation description structure
8593fbc6
TG		 2481 */
2482static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2483 struct mtd_oob_ops *ops)
2484{
8593fbc6
TG		 2485 int ret = -ENOTSUPP;
2486
2487 ops->retlen = 0;
2488
2489 /* Do not allow writes past end of device */
7014568b 2490 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2491 pr_debug("%s: attempt to write beyond end of device\n",
2492 __func__);
8593fbc6
TG		 2493 return -EINVAL;
2494 }
2495
6a8214aa 2496 nand_get_device(mtd, FL_WRITING);
8593fbc6 2497
f8ac0414 2498 switch (ops->mode) {
0612b9dd
BN		 2499 case MTD_OPS_PLACE_OOB:
2500 case MTD_OPS_AUTO_OOB:
2501 case MTD_OPS_RAW:
8593fbc6
TG		 2502 break;
2503
2504 default:
2505 goto out;
2506 }
2507
2508 if (!ops->datbuf)
2509 ret = nand_do_write_oob(mtd, to, ops);
2510 else
2511 ret = nand_do_write_ops(mtd, to, ops);
2512
7351d3a5 2513out:
1da177e4 2514 nand_release_device(mtd);
1da177e4
LT		 2515 return ret;
2516}
2517
1da177e4 2518/**
7854d3f7 2519 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2520 * @mtd: MTD device structure
2521 * @page: the page address of the block which will be erased
1da177e4 2522 *
8b6e50c9 2523 * Standard erase command for NAND chips.
1da177e4 2524 */
e0c7d767 2525static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2526{
ace4dfee 2527 struct nand_chip *chip = mtd->priv;
1da177e4 2528 /* Send commands to erase a block */
ace4dfee
TG		 2529 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2530 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2531}
2532
1da177e4
LT		 2533/**
2534 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2535 * @mtd: MTD device structure
2536 * @instr: erase instruction
1da177e4 2537 *
8b6e50c9 2538 * Erase one ore more blocks.
1da177e4 2539 */
e0c7d767 2540static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2541{
e0c7d767 2542 return nand_erase_nand(mtd, instr, 0);
1da177e4 2543}
61b03bd7 2544
1da177e4 2545/**
7854d3f7 2546 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2547 * @mtd: MTD device structure
2548 * @instr: erase instruction
2549 * @allowbbt: allow erasing the bbt area
1da177e4 2550 *
8b6e50c9 2551 * Erase one ore more blocks.
1da177e4 2552 */
ace4dfee
TG		 2553int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2554 int allowbbt)
1da177e4 2555{
69423d99 2556 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2557 struct nand_chip *chip = mtd->priv;
69423d99 2558 loff_t len;
1da177e4 2559
289c0522
BN		 2560 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2561 __func__, (unsigned long long)instr->addr,
2562 (unsigned long long)instr->len);
1da177e4 2563
6fe5a6ac 2564 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2565 return -EINVAL;
1da177e4 2566
1da177e4 2567 /* Grab the lock and see if the device is available */
6a8214aa 2568 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2569
2570 /* Shift to get first page */
ace4dfee
TG		 2571 page = (int)(instr->addr >> chip->page_shift);
2572 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2573
2574 /* Calculate pages in each block */
ace4dfee 2575 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2576
2577 /* Select the NAND device */
ace4dfee 2578 chip->select_chip(mtd, chipnr);
1da177e4 2579
1da177e4
LT		 2580 /* Check, if it is write protected */
2581 if (nand_check_wp(mtd)) {
289c0522
BN		 2582 pr_debug("%s: device is write protected!\n",
2583 __func__);
1da177e4
LT		 2584 instr->state = MTD_ERASE_FAILED;
2585 goto erase_exit;
2586 }
2587
2588 /* Loop through the pages */
2589 len = instr->len;
2590
2591 instr->state = MTD_ERASING;
2592
2593 while (len) {
12183a20 2594 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2595 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2596 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2597 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2598 __func__, page);
1da177e4
LT		 2599 instr->state = MTD_ERASE_FAILED;
2600 goto erase_exit;
2601 }
61b03bd7 2602
ace4dfee
TG		 2603 /*
2604 * Invalidate the page cache, if we erase the block which
8b6e50c9 2605 * contains the current cached page.
ace4dfee
TG		 2606 */
2607 if (page <= chip->pagebuf && chip->pagebuf <
2608 (page + pages_per_block))
2609 chip->pagebuf = -1;
1da177e4 2610
ace4dfee 2611 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2612
7bc3312b 2613 status = chip->waitfunc(mtd, chip);
1da177e4 2614
ace4dfee
TG		 2615 /*
2616 * See if operation failed and additional status checks are
2617 * available
2618 */
2619 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2620 status = chip->errstat(mtd, chip, FL_ERASING,
2621 status, page);
068e3c0a 2622
1da177e4 2623 /* See if block erase succeeded */
a4ab4c5d 2624 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2625 pr_debug("%s: failed erase, page 0x%08x\n",
2626 __func__, page);
1da177e4 2627 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2628 instr->fail_addr =
2629 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2630 goto erase_exit;
2631 }
30f464b7 2632
1da177e4 2633 /* Increment page address and decrement length */
daae74ca 2634 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 2635 page += pages_per_block;
2636
2637 /* Check, if we cross a chip boundary */
ace4dfee 2638 if (len && !(page & chip->pagemask)) {
1da177e4 2639 chipnr++;
ace4dfee
TG		 2640 chip->select_chip(mtd, -1);
2641 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2642 }
2643 }
2644 instr->state = MTD_ERASE_DONE;
2645
7351d3a5 2646erase_exit:
1da177e4
LT		 2647
2648 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2649
2650 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2651 chip->select_chip(mtd, -1);
1da177e4
LT		 2652 nand_release_device(mtd);
2653
49defc01
DW		 2654 /* Do call back function */
2655 if (!ret)
2656 mtd_erase_callback(instr);
2657
1da177e4
LT		 2658 /* Return more or less happy */
2659 return ret;
2660}
2661
2662/**
2663 * nand_sync - [MTD Interface] sync
8b6e50c9 2664 * @mtd: MTD device structure
1da177e4 2665 *
8b6e50c9 2666 * Sync is actually a wait for chip ready function.
1da177e4 2667 */
e0c7d767 2668static void nand_sync(struct mtd_info *mtd)
1da177e4 2669{
289c0522 2670 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2671
2672 /* Grab the lock and see if the device is available */
6a8214aa 2673 nand_get_device(mtd, FL_SYNCING);
1da177e4 2674 /* Release it and go back */
e0c7d767 2675 nand_release_device(mtd);
1da177e4
LT		 2676}
2677
1da177e4 2678/**
ace4dfee 2679 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2680 * @mtd: MTD device structure
2681 * @offs: offset relative to mtd start
1da177e4 2682 */
ace4dfee 2683static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2684{
ace4dfee 2685 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2686}
2687
2688/**
ace4dfee 2689 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2690 * @mtd: MTD device structure
2691 * @ofs: offset relative to mtd start
1da177e4 2692 */
e0c7d767 2693static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2694{
1da177e4
LT		 2695 int ret;
2696
f8ac0414
FF		 2697 ret = nand_block_isbad(mtd, ofs);
2698 if (ret) {
8b6e50c9 2699 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2700 if (ret > 0)
2701 return 0;
e0c7d767
DW		 2702 return ret;
2703 }
1da177e4 2704
5a0edb25 2705 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 2706}
2707
7db03ecc
HS		 2708/**
2709 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2710 * @mtd: MTD device structure
2711 * @chip: nand chip info structure
2712 * @addr: feature address.
2713 * @subfeature_param: the subfeature parameters, a four bytes array.
2714 */
2715static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2716 int addr, uint8_t *subfeature_param)
2717{
2718 int status;
2719
d914c932
DM		 2720 if (!chip->onfi_version ||
2721 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2722 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2723 return -EINVAL;
2724
2725 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2726 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2727 status = chip->waitfunc(mtd, chip);
2728 if (status & NAND_STATUS_FAIL)
2729 return -EIO;
2730 return 0;
2731}
2732
2733/**
2734 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2735 * @mtd: MTD device structure
2736 * @chip: nand chip info structure
2737 * @addr: feature address.
2738 * @subfeature_param: the subfeature parameters, a four bytes array.
2739 */
2740static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2741 int addr, uint8_t *subfeature_param)
2742{
d914c932
DM		 2743 if (!chip->onfi_version ||
2744 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2745 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 2746 return -EINVAL;
2747
2748 /* clear the sub feature parameters */
2749 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2750
2751 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2752 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2753 return 0;
2754}
2755
962034f4
VW		 2756/**
2757 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2758 * @mtd: MTD device structure
962034f4
VW		 2759 */
2760static int nand_suspend(struct mtd_info *mtd)
2761{
6a8214aa 2762 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2763}
2764
2765/**
2766 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2767 * @mtd: MTD device structure
962034f4
VW		 2768 */
2769static void nand_resume(struct mtd_info *mtd)
2770{
ace4dfee 2771 struct nand_chip *chip = mtd->priv;
962034f4 2772
ace4dfee 2773 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2774 nand_release_device(mtd);
2775 else
d0370219
BN		 2776 pr_err("%s called for a chip which is not in suspended state\n",
2777 __func__);
962034f4
VW		 2778}
2779
8b6e50c9 2780/* Set default functions */
ace4dfee 2781static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2782{
1da177e4 2783 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2784 if (!chip->chip_delay)
2785 chip->chip_delay = 20;
1da177e4
LT		 2786
2787 /* check, if a user supplied command function given */
ace4dfee
TG		 2788 if (chip->cmdfunc == NULL)
2789 chip->cmdfunc = nand_command;
1da177e4
LT		 2790
2791 /* check, if a user supplied wait function given */
ace4dfee
TG		 2792 if (chip->waitfunc == NULL)
2793 chip->waitfunc = nand_wait;
2794
2795 if (!chip->select_chip)
2796 chip->select_chip = nand_select_chip;
68e80780 2797
4204cccd
HS		 2798 /* set for ONFI nand */
2799 if (!chip->onfi_set_features)
2800 chip->onfi_set_features = nand_onfi_set_features;
2801 if (!chip->onfi_get_features)
2802 chip->onfi_get_features = nand_onfi_get_features;
2803
68e80780
BN		 2804 /* If called twice, pointers that depend on busw may need to be reset */
2805 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 2806 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2807 if (!chip->read_word)
2808 chip->read_word = nand_read_word;
2809 if (!chip->block_bad)
2810 chip->block_bad = nand_block_bad;
2811 if (!chip->block_markbad)
2812 chip->block_markbad = nand_default_block_markbad;
68e80780 2813 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 2814 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
68e80780 2815 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 2816 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2817 if (!chip->scan_bbt)
2818 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2819
2820 if (!chip->controller) {
2821 chip->controller = &chip->hwcontrol;
2822 spin_lock_init(&chip->controller->lock);
2823 init_waitqueue_head(&chip->controller->wq);
2824 }
2825
7aa65bfd
TG		 2826}
2827
8b6e50c9 2828/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2829static void sanitize_string(uint8_t *s, size_t len)
2830{
2831 ssize_t i;
2832
8b6e50c9 2833 /* Null terminate */
d1e1f4e4
FF		 2834 s[len - 1] = 0;
2835
8b6e50c9 2836 /* Remove non printable chars */
d1e1f4e4
FF		 2837 for (i = 0; i < len - 1; i++) {
2838 if (s[i] < ' ' || s[i] > 127)
2839 s[i] = '?';
2840 }
2841
8b6e50c9 2842 /* Remove trailing spaces */
d1e1f4e4
FF		 2843 strim(s);
2844}
2845
2846static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2847{
2848 int i;
2849 while (len--) {
2850 crc ^= *p++ << 8;
2851 for (i = 0; i < 8; i++)
2852 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2853 }
2854
2855 return crc;
2856}
2857
6dcbe0cd
HS		 2858/* Parse the Extended Parameter Page. */
2859static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
2860 struct nand_chip *chip, struct nand_onfi_params *p)
2861{
2862 struct onfi_ext_param_page *ep;
2863 struct onfi_ext_section *s;
2864 struct onfi_ext_ecc_info *ecc;
2865 uint8_t *cursor;
2866 int ret = -EINVAL;
2867 int len;
2868 int i;
2869
2870 len = le16_to_cpu(p->ext_param_page_length) * 16;
2871 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 2872 if (!ep)
2873 return -ENOMEM;
6dcbe0cd
HS		 2874
2875 /* Send our own NAND_CMD_PARAM. */
2876 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2877
2878 /* Use the Change Read Column command to skip the ONFI param pages. */
2879 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
2880 sizeof(*p) * p->num_of_param_pages , -1);
2881
2882 /* Read out the Extended Parameter Page. */
2883 chip->read_buf(mtd, (uint8_t *)ep, len);
2884 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
2885 != le16_to_cpu(ep->crc))) {
2886 pr_debug("fail in the CRC.\n");
2887 goto ext_out;
2888 }
2889
2890 /*
2891 * Check the signature.
2892 * Do not strictly follow the ONFI spec, maybe changed in future.
2893 */
2894 if (strncmp(ep->sig, "EPPS", 4)) {
2895 pr_debug("The signature is invalid.\n");
2896 goto ext_out;
2897 }
2898
2899 /* find the ECC section. */
2900 cursor = (uint8_t *)(ep + 1);
2901 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
2902 s = ep->sections + i;
2903 if (s->type == ONFI_SECTION_TYPE_2)
2904 break;
2905 cursor += s->length * 16;
2906 }
2907 if (i == ONFI_EXT_SECTION_MAX) {
2908 pr_debug("We can not find the ECC section.\n");
2909 goto ext_out;
2910 }
2911
2912 /* get the info we want. */
2913 ecc = (struct onfi_ext_ecc_info *)cursor;
2914
4ae7d228
BN		 2915 if (!ecc->codeword_size) {
2916 pr_debug("Invalid codeword size\n");
2917 goto ext_out;
6dcbe0cd
HS		 2918 }
2919
4ae7d228
BN		 2920 chip->ecc_strength_ds = ecc->ecc_bits;
2921 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 2922 ret = 0;
6dcbe0cd
HS		 2923
2924ext_out:
2925 kfree(ep);
2926 return ret;
2927}
2928
6fb277ba 2929/*
8b6e50c9 2930 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2931 */
2932static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2933 int *busw)
6fb277ba
FF		 2934{
2935 struct nand_onfi_params *p = &chip->onfi_params;
2936 int i;
2937 int val;
2938
7854d3f7 2939 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2940 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2941 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2942 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2943 return 0;
2944
c7f23a70
BN		 2945 /*
2946 * ONFI must be probed in 8-bit mode or with NAND_BUSWIDTH_AUTO, not
2947 * with NAND_BUSWIDTH_16
2948 */
2949 if (chip->options & NAND_BUSWIDTH_16) {
2950 pr_err("ONFI cannot be probed in 16-bit mode; aborting\n");
2951 return 0;
2952 }
2953
6fb277ba
FF		 2954 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2955 for (i = 0; i < 3; i++) {
2956 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2957 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2958 le16_to_cpu(p->crc)) {
6fb277ba
FF		 2959 break;
2960 }
2961 }
2962
c7f23a70
BN		 2963 if (i == 3) {
2964 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 2965 return 0;
c7f23a70 2966 }
6fb277ba 2967
8b6e50c9 2968 /* Check version */
6fb277ba 2969 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2970 if (val & (1 << 5))
2971 chip->onfi_version = 23;
2972 else if (val & (1 << 4))
6fb277ba
FF		 2973 chip->onfi_version = 22;
2974 else if (val & (1 << 3))
2975 chip->onfi_version = 21;
2976 else if (val & (1 << 2))
2977 chip->onfi_version = 20;
b7b1a29d 2978 else if (val & (1 << 1))
6fb277ba 2979 chip->onfi_version = 10;
b7b1a29d
BN		 2980
2981 if (!chip->onfi_version) {
d0370219 2982 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2983 return 0;
2984 }
6fb277ba
FF		 2985
2986 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2987 sanitize_string(p->model, sizeof(p->model));
2988 if (!mtd->name)
2989 mtd->name = p->model;
4355b70c 2990
6fb277ba 2991 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 2992
2993 /*
2994 * pages_per_block and blocks_per_lun may not be a power-of-2 size
2995 * (don't ask me who thought of this...). MTD assumes that these
2996 * dimensions will be power-of-2, so just truncate the remaining area.
2997 */
2998 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
2999 mtd->erasesize *= mtd->writesize;
3000
6fb277ba 3001 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3002
3003 /* See erasesize comment */
3004 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3005 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3006 chip->bits_per_cell = p->bits_per_cell;
e2985fc1
HS		 3007
3008 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
08c248fb 3009 *busw = NAND_BUSWIDTH_16;
e2985fc1
HS		 3010 else
3011 *busw = 0;
6fb277ba 3012
10c86bab
HS		 3013 if (p->ecc_bits != 0xff) {
3014 chip->ecc_strength_ds = p->ecc_bits;
3015 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3016 } else if (chip->onfi_version >= 21 &&
3017 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3018
3019 /*
3020 * The nand_flash_detect_ext_param_page() uses the
3021 * Change Read Column command which maybe not supported
3022 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3023 * now. We do not replace user supplied command function.
3024 */
3025 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3026 chip->cmdfunc = nand_command_lp;
3027
3028 /* The Extended Parameter Page is supported since ONFI 2.1. */
3029 if (nand_flash_detect_ext_param_page(mtd, chip, p))
c7f23a70
BN		 3030 pr_warn("Failed to detect ONFI extended param page\n");
3031 } else {
3032 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3033 }
3034
6fb277ba
FF		 3035 return 1;
3036}
3037
e3b88bd6
BN		 3038/*
3039 * nand_id_has_period - Check if an ID string has a given wraparound period
3040 * @id_data: the ID string
3041 * @arrlen: the length of the @id_data array
3042 * @period: the period of repitition
3043 *
3044 * Check if an ID string is repeated within a given sequence of bytes at
3045 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3046 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3047 * if the repetition has a period of @period; otherwise, returns zero.
3048 */
3049static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3050{
3051 int i, j;
3052 for (i = 0; i < period; i++)
3053 for (j = i + period; j < arrlen; j += period)
3054 if (id_data[i] != id_data[j])
3055 return 0;
3056 return 1;
3057}
3058
3059/*
3060 * nand_id_len - Get the length of an ID string returned by CMD_READID
3061 * @id_data: the ID string
3062 * @arrlen: the length of the @id_data array
3063
3064 * Returns the length of the ID string, according to known wraparound/trailing
3065 * zero patterns. If no pattern exists, returns the length of the array.
3066 */
3067static int nand_id_len(u8 *id_data, int arrlen)
3068{
3069 int last_nonzero, period;
3070
3071 /* Find last non-zero byte */
3072 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3073 if (id_data[last_nonzero])
3074 break;
3075
3076 /* All zeros */
3077 if (last_nonzero < 0)
3078 return 0;
3079
3080 /* Calculate wraparound period */
3081 for (period = 1; period < arrlen; period++)
3082 if (nand_id_has_period(id_data, arrlen, period))
3083 break;
3084
3085 /* There's a repeated pattern */
3086 if (period < arrlen)
3087 return period;
3088
3089 /* There are trailing zeros */
3090 if (last_nonzero < arrlen - 1)
3091 return last_nonzero + 1;
3092
3093 /* No pattern detected */
3094 return arrlen;
3095}
3096
7db906b7
HS		 3097/* Extract the bits of per cell from the 3rd byte of the extended ID */
3098static int nand_get_bits_per_cell(u8 cellinfo)
3099{
3100 int bits;
3101
3102 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3103 bits >>= NAND_CI_CELLTYPE_SHIFT;
3104 return bits + 1;
3105}
3106
fc09bbc0
BN		 3107/*
3108 * Many new NAND share similar device ID codes, which represent the size of the
3109 * chip. The rest of the parameters must be decoded according to generic or
3110 * manufacturer-specific "extended ID" decoding patterns.
3111 */
3112static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3113 u8 id_data[8], int *busw)
3114{
e3b88bd6 3115 int extid, id_len;
fc09bbc0 3116 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3117 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3118 /* The 4th id byte is the important one */
3119 extid = id_data[3];
3120
e3b88bd6
BN		 3121 id_len = nand_id_len(id_data, 8);
3122
fc09bbc0
BN		 3123 /*
3124 * Field definitions are in the following datasheets:
3125 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3126 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3127 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3128 *
af451af4
BN		 3129 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3130 * ID to decide what to do.
fc09bbc0 3131 */
af451af4 3132 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
1d0ed69d 3133 !nand_is_slc(chip) && id_data[5] != 0x00) {
fc09bbc0
BN		 3134 /* Calc pagesize */
3135 mtd->writesize = 2048 << (extid & 0x03);
3136 extid >>= 2;
3137 /* Calc oobsize */
e2d3a35e 3138 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3139 case 1:
3140 mtd->oobsize = 128;
3141 break;
3142 case 2:
3143 mtd->oobsize = 218;
3144 break;
3145 case 3:
3146 mtd->oobsize = 400;
3147 break;
e2d3a35e 3148 case 4:
fc09bbc0
BN		 3149 mtd->oobsize = 436;
3150 break;
e2d3a35e
BN		 3151 case 5:
3152 mtd->oobsize = 512;
3153 break;
3154 case 6:
3155 default: /* Other cases are "reserved" (unknown) */
3156 mtd->oobsize = 640;
3157 break;
fc09bbc0
BN		 3158 }
3159 extid >>= 2;
3160 /* Calc blocksize */
3161 mtd->erasesize = (128 * 1024) <<
3162 (((extid >> 1) & 0x04) | (extid & 0x03));
3163 *busw = 0;
73ca392f 3164 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
1d0ed69d 3165 !nand_is_slc(chip)) {
73ca392f
BN		 3166 unsigned int tmp;
3167
3168 /* Calc pagesize */
3169 mtd->writesize = 2048 << (extid & 0x03);
3170 extid >>= 2;
3171 /* Calc oobsize */
3172 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3173 case 0:
3174 mtd->oobsize = 128;
3175 break;
3176 case 1:
3177 mtd->oobsize = 224;
3178 break;
3179 case 2:
3180 mtd->oobsize = 448;
3181 break;
3182 case 3:
3183 mtd->oobsize = 64;
3184 break;
3185 case 4:
3186 mtd->oobsize = 32;
3187 break;
3188 case 5:
3189 mtd->oobsize = 16;
3190 break;
3191 default:
3192 mtd->oobsize = 640;
3193 break;
3194 }
3195 extid >>= 2;
3196 /* Calc blocksize */
3197 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3198 if (tmp < 0x03)
3199 mtd->erasesize = (128 * 1024) << tmp;
3200 else if (tmp == 0x03)
3201 mtd->erasesize = 768 * 1024;
3202 else
3203 mtd->erasesize = (64 * 1024) << tmp;
3204 *busw = 0;
fc09bbc0
BN		 3205 } else {
3206 /* Calc pagesize */
3207 mtd->writesize = 1024 << (extid & 0x03);
3208 extid >>= 2;
3209 /* Calc oobsize */
3210 mtd->oobsize = (8 << (extid & 0x01)) *
3211 (mtd->writesize >> 9);
3212 extid >>= 2;
3213 /* Calc blocksize. Blocksize is multiples of 64KiB */
3214 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3215 extid >>= 2;
3216 /* Get buswidth information */
3217 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
60c67382
BN		 3218
3219 /*
3220 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3221 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3222 * follows:
3223 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3224 * 110b -> 24nm
3225 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3226 */
3227 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
1d0ed69d 3228 nand_is_slc(chip) &&
60c67382
BN		 3229 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3230 !(id_data[4] & 0x80) /* !BENAND */) {
3231 mtd->oobsize = 32 * mtd->writesize >> 9;
3232 }
3233
fc09bbc0
BN		 3234 }
3235}
3236
f23a481c
BN		 3237/*
3238 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3239 * decodes a matching ID table entry and assigns the MTD size parameters for
3240 * the chip.
3241 */
3242static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3243 struct nand_flash_dev *type, u8 id_data[8],
3244 int *busw)
3245{
3246 int maf_id = id_data[0];
3247
3248 mtd->erasesize = type->erasesize;
3249 mtd->writesize = type->pagesize;
3250 mtd->oobsize = mtd->writesize / 32;
3251 *busw = type->options & NAND_BUSWIDTH_16;
3252
1c195e90
HS		 3253 /* All legacy ID NAND are small-page, SLC */
3254 chip->bits_per_cell = 1;
3255
f23a481c
BN		 3256 /*
3257 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3258 * some Spansion chips have erasesize that conflicts with size
3259 * listed in nand_ids table.
3260 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3261 */
3262 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3263 && id_data[6] == 0x00 && id_data[7] == 0x00
3264 && mtd->writesize == 512) {
3265 mtd->erasesize = 128 * 1024;
3266 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3267 }
3268}
3269
7e74c2d7
BN		 3270/*
3271 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3272 * heuristic patterns using various detected parameters (e.g., manufacturer,
3273 * page size, cell-type information).
3274 */
3275static void nand_decode_bbm_options(struct mtd_info *mtd,
3276 struct nand_chip *chip, u8 id_data[8])
3277{
3278 int maf_id = id_data[0];
3279
3280 /* Set the bad block position */
3281 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3282 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3283 else
3284 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3285
3286 /*
3287 * Bad block marker is stored in the last page of each block on Samsung
3288 * and Hynix MLC devices; stored in first two pages of each block on
3289 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3290 * AMD/Spansion, and Macronix. All others scan only the first page.
3291 */
1d0ed69d 3292 if (!nand_is_slc(chip) &&
7e74c2d7
BN		 3293 (maf_id == NAND_MFR_SAMSUNG ||
3294 maf_id == NAND_MFR_HYNIX))
3295 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
1d0ed69d 3296 else if ((nand_is_slc(chip) &&
7e74c2d7
BN		 3297 (maf_id == NAND_MFR_SAMSUNG ||
3298 maf_id == NAND_MFR_HYNIX ||
3299 maf_id == NAND_MFR_TOSHIBA ||
3300 maf_id == NAND_MFR_AMD ||
3301 maf_id == NAND_MFR_MACRONIX)) ||
3302 (mtd->writesize == 2048 &&
3303 maf_id == NAND_MFR_MICRON))
3304 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3305}
3306
ec6e87e3
HS		 3307static inline bool is_full_id_nand(struct nand_flash_dev *type)
3308{
3309 return type->id_len;
3310}
3311
3312static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3313 struct nand_flash_dev *type, u8 *id_data, int *busw)
3314{
3315 if (!strncmp(type->id, id_data, type->id_len)) {
3316 mtd->writesize = type->pagesize;
3317 mtd->erasesize = type->erasesize;
3318 mtd->oobsize = type->oobsize;
3319
7db906b7 3320 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3321 chip->chipsize = (uint64_t)type->chipsize << 20;
3322 chip->options |= type->options;
57219342
HS		 3323 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3324 chip->ecc_step_ds = NAND_ECC_STEP(type);
ec6e87e3
HS		 3325
3326 *busw = type->options & NAND_BUSWIDTH_16;
3327
3328 return true;
3329 }
3330 return false;
3331}
3332
7aa65bfd 3333/*
8b6e50c9 3334 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3335 */
3336static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3337 struct nand_chip *chip,
7351d3a5
FF		 3338 int busw,
3339 int *maf_id, int *dev_id,
5e81e88a 3340 struct nand_flash_dev *type)
7aa65bfd 3341{
d1e1f4e4 3342 int i, maf_idx;
426c457a 3343 u8 id_data[8];
1da177e4
LT		 3344
3345 /* Select the device */
ace4dfee 3346 chip->select_chip(mtd, 0);
1da177e4 3347
ef89a880
KB		 3348 /*
3349 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3350 * after power-up.
ef89a880
KB		 3351 */
3352 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3353
1da177e4 3354 /* Send the command for reading device ID */
ace4dfee 3355 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3356
3357 /* Read manufacturer and device IDs */
ace4dfee 3358 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3359 *dev_id = chip->read_byte(mtd);
1da177e4 3360
8b6e50c9
BN		 3361 /*
3362 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3363 * interface concerns can cause random data which looks like a
3364 * possibly credible NAND flash to appear. If the two results do
3365 * not match, ignore the device completely.
3366 */
3367
3368 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3369
4aef9b78
BN		 3370 /* Read entire ID string */
3371 for (i = 0; i < 8; i++)
426c457a 3372 id_data[i] = chip->read_byte(mtd);
ed8165c7 3373
d1e1f4e4 3374 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 3375 pr_info("%s: second ID read did not match "
d0370219
BN		 3376 "%02x,%02x against %02x,%02x\n", __func__,
3377 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3378 return ERR_PTR(-ENODEV);
3379 }
3380
7aa65bfd 3381 if (!type)
5e81e88a
DW		 3382 type = nand_flash_ids;
3383
ec6e87e3
HS		 3384 for (; type->name != NULL; type++) {
3385 if (is_full_id_nand(type)) {
3386 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3387 goto ident_done;
3388 } else if (*dev_id == type->dev_id) {
3389 break;
3390 }
3391 }
5e81e88a 3392
d1e1f4e4
FF		 3393 chip->onfi_version = 0;
3394 if (!type->name || !type->pagesize) {
6fb277ba 3395 /* Check is chip is ONFI compliant */
47450b35 3396 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3397 goto ident_done;
d1e1f4e4
FF		 3398 }
3399
5e81e88a 3400 if (!type->name)
7aa65bfd
TG		 3401 return ERR_PTR(-ENODEV);
3402
ba0251fe
TG		 3403 if (!mtd->name)
3404 mtd->name = type->name;
3405
69423d99 3406 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3407
12a40a57 3408 if (!type->pagesize && chip->init_size) {
8b6e50c9 3409 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3410 busw = chip->init_size(mtd, chip, id_data);
3411 } else if (!type->pagesize) {
fc09bbc0
BN		 3412 /* Decode parameters from extended ID */
3413 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3414 } else {
f23a481c 3415 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3416 }
bf7a01bf
BN		 3417 /* Get chip options */
3418 chip->options |= type->options;
d1e1f4e4 3419
8b6e50c9
BN		 3420 /*
3421 * Check if chip is not a Samsung device. Do not clear the
3422 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3423 */
3424 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3425 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3426ident_done:
3427
7aa65bfd 3428 /* Try to identify manufacturer */
9a909867 3429 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3430 if (nand_manuf_ids[maf_idx].id == *maf_id)
3431 break;
3432 }
0ea4a755 3433
64b37b2a
MC		 3434 if (chip->options & NAND_BUSWIDTH_AUTO) {
3435 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3436 chip->options |= busw;
3437 nand_set_defaults(chip, busw);
3438 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3439 /*
3440 * Check, if buswidth is correct. Hardware drivers should set
3441 * chip correct!
3442 */
9a4d4d69 3443 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3444 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3445 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3446 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3447 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3448 busw ? 16 : 8);
7aa65bfd
TG		 3449 return ERR_PTR(-EINVAL);
3450 }
61b03bd7 3451
7e74c2d7
BN		 3452 nand_decode_bbm_options(mtd, chip, id_data);
3453
7aa65bfd 3454 /* Calculate the address shift from the page size */
ace4dfee 3455 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3456 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3457 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3458
ace4dfee 3459 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3460 ffs(mtd->erasesize) - 1;
69423d99
AH		 3461 if (chip->chipsize & 0xffffffff)
3462 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3463 else {
3464 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3465 chip->chip_shift += 32 - 1;
3466 }
1da177e4 3467
26d9be11 3468 chip->badblockbits = 8;
14c65786 3469 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3470
8b6e50c9 3471 /* Do not replace user supplied command function! */
ace4dfee
TG		 3472 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3473 chip->cmdfunc = nand_command_lp;
7aa65bfd 3474
3723e93c 3475 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)\n",
886bd33d 3476 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3723e93c
HS		 3477 chip->onfi_version ? chip->onfi_params.model : type->name);
3478
3479 pr_info("NAND device: %dMiB, %s, page size: %d, OOB size: %d\n",
3480 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3481 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3482
3483 return type;
3484}
3485
7aa65bfd 3486/**
3b85c321 3487 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3488 * @mtd: MTD device structure
3489 * @maxchips: number of chips to scan for
3490 * @table: alternative NAND ID table
7aa65bfd 3491 *
8b6e50c9
BN		 3492 * This is the first phase of the normal nand_scan() function. It reads the
3493 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3494 *
3b85c321 3495 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3496 */
5e81e88a
DW		 3497int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3498 struct nand_flash_dev *table)
7aa65bfd 3499{
d1e1f4e4 3500 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3501 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3502 struct nand_flash_dev *type;
3503
7aa65bfd 3504 /* Get buswidth to select the correct functions */
ace4dfee 3505 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3506 /* Set the default functions */
ace4dfee 3507 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3508
3509 /* Read the flash type */
7351d3a5
FF		 3510 type = nand_get_flash_type(mtd, chip, busw,
3511 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3512
3513 if (IS_ERR(type)) {
b1c6e6db 3514 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3515 pr_warn("No NAND device found\n");
ace4dfee 3516 chip->select_chip(mtd, -1);
7aa65bfd 3517 return PTR_ERR(type);
1da177e4
LT		 3518 }
3519
07300164
HS		 3520 chip->select_chip(mtd, -1);
3521
7aa65bfd 3522 /* Check for a chip array */
e0c7d767 3523 for (i = 1; i < maxchips; i++) {
ace4dfee 3524 chip->select_chip(mtd, i);
ef89a880
KB		 3525 /* See comment in nand_get_flash_type for reset */
3526 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3527 /* Send the command for reading device ID */
ace4dfee 3528 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3529 /* Read manufacturer and device IDs */
ace4dfee 3530 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3531 nand_dev_id != chip->read_byte(mtd)) {
3532 chip->select_chip(mtd, -1);
1da177e4 3533 break;
07300164
HS		 3534 }
3535 chip->select_chip(mtd, -1);
1da177e4
LT		 3536 }
3537 if (i > 1)
9a4d4d69 3538 pr_info("%d NAND chips detected\n", i);
61b03bd7 3539
1da177e4 3540 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3541 chip->numchips = i;
3542 mtd->size = i * chip->chipsize;
7aa65bfd 3543
3b85c321
DW		 3544 return 0;
3545}
7351d3a5 3546EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3547
3548
3549/**
3550 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3551 * @mtd: MTD device structure
3b85c321 3552 *
8b6e50c9
BN		 3553 * This is the second phase of the normal nand_scan() function. It fills out
3554 * all the uninitialized function pointers with the defaults and scans for a
3555 * bad block table if appropriate.
3b85c321
DW		 3556 */
3557int nand_scan_tail(struct mtd_info *mtd)
3558{
3559 int i;
3560 struct nand_chip *chip = mtd->priv;
3561
e2414f4c
BN		 3562 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3563 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3564 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3565
4bf63fcb
DW		 3566 if (!(chip->options & NAND_OWN_BUFFERS))
3567 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3568 if (!chip->buffers)
3569 return -ENOMEM;
3570
7dcdcbef 3571 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3572 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3573
7aa65bfd 3574 /*
8b6e50c9 3575 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3576 */
193bd400 3577 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3578 switch (mtd->oobsize) {
1da177e4 3579 case 8:
5bd34c09 3580 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3581 break;
3582 case 16:
5bd34c09 3583 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3584 break;
3585 case 64:
5bd34c09 3586 chip->ecc.layout = &nand_oob_64;
1da177e4 3587 break;
81ec5364
TG		 3588 case 128:
3589 chip->ecc.layout = &nand_oob_128;
3590 break;
1da177e4 3591 default:
d0370219
BN		 3592 pr_warn("No oob scheme defined for oobsize %d\n",
3593 mtd->oobsize);
1da177e4
LT		 3594 BUG();
3595 }
3596 }
61b03bd7 3597
956e944c
DW		 3598 if (!chip->write_page)
3599 chip->write_page = nand_write_page;
3600
61b03bd7 3601 /*
8b6e50c9 3602 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3603 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3604 */
956e944c 3605
ace4dfee 3606 switch (chip->ecc.mode) {
6e0cb135
SN		 3607 case NAND_ECC_HW_OOB_FIRST:
3608 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3609 if (!chip->ecc.calculate || !chip->ecc.correct ||
3610 !chip->ecc.hwctl) {
9a4d4d69 3611 pr_warn("No ECC functions supplied; "
d0370219 3612 "hardware ECC not possible\n");
6e0cb135
SN		 3613 BUG();
3614 }
3615 if (!chip->ecc.read_page)
3616 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3617
6dfc6d25 3618 case NAND_ECC_HW:
8b6e50c9 3619 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3620 if (!chip->ecc.read_page)
3621 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3622 if (!chip->ecc.write_page)
3623 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3624 if (!chip->ecc.read_page_raw)
3625 chip->ecc.read_page_raw = nand_read_page_raw;
3626 if (!chip->ecc.write_page_raw)
3627 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3628 if (!chip->ecc.read_oob)
3629 chip->ecc.read_oob = nand_read_oob_std;
3630 if (!chip->ecc.write_oob)
3631 chip->ecc.write_oob = nand_write_oob_std;
837a6ba4
GP		 3632 if (!chip->ecc.read_subpage)
3633 chip->ecc.read_subpage = nand_read_subpage;
3634 if (!chip->ecc.write_subpage)
3635 chip->ecc.write_subpage = nand_write_subpage_hwecc;
f5bbdacc 3636
6dfc6d25 3637 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3638 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3639 !chip->ecc.hwctl) &&
3640 (!chip->ecc.read_page ||
1c45f604 3641 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3642 !chip->ecc.write_page ||
1c45f604 3643 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3644 pr_warn("No ECC functions supplied; "
d0370219 3645 "hardware ECC not possible\n");
6dfc6d25
TG		 3646 BUG();
3647 }
8b6e50c9 3648 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3649 if (!chip->ecc.read_page)
3650 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3651 if (!chip->ecc.write_page)
3652 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3653 if (!chip->ecc.read_page_raw)
3654 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3655 if (!chip->ecc.write_page_raw)
3656 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3657 if (!chip->ecc.read_oob)
3658 chip->ecc.read_oob = nand_read_oob_syndrome;
3659 if (!chip->ecc.write_oob)
3660 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3661
e2788c98
MD		 3662 if (mtd->writesize >= chip->ecc.size) {
3663 if (!chip->ecc.strength) {
3664 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3665 BUG();
3666 }
6dfc6d25 3667 break;
e2788c98 3668 }
9a4d4d69 3669 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3670 "%d byte page size, fallback to SW ECC\n",
3671 chip->ecc.size, mtd->writesize);
ace4dfee 3672 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3673
6dfc6d25 3674 case NAND_ECC_SOFT:
ace4dfee
TG		 3675 chip->ecc.calculate = nand_calculate_ecc;
3676 chip->ecc.correct = nand_correct_data;
f5bbdacc 3677 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3678 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3679 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3680 chip->ecc.read_page_raw = nand_read_page_raw;
3681 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3682 chip->ecc.read_oob = nand_read_oob_std;
3683 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3684 if (!chip->ecc.size)
3685 chip->ecc.size = 256;
ace4dfee 3686 chip->ecc.bytes = 3;
6a918bad 3687 chip->ecc.strength = 1;
1da177e4 3688 break;
61b03bd7 3689
193bd400
ID		 3690 case NAND_ECC_SOFT_BCH:
3691 if (!mtd_nand_has_bch()) {
9a4d4d69 3692 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3693 BUG();
3694 }
3695 chip->ecc.calculate = nand_bch_calculate_ecc;
3696 chip->ecc.correct = nand_bch_correct_data;
3697 chip->ecc.read_page = nand_read_page_swecc;
3698 chip->ecc.read_subpage = nand_read_subpage;
3699 chip->ecc.write_page = nand_write_page_swecc;
3700 chip->ecc.read_page_raw = nand_read_page_raw;
3701 chip->ecc.write_page_raw = nand_write_page_raw;
3702 chip->ecc.read_oob = nand_read_oob_std;
3703 chip->ecc.write_oob = nand_write_oob_std;
3704 /*
3705 * Board driver should supply ecc.size and ecc.bytes values to
3706 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3707 * for details. Otherwise, default to 4 bits for large page
3708 * devices.
193bd400
ID		 3709 */
3710 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3711 chip->ecc.size = 512;
3712 chip->ecc.bytes = 7;
3713 }
3714 chip->ecc.priv = nand_bch_init(mtd,
3715 chip->ecc.size,
3716 chip->ecc.bytes,
3717 &chip->ecc.layout);
3718 if (!chip->ecc.priv) {
9a4d4d69 3719 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3720 BUG();
3721 }
6a918bad 3722 chip->ecc.strength =
e2788c98 3723 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3724 break;
3725
61b03bd7 3726 case NAND_ECC_NONE:
9a4d4d69 3727 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3728 "This is not recommended!\n");
8593fbc6
TG		 3729 chip->ecc.read_page = nand_read_page_raw;
3730 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3731 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3732 chip->ecc.read_page_raw = nand_read_page_raw;
3733 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3734 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3735 chip->ecc.size = mtd->writesize;
3736 chip->ecc.bytes = 0;
6a918bad 3737 chip->ecc.strength = 0;
1da177e4 3738 break;
956e944c 3739
1da177e4 3740 default:
d0370219 3741 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3742 BUG();
1da177e4 3743 }
61b03bd7 3744
9ce244b3 3745 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3746 if (!chip->ecc.read_oob_raw)
3747 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3748 if (!chip->ecc.write_oob_raw)
3749 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3750
5bd34c09
TG		 3751 /*
3752 * The number of bytes available for a client to place data into
8b6e50c9 3753 * the out of band area.
5bd34c09
TG		 3754 */
3755 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3756 for (i = 0; chip->ecc.layout->oobfree[i].length
3757 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3758 chip->ecc.layout->oobavail +=
3759 chip->ecc.layout->oobfree[i].length;
1f92267c 3760 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3761
7aa65bfd
TG		 3762 /*
3763 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3764 * mode.
7aa65bfd 3765 */
ace4dfee 3766 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3767 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3768 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3769 BUG();
1da177e4 3770 }
f5bbdacc 3771 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3772
8b6e50c9 3773 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 3774 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
f8ac0414 3775 switch (chip->ecc.steps) {
29072b96
TG		 3776 case 2:
3777 mtd->subpage_sft = 1;
3778 break;
3779 case 4:
3780 case 8:
81ec5364 3781 case 16:
29072b96
TG		 3782 mtd->subpage_sft = 2;
3783 break;
3784 }
3785 }
3786 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3787
04bbd0ea 3788 /* Initialize state */
ace4dfee 3789 chip->state = FL_READY;
1da177e4 3790
1da177e4 3791 /* Invalidate the pagebuffer reference */
ace4dfee 3792 chip->pagebuf = -1;
1da177e4 3793
a5ff4f10
JW		 3794 /* Large page NAND with SOFT_ECC should support subpage reads */
3795 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3796 chip->options |= NAND_SUBPAGE_READ;
3797
1da177e4 3798 /* Fill in remaining MTD driver data */
963d1c28 3799 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 3800 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3801 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3802 mtd->_erase = nand_erase;
3803 mtd->_point = NULL;
3804 mtd->_unpoint = NULL;
3805 mtd->_read = nand_read;
3806 mtd->_write = nand_write;
3807 mtd->_panic_write = panic_nand_write;
3808 mtd->_read_oob = nand_read_oob;
3809 mtd->_write_oob = nand_write_oob;
3810 mtd->_sync = nand_sync;
3811 mtd->_lock = NULL;
3812 mtd->_unlock = NULL;
3813 mtd->_suspend = nand_suspend;
3814 mtd->_resume = nand_resume;
3815 mtd->_block_isbad = nand_block_isbad;
3816 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3817 mtd->writebufsize = mtd->writesize;
1da177e4 3818
6a918bad 3819 /* propagate ecc info to mtd_info */
5bd34c09 3820 mtd->ecclayout = chip->ecc.layout;
86c2072b 3821 mtd->ecc_strength = chip->ecc.strength;
bdf69c47 3822 mtd->ecc_step_size = chip->ecc.size;
ea3b2ea2
SL		 3823 /*
3824 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3825 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3826 * properly set.
3827 */
3828 if (!mtd->bitflip_threshold)
3829 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3830
0040bf38 3831 /* Check, if we should skip the bad block table scan */
ace4dfee 3832 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3833 return 0;
1da177e4
LT		 3834
3835 /* Build bad block table */
ace4dfee 3836 return chip->scan_bbt(mtd);
1da177e4 3837}
7351d3a5 3838EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3839
8b6e50c9
BN		 3840/*
3841 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3842 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3843 * to call us from in-kernel code if the core NAND support is modular.
3844 */
3b85c321
DW		 3845#ifdef MODULE
3846#define caller_is_module() (1)
3847#else
3848#define caller_is_module() \
a6e6abd5 3849 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3850#endif
3851
3852/**
3853 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3854 * @mtd: MTD device structure
3855 * @maxchips: number of chips to scan for
3b85c321 3856 *
8b6e50c9
BN		 3857 * This fills out all the uninitialized function pointers with the defaults.
3858 * The flash ID is read and the mtd/chip structures are filled with the
3859 * appropriate values. The mtd->owner field must be set to the module of the
3860 * caller.
3b85c321
DW		 3861 */
3862int nand_scan(struct mtd_info *mtd, int maxchips)
3863{
3864 int ret;
3865
3866 /* Many callers got this wrong, so check for it for a while... */
3867 if (!mtd->owner && caller_is_module()) {
d0370219 3868 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3869 BUG();
3870 }
3871
5e81e88a 3872 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3873 if (!ret)
3874 ret = nand_scan_tail(mtd);
3875 return ret;
3876}
7351d3a5 3877EXPORT_SYMBOL(nand_scan);
3b85c321 3878
1da177e4 3879/**
61b03bd7 3880 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3881 * @mtd: MTD device structure
3882 */
e0c7d767 3883void nand_release(struct mtd_info *mtd)
1da177e4 3884{
ace4dfee 3885 struct nand_chip *chip = mtd->priv;
1da177e4 3886
193bd400
ID		 3887 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3888 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3889
5ffcaf3d 3890 mtd_device_unregister(mtd);
1da177e4 3891
fa671646 3892 /* Free bad block table memory */
ace4dfee 3893 kfree(chip->bbt);
4bf63fcb
DW		 3894 if (!(chip->options & NAND_OWN_BUFFERS))
3895 kfree(chip->buffers);
58373ff0
BN		 3896
3897 /* Free bad block descriptor memory */
3898 if (chip->badblock_pattern && chip->badblock_pattern->options
3899 & NAND_BBT_DYNAMICSTRUCT)
3900 kfree(chip->badblock_pattern);
1da177e4 3901}
e0c7d767 3902EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3903
3904static int __init nand_base_init(void)
3905{
3906 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3907 return 0;
3908}
3909
3910static void __exit nand_base_exit(void)
3911{
3912 led_trigger_unregister_simple(nand_led_trigger);
3913}
3914
3915module_init(nand_base_init);
3916module_exit(nand_base_exit);
3917
e0c7d767 3918MODULE_LICENSE("GPL");
7351d3a5
FF		 3919MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3920MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3921MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)