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mtd: nand: Use standard large page OOB layout when using NAND_ECC_NONE
[linux-2.6-block.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Overview:
3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
61b03bd7 5 *
1da177e4 6 * Additional technical information is available on
8b2b403c 7 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 8 *
1da177e4 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 11 *
ace4dfee 12 * Credits:
61b03bd7
TG		 13 * David Woodhouse for adding multichip support
14 *
1da177e4
LT		 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
17 *
ace4dfee 18 * TODO:
1da177e4
LT		 19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 21 * if we have HW ECC support.
c0b8ba7b 22 * BBT table is not serialized, has to be fixed
1da177e4 23 *
1da177e4
LT		 24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
20171642
EG		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
66507c7b 38#include <linux/mm.h>
38b8d208 39#include <linux/nmi.h>
1da177e4
LT		 40#include <linux/types.h>
41#include <linux/mtd/mtd.h>
d4092d76 42#include <linux/mtd/rawnand.h>
1da177e4 43#include <linux/mtd/nand_ecc.h>
193bd400 44#include <linux/mtd/nand_bch.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
7351d3a5 47#include <linux/io.h>
1da177e4 48#include <linux/mtd/partitions.h>
d48f62b9 49#include <linux/of.h>
1da177e4 50
41b207a7
BB		 51static int nand_get_device(struct mtd_info *mtd, int new_state);
52
53static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
54 struct mtd_oob_ops *ops);
1da177e4
LT		 55
56/* Define default oob placement schemes for large and small page devices */
41b207a7
BB		 57static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
58 struct mtd_oob_region *oobregion)
59{
60 struct nand_chip *chip = mtd_to_nand(mtd);
61 struct nand_ecc_ctrl *ecc = &chip->ecc;
1da177e4 62
41b207a7
BB		 63 if (section > 1)
64 return -ERANGE;
1da177e4 65
41b207a7
BB		 66 if (!section) {
67 oobregion->offset = 0;
f7f8c175
MR		 68 if (mtd->oobsize == 16)
69 oobregion->length = 4;
70 else
71 oobregion->length = 3;
41b207a7 72 } else {
f7f8c175
MR		 73 if (mtd->oobsize == 8)
74 return -ERANGE;
75
41b207a7
BB		 76 oobregion->offset = 6;
77 oobregion->length = ecc->total - 4;
78 }
1da177e4 79
41b207a7
BB		 80 return 0;
81}
82
83static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
84 struct mtd_oob_region *oobregion)
85{
86 if (section > 1)
87 return -ERANGE;
1da177e4 88
41b207a7
BB		 89 if (mtd->oobsize == 16) {
90 if (section)
91 return -ERANGE;
92
93 oobregion->length = 8;
94 oobregion->offset = 8;
95 } else {
96 oobregion->length = 2;
97 if (!section)
98 oobregion->offset = 3;
99 else
100 oobregion->offset = 6;
101 }
102
103 return 0;
104}
105
106const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
107 .ecc = nand_ooblayout_ecc_sp,
108 .free = nand_ooblayout_free_sp,
81ec5364 109};
41b207a7 110EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
81ec5364 111
41b207a7
BB		 112static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
113 struct mtd_oob_region *oobregion)
114{
115 struct nand_chip *chip = mtd_to_nand(mtd);
116 struct nand_ecc_ctrl *ecc = &chip->ecc;
1da177e4 117
882fd157 118 if (section || !ecc->total)
41b207a7 119 return -ERANGE;
8593fbc6 120
41b207a7
BB		 121 oobregion->length = ecc->total;
122 oobregion->offset = mtd->oobsize - oobregion->length;
123
124 return 0;
125}
126
127static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
128 struct mtd_oob_region *oobregion)
129{
130 struct nand_chip *chip = mtd_to_nand(mtd);
131 struct nand_ecc_ctrl *ecc = &chip->ecc;
132
133 if (section)
134 return -ERANGE;
135
136 oobregion->length = mtd->oobsize - ecc->total - 2;
137 oobregion->offset = 2;
138
139 return 0;
140}
141
142const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
143 .ecc = nand_ooblayout_ecc_lp,
144 .free = nand_ooblayout_free_lp,
145};
146EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
d470a97c 147
6a623e07
AC		 148/*
149 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC
150 * are placed at a fixed offset.
151 */
152static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section,
153 struct mtd_oob_region *oobregion)
154{
155 struct nand_chip *chip = mtd_to_nand(mtd);
156 struct nand_ecc_ctrl *ecc = &chip->ecc;
157
158 if (section)
159 return -ERANGE;
160
161 switch (mtd->oobsize) {
162 case 64:
163 oobregion->offset = 40;
164 break;
165 case 128:
166 oobregion->offset = 80;
167 break;
168 default:
169 return -EINVAL;
170 }
171
172 oobregion->length = ecc->total;
173 if (oobregion->offset + oobregion->length > mtd->oobsize)
174 return -ERANGE;
175
176 return 0;
177}
178
179static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section,
180 struct mtd_oob_region *oobregion)
181{
182 struct nand_chip *chip = mtd_to_nand(mtd);
183 struct nand_ecc_ctrl *ecc = &chip->ecc;
184 int ecc_offset = 0;
185
186 if (section < 0 || section > 1)
187 return -ERANGE;
188
189 switch (mtd->oobsize) {
190 case 64:
191 ecc_offset = 40;
192 break;
193 case 128:
194 ecc_offset = 80;
195 break;
196 default:
197 return -EINVAL;
198 }
199
200 if (section == 0) {
201 oobregion->offset = 2;
202 oobregion->length = ecc_offset - 2;
203 } else {
204 oobregion->offset = ecc_offset + ecc->total;
205 oobregion->length = mtd->oobsize - oobregion->offset;
206 }
207
208 return 0;
209}
210
d4ed3b90 211static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = {
6a623e07
AC		 212 .ecc = nand_ooblayout_ecc_lp_hamming,
213 .free = nand_ooblayout_free_lp_hamming,
214};
215
6fe5a6ac
VS		 216static int check_offs_len(struct mtd_info *mtd,
217 loff_t ofs, uint64_t len)
218{
862eba51 219 struct nand_chip *chip = mtd_to_nand(mtd);
6fe5a6ac
VS		 220 int ret = 0;
221
222 /* Start address must align on block boundary */
daae74ca 223 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 224 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 225 ret = -EINVAL;
226 }
227
228 /* Length must align on block boundary */
daae74ca 229 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
289c0522 230 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 231 ret = -EINVAL;
232 }
233
6fe5a6ac
VS		 234 return ret;
235}
236
1da177e4
LT		 237/**
238 * nand_release_device - [GENERIC] release chip
8b6e50c9 239 * @mtd: MTD device structure
61b03bd7 240 *
b0bb6903 241 * Release chip lock and wake up anyone waiting on the device.
1da177e4 242 */
e0c7d767 243static void nand_release_device(struct mtd_info *mtd)
1da177e4 244{
862eba51 245 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 246
a36ed299 247 /* Release the controller and the chip */
ace4dfee
TG		 248 spin_lock(&chip->controller->lock);
249 chip->controller->active = NULL;
250 chip->state = FL_READY;
251 wake_up(&chip->controller->wq);
252 spin_unlock(&chip->controller->lock);
1da177e4
LT		 253}
254
255/**
256 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 257 * @mtd: MTD device structure
1da177e4 258 *
7854d3f7 259 * Default read function for 8bit buswidth
1da177e4 260 */
58dd8f2b 261static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 262{
862eba51 263 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 264 return readb(chip->IO_ADDR_R);
1da177e4
LT		 265}
266
1da177e4 267/**
7854d3f7 268 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 269 * @mtd: MTD device structure
1da177e4 270 *
7854d3f7
BN		 271 * Default read function for 16bit buswidth with endianness conversion.
272 *
1da177e4 273 */
58dd8f2b 274static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 275{
862eba51 276 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 277 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 278}
279
1da177e4
LT		 280/**
281 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 282 * @mtd: MTD device structure
1da177e4 283 *
7854d3f7 284 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 285 */
286static u16 nand_read_word(struct mtd_info *mtd)
287{
862eba51 288 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee 289 return readw(chip->IO_ADDR_R);
1da177e4
LT		 290}
291
1da177e4
LT		 292/**
293 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 294 * @mtd: MTD device structure
295 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 296 *
297 * Default select function for 1 chip devices.
298 */
ace4dfee 299static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 300{
862eba51 301 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 302
303 switch (chipnr) {
1da177e4 304 case -1:
ace4dfee 305 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 306 break;
307 case 0:
1da177e4
LT		 308 break;
309
310 default:
311 BUG();
312 }
313}
314
05f78359
UKK		 315/**
316 * nand_write_byte - [DEFAULT] write single byte to chip
317 * @mtd: MTD device structure
318 * @byte: value to write
319 *
320 * Default function to write a byte to I/O[7:0]
321 */
322static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
323{
862eba51 324 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 325
326 chip->write_buf(mtd, &byte, 1);
327}
328
329/**
330 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
331 * @mtd: MTD device structure
332 * @byte: value to write
333 *
334 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
335 */
336static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
337{
862eba51 338 struct nand_chip *chip = mtd_to_nand(mtd);
05f78359
UKK		 339 uint16_t word = byte;
340
341 /*
342 * It's not entirely clear what should happen to I/O[15:8] when writing
343 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
344 *
345 * When the host supports a 16-bit bus width, only data is
346 * transferred at the 16-bit width. All address and command line
347 * transfers shall use only the lower 8-bits of the data bus. During
348 * command transfers, the host may place any value on the upper
349 * 8-bits of the data bus. During address transfers, the host shall
350 * set the upper 8-bits of the data bus to 00h.
351 *
352 * One user of the write_byte callback is nand_onfi_set_features. The
353 * four parameters are specified to be written to I/O[7:0], but this is
354 * neither an address nor a command transfer. Let's assume a 0 on the
355 * upper I/O lines is OK.
356 */
357 chip->write_buf(mtd, (uint8_t *)&word, 2);
358}
359
1da177e4
LT		 360/**
361 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 362 * @mtd: MTD device structure
363 * @buf: data buffer
364 * @len: number of bytes to write
1da177e4 365 *
7854d3f7 366 * Default write function for 8bit buswidth.
1da177e4 367 */
58dd8f2b 368static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 369{
862eba51 370 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 371
76413839 372 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 373}
374
375/**
61b03bd7 376 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 377 * @mtd: MTD device structure
378 * @buf: buffer to store date
379 * @len: number of bytes to read
1da177e4 380 *
7854d3f7 381 * Default read function for 8bit buswidth.
1da177e4 382 */
58dd8f2b 383static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 384{
862eba51 385 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 386
76413839 387 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 388}
389
1da177e4
LT		 390/**
391 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 392 * @mtd: MTD device structure
393 * @buf: data buffer
394 * @len: number of bytes to write
1da177e4 395 *
7854d3f7 396 * Default write function for 16bit buswidth.
1da177e4 397 */
58dd8f2b 398static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 399{
862eba51 400 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 401 u16 *p = (u16 *) buf;
61b03bd7 402
76413839 403 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 404}
405
406/**
61b03bd7 407 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 408 * @mtd: MTD device structure
409 * @buf: buffer to store date
410 * @len: number of bytes to read
1da177e4 411 *
7854d3f7 412 * Default read function for 16bit buswidth.
1da177e4 413 */
58dd8f2b 414static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 415{
862eba51 416 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 417 u16 *p = (u16 *) buf;
1da177e4 418
76413839 419 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 420}
421
1da177e4
LT		 422/**
423 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 424 * @mtd: MTD device structure
425 * @ofs: offset from device start
1da177e4 426 *
61b03bd7 427 * Check, if the block is bad.
1da177e4 428 */
9f3e0429 429static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1da177e4 430{
c120e75e 431 int page, page_end, res;
862eba51 432 struct nand_chip *chip = mtd_to_nand(mtd);
c120e75e 433 u8 bad;
1da177e4 434
5fb1549d 435 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 436 ofs += mtd->erasesize - mtd->writesize;
437
1a12f46a 438 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
c120e75e 439 page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1);
1a12f46a 440
c120e75e
MY		 441 for (; page < page_end; page++) {
442 res = chip->ecc.read_oob(mtd, chip, page);
443 if (res)
444 return res;
445
446 bad = chip->oob_poi[chip->badblockpos];
cdbec050
BN		 447
448 if (likely(chip->badblockbits == 8))
449 res = bad != 0xFF;
e0b58d0a 450 else
cdbec050 451 res = hweight8(bad) < chip->badblockbits;
c120e75e
MY		 452 if (res)
453 return res;
454 }
e0b58d0a 455
c120e75e 456 return 0;
1da177e4
LT		 457}
458
459/**
5a0edb25 460 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
8b6e50c9
BN		 461 * @mtd: MTD device structure
462 * @ofs: offset from device start
1da177e4 463 *
8b6e50c9 464 * This is the default implementation, which can be overridden by a hardware
5a0edb25
BN		 465 * specific driver. It provides the details for writing a bad block marker to a
466 * block.
467 */
468static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
469{
862eba51 470 struct nand_chip *chip = mtd_to_nand(mtd);
5a0edb25
BN		 471 struct mtd_oob_ops ops;
472 uint8_t buf[2] = { 0, 0 };
473 int ret = 0, res, i = 0;
474
0ec56dc4 475 memset(&ops, 0, sizeof(ops));
5a0edb25
BN		 476 ops.oobbuf = buf;
477 ops.ooboffs = chip->badblockpos;
478 if (chip->options & NAND_BUSWIDTH_16) {
479 ops.ooboffs &= ~0x01;
480 ops.len = ops.ooblen = 2;
481 } else {
482 ops.len = ops.ooblen = 1;
483 }
484 ops.mode = MTD_OPS_PLACE_OOB;
485
486 /* Write to first/last page(s) if necessary */
487 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
488 ofs += mtd->erasesize - mtd->writesize;
489 do {
490 res = nand_do_write_oob(mtd, ofs, &ops);
491 if (!ret)
492 ret = res;
493
494 i++;
495 ofs += mtd->writesize;
496 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
497
498 return ret;
499}
500
501/**
502 * nand_block_markbad_lowlevel - mark a block bad
503 * @mtd: MTD device structure
504 * @ofs: offset from device start
505 *
506 * This function performs the generic NAND bad block marking steps (i.e., bad
507 * block table(s) and/or marker(s)). We only allow the hardware driver to
508 * specify how to write bad block markers to OOB (chip->block_markbad).
509 *
b32843b7 510 * We try operations in the following order:
b6f6c294 511 *
e2414f4c 512 * (1) erase the affected block, to allow OOB marker to be written cleanly
b32843b7
BN		 513 * (2) write bad block marker to OOB area of affected block (unless flag
514 * NAND_BBT_NO_OOB_BBM is present)
515 * (3) update the BBT
b6f6c294 516 *
b32843b7 517 * Note that we retain the first error encountered in (2) or (3), finish the
e2414f4c 518 * procedures, and dump the error in the end.
1da177e4 519*/
5a0edb25 520static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
1da177e4 521{
862eba51 522 struct nand_chip *chip = mtd_to_nand(mtd);
b32843b7 523 int res, ret = 0;
61b03bd7 524
b32843b7 525 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
00918429
BN		 526 struct erase_info einfo;
527
528 /* Attempt erase before marking OOB */
529 memset(&einfo, 0, sizeof(einfo));
530 einfo.mtd = mtd;
531 einfo.addr = ofs;
daae74ca 532 einfo.len = 1ULL << chip->phys_erase_shift;
00918429 533 nand_erase_nand(mtd, &einfo, 0);
1da177e4 534
b32843b7 535 /* Write bad block marker to OOB */
6a8214aa 536 nand_get_device(mtd, FL_WRITING);
5a0edb25 537 ret = chip->block_markbad(mtd, ofs);
c0b8ba7b 538 nand_release_device(mtd);
f1a28c02 539 }
e2414f4c 540
b32843b7
BN		 541 /* Mark block bad in BBT */
542 if (chip->bbt) {
543 res = nand_markbad_bbt(mtd, ofs);
e2414f4c
BN		 544 if (!ret)
545 ret = res;
546 }
547
f1a28c02
TG		 548 if (!ret)
549 mtd->ecc_stats.badblocks++;
c0b8ba7b 550
f1a28c02 551 return ret;
1da177e4
LT		 552}
553
61b03bd7 554/**
1da177e4 555 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 556 * @mtd: MTD device structure
1da177e4 557 *
8b6e50c9
BN		 558 * Check, if the device is write protected. The function expects, that the
559 * device is already selected.
1da177e4 560 */
e0c7d767 561static int nand_check_wp(struct mtd_info *mtd)
1da177e4 562{
862eba51 563 struct nand_chip *chip = mtd_to_nand(mtd);
93edbad6 564
8b6e50c9 565 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 566 if (chip->options & NAND_BROKEN_XD)
567 return 0;
568
1da177e4 569 /* Check the WP bit */
ace4dfee
TG		 570 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
571 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 572}
573
8471bb73 574/**
c30e1f79 575 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
8471bb73
EG		 576 * @mtd: MTD device structure
577 * @ofs: offset from device start
578 *
c30e1f79 579 * Check if the block is marked as reserved.
8471bb73
EG		 580 */
581static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
582{
862eba51 583 struct nand_chip *chip = mtd_to_nand(mtd);
8471bb73
EG		 584
585 if (!chip->bbt)
586 return 0;
587 /* Return info from the table */
588 return nand_isreserved_bbt(mtd, ofs);
589}
590
1da177e4
LT		 591/**
592 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 593 * @mtd: MTD device structure
594 * @ofs: offset from device start
8b6e50c9 595 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 596 *
597 * Check, if the block is bad. Either by reading the bad block table or
598 * calling of the scan function.
599 */
9f3e0429 600static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
1da177e4 601{
862eba51 602 struct nand_chip *chip = mtd_to_nand(mtd);
61b03bd7 603
ace4dfee 604 if (!chip->bbt)
9f3e0429 605 return chip->block_bad(mtd, ofs);
61b03bd7 606
1da177e4 607 /* Return info from the table */
e0c7d767 608 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 609}
610
2af7c653
SK		 611/**
612 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 613 * @mtd: MTD device structure
614 * @timeo: Timeout
2af7c653
SK		 615 *
616 * Helper function for nand_wait_ready used when needing to wait in interrupt
617 * context.
618 */
619static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
620{
862eba51 621 struct nand_chip *chip = mtd_to_nand(mtd);
2af7c653
SK		 622 int i;
623
624 /* Wait for the device to get ready */
625 for (i = 0; i < timeo; i++) {
626 if (chip->dev_ready(mtd))
627 break;
628 touch_softlockup_watchdog();
629 mdelay(1);
630 }
631}
632
b70af9be
AS		 633/**
634 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
635 * @mtd: MTD device structure
636 *
637 * Wait for the ready pin after a command, and warn if a timeout occurs.
638 */
4b648b02 639void nand_wait_ready(struct mtd_info *mtd)
3b88775c 640{
862eba51 641 struct nand_chip *chip = mtd_to_nand(mtd);
b70af9be 642 unsigned long timeo = 400;
3b88775c 643
2af7c653 644 if (in_interrupt() || oops_in_progress)
b70af9be 645 return panic_nand_wait_ready(mtd, timeo);
2af7c653 646
7854d3f7 647 /* Wait until command is processed or timeout occurs */
b70af9be 648 timeo = jiffies + msecs_to_jiffies(timeo);
3b88775c 649 do {
ace4dfee 650 if (chip->dev_ready(mtd))
4c7e054f 651 return;
b70af9be 652 cond_resched();
61b03bd7 653 } while (time_before(jiffies, timeo));
b70af9be 654
9ebfdf5b
BN		 655 if (!chip->dev_ready(mtd))
656 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
3b88775c 657}
4b648b02 658EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 659
60c70d66
RQ		 660/**
661 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
662 * @mtd: MTD device structure
663 * @timeo: Timeout in ms
664 *
665 * Wait for status ready (i.e. command done) or timeout.
666 */
667static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
668{
862eba51 669 register struct nand_chip *chip = mtd_to_nand(mtd);
60c70d66
RQ		 670
671 timeo = jiffies + msecs_to_jiffies(timeo);
672 do {
673 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
674 break;
675 touch_softlockup_watchdog();
676 } while (time_before(jiffies, timeo));
677};
678
1da177e4
LT		 679/**
680 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 681 * @mtd: MTD device structure
682 * @command: the command to be sent
683 * @column: the column address for this command, -1 if none
684 * @page_addr: the page address for this command, -1 if none
1da177e4 685 *
8b6e50c9 686 * Send command to NAND device. This function is used for small page devices
51148f1f 687 * (512 Bytes per page).
1da177e4 688 */
7abd3ef9
TG		 689static void nand_command(struct mtd_info *mtd, unsigned int command,
690 int column, int page_addr)
1da177e4 691{
862eba51 692 register struct nand_chip *chip = mtd_to_nand(mtd);
7abd3ef9 693 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 694
8b6e50c9 695 /* Write out the command to the device */
1da177e4
LT		 696 if (command == NAND_CMD_SEQIN) {
697 int readcmd;
698
28318776 699 if (column >= mtd->writesize) {
1da177e4 700 /* OOB area */
28318776 701 column -= mtd->writesize;
1da177e4
LT		 702 readcmd = NAND_CMD_READOOB;
703 } else if (column < 256) {
704 /* First 256 bytes --> READ0 */
705 readcmd = NAND_CMD_READ0;
706 } else {
707 column -= 256;
708 readcmd = NAND_CMD_READ1;
709 }
ace4dfee 710 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 711 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 712 }
ace4dfee 713 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 714
8b6e50c9 715 /* Address cycle, when necessary */
7abd3ef9
TG		 716 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
717 /* Serially input address */
718 if (column != -1) {
719 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 720 if (chip->options & NAND_BUSWIDTH_16 &&
721 !nand_opcode_8bits(command))
7abd3ef9 722 column >>= 1;
ace4dfee 723 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 724 ctrl &= ~NAND_CTRL_CHANGE;
725 }
726 if (page_addr != -1) {
ace4dfee 727 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 728 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 729 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 730 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 731 if (chip->chipsize > (32 << 20))
732 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 733 }
ace4dfee 734 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 735
736 /*
8b6e50c9
BN		 737 * Program and erase have their own busy handlers status and sequential
738 * in needs no delay
e0c7d767 739 */
1da177e4 740 switch (command) {
61b03bd7 741
1da177e4
LT		 742 case NAND_CMD_PAGEPROG:
743 case NAND_CMD_ERASE1:
744 case NAND_CMD_ERASE2:
745 case NAND_CMD_SEQIN:
746 case NAND_CMD_STATUS:
3158fa0e 747 case NAND_CMD_READID:
c5d664aa 748 case NAND_CMD_SET_FEATURES:
1da177e4
LT		 749 return;
750
751 case NAND_CMD_RESET:
ace4dfee 752 if (chip->dev_ready)
1da177e4 753 break;
ace4dfee
TG		 754 udelay(chip->chip_delay);
755 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 756 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 757 chip->cmd_ctrl(mtd,
758 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 759 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
760 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 761 return;
762
e0c7d767 763 /* This applies to read commands */
2165c4a1
BB		 764 case NAND_CMD_READ0:
765 /*
766 * READ0 is sometimes used to exit GET STATUS mode. When this
767 * is the case no address cycles are requested, and we can use
768 * this information to detect that we should not wait for the
769 * device to be ready.
770 */
771 if (column == -1 && page_addr == -1)
772 return;
773
1da177e4 774 default:
61b03bd7 775 /*
1da177e4
LT		 776 * If we don't have access to the busy pin, we apply the given
777 * command delay
e0c7d767 778 */
ace4dfee
TG		 779 if (!chip->dev_ready) {
780 udelay(chip->chip_delay);
1da177e4 781 return;
61b03bd7 782 }
1da177e4 783 }
8b6e50c9
BN		 784 /*
785 * Apply this short delay always to ensure that we do wait tWB in
786 * any case on any machine.
787 */
e0c7d767 788 ndelay(100);
3b88775c
TG		 789
790 nand_wait_ready(mtd);
1da177e4
LT		 791}
792
6ea40a3b
BB		 793static void nand_ccs_delay(struct nand_chip *chip)
794{
795 /*
796 * The controller already takes care of waiting for tCCS when the RNDIN
797 * or RNDOUT command is sent, return directly.
798 */
799 if (!(chip->options & NAND_WAIT_TCCS))
800 return;
801
802 /*
803 * Wait tCCS_min if it is correctly defined, otherwise wait 500ns
804 * (which should be safe for all NANDs).
805 */
806 if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
807 ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
808 else
809 ndelay(500);
810}
811
1da177e4
LT		 812/**
813 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 814 * @mtd: MTD device structure
815 * @command: the command to be sent
816 * @column: the column address for this command, -1 if none
817 * @page_addr: the page address for this command, -1 if none
1da177e4 818 *
7abd3ef9 819 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 820 * devices. We don't have the separate regions as we have in the small page
821 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 822 */
7abd3ef9
TG		 823static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
824 int column, int page_addr)
1da177e4 825{
862eba51 826 register struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4
LT		 827
828 /* Emulate NAND_CMD_READOOB */
829 if (command == NAND_CMD_READOOB) {
28318776 830 column += mtd->writesize;
1da177e4
LT		 831 command = NAND_CMD_READ0;
832 }
61b03bd7 833
7abd3ef9 834 /* Command latch cycle */
fb066ada 835 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 836
837 if (column != -1 || page_addr != -1) {
7abd3ef9 838 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 839
840 /* Serially input address */
841 if (column != -1) {
842 /* Adjust columns for 16 bit buswidth */
3dad2344
BN		 843 if (chip->options & NAND_BUSWIDTH_16 &&
844 !nand_opcode_8bits(command))
1da177e4 845 column >>= 1;
ace4dfee 846 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 847 ctrl &= ~NAND_CTRL_CHANGE;
fde85cfd 848
f5b88de2 849 /* Only output a single addr cycle for 8bits opcodes. */
fde85cfd
BB		 850 if (!nand_opcode_8bits(command))
851 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 852 }
1da177e4 853 if (page_addr != -1) {
ace4dfee
TG		 854 chip->cmd_ctrl(mtd, page_addr, ctrl);
855 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 856 NAND_NCE | NAND_ALE);
1da177e4 857 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 858 if (chip->chipsize > (128 << 20))
859 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 860 NAND_NCE | NAND_ALE);
1da177e4 861 }
1da177e4 862 }
ace4dfee 863 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 864
865 /*
8b6e50c9 866 * Program and erase have their own busy handlers status, sequential
7a442f17 867 * in and status need no delay.
30f464b7 868 */
1da177e4 869 switch (command) {
61b03bd7 870
1da177e4
LT		 871 case NAND_CMD_CACHEDPROG:
872 case NAND_CMD_PAGEPROG:
873 case NAND_CMD_ERASE1:
874 case NAND_CMD_ERASE2:
875 case NAND_CMD_SEQIN:
876 case NAND_CMD_STATUS:
3158fa0e 877 case NAND_CMD_READID:
c5d664aa 878 case NAND_CMD_SET_FEATURES:
30f464b7 879 return;
1da177e4 880
6ea40a3b
BB		 881 case NAND_CMD_RNDIN:
882 nand_ccs_delay(chip);
883 return;
884
1da177e4 885 case NAND_CMD_RESET:
ace4dfee 886 if (chip->dev_ready)
1da177e4 887 break;
ace4dfee 888 udelay(chip->chip_delay);
12efdde3
TG		 889 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
890 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
891 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
892 NAND_NCE | NAND_CTRL_CHANGE);
60c70d66
RQ		 893 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
894 nand_wait_status_ready(mtd, 250);
1da177e4
LT		 895 return;
896
7bc3312b
TG		 897 case NAND_CMD_RNDOUT:
898 /* No ready / busy check necessary */
899 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
900 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
901 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
902 NAND_NCE | NAND_CTRL_CHANGE);
6ea40a3b
BB		 903
904 nand_ccs_delay(chip);
7bc3312b
TG		 905 return;
906
1da177e4 907 case NAND_CMD_READ0:
2165c4a1
BB		 908 /*
909 * READ0 is sometimes used to exit GET STATUS mode. When this
910 * is the case no address cycles are requested, and we can use
911 * this information to detect that READSTART should not be
912 * issued.
913 */
914 if (column == -1 && page_addr == -1)
915 return;
916
12efdde3
TG		 917 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
918 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
919 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
920 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 921
e0c7d767 922 /* This applies to read commands */
1da177e4 923 default:
61b03bd7 924 /*
1da177e4 925 * If we don't have access to the busy pin, we apply the given
8b6e50c9 926 * command delay.
e0c7d767 927 */
ace4dfee
TG		 928 if (!chip->dev_ready) {
929 udelay(chip->chip_delay);
1da177e4 930 return;
61b03bd7 931 }
1da177e4 932 }
3b88775c 933
8b6e50c9
BN		 934 /*
935 * Apply this short delay always to ensure that we do wait tWB in
936 * any case on any machine.
937 */
e0c7d767 938 ndelay(100);
3b88775c
TG		 939
940 nand_wait_ready(mtd);
1da177e4
LT		 941}
942
2af7c653
SK		 943/**
944 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 945 * @chip: the nand chip descriptor
946 * @mtd: MTD device structure
947 * @new_state: the state which is requested
2af7c653
SK		 948 *
949 * Used when in panic, no locks are taken.
950 */
951static void panic_nand_get_device(struct nand_chip *chip,
952 struct mtd_info *mtd, int new_state)
953{
7854d3f7 954 /* Hardware controller shared among independent devices */
2af7c653
SK		 955 chip->controller->active = chip;
956 chip->state = new_state;
957}
958
1da177e4
LT		 959/**
960 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 961 * @mtd: MTD device structure
962 * @new_state: the state which is requested
1da177e4
LT		 963 *
964 * Get the device and lock it for exclusive access
965 */
2c0a2bed 966static int
6a8214aa 967nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 968{
862eba51 969 struct nand_chip *chip = mtd_to_nand(mtd);
ace4dfee
TG		 970 spinlock_t *lock = &chip->controller->lock;
971 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 972 DECLARE_WAITQUEUE(wait, current);
7351d3a5 973retry:
0dfc6246
TG		 974 spin_lock(lock);
975
b8b3ee9a 976 /* Hardware controller shared among independent devices */
ace4dfee
TG		 977 if (!chip->controller->active)
978 chip->controller->active = chip;
a36ed299 979
ace4dfee
TG		 980 if (chip->controller->active == chip && chip->state == FL_READY) {
981 chip->state = new_state;
0dfc6246 982 spin_unlock(lock);
962034f4
VW		 983 return 0;
984 }
985 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 986 if (chip->controller->active->state == FL_PM_SUSPENDED) {
987 chip->state = FL_PM_SUSPENDED;
988 spin_unlock(lock);
989 return 0;
6b0d9a84 990 }
0dfc6246
TG		 991 }
992 set_current_state(TASK_UNINTERRUPTIBLE);
993 add_wait_queue(wq, &wait);
994 spin_unlock(lock);
995 schedule();
996 remove_wait_queue(wq, &wait);
1da177e4
LT		 997 goto retry;
998}
999
2af7c653 1000/**
8b6e50c9
BN		 1001 * panic_nand_wait - [GENERIC] wait until the command is done
1002 * @mtd: MTD device structure
1003 * @chip: NAND chip structure
1004 * @timeo: timeout
2af7c653
SK		 1005 *
1006 * Wait for command done. This is a helper function for nand_wait used when
1007 * we are in interrupt context. May happen when in panic and trying to write
b595076a 1008 * an oops through mtdoops.
2af7c653
SK		 1009 */
1010static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
1011 unsigned long timeo)
1012{
1013 int i;
1014 for (i = 0; i < timeo; i++) {
1015 if (chip->dev_ready) {
1016 if (chip->dev_ready(mtd))
1017 break;
1018 } else {
1019 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1020 break;
1021 }
1022 mdelay(1);
f8ac0414 1023 }
2af7c653
SK		 1024}
1025
1da177e4 1026/**
8b6e50c9
BN		 1027 * nand_wait - [DEFAULT] wait until the command is done
1028 * @mtd: MTD device structure
1029 * @chip: NAND chip structure
1da177e4 1030 *
b70af9be 1031 * Wait for command done. This applies to erase and program only.
844d3b42 1032 */
7bc3312b 1033static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 1034{
1035
b70af9be
AS		 1036 int status;
1037 unsigned long timeo = 400;
1da177e4 1038
8b6e50c9
BN		 1039 /*
1040 * Apply this short delay always to ensure that we do wait tWB in any
1041 * case on any machine.
1042 */
e0c7d767 1043 ndelay(100);
1da177e4 1044
14c65786 1045 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 1046
2af7c653
SK		 1047 if (in_interrupt() || oops_in_progress)
1048 panic_nand_wait(mtd, chip, timeo);
1049 else {
6d2559f8 1050 timeo = jiffies + msecs_to_jiffies(timeo);
b70af9be 1051 do {
2af7c653
SK		 1052 if (chip->dev_ready) {
1053 if (chip->dev_ready(mtd))
1054 break;
1055 } else {
1056 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1057 break;
1058 }
1059 cond_resched();
b70af9be 1060 } while (time_before(jiffies, timeo));
1da177e4 1061 }
8fe833c1 1062
ace4dfee 1063 status = (int)chip->read_byte(mtd);
f251b8df
MC		 1064 /* This can happen if in case of timeout or buggy dev_ready */
1065 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 1066 return status;
1067}
1068
d8e725dd
BB		 1069/**
1070 * nand_reset_data_interface - Reset data interface and timings
1071 * @chip: The NAND chip
104e442a 1072 * @chipnr: Internal die id
d8e725dd
BB		 1073 *
1074 * Reset the Data interface and timings to ONFI mode 0.
1075 *
1076 * Returns 0 for success or negative error code otherwise.
1077 */
104e442a 1078static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
d8e725dd
BB		 1079{
1080 struct mtd_info *mtd = nand_to_mtd(chip);
1081 const struct nand_data_interface *conf;
1082 int ret;
1083
1084 if (!chip->setup_data_interface)
1085 return 0;
1086
1087 /*
1088 * The ONFI specification says:
1089 * "
1090 * To transition from NV-DDR or NV-DDR2 to the SDR data
1091 * interface, the host shall use the Reset (FFh) command
1092 * using SDR timing mode 0. A device in any timing mode is
1093 * required to recognize Reset (FFh) command issued in SDR
1094 * timing mode 0.
1095 * "
1096 *
1097 * Configure the data interface in SDR mode and set the
1098 * timings to timing mode 0.
1099 */
1100
1101 conf = nand_get_default_data_interface();
104e442a 1102 ret = chip->setup_data_interface(mtd, chipnr, conf);
d8e725dd
BB		 1103 if (ret)
1104 pr_err("Failed to configure data interface to SDR timing mode 0\n");
1105
1106 return ret;
1107}
1108
1109/**
1110 * nand_setup_data_interface - Setup the best data interface and timings
1111 * @chip: The NAND chip
104e442a 1112 * @chipnr: Internal die id
d8e725dd
BB		 1113 *
1114 * Find and configure the best data interface and NAND timings supported by
1115 * the chip and the driver.
1116 * First tries to retrieve supported timing modes from ONFI information,
1117 * and if the NAND chip does not support ONFI, relies on the
1118 * ->onfi_timing_mode_default specified in the nand_ids table.
1119 *
1120 * Returns 0 for success or negative error code otherwise.
1121 */
104e442a 1122static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
d8e725dd
BB		 1123{
1124 struct mtd_info *mtd = nand_to_mtd(chip);
1125 int ret;
1126
1127 if (!chip->setup_data_interface || !chip->data_interface)
1128 return 0;
1129
1130 /*
1131 * Ensure the timing mode has been changed on the chip side
1132 * before changing timings on the controller side.
1133 */
a11bf5ed
BB		 1134 if (chip->onfi_version &&
1135 (le16_to_cpu(chip->onfi_params.opt_cmd) &
1136 ONFI_OPT_CMD_SET_GET_FEATURES)) {
d8e725dd
BB		 1137 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1138 chip->onfi_timing_mode_default,
1139 };
1140
1141 ret = chip->onfi_set_features(mtd, chip,
1142 ONFI_FEATURE_ADDR_TIMING_MODE,
1143 tmode_param);
1144 if (ret)
1145 goto err;
1146 }
1147
104e442a 1148 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
d8e725dd
BB		 1149err:
1150 return ret;
1151}
1152
1153/**
1154 * nand_init_data_interface - find the best data interface and timings
1155 * @chip: The NAND chip
1156 *
1157 * Find the best data interface and NAND timings supported by the chip
1158 * and the driver.
1159 * First tries to retrieve supported timing modes from ONFI information,
1160 * and if the NAND chip does not support ONFI, relies on the
1161 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1162 * function nand_chip->data_interface is initialized with the best timing mode
1163 * available.
1164 *
1165 * Returns 0 for success or negative error code otherwise.
1166 */
1167static int nand_init_data_interface(struct nand_chip *chip)
1168{
1169 struct mtd_info *mtd = nand_to_mtd(chip);
1170 int modes, mode, ret;
1171
1172 if (!chip->setup_data_interface)
1173 return 0;
1174
1175 /*
1176 * First try to identify the best timings from ONFI parameters and
1177 * if the NAND does not support ONFI, fallback to the default ONFI
1178 * timing mode.
1179 */
1180 modes = onfi_get_async_timing_mode(chip);
1181 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1182 if (!chip->onfi_timing_mode_default)
1183 return 0;
1184
1185 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1186 }
1187
1188 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1189 GFP_KERNEL);
1190 if (!chip->data_interface)
1191 return -ENOMEM;
1192
1193 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1194 ret = onfi_init_data_interface(chip, chip->data_interface,
1195 NAND_SDR_IFACE, mode);
1196 if (ret)
1197 continue;
1198
104e442a
BB		 1199 /* Pass -1 to only */
1200 ret = chip->setup_data_interface(mtd,
1201 NAND_DATA_IFACE_CHECK_ONLY,
1202 chip->data_interface);
d8e725dd
BB		 1203 if (!ret) {
1204 chip->onfi_timing_mode_default = mode;
1205 break;
1206 }
1207 }
1208
1209 return 0;
1210}
1211
1212static void nand_release_data_interface(struct nand_chip *chip)
1213{
1214 kfree(chip->data_interface);
1215}
1216
2f94abfe
SH		 1217/**
1218 * nand_reset - Reset and initialize a NAND device
1219 * @chip: The NAND chip
73f907fd 1220 * @chipnr: Internal die id
2f94abfe
SH		 1221 *
1222 * Returns 0 for success or negative error code otherwise
1223 */
73f907fd 1224int nand_reset(struct nand_chip *chip, int chipnr)
2f94abfe
SH		 1225{
1226 struct mtd_info *mtd = nand_to_mtd(chip);
d8e725dd
BB		 1227 int ret;
1228
104e442a 1229 ret = nand_reset_data_interface(chip, chipnr);
d8e725dd
BB		 1230 if (ret)
1231 return ret;
2f94abfe 1232
73f907fd
BB		 1233 /*
1234 * The CS line has to be released before we can apply the new NAND
1235 * interface settings, hence this weird ->select_chip() dance.
1236 */
1237 chip->select_chip(mtd, chipnr);
2f94abfe 1238 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
73f907fd 1239 chip->select_chip(mtd, -1);
2f94abfe 1240
73f907fd 1241 chip->select_chip(mtd, chipnr);
104e442a 1242 ret = nand_setup_data_interface(chip, chipnr);
73f907fd 1243 chip->select_chip(mtd, -1);
d8e725dd
BB		 1244 if (ret)
1245 return ret;
1246
2f94abfe
SH		 1247 return 0;
1248}
1249
730a43fb
BB		 1250/**
1251 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1252 * @buf: buffer to test
1253 * @len: buffer length
1254 * @bitflips_threshold: maximum number of bitflips
1255 *
1256 * Check if a buffer contains only 0xff, which means the underlying region
1257 * has been erased and is ready to be programmed.
1258 * The bitflips_threshold specify the maximum number of bitflips before
1259 * considering the region is not erased.
1260 * Note: The logic of this function has been extracted from the memweight
1261 * implementation, except that nand_check_erased_buf function exit before
1262 * testing the whole buffer if the number of bitflips exceed the
1263 * bitflips_threshold value.
1264 *
1265 * Returns a positive number of bitflips less than or equal to
1266 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1267 * threshold.
1268 */
1269static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1270{
1271 const unsigned char *bitmap = buf;
1272 int bitflips = 0;
1273 int weight;
1274
1275 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1276 len--, bitmap++) {
1277 weight = hweight8(*bitmap);
1278 bitflips += BITS_PER_BYTE - weight;
1279 if (unlikely(bitflips > bitflips_threshold))
1280 return -EBADMSG;
1281 }
1282
1283 for (; len >= sizeof(long);
1284 len -= sizeof(long), bitmap += sizeof(long)) {
086567f1
PM		 1285 unsigned long d = *((unsigned long *)bitmap);
1286 if (d == ~0UL)
1287 continue;
1288 weight = hweight_long(d);
730a43fb
BB		 1289 bitflips += BITS_PER_LONG - weight;
1290 if (unlikely(bitflips > bitflips_threshold))
1291 return -EBADMSG;
1292 }
1293
1294 for (; len > 0; len--, bitmap++) {
1295 weight = hweight8(*bitmap);
1296 bitflips += BITS_PER_BYTE - weight;
1297 if (unlikely(bitflips > bitflips_threshold))
1298 return -EBADMSG;
1299 }
1300
1301 return bitflips;
1302}
1303
1304/**
1305 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1306 * 0xff data
1307 * @data: data buffer to test
1308 * @datalen: data length
1309 * @ecc: ECC buffer
1310 * @ecclen: ECC length
1311 * @extraoob: extra OOB buffer
1312 * @extraooblen: extra OOB length
1313 * @bitflips_threshold: maximum number of bitflips
1314 *
1315 * Check if a data buffer and its associated ECC and OOB data contains only
1316 * 0xff pattern, which means the underlying region has been erased and is
1317 * ready to be programmed.
1318 * The bitflips_threshold specify the maximum number of bitflips before
1319 * considering the region as not erased.
1320 *
1321 * Note:
1322 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1323 * different from the NAND page size. When fixing bitflips, ECC engines will
1324 * report the number of errors per chunk, and the NAND core infrastructure
1325 * expect you to return the maximum number of bitflips for the whole page.
1326 * This is why you should always use this function on a single chunk and
1327 * not on the whole page. After checking each chunk you should update your
1328 * max_bitflips value accordingly.
1329 * 2/ When checking for bitflips in erased pages you should not only check
1330 * the payload data but also their associated ECC data, because a user might
1331 * have programmed almost all bits to 1 but a few. In this case, we
1332 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1333 * this case.
1334 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1335 * data are protected by the ECC engine.
1336 * It could also be used if you support subpages and want to attach some
1337 * extra OOB data to an ECC chunk.
1338 *
1339 * Returns a positive number of bitflips less than or equal to
1340 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1341 * threshold. In case of success, the passed buffers are filled with 0xff.
1342 */
1343int nand_check_erased_ecc_chunk(void *data, int datalen,
1344 void *ecc, int ecclen,
1345 void *extraoob, int extraooblen,
1346 int bitflips_threshold)
1347{
1348 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1349
1350 data_bitflips = nand_check_erased_buf(data, datalen,
1351 bitflips_threshold);
1352 if (data_bitflips < 0)
1353 return data_bitflips;
1354
1355 bitflips_threshold -= data_bitflips;
1356
1357 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1358 if (ecc_bitflips < 0)
1359 return ecc_bitflips;
1360
1361 bitflips_threshold -= ecc_bitflips;
1362
1363 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1364 bitflips_threshold);
1365 if (extraoob_bitflips < 0)
1366 return extraoob_bitflips;
1367
1368 if (data_bitflips)
1369 memset(data, 0xff, datalen);
1370
1371 if (ecc_bitflips)
1372 memset(ecc, 0xff, ecclen);
1373
1374 if (extraoob_bitflips)
1375 memset(extraoob, 0xff, extraooblen);
1376
1377 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1378}
1379EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1380
8593fbc6 1381/**
7854d3f7 1382 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1383 * @mtd: mtd info structure
1384 * @chip: nand chip info structure
1385 * @buf: buffer to store read data
1fbb938d 1386 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1387 * @page: page number to read
52ff49df 1388 *
7854d3f7 1389 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1390 */
cc0f51ec
TP		 1391int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1392 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1393{
1394 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1395 if (oob_required)
1396 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1397 return 0;
1398}
cc0f51ec 1399EXPORT_SYMBOL(nand_read_page_raw);
8593fbc6 1400
52ff49df 1401/**
7854d3f7 1402 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1403 * @mtd: mtd info structure
1404 * @chip: nand chip info structure
1405 * @buf: buffer to store read data
1fbb938d 1406 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1407 * @page: page number to read
52ff49df
DB		 1408 *
1409 * We need a special oob layout and handling even when OOB isn't used.
1410 */
7351d3a5 1411static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1412 struct nand_chip *chip, uint8_t *buf,
1413 int oob_required, int page)
52ff49df
DB		 1414{
1415 int eccsize = chip->ecc.size;
1416 int eccbytes = chip->ecc.bytes;
1417 uint8_t *oob = chip->oob_poi;
1418 int steps, size;
1419
1420 for (steps = chip->ecc.steps; steps > 0; steps--) {
1421 chip->read_buf(mtd, buf, eccsize);
1422 buf += eccsize;
1423
1424 if (chip->ecc.prepad) {
1425 chip->read_buf(mtd, oob, chip->ecc.prepad);
1426 oob += chip->ecc.prepad;
1427 }
1428
1429 chip->read_buf(mtd, oob, eccbytes);
1430 oob += eccbytes;
1431
1432 if (chip->ecc.postpad) {
1433 chip->read_buf(mtd, oob, chip->ecc.postpad);
1434 oob += chip->ecc.postpad;
1435 }
1436 }
1437
1438 size = mtd->oobsize - (oob - chip->oob_poi);
1439 if (size)
1440 chip->read_buf(mtd, oob, size);
1441
1442 return 0;
1443}
1444
1da177e4 1445/**
7854d3f7 1446 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1447 * @mtd: mtd info structure
1448 * @chip: nand chip info structure
1449 * @buf: buffer to store read data
1fbb938d 1450 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1451 * @page: page number to read
068e3c0a 1452 */
f5bbdacc 1453static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1454 uint8_t *buf, int oob_required, int page)
1da177e4 1455{
846031d3 1456 int i, eccsize = chip->ecc.size, ret;
f5bbdacc
TG		 1457 int eccbytes = chip->ecc.bytes;
1458 int eccsteps = chip->ecc.steps;
1459 uint8_t *p = buf;
4bf63fcb
DW		 1460 uint8_t *ecc_calc = chip->buffers->ecccalc;
1461 uint8_t *ecc_code = chip->buffers->ecccode;
3f91e94f 1462 unsigned int max_bitflips = 0;
f5bbdacc 1463
1fbb938d 1464 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1465
1466 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1467 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1468
846031d3
BB		 1469 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1470 chip->ecc.total);
1471 if (ret)
1472 return ret;
f5bbdacc
TG		 1473
1474 eccsteps = chip->ecc.steps;
1475 p = buf;
1476
1477 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1478 int stat;
1479
1480 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1481 if (stat < 0) {
f5bbdacc 1482 mtd->ecc_stats.failed++;
3f91e94f 1483 } else {
f5bbdacc 1484 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1485 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1486 }
f5bbdacc 1487 }
3f91e94f 1488 return max_bitflips;
22c60f5f 1489}
1da177e4 1490
3d459559 1491/**
837a6ba4 1492 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1493 * @mtd: mtd info structure
1494 * @chip: nand chip info structure
1495 * @data_offs: offset of requested data within the page
1496 * @readlen: data length
1497 * @bufpoi: buffer to store read data
e004debd 1498 * @page: page number to read
3d459559 1499 */
7351d3a5 1500static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
e004debd
HS		 1501 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1502 int page)
3d459559 1503{
846031d3 1504 int start_step, end_step, num_steps, ret;
3d459559
AK		 1505 uint8_t *p;
1506 int data_col_addr, i, gaps = 0;
1507 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1508 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
846031d3 1509 int index, section = 0;
3f91e94f 1510 unsigned int max_bitflips = 0;
846031d3 1511 struct mtd_oob_region oobregion = { };
3d459559 1512
7854d3f7 1513 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1514 start_step = data_offs / chip->ecc.size;
1515 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1516 num_steps = end_step - start_step + 1;
4a4163ca 1517 index = start_step * chip->ecc.bytes;
3d459559 1518
8b6e50c9 1519 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1520 datafrag_len = num_steps * chip->ecc.size;
1521 eccfrag_len = num_steps * chip->ecc.bytes;
1522
1523 data_col_addr = start_step * chip->ecc.size;
1524 /* If we read not a page aligned data */
1525 if (data_col_addr != 0)
1526 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1527
1528 p = bufpoi + data_col_addr;
1529 chip->read_buf(mtd, p, datafrag_len);
1530
8b6e50c9 1531 /* Calculate ECC */
3d459559
AK		 1532 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1533 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1534
8b6e50c9
BN		 1535 /*
1536 * The performance is faster if we position offsets according to
7854d3f7 1537 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1538 */
846031d3
BB		 1539 ret = mtd_ooblayout_find_eccregion(mtd, index, &section, &oobregion);
1540 if (ret)
1541 return ret;
1542
1543 if (oobregion.length < eccfrag_len)
1544 gaps = 1;
1545
3d459559
AK		 1546 if (gaps) {
1547 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1548 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1549 } else {
8b6e50c9 1550 /*
7854d3f7 1551 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1552 * about buswidth alignment in read_buf.
1553 */
846031d3 1554 aligned_pos = oobregion.offset & ~(busw - 1);
3d459559 1555 aligned_len = eccfrag_len;
846031d3 1556 if (oobregion.offset & (busw - 1))
3d459559 1557 aligned_len++;
846031d3
BB		 1558 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
1559 (busw - 1))
3d459559
AK		 1560 aligned_len++;
1561
7351d3a5 1562 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
846031d3 1563 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1564 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1565 }
1566
846031d3
BB		 1567 ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
1568 chip->oob_poi, index, eccfrag_len);
1569 if (ret)
1570 return ret;
3d459559
AK		 1571
1572 p = bufpoi + data_col_addr;
1573 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1574 int stat;
1575
7351d3a5
FF		 1576 stat = chip->ecc.correct(mtd, p,
1577 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
40cbe6ee
BB		 1578 if (stat == -EBADMSG &&
1579 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1580 /* check for empty pages with bitflips */
1581 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1582 &chip->buffers->ecccode[i],
1583 chip->ecc.bytes,
1584 NULL, 0,
1585 chip->ecc.strength);
1586 }
1587
3f91e94f 1588 if (stat < 0) {
3d459559 1589 mtd->ecc_stats.failed++;
3f91e94f 1590 } else {
3d459559 1591 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1592 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1593 }
3d459559 1594 }
3f91e94f 1595 return max_bitflips;
3d459559
AK		 1596}
1597
068e3c0a 1598/**
7854d3f7 1599 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1600 * @mtd: mtd info structure
1601 * @chip: nand chip info structure
1602 * @buf: buffer to store read data
1fbb938d 1603 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1604 * @page: page number to read
068e3c0a 1605 *
7854d3f7 1606 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1607 */
f5bbdacc 1608static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1609 uint8_t *buf, int oob_required, int page)
1da177e4 1610{
846031d3 1611 int i, eccsize = chip->ecc.size, ret;
f5bbdacc
TG		 1612 int eccbytes = chip->ecc.bytes;
1613 int eccsteps = chip->ecc.steps;
1614 uint8_t *p = buf;
4bf63fcb
DW		 1615 uint8_t *ecc_calc = chip->buffers->ecccalc;
1616 uint8_t *ecc_code = chip->buffers->ecccode;
3f91e94f 1617 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1618
1619 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1620 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1621 chip->read_buf(mtd, p, eccsize);
1622 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1623 }
f75e5097 1624 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1625
846031d3
BB		 1626 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1627 chip->ecc.total);
1628 if (ret)
1629 return ret;
1da177e4 1630
f5bbdacc
TG		 1631 eccsteps = chip->ecc.steps;
1632 p = buf;
61b03bd7 1633
f5bbdacc
TG		 1634 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1635 int stat;
1da177e4 1636
f5bbdacc 1637 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
40cbe6ee
BB		 1638 if (stat == -EBADMSG &&
1639 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1640 /* check for empty pages with bitflips */
1641 stat = nand_check_erased_ecc_chunk(p, eccsize,
1642 &ecc_code[i], eccbytes,
1643 NULL, 0,
1644 chip->ecc.strength);
1645 }
1646
3f91e94f 1647 if (stat < 0) {
f5bbdacc 1648 mtd->ecc_stats.failed++;
3f91e94f 1649 } else {
f5bbdacc 1650 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1651 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1652 }
f5bbdacc 1653 }
3f91e94f 1654 return max_bitflips;
f5bbdacc 1655}
1da177e4 1656
6e0cb135 1657/**
7854d3f7 1658 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1659 * @mtd: mtd info structure
1660 * @chip: nand chip info structure
1661 * @buf: buffer to store read data
1fbb938d 1662 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1663 * @page: page number to read
6e0cb135 1664 *
8b6e50c9
BN		 1665 * Hardware ECC for large page chips, require OOB to be read first. For this
1666 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1667 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1668 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1669 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1670 */
1671static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1672 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135 1673{
846031d3 1674 int i, eccsize = chip->ecc.size, ret;
6e0cb135
SN		 1675 int eccbytes = chip->ecc.bytes;
1676 int eccsteps = chip->ecc.steps;
1677 uint8_t *p = buf;
1678 uint8_t *ecc_code = chip->buffers->ecccode;
6e0cb135 1679 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1680 unsigned int max_bitflips = 0;
6e0cb135
SN		 1681
1682 /* Read the OOB area first */
1683 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1684 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1685 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1686
846031d3
BB		 1687 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1688 chip->ecc.total);
1689 if (ret)
1690 return ret;
6e0cb135
SN		 1691
1692 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1693 int stat;
1694
1695 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1696 chip->read_buf(mtd, p, eccsize);
1697 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1698
1699 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
40cbe6ee
BB		 1700 if (stat == -EBADMSG &&
1701 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1702 /* check for empty pages with bitflips */
1703 stat = nand_check_erased_ecc_chunk(p, eccsize,
1704 &ecc_code[i], eccbytes,
1705 NULL, 0,
1706 chip->ecc.strength);
1707 }
1708
3f91e94f 1709 if (stat < 0) {
6e0cb135 1710 mtd->ecc_stats.failed++;
3f91e94f 1711 } else {
6e0cb135 1712 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1713 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1714 }
6e0cb135 1715 }
3f91e94f 1716 return max_bitflips;
6e0cb135
SN		 1717}
1718
f5bbdacc 1719/**
7854d3f7 1720 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1721 * @mtd: mtd info structure
1722 * @chip: nand chip info structure
1723 * @buf: buffer to store read data
1fbb938d 1724 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1725 * @page: page number to read
f5bbdacc 1726 *
8b6e50c9
BN		 1727 * The hw generator calculates the error syndrome automatically. Therefore we
1728 * need a special oob layout and handling.
f5bbdacc
TG		 1729 */
1730static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1731 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1732{
1733 int i, eccsize = chip->ecc.size;
1734 int eccbytes = chip->ecc.bytes;
1735 int eccsteps = chip->ecc.steps;
40cbe6ee 1736 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
f5bbdacc 1737 uint8_t *p = buf;
f75e5097 1738 uint8_t *oob = chip->oob_poi;
3f91e94f 1739 unsigned int max_bitflips = 0;
1da177e4 1740
f5bbdacc
TG		 1741 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1742 int stat;
61b03bd7 1743
f5bbdacc
TG		 1744 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1745 chip->read_buf(mtd, p, eccsize);
1da177e4 1746
f5bbdacc
TG		 1747 if (chip->ecc.prepad) {
1748 chip->read_buf(mtd, oob, chip->ecc.prepad);
1749 oob += chip->ecc.prepad;
1750 }
1da177e4 1751
f5bbdacc
TG		 1752 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1753 chip->read_buf(mtd, oob, eccbytes);
1754 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1755
f5bbdacc 1756 oob += eccbytes;
1da177e4 1757
f5bbdacc
TG		 1758 if (chip->ecc.postpad) {
1759 chip->read_buf(mtd, oob, chip->ecc.postpad);
1760 oob += chip->ecc.postpad;
61b03bd7 1761 }
40cbe6ee
BB		 1762
1763 if (stat == -EBADMSG &&
1764 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1765 /* check for empty pages with bitflips */
1766 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1767 oob - eccpadbytes,
1768 eccpadbytes,
1769 NULL, 0,
1770 chip->ecc.strength);
1771 }
1772
1773 if (stat < 0) {
1774 mtd->ecc_stats.failed++;
1775 } else {
1776 mtd->ecc_stats.corrected += stat;
1777 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1778 }
f5bbdacc 1779 }
1da177e4 1780
f5bbdacc 1781 /* Calculate remaining oob bytes */
7e4178f9 1782 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1783 if (i)
1784 chip->read_buf(mtd, oob, i);
61b03bd7 1785
3f91e94f 1786 return max_bitflips;
f5bbdacc 1787}
1da177e4 1788
f5bbdacc 1789/**
7854d3f7 1790 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
846031d3 1791 * @mtd: mtd info structure
8b6e50c9
BN		 1792 * @oob: oob destination address
1793 * @ops: oob ops structure
1794 * @len: size of oob to transfer
8593fbc6 1795 */
846031d3 1796static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
7014568b 1797 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1798{
846031d3
BB		 1799 struct nand_chip *chip = mtd_to_nand(mtd);
1800 int ret;
1801
f8ac0414 1802 switch (ops->mode) {
8593fbc6 1803
0612b9dd
BN		 1804 case MTD_OPS_PLACE_OOB:
1805 case MTD_OPS_RAW:
8593fbc6
TG		 1806 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1807 return oob + len;
1808
846031d3
BB		 1809 case MTD_OPS_AUTO_OOB:
1810 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
1811 ops->ooboffs, len);
1812 BUG_ON(ret);
1813 return oob + len;
1814
8593fbc6
TG		 1815 default:
1816 BUG();
1817 }
1818 return NULL;
1819}
1820
ba84fb59
BN		 1821/**
1822 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1823 * @mtd: MTD device structure
1824 * @retry_mode: the retry mode to use
1825 *
1826 * Some vendors supply a special command to shift the Vt threshold, to be used
1827 * when there are too many bitflips in a page (i.e., ECC error). After setting
1828 * a new threshold, the host should retry reading the page.
1829 */
1830static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1831{
862eba51 1832 struct nand_chip *chip = mtd_to_nand(mtd);
ba84fb59
BN		 1833
1834 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1835
1836 if (retry_mode >= chip->read_retries)
1837 return -EINVAL;
1838
1839 if (!chip->setup_read_retry)
1840 return -EOPNOTSUPP;
1841
1842 return chip->setup_read_retry(mtd, retry_mode);
1843}
1844
8593fbc6 1845/**
7854d3f7 1846 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1847 * @mtd: MTD device structure
1848 * @from: offset to read from
1849 * @ops: oob ops structure
f5bbdacc
TG		 1850 *
1851 * Internal function. Called with chip held.
1852 */
8593fbc6
TG		 1853static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1854 struct mtd_oob_ops *ops)
f5bbdacc 1855{
e47f3db4 1856 int chipnr, page, realpage, col, bytes, aligned, oob_required;
862eba51 1857 struct nand_chip *chip = mtd_to_nand(mtd);
f5bbdacc 1858 int ret = 0;
8593fbc6 1859 uint32_t readlen = ops->len;
7014568b 1860 uint32_t oobreadlen = ops->ooblen;
29f1058a 1861 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
9aca334e 1862
8593fbc6 1863 uint8_t *bufpoi, *oob, *buf;
66507c7b 1864 int use_bufpoi;
edbc4540 1865 unsigned int max_bitflips = 0;
ba84fb59 1866 int retry_mode = 0;
b72f3dfb 1867 bool ecc_fail = false;
1da177e4 1868
f5bbdacc
TG		 1869 chipnr = (int)(from >> chip->chip_shift);
1870 chip->select_chip(mtd, chipnr);
61b03bd7 1871
f5bbdacc
TG		 1872 realpage = (int)(from >> chip->page_shift);
1873 page = realpage & chip->pagemask;
1da177e4 1874
f5bbdacc 1875 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1876
8593fbc6
TG		 1877 buf = ops->datbuf;
1878 oob = ops->oobbuf;
e47f3db4 1879 oob_required = oob ? 1 : 0;
8593fbc6 1880
f8ac0414 1881 while (1) {
b72f3dfb
BN		 1882 unsigned int ecc_failures = mtd->ecc_stats.failed;
1883
f5bbdacc
TG		 1884 bytes = min(mtd->writesize - col, readlen);
1885 aligned = (bytes == mtd->writesize);
61b03bd7 1886
66507c7b
KD		 1887 if (!aligned)
1888 use_bufpoi = 1;
1889 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
477544c6
MY		 1890 use_bufpoi = !virt_addr_valid(buf) ||
1891 !IS_ALIGNED((unsigned long)buf,
1892 chip->buf_align);
66507c7b
KD		 1893 else
1894 use_bufpoi = 0;
1895
8b6e50c9 1896 /* Is the current page in the buffer? */
8593fbc6 1897 if (realpage != chip->pagebuf || oob) {
66507c7b
KD		 1898 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1899
1900 if (use_bufpoi && aligned)
1901 pr_debug("%s: using read bounce buffer for buf@%p\n",
1902 __func__, buf);
61b03bd7 1903
ba84fb59 1904read_retry:
3371d663
MG		 1905 if (nand_standard_page_accessors(&chip->ecc))
1906 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1907
edbc4540
MD		 1908 /*
1909 * Now read the page into the buffer. Absent an error,
1910 * the read methods return max bitflips per ecc step.
1911 */
0612b9dd 1912 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1913 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1914 oob_required,
1915 page);
a5ff4f10
JW		 1916 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1917 !oob)
7351d3a5 1918 ret = chip->ecc.read_subpage(mtd, chip,
e004debd
HS		 1919 col, bytes, bufpoi,
1920 page);
956e944c 1921 else
46a8cf2d 1922 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1923 oob_required, page);
6d77b9d0 1924 if (ret < 0) {
66507c7b 1925 if (use_bufpoi)
6d77b9d0
BN		 1926 /* Invalidate page cache */
1927 chip->pagebuf = -1;
1da177e4 1928 break;
6d77b9d0 1929 }
f5bbdacc
TG		 1930
1931 /* Transfer not aligned data */
66507c7b 1932 if (use_bufpoi) {
a5ff4f10 1933 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
b72f3dfb 1934 !(mtd->ecc_stats.failed - ecc_failures) &&
edbc4540 1935 (ops->mode != MTD_OPS_RAW)) {
3d459559 1936 chip->pagebuf = realpage;
edbc4540
MD		 1937 chip->pagebuf_bitflips = ret;
1938 } else {
6d77b9d0
BN		 1939 /* Invalidate page cache */
1940 chip->pagebuf = -1;
edbc4540 1941 }
4bf63fcb 1942 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1943 }
1944
8593fbc6 1945 if (unlikely(oob)) {
b64d39d8
ML		 1946 int toread = min(oobreadlen, max_oobsize);
1947
1948 if (toread) {
846031d3 1949 oob = nand_transfer_oob(mtd,
b64d39d8
ML		 1950 oob, ops, toread);
1951 oobreadlen -= toread;
1952 }
8593fbc6 1953 }
5bc7c33c
BN		 1954
1955 if (chip->options & NAND_NEED_READRDY) {
1956 /* Apply delay or wait for ready/busy pin */
1957 if (!chip->dev_ready)
1958 udelay(chip->chip_delay);
1959 else
1960 nand_wait_ready(mtd);
1961 }
b72f3dfb 1962
ba84fb59 1963 if (mtd->ecc_stats.failed - ecc_failures) {
28fa65e6 1964 if (retry_mode + 1 < chip->read_retries) {
ba84fb59
BN		 1965 retry_mode++;
1966 ret = nand_setup_read_retry(mtd,
1967 retry_mode);
1968 if (ret < 0)
1969 break;
1970
1971 /* Reset failures; retry */
1972 mtd->ecc_stats.failed = ecc_failures;
1973 goto read_retry;
1974 } else {
1975 /* No more retry modes; real failure */
1976 ecc_fail = true;
1977 }
1978 }
1979
1980 buf += bytes;
07604686 1981 max_bitflips = max_t(unsigned int, max_bitflips, ret);
8593fbc6 1982 } else {
4bf63fcb 1983 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1984 buf += bytes;
edbc4540
MD		 1985 max_bitflips = max_t(unsigned int, max_bitflips,
1986 chip->pagebuf_bitflips);
8593fbc6 1987 }
1da177e4 1988
f5bbdacc 1989 readlen -= bytes;
61b03bd7 1990
ba84fb59
BN		 1991 /* Reset to retry mode 0 */
1992 if (retry_mode) {
1993 ret = nand_setup_read_retry(mtd, 0);
1994 if (ret < 0)
1995 break;
1996 retry_mode = 0;
1997 }
1998
f5bbdacc 1999 if (!readlen)
61b03bd7 2000 break;
1da177e4 2001
8b6e50c9 2002 /* For subsequent reads align to page boundary */
1da177e4
LT		 2003 col = 0;
2004 /* Increment page address */
2005 realpage++;
2006
ace4dfee 2007 page = realpage & chip->pagemask;
1da177e4
LT		 2008 /* Check, if we cross a chip boundary */
2009 if (!page) {
2010 chipnr++;
ace4dfee
TG		 2011 chip->select_chip(mtd, -1);
2012 chip->select_chip(mtd, chipnr);
1da177e4 2013 }
1da177e4 2014 }
b0bb6903 2015 chip->select_chip(mtd, -1);
1da177e4 2016
8593fbc6 2017 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 2018 if (oob)
2019 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 2020
3f91e94f 2021 if (ret < 0)
f5bbdacc
TG		 2022 return ret;
2023
b72f3dfb 2024 if (ecc_fail)
9a1fcdfd
TG		 2025 return -EBADMSG;
2026
edbc4540 2027 return max_bitflips;
f5bbdacc
TG		 2028}
2029
2030/**
25985edc 2031 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 2032 * @mtd: MTD device structure
2033 * @from: offset to read from
2034 * @len: number of bytes to read
2035 * @retlen: pointer to variable to store the number of read bytes
2036 * @buf: the databuffer to put data
f5bbdacc 2037 *
8b6e50c9 2038 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 2039 */
2040static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
2041 size_t *retlen, uint8_t *buf)
2042{
4a89ff88 2043 struct mtd_oob_ops ops;
f5bbdacc
TG		 2044 int ret;
2045
6a8214aa 2046 nand_get_device(mtd, FL_READING);
0ec56dc4 2047 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2048 ops.len = len;
2049 ops.datbuf = buf;
11041ae6 2050 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2051 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 2052 *retlen = ops.retlen;
f5bbdacc 2053 nand_release_device(mtd);
f5bbdacc 2054 return ret;
1da177e4
LT		 2055}
2056
7bc3312b 2057/**
7854d3f7 2058 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 2059 * @mtd: mtd info structure
2060 * @chip: nand chip info structure
2061 * @page: page number to read
7bc3312b 2062 */
9d02fc2a 2063int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b 2064{
5c2ffb11 2065 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 2066 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 2067 return 0;
7bc3312b 2068}
9d02fc2a 2069EXPORT_SYMBOL(nand_read_oob_std);
7bc3312b
TG		 2070
2071/**
7854d3f7 2072 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 2073 * with syndromes
8b6e50c9
BN		 2074 * @mtd: mtd info structure
2075 * @chip: nand chip info structure
2076 * @page: page number to read
7bc3312b 2077 */
9d02fc2a
BB		 2078int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2079 int page)
7bc3312b 2080{
7bc3312b
TG		 2081 int length = mtd->oobsize;
2082 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2083 int eccsize = chip->ecc.size;
2ea69d21 2084 uint8_t *bufpoi = chip->oob_poi;
7bc3312b
TG		 2085 int i, toread, sndrnd = 0, pos;
2086
2087 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
2088 for (i = 0; i < chip->ecc.steps; i++) {
2089 if (sndrnd) {
2090 pos = eccsize + i * (eccsize + chunk);
2091 if (mtd->writesize > 512)
2092 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
2093 else
2094 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
2095 } else
2096 sndrnd = 1;
2097 toread = min_t(int, length, chunk);
2098 chip->read_buf(mtd, bufpoi, toread);
2099 bufpoi += toread;
2100 length -= toread;
2101 }
2102 if (length > 0)
2103 chip->read_buf(mtd, bufpoi, length);
2104
5c2ffb11 2105 return 0;
7bc3312b 2106}
9d02fc2a 2107EXPORT_SYMBOL(nand_read_oob_syndrome);
7bc3312b
TG		 2108
2109/**
7854d3f7 2110 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 2111 * @mtd: mtd info structure
2112 * @chip: nand chip info structure
2113 * @page: page number to write
7bc3312b 2114 */
9d02fc2a 2115int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
7bc3312b
TG		 2116{
2117 int status = 0;
2118 const uint8_t *buf = chip->oob_poi;
2119 int length = mtd->oobsize;
2120
2121 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
2122 chip->write_buf(mtd, buf, length);
2123 /* Send command to program the OOB data */
2124 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2125
2126 status = chip->waitfunc(mtd, chip);
2127
0d420f9d 2128 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b 2129}
9d02fc2a 2130EXPORT_SYMBOL(nand_write_oob_std);
7bc3312b
TG		 2131
2132/**
7854d3f7 2133 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 2134 * with syndrome - only for large page flash
2135 * @mtd: mtd info structure
2136 * @chip: nand chip info structure
2137 * @page: page number to write
7bc3312b 2138 */
9d02fc2a
BB		 2139int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2140 int page)
7bc3312b
TG		 2141{
2142 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2143 int eccsize = chip->ecc.size, length = mtd->oobsize;
2144 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2145 const uint8_t *bufpoi = chip->oob_poi;
2146
2147 /*
2148 * data-ecc-data-ecc ... ecc-oob
2149 * or
2150 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2151 */
2152 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2153 pos = steps * (eccsize + chunk);
2154 steps = 0;
2155 } else
8b0036ee 2156 pos = eccsize;
7bc3312b
TG		 2157
2158 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2159 for (i = 0; i < steps; i++) {
2160 if (sndcmd) {
2161 if (mtd->writesize <= 512) {
2162 uint32_t fill = 0xFFFFFFFF;
2163
2164 len = eccsize;
2165 while (len > 0) {
2166 int num = min_t(int, len, 4);
2167 chip->write_buf(mtd, (uint8_t *)&fill,
2168 num);
2169 len -= num;
2170 }
2171 } else {
2172 pos = eccsize + i * (eccsize + chunk);
2173 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2174 }
2175 } else
2176 sndcmd = 1;
2177 len = min_t(int, length, chunk);
2178 chip->write_buf(mtd, bufpoi, len);
2179 bufpoi += len;
2180 length -= len;
2181 }
2182 if (length > 0)
2183 chip->write_buf(mtd, bufpoi, length);
2184
2185 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2186 status = chip->waitfunc(mtd, chip);
2187
2188 return status & NAND_STATUS_FAIL ? -EIO : 0;
2189}
9d02fc2a 2190EXPORT_SYMBOL(nand_write_oob_syndrome);
7bc3312b 2191
1da177e4 2192/**
7854d3f7 2193 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 2194 * @mtd: MTD device structure
2195 * @from: offset to read from
2196 * @ops: oob operations description structure
1da177e4 2197 *
8b6e50c9 2198 * NAND read out-of-band data from the spare area.
1da177e4 2199 */
8593fbc6
TG		 2200static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2201 struct mtd_oob_ops *ops)
1da177e4 2202{
c00a0991 2203 int page, realpage, chipnr;
862eba51 2204 struct nand_chip *chip = mtd_to_nand(mtd);
041e4575 2205 struct mtd_ecc_stats stats;
7014568b
VW		 2206 int readlen = ops->ooblen;
2207 int len;
7bc3312b 2208 uint8_t *buf = ops->oobbuf;
1951f2f7 2209 int ret = 0;
61b03bd7 2210
289c0522 2211 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 2212 __func__, (unsigned long long)from, readlen);
1da177e4 2213
041e4575
BN		 2214 stats = mtd->ecc_stats;
2215
29f1058a 2216 len = mtd_oobavail(mtd, ops);
03736155
AH		 2217
2218 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2219 pr_debug("%s: attempt to start read outside oob\n",
2220 __func__);
03736155
AH		 2221 return -EINVAL;
2222 }
2223
2224 /* Do not allow reads past end of device */
2225 if (unlikely(from >= mtd->size ||
2226 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2227 (from >> chip->page_shift)) * len)) {
289c0522
BN		 2228 pr_debug("%s: attempt to read beyond end of device\n",
2229 __func__);
03736155
AH		 2230 return -EINVAL;
2231 }
7014568b 2232
7314e9e7 2233 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 2234 chip->select_chip(mtd, chipnr);
1da177e4 2235
7314e9e7
TG		 2236 /* Shift to get page */
2237 realpage = (int)(from >> chip->page_shift);
2238 page = realpage & chip->pagemask;
1da177e4 2239
f8ac0414 2240 while (1) {
0612b9dd 2241 if (ops->mode == MTD_OPS_RAW)
1951f2f7 2242 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 2243 else
1951f2f7
SL		 2244 ret = chip->ecc.read_oob(mtd, chip, page);
2245
2246 if (ret < 0)
2247 break;
7014568b
VW		 2248
2249 len = min(len, readlen);
846031d3 2250 buf = nand_transfer_oob(mtd, buf, ops, len);
8593fbc6 2251
5bc7c33c
BN		 2252 if (chip->options & NAND_NEED_READRDY) {
2253 /* Apply delay or wait for ready/busy pin */
2254 if (!chip->dev_ready)
2255 udelay(chip->chip_delay);
2256 else
2257 nand_wait_ready(mtd);
2258 }
2259
7014568b 2260 readlen -= len;
0d420f9d
SZ		 2261 if (!readlen)
2262 break;
2263
7314e9e7
TG		 2264 /* Increment page address */
2265 realpage++;
2266
2267 page = realpage & chip->pagemask;
2268 /* Check, if we cross a chip boundary */
2269 if (!page) {
2270 chipnr++;
2271 chip->select_chip(mtd, -1);
2272 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2273 }
2274 }
b0bb6903 2275 chip->select_chip(mtd, -1);
1da177e4 2276
1951f2f7
SL		 2277 ops->oobretlen = ops->ooblen - readlen;
2278
2279 if (ret < 0)
2280 return ret;
041e4575
BN		 2281
2282 if (mtd->ecc_stats.failed - stats.failed)
2283 return -EBADMSG;
2284
2285 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 2286}
2287
2288/**
8593fbc6 2289 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 2290 * @mtd: MTD device structure
2291 * @from: offset to read from
2292 * @ops: oob operation description structure
1da177e4 2293 *
8b6e50c9 2294 * NAND read data and/or out-of-band data.
1da177e4 2295 */
8593fbc6
TG		 2296static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2297 struct mtd_oob_ops *ops)
1da177e4 2298{
fc6b4d12 2299 int ret;
8593fbc6
TG		 2300
2301 ops->retlen = 0;
1da177e4
LT		 2302
2303 /* Do not allow reads past end of device */
7014568b 2304 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 2305 pr_debug("%s: attempt to read beyond end of device\n",
2306 __func__);
1da177e4
LT		 2307 return -EINVAL;
2308 }
2309
fc6b4d12
AS		 2310 if (ops->mode != MTD_OPS_PLACE_OOB &&
2311 ops->mode != MTD_OPS_AUTO_OOB &&
2312 ops->mode != MTD_OPS_RAW)
2313 return -ENOTSUPP;
1da177e4 2314
fc6b4d12 2315 nand_get_device(mtd, FL_READING);
1da177e4 2316
8593fbc6
TG		 2317 if (!ops->datbuf)
2318 ret = nand_do_read_oob(mtd, from, ops);
2319 else
2320 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 2321
8593fbc6
TG		 2322 nand_release_device(mtd);
2323 return ret;
2324}
61b03bd7 2325
1da177e4 2326
8593fbc6 2327/**
7854d3f7 2328 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2329 * @mtd: mtd info structure
2330 * @chip: nand chip info structure
2331 * @buf: data buffer
1fbb938d 2332 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2333 * @page: page number to write
52ff49df 2334 *
7854d3f7 2335 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2336 */
cc0f51ec
TP		 2337int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2338 const uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 2339{
2340 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2341 if (oob_required)
2342 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2343
2344 return 0;
1da177e4 2345}
cc0f51ec 2346EXPORT_SYMBOL(nand_write_page_raw);
1da177e4 2347
52ff49df 2348/**
7854d3f7 2349 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2350 * @mtd: mtd info structure
2351 * @chip: nand chip info structure
2352 * @buf: data buffer
1fbb938d 2353 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2354 * @page: page number to write
52ff49df
DB		 2355 *
2356 * We need a special oob layout and handling even when ECC isn't checked.
2357 */
fdbad98d 2358static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2359 struct nand_chip *chip,
45aaeff9
BB		 2360 const uint8_t *buf, int oob_required,
2361 int page)
52ff49df
DB		 2362{
2363 int eccsize = chip->ecc.size;
2364 int eccbytes = chip->ecc.bytes;
2365 uint8_t *oob = chip->oob_poi;
2366 int steps, size;
2367
2368 for (steps = chip->ecc.steps; steps > 0; steps--) {
2369 chip->write_buf(mtd, buf, eccsize);
2370 buf += eccsize;
2371
2372 if (chip->ecc.prepad) {
2373 chip->write_buf(mtd, oob, chip->ecc.prepad);
2374 oob += chip->ecc.prepad;
2375 }
2376
60c3bc1f 2377 chip->write_buf(mtd, oob, eccbytes);
52ff49df
DB		 2378 oob += eccbytes;
2379
2380 if (chip->ecc.postpad) {
2381 chip->write_buf(mtd, oob, chip->ecc.postpad);
2382 oob += chip->ecc.postpad;
2383 }
2384 }
2385
2386 size = mtd->oobsize - (oob - chip->oob_poi);
2387 if (size)
2388 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2389
2390 return 0;
52ff49df 2391}
9223a456 2392/**
7854d3f7 2393 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2394 * @mtd: mtd info structure
2395 * @chip: nand chip info structure
2396 * @buf: data buffer
1fbb938d 2397 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2398 * @page: page number to write
9223a456 2399 */
fdbad98d 2400static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2401 const uint8_t *buf, int oob_required,
2402 int page)
9223a456 2403{
846031d3 2404 int i, eccsize = chip->ecc.size, ret;
f75e5097
TG		 2405 int eccbytes = chip->ecc.bytes;
2406 int eccsteps = chip->ecc.steps;
4bf63fcb 2407 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2408 const uint8_t *p = buf;
9223a456 2409
7854d3f7 2410 /* Software ECC calculation */
8593fbc6
TG		 2411 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2412 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2413
846031d3
BB		 2414 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2415 chip->ecc.total);
2416 if (ret)
2417 return ret;
9223a456 2418
45aaeff9 2419 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
f75e5097 2420}
9223a456 2421
f75e5097 2422/**
7854d3f7 2423 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2424 * @mtd: mtd info structure
2425 * @chip: nand chip info structure
2426 * @buf: data buffer
1fbb938d 2427 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2428 * @page: page number to write
f75e5097 2429 */
fdbad98d 2430static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
45aaeff9
BB		 2431 const uint8_t *buf, int oob_required,
2432 int page)
f75e5097 2433{
846031d3 2434 int i, eccsize = chip->ecc.size, ret;
f75e5097
TG		 2435 int eccbytes = chip->ecc.bytes;
2436 int eccsteps = chip->ecc.steps;
4bf63fcb 2437 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2438 const uint8_t *p = buf;
9223a456 2439
f75e5097
TG		 2440 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2441 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2442 chip->write_buf(mtd, p, eccsize);
f75e5097 2443 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2444 }
2445
846031d3
BB		 2446 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2447 chip->ecc.total);
2448 if (ret)
2449 return ret;
f75e5097
TG		 2450
2451 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2452
2453 return 0;
9223a456
TG		 2454}
2455
837a6ba4
GP		 2456
2457/**
73c8aaf4 2458 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
837a6ba4
GP		 2459 * @mtd: mtd info structure
2460 * @chip: nand chip info structure
d6a95080 2461 * @offset: column address of subpage within the page
837a6ba4 2462 * @data_len: data length
d6a95080 2463 * @buf: data buffer
837a6ba4 2464 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2465 * @page: page number to write
837a6ba4
GP		 2466 */
2467static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2468 struct nand_chip *chip, uint32_t offset,
d6a95080 2469 uint32_t data_len, const uint8_t *buf,
45aaeff9 2470 int oob_required, int page)
837a6ba4
GP		 2471{
2472 uint8_t *oob_buf = chip->oob_poi;
2473 uint8_t *ecc_calc = chip->buffers->ecccalc;
2474 int ecc_size = chip->ecc.size;
2475 int ecc_bytes = chip->ecc.bytes;
2476 int ecc_steps = chip->ecc.steps;
837a6ba4
GP		 2477 uint32_t start_step = offset / ecc_size;
2478 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2479 int oob_bytes = mtd->oobsize / ecc_steps;
846031d3 2480 int step, ret;
837a6ba4
GP		 2481
2482 for (step = 0; step < ecc_steps; step++) {
2483 /* configure controller for WRITE access */
2484 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2485
2486 /* write data (untouched subpages already masked by 0xFF) */
d6a95080 2487 chip->write_buf(mtd, buf, ecc_size);
837a6ba4
GP		 2488
2489 /* mask ECC of un-touched subpages by padding 0xFF */
2490 if ((step < start_step) || (step > end_step))
2491 memset(ecc_calc, 0xff, ecc_bytes);
2492 else
d6a95080 2493 chip->ecc.calculate(mtd, buf, ecc_calc);
837a6ba4
GP		 2494
2495 /* mask OOB of un-touched subpages by padding 0xFF */
2496 /* if oob_required, preserve OOB metadata of written subpage */
2497 if (!oob_required || (step < start_step) || (step > end_step))
2498 memset(oob_buf, 0xff, oob_bytes);
2499
d6a95080 2500 buf += ecc_size;
837a6ba4
GP		 2501 ecc_calc += ecc_bytes;
2502 oob_buf += oob_bytes;
2503 }
2504
2505 /* copy calculated ECC for whole page to chip->buffer->oob */
2506 /* this include masked-value(0xFF) for unwritten subpages */
2507 ecc_calc = chip->buffers->ecccalc;
846031d3
BB		 2508 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2509 chip->ecc.total);
2510 if (ret)
2511 return ret;
837a6ba4
GP		 2512
2513 /* write OOB buffer to NAND device */
2514 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2515
2516 return 0;
2517}
2518
2519
61b03bd7 2520/**
7854d3f7 2521 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2522 * @mtd: mtd info structure
2523 * @chip: nand chip info structure
2524 * @buf: data buffer
1fbb938d 2525 * @oob_required: must write chip->oob_poi to OOB
45aaeff9 2526 * @page: page number to write
1da177e4 2527 *
8b6e50c9
BN		 2528 * The hw generator calculates the error syndrome automatically. Therefore we
2529 * need a special oob layout and handling.
f75e5097 2530 */
fdbad98d 2531static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d 2532 struct nand_chip *chip,
45aaeff9
BB		 2533 const uint8_t *buf, int oob_required,
2534 int page)
1da177e4 2535{
f75e5097
TG		 2536 int i, eccsize = chip->ecc.size;
2537 int eccbytes = chip->ecc.bytes;
2538 int eccsteps = chip->ecc.steps;
2539 const uint8_t *p = buf;
2540 uint8_t *oob = chip->oob_poi;
1da177e4 2541
f75e5097 2542 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2543
f75e5097
TG		 2544 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2545 chip->write_buf(mtd, p, eccsize);
61b03bd7 2546
f75e5097
TG		 2547 if (chip->ecc.prepad) {
2548 chip->write_buf(mtd, oob, chip->ecc.prepad);
2549 oob += chip->ecc.prepad;
2550 }
2551
2552 chip->ecc.calculate(mtd, p, oob);
2553 chip->write_buf(mtd, oob, eccbytes);
2554 oob += eccbytes;
2555
2556 if (chip->ecc.postpad) {
2557 chip->write_buf(mtd, oob, chip->ecc.postpad);
2558 oob += chip->ecc.postpad;
1da177e4 2559 }
1da177e4 2560 }
f75e5097
TG		 2561
2562 /* Calculate remaining oob bytes */
7e4178f9 2563 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2564 if (i)
2565 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2566
2567 return 0;
f75e5097
TG		 2568}
2569
2570/**
f107d7a4 2571 * nand_write_page - write one page
8b6e50c9
BN		 2572 * @mtd: MTD device structure
2573 * @chip: NAND chip descriptor
837a6ba4
GP		 2574 * @offset: address offset within the page
2575 * @data_len: length of actual data to be written
8b6e50c9 2576 * @buf: the data to write
1fbb938d 2577 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9 2578 * @page: page number to write
8b6e50c9 2579 * @raw: use _raw version of write_page
f75e5097
TG		 2580 */
2581static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4 2582 uint32_t offset, int data_len, const uint8_t *buf,
0b4773fd 2583 int oob_required, int page, int raw)
f75e5097 2584{
837a6ba4
GP		 2585 int status, subpage;
2586
2587 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2588 chip->ecc.write_subpage)
2589 subpage = offset || (data_len < mtd->writesize);
2590 else
2591 subpage = 0;
f75e5097 2592
3371d663
MG		 2593 if (nand_standard_page_accessors(&chip->ecc))
2594 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
f75e5097 2595
956e944c 2596 if (unlikely(raw))
837a6ba4 2597 status = chip->ecc.write_page_raw(mtd, chip, buf,
45aaeff9 2598 oob_required, page);
837a6ba4
GP		 2599 else if (subpage)
2600 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
45aaeff9 2601 buf, oob_required, page);
956e944c 2602 else
45aaeff9
BB		 2603 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2604 page);
fdbad98d
JW		 2605
2606 if (status < 0)
2607 return status;
f75e5097 2608
41145649 2609 if (nand_standard_page_accessors(&chip->ecc)) {
0b4773fd 2610 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
f75e5097 2611
7bc3312b 2612 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2613 if (status & NAND_STATUS_FAIL)
2614 return -EIO;
f75e5097
TG		 2615 }
2616
f75e5097 2617 return 0;
1da177e4
LT		 2618}
2619
8593fbc6 2620/**
7854d3f7 2621 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2622 * @mtd: MTD device structure
8b6e50c9
BN		 2623 * @oob: oob data buffer
2624 * @len: oob data write length
2625 * @ops: oob ops structure
8593fbc6 2626 */
f722013e
TAA		 2627static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2628 struct mtd_oob_ops *ops)
8593fbc6 2629{
862eba51 2630 struct nand_chip *chip = mtd_to_nand(mtd);
846031d3 2631 int ret;
f722013e
TAA		 2632
2633 /*
2634 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2635 * data from a previous OOB read.
2636 */
2637 memset(chip->oob_poi, 0xff, mtd->oobsize);
2638
f8ac0414 2639 switch (ops->mode) {
8593fbc6 2640
0612b9dd
BN		 2641 case MTD_OPS_PLACE_OOB:
2642 case MTD_OPS_RAW:
8593fbc6
TG		 2643 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2644 return oob + len;
2645
846031d3
BB		 2646 case MTD_OPS_AUTO_OOB:
2647 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
2648 ops->ooboffs, len);
2649 BUG_ON(ret);
2650 return oob + len;
2651
8593fbc6
TG		 2652 default:
2653 BUG();
2654 }
2655 return NULL;
2656}
2657
f8ac0414 2658#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2659
2660/**
7854d3f7 2661 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2662 * @mtd: MTD device structure
2663 * @to: offset to write to
2664 * @ops: oob operations description structure
1da177e4 2665 *
8b6e50c9 2666 * NAND write with ECC.
1da177e4 2667 */
8593fbc6
TG		 2668static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2669 struct mtd_oob_ops *ops)
1da177e4 2670{
29072b96 2671 int chipnr, realpage, page, blockmask, column;
862eba51 2672 struct nand_chip *chip = mtd_to_nand(mtd);
8593fbc6 2673 uint32_t writelen = ops->len;
782ce79a
ML		 2674
2675 uint32_t oobwritelen = ops->ooblen;
29f1058a 2676 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
782ce79a 2677
8593fbc6
TG		 2678 uint8_t *oob = ops->oobbuf;
2679 uint8_t *buf = ops->datbuf;
837a6ba4 2680 int ret;
e47f3db4 2681 int oob_required = oob ? 1 : 0;
1da177e4 2682
8593fbc6 2683 ops->retlen = 0;
29072b96
TG		 2684 if (!writelen)
2685 return 0;
1da177e4 2686
8b6e50c9 2687 /* Reject writes, which are not page aligned */
8593fbc6 2688 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2689 pr_notice("%s: attempt to write non page aligned data\n",
2690 __func__);
1da177e4
LT		 2691 return -EINVAL;
2692 }
2693
29072b96 2694 column = to & (mtd->writesize - 1);
1da177e4 2695
6a930961
TG		 2696 chipnr = (int)(to >> chip->chip_shift);
2697 chip->select_chip(mtd, chipnr);
2698
1da177e4 2699 /* Check, if it is write protected */
b0bb6903
HS		 2700 if (nand_check_wp(mtd)) {
2701 ret = -EIO;
2702 goto err_out;
2703 }
1da177e4 2704
f75e5097
TG		 2705 realpage = (int)(to >> chip->page_shift);
2706 page = realpage & chip->pagemask;
2707 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2708
2709 /* Invalidate the page cache, when we write to the cached page */
537ab1bd
BN		 2710 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2711 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2712 chip->pagebuf = -1;
61b03bd7 2713
782ce79a 2714 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2715 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2716 ret = -EINVAL;
2717 goto err_out;
2718 }
782ce79a 2719
f8ac0414 2720 while (1) {
29072b96 2721 int bytes = mtd->writesize;
29072b96 2722 uint8_t *wbuf = buf;
66507c7b 2723 int use_bufpoi;
144f4c98 2724 int part_pagewr = (column || writelen < mtd->writesize);
66507c7b
KD		 2725
2726 if (part_pagewr)
2727 use_bufpoi = 1;
2728 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
477544c6
MY		 2729 use_bufpoi = !virt_addr_valid(buf) ||
2730 !IS_ALIGNED((unsigned long)buf,
2731 chip->buf_align);
66507c7b
KD		 2732 else
2733 use_bufpoi = 0;
29072b96 2734
66507c7b
KD		 2735 /* Partial page write?, or need to use bounce buffer */
2736 if (use_bufpoi) {
2737 pr_debug("%s: using write bounce buffer for buf@%p\n",
2738 __func__, buf);
66507c7b
KD		 2739 if (part_pagewr)
2740 bytes = min_t(int, bytes - column, writelen);
29072b96
TG		 2741 chip->pagebuf = -1;
2742 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2743 memcpy(&chip->buffers->databuf[column], buf, bytes);
2744 wbuf = chip->buffers->databuf;
2745 }
1da177e4 2746
782ce79a
ML		 2747 if (unlikely(oob)) {
2748 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2749 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2750 oobwritelen -= len;
f722013e
TAA		 2751 } else {
2752 /* We still need to erase leftover OOB data */
2753 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2754 }
f107d7a4
BB		 2755
2756 ret = nand_write_page(mtd, chip, column, bytes, wbuf,
0b4773fd 2757 oob_required, page,
f107d7a4 2758 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2759 if (ret)
2760 break;
2761
2762 writelen -= bytes;
2763 if (!writelen)
2764 break;
2765
29072b96 2766 column = 0;
f75e5097
TG		 2767 buf += bytes;
2768 realpage++;
2769
2770 page = realpage & chip->pagemask;
2771 /* Check, if we cross a chip boundary */
2772 if (!page) {
2773 chipnr++;
2774 chip->select_chip(mtd, -1);
2775 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2776 }
2777 }
8593fbc6 2778
8593fbc6 2779 ops->retlen = ops->len - writelen;
7014568b
VW		 2780 if (unlikely(oob))
2781 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2782
2783err_out:
2784 chip->select_chip(mtd, -1);
1da177e4
LT		 2785 return ret;
2786}
2787
2af7c653
SK		 2788/**
2789 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2790 * @mtd: MTD device structure
2791 * @to: offset to write to
2792 * @len: number of bytes to write
2793 * @retlen: pointer to variable to store the number of written bytes
2794 * @buf: the data to write
2af7c653
SK		 2795 *
2796 * NAND write with ECC. Used when performing writes in interrupt context, this
2797 * may for example be called by mtdoops when writing an oops while in panic.
2798 */
2799static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2800 size_t *retlen, const uint8_t *buf)
2801{
862eba51 2802 struct nand_chip *chip = mtd_to_nand(mtd);
4a89ff88 2803 struct mtd_oob_ops ops;
2af7c653
SK		 2804 int ret;
2805
8b6e50c9 2806 /* Wait for the device to get ready */
2af7c653
SK		 2807 panic_nand_wait(mtd, chip, 400);
2808
8b6e50c9 2809 /* Grab the device */
2af7c653
SK		 2810 panic_nand_get_device(chip, mtd, FL_WRITING);
2811
0ec56dc4 2812 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2813 ops.len = len;
2814 ops.datbuf = (uint8_t *)buf;
11041ae6 2815 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2816
4a89ff88 2817 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2818
4a89ff88 2819 *retlen = ops.retlen;
2af7c653
SK		 2820 return ret;
2821}
2822
f75e5097 2823/**
8593fbc6 2824 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2825 * @mtd: MTD device structure
2826 * @to: offset to write to
2827 * @len: number of bytes to write
2828 * @retlen: pointer to variable to store the number of written bytes
2829 * @buf: the data to write
f75e5097 2830 *
8b6e50c9 2831 * NAND write with ECC.
f75e5097 2832 */
8593fbc6
TG		 2833static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2834 size_t *retlen, const uint8_t *buf)
f75e5097 2835{
4a89ff88 2836 struct mtd_oob_ops ops;
f75e5097
TG		 2837 int ret;
2838
6a8214aa 2839 nand_get_device(mtd, FL_WRITING);
0ec56dc4 2840 memset(&ops, 0, sizeof(ops));
4a89ff88
BN		 2841 ops.len = len;
2842 ops.datbuf = (uint8_t *)buf;
11041ae6 2843 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2844 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2845 *retlen = ops.retlen;
f75e5097 2846 nand_release_device(mtd);
8593fbc6 2847 return ret;
f75e5097 2848}
7314e9e7 2849
1da177e4 2850/**
8593fbc6 2851 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2852 * @mtd: MTD device structure
2853 * @to: offset to write to
2854 * @ops: oob operation description structure
1da177e4 2855 *
8b6e50c9 2856 * NAND write out-of-band.
1da177e4 2857 */
8593fbc6
TG		 2858static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2859 struct mtd_oob_ops *ops)
1da177e4 2860{
03736155 2861 int chipnr, page, status, len;
862eba51 2862 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2863
289c0522 2864 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2865 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2866
29f1058a 2867 len = mtd_oobavail(mtd, ops);
03736155 2868
1da177e4 2869 /* Do not allow write past end of page */
03736155 2870 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2871 pr_debug("%s: attempt to write past end of page\n",
2872 __func__);
1da177e4
LT		 2873 return -EINVAL;
2874 }
2875
03736155 2876 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2877 pr_debug("%s: attempt to start write outside oob\n",
2878 __func__);
03736155
AH		 2879 return -EINVAL;
2880 }
2881
775adc3d 2882 /* Do not allow write past end of device */
03736155
AH		 2883 if (unlikely(to >= mtd->size ||
2884 ops->ooboffs + ops->ooblen >
2885 ((mtd->size >> chip->page_shift) -
2886 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2887 pr_debug("%s: attempt to write beyond end of device\n",
2888 __func__);
03736155
AH		 2889 return -EINVAL;
2890 }
2891
7314e9e7 2892 chipnr = (int)(to >> chip->chip_shift);
7314e9e7
TG		 2893
2894 /*
2895 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2896 * of my DiskOnChip 2000 test units) will clear the whole data page too
2897 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2898 * it in the doc2000 driver in August 1999. dwmw2.
2899 */
73f907fd
BB		 2900 nand_reset(chip, chipnr);
2901
2902 chip->select_chip(mtd, chipnr);
2903
2904 /* Shift to get page */
2905 page = (int)(to >> chip->page_shift);
1da177e4
LT		 2906
2907 /* Check, if it is write protected */
b0bb6903
HS		 2908 if (nand_check_wp(mtd)) {
2909 chip->select_chip(mtd, -1);
8593fbc6 2910 return -EROFS;
b0bb6903 2911 }
61b03bd7 2912
1da177e4 2913 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2914 if (page == chip->pagebuf)
2915 chip->pagebuf = -1;
1da177e4 2916
f722013e 2917 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2918
0612b9dd 2919 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2920 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2921 else
2922 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2923
b0bb6903
HS		 2924 chip->select_chip(mtd, -1);
2925
7bc3312b
TG		 2926 if (status)
2927 return status;
1da177e4 2928
7014568b 2929 ops->oobretlen = ops->ooblen;
1da177e4 2930
7bc3312b 2931 return 0;
8593fbc6
TG		 2932}
2933
2934/**
2935 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2936 * @mtd: MTD device structure
2937 * @to: offset to write to
2938 * @ops: oob operation description structure
8593fbc6
TG		 2939 */
2940static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2941 struct mtd_oob_ops *ops)
2942{
8593fbc6
TG		 2943 int ret = -ENOTSUPP;
2944
2945 ops->retlen = 0;
2946
2947 /* Do not allow writes past end of device */
7014568b 2948 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2949 pr_debug("%s: attempt to write beyond end of device\n",
2950 __func__);
8593fbc6
TG		 2951 return -EINVAL;
2952 }
2953
6a8214aa 2954 nand_get_device(mtd, FL_WRITING);
8593fbc6 2955
f8ac0414 2956 switch (ops->mode) {
0612b9dd
BN		 2957 case MTD_OPS_PLACE_OOB:
2958 case MTD_OPS_AUTO_OOB:
2959 case MTD_OPS_RAW:
8593fbc6
TG		 2960 break;
2961
2962 default:
2963 goto out;
2964 }
2965
2966 if (!ops->datbuf)
2967 ret = nand_do_write_oob(mtd, to, ops);
2968 else
2969 ret = nand_do_write_ops(mtd, to, ops);
2970
7351d3a5 2971out:
1da177e4 2972 nand_release_device(mtd);
1da177e4
LT		 2973 return ret;
2974}
2975
1da177e4 2976/**
49c50b97 2977 * single_erase - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2978 * @mtd: MTD device structure
2979 * @page: the page address of the block which will be erased
1da177e4 2980 *
49c50b97 2981 * Standard erase command for NAND chips. Returns NAND status.
1da177e4 2982 */
49c50b97 2983static int single_erase(struct mtd_info *mtd, int page)
1da177e4 2984{
862eba51 2985 struct nand_chip *chip = mtd_to_nand(mtd);
1da177e4 2986 /* Send commands to erase a block */
ace4dfee
TG		 2987 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2988 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
49c50b97
BN		 2989
2990 return chip->waitfunc(mtd, chip);
1da177e4
LT		 2991}
2992
1da177e4
LT		 2993/**
2994 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2995 * @mtd: MTD device structure
2996 * @instr: erase instruction
1da177e4 2997 *
8b6e50c9 2998 * Erase one ore more blocks.
1da177e4 2999 */
e0c7d767 3000static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 3001{
e0c7d767 3002 return nand_erase_nand(mtd, instr, 0);
1da177e4 3003}
61b03bd7 3004
1da177e4 3005/**
7854d3f7 3006 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 3007 * @mtd: MTD device structure
3008 * @instr: erase instruction
3009 * @allowbbt: allow erasing the bbt area
1da177e4 3010 *
8b6e50c9 3011 * Erase one ore more blocks.
1da177e4 3012 */
ace4dfee
TG		 3013int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3014 int allowbbt)
1da177e4 3015{
69423d99 3016 int page, status, pages_per_block, ret, chipnr;
862eba51 3017 struct nand_chip *chip = mtd_to_nand(mtd);
69423d99 3018 loff_t len;
1da177e4 3019
289c0522
BN		 3020 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3021 __func__, (unsigned long long)instr->addr,
3022 (unsigned long long)instr->len);
1da177e4 3023
6fe5a6ac 3024 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 3025 return -EINVAL;
1da177e4 3026
1da177e4 3027 /* Grab the lock and see if the device is available */
6a8214aa 3028 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 3029
3030 /* Shift to get first page */
ace4dfee
TG		 3031 page = (int)(instr->addr >> chip->page_shift);
3032 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 3033
3034 /* Calculate pages in each block */
ace4dfee 3035 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 3036
3037 /* Select the NAND device */
ace4dfee 3038 chip->select_chip(mtd, chipnr);
1da177e4 3039
1da177e4
LT		 3040 /* Check, if it is write protected */
3041 if (nand_check_wp(mtd)) {
289c0522
BN		 3042 pr_debug("%s: device is write protected!\n",
3043 __func__);
1da177e4
LT		 3044 instr->state = MTD_ERASE_FAILED;
3045 goto erase_exit;
3046 }
3047
3048 /* Loop through the pages */
3049 len = instr->len;
3050
3051 instr->state = MTD_ERASING;
3052
3053 while (len) {
12183a20 3054 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee 3055 if (nand_block_checkbad(mtd, ((loff_t) page) <<
9f3e0429 3056 chip->page_shift, allowbbt)) {
d0370219
BN		 3057 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3058 __func__, page);
1da177e4
LT		 3059 instr->state = MTD_ERASE_FAILED;
3060 goto erase_exit;
3061 }
61b03bd7 3062
ace4dfee
TG		 3063 /*
3064 * Invalidate the page cache, if we erase the block which
8b6e50c9 3065 * contains the current cached page.
ace4dfee
TG		 3066 */
3067 if (page <= chip->pagebuf && chip->pagebuf <
3068 (page + pages_per_block))
3069 chip->pagebuf = -1;
1da177e4 3070
49c50b97 3071 status = chip->erase(mtd, page & chip->pagemask);
1da177e4
LT		 3072
3073 /* See if block erase succeeded */
a4ab4c5d 3074 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 3075 pr_debug("%s: failed erase, page 0x%08x\n",
3076 __func__, page);
1da177e4 3077 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 3078 instr->fail_addr =
3079 ((loff_t)page << chip->page_shift);
1da177e4
LT		 3080 goto erase_exit;
3081 }
30f464b7 3082
1da177e4 3083 /* Increment page address and decrement length */
daae74ca 3084 len -= (1ULL << chip->phys_erase_shift);
1da177e4
LT		 3085 page += pages_per_block;
3086
3087 /* Check, if we cross a chip boundary */
ace4dfee 3088 if (len && !(page & chip->pagemask)) {
1da177e4 3089 chipnr++;
ace4dfee
TG		 3090 chip->select_chip(mtd, -1);
3091 chip->select_chip(mtd, chipnr);
1da177e4
LT		 3092 }
3093 }
3094 instr->state = MTD_ERASE_DONE;
3095
7351d3a5 3096erase_exit:
1da177e4
LT		 3097
3098 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 3099
3100 /* Deselect and wake up anyone waiting on the device */
b0bb6903 3101 chip->select_chip(mtd, -1);
1da177e4
LT		 3102 nand_release_device(mtd);
3103
49defc01
DW		 3104 /* Do call back function */
3105 if (!ret)
3106 mtd_erase_callback(instr);
3107
1da177e4
LT		 3108 /* Return more or less happy */
3109 return ret;
3110}
3111
3112/**
3113 * nand_sync - [MTD Interface] sync
8b6e50c9 3114 * @mtd: MTD device structure
1da177e4 3115 *
8b6e50c9 3116 * Sync is actually a wait for chip ready function.
1da177e4 3117 */
e0c7d767 3118static void nand_sync(struct mtd_info *mtd)
1da177e4 3119{
289c0522 3120 pr_debug("%s: called\n", __func__);
1da177e4
LT		 3121
3122 /* Grab the lock and see if the device is available */
6a8214aa 3123 nand_get_device(mtd, FL_SYNCING);
1da177e4 3124 /* Release it and go back */
e0c7d767 3125 nand_release_device(mtd);
1da177e4
LT		 3126}
3127
1da177e4 3128/**
ace4dfee 3129 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 3130 * @mtd: MTD device structure
3131 * @offs: offset relative to mtd start
1da177e4 3132 */
ace4dfee 3133static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 3134{
9f3e0429
AT		 3135 struct nand_chip *chip = mtd_to_nand(mtd);
3136 int chipnr = (int)(offs >> chip->chip_shift);
3137 int ret;
3138
3139 /* Select the NAND device */
3140 nand_get_device(mtd, FL_READING);
3141 chip->select_chip(mtd, chipnr);
3142
3143 ret = nand_block_checkbad(mtd, offs, 0);
3144
3145 chip->select_chip(mtd, -1);
3146 nand_release_device(mtd);
3147
3148 return ret;
1da177e4
LT		 3149}
3150
3151/**
ace4dfee 3152 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 3153 * @mtd: MTD device structure
3154 * @ofs: offset relative to mtd start
1da177e4 3155 */
e0c7d767 3156static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 3157{
1da177e4
LT		 3158 int ret;
3159
f8ac0414
FF		 3160 ret = nand_block_isbad(mtd, ofs);
3161 if (ret) {
8b6e50c9 3162 /* If it was bad already, return success and do nothing */
1da177e4
LT		 3163 if (ret > 0)
3164 return 0;
e0c7d767
DW		 3165 return ret;
3166 }
1da177e4 3167
5a0edb25 3168 return nand_block_markbad_lowlevel(mtd, ofs);
1da177e4
LT		 3169}
3170
5671842f
ZB		 3171/**
3172 * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd
3173 * @mtd: MTD device structure
3174 * @ofs: offset relative to mtd start
3175 * @len: length of mtd
3176 */
3177static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len)
3178{
3179 struct nand_chip *chip = mtd_to_nand(mtd);
3180 u32 part_start_block;
3181 u32 part_end_block;
3182 u32 part_start_die;
3183 u32 part_end_die;
3184
3185 /*
3186 * max_bb_per_die and blocks_per_die used to determine
3187 * the maximum bad block count.
3188 */
3189 if (!chip->max_bb_per_die || !chip->blocks_per_die)
3190 return -ENOTSUPP;
3191
3192 /* Get the start and end of the partition in erase blocks. */
3193 part_start_block = mtd_div_by_eb(ofs, mtd);
3194 part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1;
3195
3196 /* Get the start and end LUNs of the partition. */
3197 part_start_die = part_start_block / chip->blocks_per_die;
3198 part_end_die = part_end_block / chip->blocks_per_die;
3199
3200 /*
3201 * Look up the bad blocks per unit and multiply by the number of units
3202 * that the partition spans.
3203 */
3204 return chip->max_bb_per_die * (part_end_die - part_start_die + 1);
3205}
3206
7db03ecc
HS		 3207/**
3208 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3209 * @mtd: MTD device structure
3210 * @chip: nand chip info structure
3211 * @addr: feature address.
3212 * @subfeature_param: the subfeature parameters, a four bytes array.
3213 */
3214static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3215 int addr, uint8_t *subfeature_param)
3216{
3217 int status;
05f78359 3218 int i;
7db03ecc 3219
d914c932
DM		 3220 if (!chip->onfi_version ||
3221 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3222 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3223 return -EINVAL;
3224
3225 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
05f78359
UKK		 3226 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3227 chip->write_byte(mtd, subfeature_param[i]);
3228
7db03ecc
HS		 3229 status = chip->waitfunc(mtd, chip);
3230 if (status & NAND_STATUS_FAIL)
3231 return -EIO;
3232 return 0;
3233}
3234
3235/**
3236 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3237 * @mtd: MTD device structure
3238 * @chip: nand chip info structure
3239 * @addr: feature address.
3240 * @subfeature_param: the subfeature parameters, a four bytes array.
3241 */
3242static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3243 int addr, uint8_t *subfeature_param)
3244{
05f78359
UKK		 3245 int i;
3246
d914c932
DM		 3247 if (!chip->onfi_version ||
3248 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3249 & ONFI_OPT_CMD_SET_GET_FEATURES))
7db03ecc
HS		 3250 return -EINVAL;
3251
7db03ecc 3252 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
05f78359
UKK		 3253 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3254 *subfeature_param++ = chip->read_byte(mtd);
7db03ecc
HS		 3255 return 0;
3256}
3257
4a78cc64
BB		 3258/**
3259 * nand_onfi_get_set_features_notsupp - set/get features stub returning
3260 * -ENOTSUPP
3261 * @mtd: MTD device structure
3262 * @chip: nand chip info structure
3263 * @addr: feature address.
3264 * @subfeature_param: the subfeature parameters, a four bytes array.
3265 *
3266 * Should be used by NAND controller drivers that do not support the SET/GET
3267 * FEATURES operations.
3268 */
3269int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd,
3270 struct nand_chip *chip, int addr,
3271 u8 *subfeature_param)
3272{
3273 return -ENOTSUPP;
3274}
3275EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp);
3276
962034f4
VW		 3277/**
3278 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 3279 * @mtd: MTD device structure
962034f4
VW		 3280 */
3281static int nand_suspend(struct mtd_info *mtd)
3282{
6a8214aa 3283 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 3284}
3285
3286/**
3287 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 3288 * @mtd: MTD device structure
962034f4
VW		 3289 */
3290static void nand_resume(struct mtd_info *mtd)
3291{
862eba51 3292 struct nand_chip *chip = mtd_to_nand(mtd);
962034f4 3293
ace4dfee 3294 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 3295 nand_release_device(mtd);
3296 else
d0370219
BN		 3297 pr_err("%s called for a chip which is not in suspended state\n",
3298 __func__);
962034f4
VW		 3299}
3300
72ea4036
SB		 3301/**
3302 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3303 * prevent further operations
3304 * @mtd: MTD device structure
3305 */
3306static void nand_shutdown(struct mtd_info *mtd)
3307{
9ca641b0 3308 nand_get_device(mtd, FL_PM_SUSPENDED);
72ea4036
SB		 3309}
3310
8b6e50c9 3311/* Set default functions */
29a198a1 3312static void nand_set_defaults(struct nand_chip *chip)
7aa65bfd 3313{
29a198a1
BB		 3314 unsigned int busw = chip->options & NAND_BUSWIDTH_16;
3315
1da177e4 3316 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 3317 if (!chip->chip_delay)
3318 chip->chip_delay = 20;
1da177e4
LT		 3319
3320 /* check, if a user supplied command function given */
ace4dfee
TG		 3321 if (chip->cmdfunc == NULL)
3322 chip->cmdfunc = nand_command;
1da177e4
LT		 3323
3324 /* check, if a user supplied wait function given */
ace4dfee
TG		 3325 if (chip->waitfunc == NULL)
3326 chip->waitfunc = nand_wait;
3327
3328 if (!chip->select_chip)
3329 chip->select_chip = nand_select_chip;
68e80780 3330
4204cccd
HS		 3331 /* set for ONFI nand */
3332 if (!chip->onfi_set_features)
3333 chip->onfi_set_features = nand_onfi_set_features;
3334 if (!chip->onfi_get_features)
3335 chip->onfi_get_features = nand_onfi_get_features;
3336
68e80780
BN		 3337 /* If called twice, pointers that depend on busw may need to be reset */
3338 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 3339 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3340 if (!chip->read_word)
3341 chip->read_word = nand_read_word;
3342 if (!chip->block_bad)
3343 chip->block_bad = nand_block_bad;
3344 if (!chip->block_markbad)
3345 chip->block_markbad = nand_default_block_markbad;
68e80780 3346 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3347 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
05f78359
UKK		 3348 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3349 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
68e80780 3350 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3351 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3352 if (!chip->scan_bbt)
3353 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3354
3355 if (!chip->controller) {
3356 chip->controller = &chip->hwcontrol;
d45bc58d 3357 nand_hw_control_init(chip->controller);
f75e5097
TG		 3358 }
3359
477544c6
MY		 3360 if (!chip->buf_align)
3361 chip->buf_align = 1;
7aa65bfd
TG		 3362}
3363
8b6e50c9 3364/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3365static void sanitize_string(uint8_t *s, size_t len)
3366{
3367 ssize_t i;
3368
8b6e50c9 3369 /* Null terminate */
d1e1f4e4
FF		 3370 s[len - 1] = 0;
3371
8b6e50c9 3372 /* Remove non printable chars */
d1e1f4e4
FF		 3373 for (i = 0; i < len - 1; i++) {
3374 if (s[i] < ' ' || s[i] > 127)
3375 s[i] = '?';
3376 }
3377
8b6e50c9 3378 /* Remove trailing spaces */
d1e1f4e4
FF		 3379 strim(s);
3380}
3381
3382static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3383{
3384 int i;
3385 while (len--) {
3386 crc ^= *p++ << 8;
3387 for (i = 0; i < 8; i++)
3388 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3389 }
3390
3391 return crc;
3392}
3393
6dcbe0cd 3394/* Parse the Extended Parameter Page. */
cbe435a1
BB		 3395static int nand_flash_detect_ext_param_page(struct nand_chip *chip,
3396 struct nand_onfi_params *p)
6dcbe0cd 3397{
cbe435a1 3398 struct mtd_info *mtd = nand_to_mtd(chip);
6dcbe0cd
HS		 3399 struct onfi_ext_param_page *ep;
3400 struct onfi_ext_section *s;
3401 struct onfi_ext_ecc_info *ecc;
3402 uint8_t *cursor;
3403 int ret = -EINVAL;
3404 int len;
3405 int i;
3406
3407 len = le16_to_cpu(p->ext_param_page_length) * 16;
3408 ep = kmalloc(len, GFP_KERNEL);
5cb13271
BN		 3409 if (!ep)
3410 return -ENOMEM;
6dcbe0cd
HS		 3411
3412 /* Send our own NAND_CMD_PARAM. */
3413 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3414
3415 /* Use the Change Read Column command to skip the ONFI param pages. */
3416 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3417 sizeof(*p) * p->num_of_param_pages , -1);
3418
3419 /* Read out the Extended Parameter Page. */
3420 chip->read_buf(mtd, (uint8_t *)ep, len);
3421 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3422 != le16_to_cpu(ep->crc))) {
3423 pr_debug("fail in the CRC.\n");
3424 goto ext_out;
3425 }
3426
3427 /*
3428 * Check the signature.
3429 * Do not strictly follow the ONFI spec, maybe changed in future.
3430 */
3431 if (strncmp(ep->sig, "EPPS", 4)) {
3432 pr_debug("The signature is invalid.\n");
3433 goto ext_out;
3434 }
3435
3436 /* find the ECC section. */
3437 cursor = (uint8_t *)(ep + 1);
3438 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3439 s = ep->sections + i;
3440 if (s->type == ONFI_SECTION_TYPE_2)
3441 break;
3442 cursor += s->length * 16;
3443 }
3444 if (i == ONFI_EXT_SECTION_MAX) {
3445 pr_debug("We can not find the ECC section.\n");
3446 goto ext_out;
3447 }
3448
3449 /* get the info we want. */
3450 ecc = (struct onfi_ext_ecc_info *)cursor;
3451
4ae7d228
BN		 3452 if (!ecc->codeword_size) {
3453 pr_debug("Invalid codeword size\n");
3454 goto ext_out;
6dcbe0cd
HS		 3455 }
3456
4ae7d228
BN		 3457 chip->ecc_strength_ds = ecc->ecc_bits;
3458 chip->ecc_step_ds = 1 << ecc->codeword_size;
5cb13271 3459 ret = 0;
6dcbe0cd
HS		 3460
3461ext_out:
3462 kfree(ep);
3463 return ret;
3464}
3465
6fb277ba 3466/*
8b6e50c9 3467 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba 3468 */
29a198a1 3469static int nand_flash_detect_onfi(struct nand_chip *chip)
6fb277ba 3470{
cbe435a1 3471 struct mtd_info *mtd = nand_to_mtd(chip);
6fb277ba 3472 struct nand_onfi_params *p = &chip->onfi_params;
bd9c6e99 3473 int i, j;
6fb277ba
FF		 3474 int val;
3475
7854d3f7 3476 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3477 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3478 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3479 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3480 return 0;
3481
6fb277ba
FF		 3482 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3483 for (i = 0; i < 3; i++) {
bd9c6e99
BN		 3484 for (j = 0; j < sizeof(*p); j++)
3485 ((uint8_t *)p)[j] = chip->read_byte(mtd);
6fb277ba
FF		 3486 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3487 le16_to_cpu(p->crc)) {
6fb277ba
FF		 3488 break;
3489 }
3490 }
3491
c7f23a70
BN		 3492 if (i == 3) {
3493 pr_err("Could not find valid ONFI parameter page; aborting\n");
6fb277ba 3494 return 0;
c7f23a70 3495 }
6fb277ba 3496
8b6e50c9 3497 /* Check version */
6fb277ba 3498 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3499 if (val & (1 << 5))
3500 chip->onfi_version = 23;
3501 else if (val & (1 << 4))
6fb277ba
FF		 3502 chip->onfi_version = 22;
3503 else if (val & (1 << 3))
3504 chip->onfi_version = 21;
3505 else if (val & (1 << 2))
3506 chip->onfi_version = 20;
b7b1a29d 3507 else if (val & (1 << 1))
6fb277ba 3508 chip->onfi_version = 10;
b7b1a29d
BN		 3509
3510 if (!chip->onfi_version) {
20171642 3511 pr_info("unsupported ONFI version: %d\n", val);
b7b1a29d
BN		 3512 return 0;
3513 }
6fb277ba
FF		 3514
3515 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3516 sanitize_string(p->model, sizeof(p->model));
3517 if (!mtd->name)
3518 mtd->name = p->model;
4355b70c 3519
6fb277ba 3520 mtd->writesize = le32_to_cpu(p->byte_per_page);
4355b70c
BN		 3521
3522 /*
3523 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3524 * (don't ask me who thought of this...). MTD assumes that these
3525 * dimensions will be power-of-2, so just truncate the remaining area.
3526 */
3527 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3528 mtd->erasesize *= mtd->writesize;
3529
6fb277ba 3530 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4355b70c
BN		 3531
3532 /* See erasesize comment */
3533 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3534 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
13fbd179 3535 chip->bits_per_cell = p->bits_per_cell;
e2985fc1 3536
34da5f5f
ZB		 3537 chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun);
3538 chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun);
3539
e2985fc1 3540 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
29a198a1 3541 chip->options |= NAND_BUSWIDTH_16;
6fb277ba 3542
10c86bab
HS		 3543 if (p->ecc_bits != 0xff) {
3544 chip->ecc_strength_ds = p->ecc_bits;
3545 chip->ecc_step_ds = 512;
6dcbe0cd
HS		 3546 } else if (chip->onfi_version >= 21 &&
3547 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3548
3549 /*
3550 * The nand_flash_detect_ext_param_page() uses the
3551 * Change Read Column command which maybe not supported
3552 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3553 * now. We do not replace user supplied command function.
3554 */
3555 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3556 chip->cmdfunc = nand_command_lp;
3557
3558 /* The Extended Parameter Page is supported since ONFI 2.1. */
cbe435a1 3559 if (nand_flash_detect_ext_param_page(chip, p))
c7f23a70
BN		 3560 pr_warn("Failed to detect ONFI extended param page\n");
3561 } else {
3562 pr_warn("Could not retrieve ONFI ECC requirements\n");
10c86bab
HS		 3563 }
3564
6fb277ba
FF		 3565 return 1;
3566}
3567
91361818
HS		 3568/*
3569 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3570 */
29a198a1 3571static int nand_flash_detect_jedec(struct nand_chip *chip)
91361818 3572{
cbe435a1 3573 struct mtd_info *mtd = nand_to_mtd(chip);
91361818
HS		 3574 struct nand_jedec_params *p = &chip->jedec_params;
3575 struct jedec_ecc_info *ecc;
3576 int val;
3577 int i, j;
3578
3579 /* Try JEDEC for unknown chip or LP */
3580 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3581 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3582 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3583 chip->read_byte(mtd) != 'C')
3584 return 0;
3585
3586 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3587 for (i = 0; i < 3; i++) {
3588 for (j = 0; j < sizeof(*p); j++)
3589 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3590
3591 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3592 le16_to_cpu(p->crc))
3593 break;
3594 }
3595
3596 if (i == 3) {
3597 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3598 return 0;
3599 }
3600
3601 /* Check version */
3602 val = le16_to_cpu(p->revision);
3603 if (val & (1 << 2))
3604 chip->jedec_version = 10;
3605 else if (val & (1 << 1))
3606 chip->jedec_version = 1; /* vendor specific version */
3607
3608 if (!chip->jedec_version) {
3609 pr_info("unsupported JEDEC version: %d\n", val);
3610 return 0;
3611 }
3612
3613 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3614 sanitize_string(p->model, sizeof(p->model));
3615 if (!mtd->name)
3616 mtd->name = p->model;
3617
3618 mtd->writesize = le32_to_cpu(p->byte_per_page);
3619
3620 /* Please reference to the comment for nand_flash_detect_onfi. */
3621 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3622 mtd->erasesize *= mtd->writesize;
3623
3624 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3625
3626 /* Please reference to the comment for nand_flash_detect_onfi. */
3627 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3628 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3629 chip->bits_per_cell = p->bits_per_cell;
3630
3631 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
29a198a1 3632 chip->options |= NAND_BUSWIDTH_16;
91361818
HS		 3633
3634 /* ECC info */
3635 ecc = &p->ecc_info[0];
3636
3637 if (ecc->codeword_size >= 9) {
3638 chip->ecc_strength_ds = ecc->ecc_bits;
3639 chip->ecc_step_ds = 1 << ecc->codeword_size;
3640 } else {
3641 pr_warn("Invalid codeword size\n");
3642 }
3643
3644 return 1;
3645}
3646
e3b88bd6
BN		 3647/*
3648 * nand_id_has_period - Check if an ID string has a given wraparound period
3649 * @id_data: the ID string
3650 * @arrlen: the length of the @id_data array
3651 * @period: the period of repitition
3652 *
3653 * Check if an ID string is repeated within a given sequence of bytes at
3654 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3655 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3656 * if the repetition has a period of @period; otherwise, returns zero.
3657 */
3658static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3659{
3660 int i, j;
3661 for (i = 0; i < period; i++)
3662 for (j = i + period; j < arrlen; j += period)
3663 if (id_data[i] != id_data[j])
3664 return 0;
3665 return 1;
3666}
3667
3668/*
3669 * nand_id_len - Get the length of an ID string returned by CMD_READID
3670 * @id_data: the ID string
3671 * @arrlen: the length of the @id_data array
3672
3673 * Returns the length of the ID string, according to known wraparound/trailing
3674 * zero patterns. If no pattern exists, returns the length of the array.
3675 */
3676static int nand_id_len(u8 *id_data, int arrlen)
3677{
3678 int last_nonzero, period;
3679
3680 /* Find last non-zero byte */
3681 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3682 if (id_data[last_nonzero])
3683 break;
3684
3685 /* All zeros */
3686 if (last_nonzero < 0)
3687 return 0;
3688
3689 /* Calculate wraparound period */
3690 for (period = 1; period < arrlen; period++)
3691 if (nand_id_has_period(id_data, arrlen, period))
3692 break;
3693
3694 /* There's a repeated pattern */
3695 if (period < arrlen)
3696 return period;
3697
3698 /* There are trailing zeros */
3699 if (last_nonzero < arrlen - 1)
3700 return last_nonzero + 1;
3701
3702 /* No pattern detected */
3703 return arrlen;
3704}
3705
7db906b7
HS		 3706/* Extract the bits of per cell from the 3rd byte of the extended ID */
3707static int nand_get_bits_per_cell(u8 cellinfo)
3708{
3709 int bits;
3710
3711 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3712 bits >>= NAND_CI_CELLTYPE_SHIFT;
3713 return bits + 1;
3714}
3715
fc09bbc0
BN		 3716/*
3717 * Many new NAND share similar device ID codes, which represent the size of the
3718 * chip. The rest of the parameters must be decoded according to generic or
3719 * manufacturer-specific "extended ID" decoding patterns.
3720 */
abbe26d1 3721void nand_decode_ext_id(struct nand_chip *chip)
fc09bbc0 3722{
cbe435a1 3723 struct mtd_info *mtd = nand_to_mtd(chip);
9b2d61f8 3724 int extid;
7f501f0a 3725 u8 *id_data = chip->id.data;
fc09bbc0 3726 /* The 3rd id byte holds MLC / multichip data */
7db906b7 3727 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
fc09bbc0
BN		 3728 /* The 4th id byte is the important one */
3729 extid = id_data[3];
3730
01389b6b
BB		 3731 /* Calc pagesize */
3732 mtd->writesize = 1024 << (extid & 0x03);
3733 extid >>= 2;
3734 /* Calc oobsize */
3735 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
3736 extid >>= 2;
3737 /* Calc blocksize. Blocksize is multiples of 64KiB */
3738 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3739 extid >>= 2;
3740 /* Get buswidth information */
3741 if (extid & 0x1)
3742 chip->options |= NAND_BUSWIDTH_16;
fc09bbc0 3743}
abbe26d1 3744EXPORT_SYMBOL_GPL(nand_decode_ext_id);
fc09bbc0 3745
f23a481c
BN		 3746/*
3747 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3748 * decodes a matching ID table entry and assigns the MTD size parameters for
3749 * the chip.
3750 */
29a198a1 3751static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
f23a481c 3752{
cbe435a1 3753 struct mtd_info *mtd = nand_to_mtd(chip);
f23a481c
BN		 3754
3755 mtd->erasesize = type->erasesize;
3756 mtd->writesize = type->pagesize;
3757 mtd->oobsize = mtd->writesize / 32;
f23a481c 3758
1c195e90
HS		 3759 /* All legacy ID NAND are small-page, SLC */
3760 chip->bits_per_cell = 1;
f23a481c
BN		 3761}
3762
7e74c2d7
BN		 3763/*
3764 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3765 * heuristic patterns using various detected parameters (e.g., manufacturer,
3766 * page size, cell-type information).
3767 */
7f501f0a 3768static void nand_decode_bbm_options(struct nand_chip *chip)
7e74c2d7 3769{
cbe435a1 3770 struct mtd_info *mtd = nand_to_mtd(chip);
7e74c2d7
BN		 3771
3772 /* Set the bad block position */
3773 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3774 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3775 else
3776 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
7e74c2d7
BN		 3777}
3778
ec6e87e3
HS		 3779static inline bool is_full_id_nand(struct nand_flash_dev *type)
3780{
3781 return type->id_len;
3782}
3783
cbe435a1 3784static bool find_full_id_nand(struct nand_chip *chip,
29a198a1 3785 struct nand_flash_dev *type)
ec6e87e3 3786{
cbe435a1 3787 struct mtd_info *mtd = nand_to_mtd(chip);
7f501f0a 3788 u8 *id_data = chip->id.data;
cbe435a1 3789
ec6e87e3
HS		 3790 if (!strncmp(type->id, id_data, type->id_len)) {
3791 mtd->writesize = type->pagesize;
3792 mtd->erasesize = type->erasesize;
3793 mtd->oobsize = type->oobsize;
3794
7db906b7 3795 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
ec6e87e3
HS		 3796 chip->chipsize = (uint64_t)type->chipsize << 20;
3797 chip->options |= type->options;
57219342
HS		 3798 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3799 chip->ecc_step_ds = NAND_ECC_STEP(type);
57a94e24
BB		 3800 chip->onfi_timing_mode_default =
3801 type->onfi_timing_mode_default;
ec6e87e3 3802
092b6a1d
CZ		 3803 if (!mtd->name)
3804 mtd->name = type->name;
3805
ec6e87e3
HS		 3806 return true;
3807 }
3808 return false;
3809}
3810
abbe26d1
BB		 3811/*
3812 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
3813 * compliant and does not have a full-id or legacy-id entry in the nand_ids
3814 * table.
3815 */
3816static void nand_manufacturer_detect(struct nand_chip *chip)
3817{
3818 /*
3819 * Try manufacturer detection if available and use
3820 * nand_decode_ext_id() otherwise.
3821 */
3822 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
69fc0129
LW		 3823 chip->manufacturer.desc->ops->detect) {
3824 /* The 3rd id byte holds MLC / multichip data */
3825 chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
abbe26d1 3826 chip->manufacturer.desc->ops->detect(chip);
69fc0129 3827 } else {
abbe26d1 3828 nand_decode_ext_id(chip);
69fc0129 3829 }
abbe26d1
BB		 3830}
3831
3832/*
3833 * Manufacturer initialization. This function is called for all NANDs including
3834 * ONFI and JEDEC compliant ones.
3835 * Manufacturer drivers should put all their specific initialization code in
3836 * their ->init() hook.
3837 */
3838static int nand_manufacturer_init(struct nand_chip *chip)
3839{
3840 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
3841 !chip->manufacturer.desc->ops->init)
3842 return 0;
3843
3844 return chip->manufacturer.desc->ops->init(chip);
3845}
3846
3847/*
3848 * Manufacturer cleanup. This function is called for all NANDs including
3849 * ONFI and JEDEC compliant ones.
3850 * Manufacturer drivers should put all their specific cleanup code in their
3851 * ->cleanup() hook.
3852 */
3853static void nand_manufacturer_cleanup(struct nand_chip *chip)
3854{
3855 /* Release manufacturer private data */
3856 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
3857 chip->manufacturer.desc->ops->cleanup)
3858 chip->manufacturer.desc->ops->cleanup(chip);
3859}
3860
7aa65bfd 3861/*
8b6e50c9 3862 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd 3863 */
7bb42799 3864static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
7aa65bfd 3865{
bcc678c2 3866 const struct nand_manufacturer *manufacturer;
cbe435a1 3867 struct mtd_info *mtd = nand_to_mtd(chip);
bb77082f 3868 int busw;
f84674b8 3869 int i;
7f501f0a
BB		 3870 u8 *id_data = chip->id.data;
3871 u8 maf_id, dev_id;
1da177e4 3872
ef89a880
KB		 3873 /*
3874 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3875 * after power-up.
ef89a880 3876 */
73f907fd
BB		 3877 nand_reset(chip, 0);
3878
3879 /* Select the device */
3880 chip->select_chip(mtd, 0);
ef89a880 3881
1da177e4 3882 /* Send the command for reading device ID */
ace4dfee 3883 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3884
3885 /* Read manufacturer and device IDs */
7f501f0a
BB		 3886 maf_id = chip->read_byte(mtd);
3887 dev_id = chip->read_byte(mtd);
1da177e4 3888
8b6e50c9
BN		 3889 /*
3890 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3891 * interface concerns can cause random data which looks like a
3892 * possibly credible NAND flash to appear. If the two results do
3893 * not match, ignore the device completely.
3894 */
3895
3896 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3897
4aef9b78 3898 /* Read entire ID string */
5158bd55 3899 for (i = 0; i < ARRAY_SIZE(chip->id.data); i++)
426c457a 3900 id_data[i] = chip->read_byte(mtd);
ed8165c7 3901
7f501f0a 3902 if (id_data[0] != maf_id || id_data[1] != dev_id) {
20171642 3903 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
7f501f0a 3904 maf_id, dev_id, id_data[0], id_data[1]);
4722c0e9 3905 return -ENODEV;
ed8165c7
BD		 3906 }
3907
5158bd55 3908 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
7f501f0a 3909
abbe26d1
BB		 3910 /* Try to identify manufacturer */
3911 manufacturer = nand_get_manufacturer(maf_id);
3912 chip->manufacturer.desc = manufacturer;
3913
7aa65bfd 3914 if (!type)
5e81e88a
DW		 3915 type = nand_flash_ids;
3916
29a198a1
BB		 3917 /*
3918 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
3919 * override it.
3920 * This is required to make sure initial NAND bus width set by the
3921 * NAND controller driver is coherent with the real NAND bus width
3922 * (extracted by auto-detection code).
3923 */
3924 busw = chip->options & NAND_BUSWIDTH_16;
3925
3926 /*
3927 * The flag is only set (never cleared), reset it to its default value
3928 * before starting auto-detection.
3929 */
3930 chip->options &= ~NAND_BUSWIDTH_16;
3931
ec6e87e3
HS		 3932 for (; type->name != NULL; type++) {
3933 if (is_full_id_nand(type)) {
29a198a1 3934 if (find_full_id_nand(chip, type))
ec6e87e3 3935 goto ident_done;
7f501f0a 3936 } else if (dev_id == type->dev_id) {
db5b09f6 3937 break;
ec6e87e3
HS		 3938 }
3939 }
5e81e88a 3940
d1e1f4e4
FF		 3941 chip->onfi_version = 0;
3942 if (!type->name || !type->pagesize) {
35fc5195 3943 /* Check if the chip is ONFI compliant */
29a198a1 3944 if (nand_flash_detect_onfi(chip))
6fb277ba 3945 goto ident_done;
91361818
HS		 3946
3947 /* Check if the chip is JEDEC compliant */
29a198a1 3948 if (nand_flash_detect_jedec(chip))
91361818 3949 goto ident_done;
d1e1f4e4
FF		 3950 }
3951
5e81e88a 3952 if (!type->name)
4722c0e9 3953 return -ENODEV;
7aa65bfd 3954
ba0251fe
TG		 3955 if (!mtd->name)
3956 mtd->name = type->name;
3957
69423d99 3958 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3959
abbe26d1
BB		 3960 if (!type->pagesize)
3961 nand_manufacturer_detect(chip);
3962 else
29a198a1 3963 nand_decode_id(chip, type);
abbe26d1 3964
bf7a01bf
BN		 3965 /* Get chip options */
3966 chip->options |= type->options;
d1e1f4e4 3967
d1e1f4e4
FF		 3968ident_done:
3969
64b37b2a 3970 if (chip->options & NAND_BUSWIDTH_AUTO) {
29a198a1
BB		 3971 WARN_ON(busw & NAND_BUSWIDTH_16);
3972 nand_set_defaults(chip);
64b37b2a
MC		 3973 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3974 /*
3975 * Check, if buswidth is correct. Hardware drivers should set
3976 * chip correct!
3977 */
20171642 3978 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
7f501f0a 3979 maf_id, dev_id);
bcc678c2
BB		 3980 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
3981 mtd->name);
29a198a1
BB		 3982 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
3983 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
4722c0e9 3984 return -EINVAL;
7aa65bfd 3985 }
61b03bd7 3986
7f501f0a 3987 nand_decode_bbm_options(chip);
7e74c2d7 3988
7aa65bfd 3989 /* Calculate the address shift from the page size */
ace4dfee 3990 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3991 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3992 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3993
ace4dfee 3994 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3995 ffs(mtd->erasesize) - 1;
69423d99
AH		 3996 if (chip->chipsize & 0xffffffff)
3997 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3998 else {
3999 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4000 chip->chip_shift += 32 - 1;
4001 }
1da177e4 4002
26d9be11 4003 chip->badblockbits = 8;
49c50b97 4004 chip->erase = single_erase;
7aa65bfd 4005
8b6e50c9 4006 /* Do not replace user supplied command function! */
ace4dfee
TG		 4007 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4008 chip->cmdfunc = nand_command_lp;
7aa65bfd 4009
20171642 4010 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
7f501f0a 4011 maf_id, dev_id);
ffdac6cd
HS		 4012
4013 if (chip->onfi_version)
bcc678c2
BB		 4014 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4015 chip->onfi_params.model);
ffdac6cd 4016 else if (chip->jedec_version)
bcc678c2
BB		 4017 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4018 chip->jedec_params.model);
ffdac6cd 4019 else
bcc678c2
BB		 4020 pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
4021 type->name);
ffdac6cd 4022
3755a991 4023 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
3723e93c 4024 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3755a991 4025 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4722c0e9 4026 return 0;
7aa65bfd
TG		 4027}
4028
d48f62b9
BB		 4029static const char * const nand_ecc_modes[] = {
4030 [NAND_ECC_NONE] = "none",
4031 [NAND_ECC_SOFT] = "soft",
4032 [NAND_ECC_HW] = "hw",
4033 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
4034 [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
785818fa 4035 [NAND_ECC_ON_DIE] = "on-die",
d48f62b9
BB		 4036};
4037
4038static int of_get_nand_ecc_mode(struct device_node *np)
4039{
4040 const char *pm;
4041 int err, i;
4042
4043 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4044 if (err < 0)
4045 return err;
4046
4047 for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
4048 if (!strcasecmp(pm, nand_ecc_modes[i]))
4049 return i;
4050
ae211bcf
RM		 4051 /*
4052 * For backward compatibility we support few obsoleted values that don't
4053 * have their mappings into nand_ecc_modes_t anymore (they were merged
4054 * with other enums).
4055 */
4056 if (!strcasecmp(pm, "soft_bch"))
4057 return NAND_ECC_SOFT;
4058
d48f62b9
BB		 4059 return -ENODEV;
4060}
4061
ba4f46b2
RM		 4062static const char * const nand_ecc_algos[] = {
4063 [NAND_ECC_HAMMING] = "hamming",
4064 [NAND_ECC_BCH] = "bch",
4065};
4066
d48f62b9
BB		 4067static int of_get_nand_ecc_algo(struct device_node *np)
4068{
4069 const char *pm;
ba4f46b2 4070 int err, i;
d48f62b9 4071
ba4f46b2
RM		 4072 err = of_property_read_string(np, "nand-ecc-algo", &pm);
4073 if (!err) {
4074 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4075 if (!strcasecmp(pm, nand_ecc_algos[i]))
4076 return i;
4077 return -ENODEV;
4078 }
d48f62b9
BB		 4079
4080 /*
4081 * For backward compatibility we also read "nand-ecc-mode" checking
4082 * for some obsoleted values that were specifying ECC algorithm.
4083 */
4084 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4085 if (err < 0)
4086 return err;
4087
4088 if (!strcasecmp(pm, "soft"))
4089 return NAND_ECC_HAMMING;
4090 else if (!strcasecmp(pm, "soft_bch"))
4091 return NAND_ECC_BCH;
4092
4093 return -ENODEV;
4094}
4095
4096static int of_get_nand_ecc_step_size(struct device_node *np)
4097{
4098 int ret;
4099 u32 val;
4100
4101 ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
4102 return ret ? ret : val;
4103}
4104
4105static int of_get_nand_ecc_strength(struct device_node *np)
4106{
4107 int ret;
4108 u32 val;
4109
4110 ret = of_property_read_u32(np, "nand-ecc-strength", &val);
4111 return ret ? ret : val;
4112}
4113
4114static int of_get_nand_bus_width(struct device_node *np)
4115{
4116 u32 val;
4117
4118 if (of_property_read_u32(np, "nand-bus-width", &val))
4119 return 8;
4120
4121 switch (val) {
4122 case 8:
4123 case 16:
4124 return val;
4125 default:
4126 return -EIO;
4127 }
4128}
4129
4130static bool of_get_nand_on_flash_bbt(struct device_node *np)
4131{
4132 return of_property_read_bool(np, "nand-on-flash-bbt");
4133}
4134
7194a29a 4135static int nand_dt_init(struct nand_chip *chip)
5844feea 4136{
7194a29a 4137 struct device_node *dn = nand_get_flash_node(chip);
79082457 4138 int ecc_mode, ecc_algo, ecc_strength, ecc_step;
5844feea 4139
7194a29a
BB		 4140 if (!dn)
4141 return 0;
4142
5844feea
BN		 4143 if (of_get_nand_bus_width(dn) == 16)
4144 chip->options |= NAND_BUSWIDTH_16;
4145
4146 if (of_get_nand_on_flash_bbt(dn))
4147 chip->bbt_options |= NAND_BBT_USE_FLASH;
4148
4149 ecc_mode = of_get_nand_ecc_mode(dn);
79082457 4150 ecc_algo = of_get_nand_ecc_algo(dn);
5844feea
BN		 4151 ecc_strength = of_get_nand_ecc_strength(dn);
4152 ecc_step = of_get_nand_ecc_step_size(dn);
4153
5844feea
BN		 4154 if (ecc_mode >= 0)
4155 chip->ecc.mode = ecc_mode;
4156
79082457
RM		 4157 if (ecc_algo >= 0)
4158 chip->ecc.algo = ecc_algo;
4159
5844feea
BN		 4160 if (ecc_strength >= 0)
4161 chip->ecc.strength = ecc_strength;
4162
4163 if (ecc_step > 0)
4164 chip->ecc.size = ecc_step;
4165
ba78ee00
BB		 4166 if (of_property_read_bool(dn, "nand-ecc-maximize"))
4167 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4168
5844feea
BN		 4169 return 0;
4170}
4171
7aa65bfd 4172/**
3b85c321 4173 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4174 * @mtd: MTD device structure
4175 * @maxchips: number of chips to scan for
4176 * @table: alternative NAND ID table
7aa65bfd 4177 *
8b6e50c9
BN		 4178 * This is the first phase of the normal nand_scan() function. It reads the
4179 * flash ID and sets up MTD fields accordingly.
7aa65bfd
TG		 4180 *
4181 */
5e81e88a
DW		 4182int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4183 struct nand_flash_dev *table)
7aa65bfd 4184{
bb77082f 4185 int i, nand_maf_id, nand_dev_id;
862eba51 4186 struct nand_chip *chip = mtd_to_nand(mtd);
5844feea
BN		 4187 int ret;
4188
7194a29a
BB		 4189 ret = nand_dt_init(chip);
4190 if (ret)
4191 return ret;
7aa65bfd 4192
f7a8e38f
BN		 4193 if (!mtd->name && mtd->dev.parent)
4194 mtd->name = dev_name(mtd->dev.parent);
4195
76fe334f
AS		 4196 if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
4197 /*
4198 * Default functions assigned for chip_select() and
4199 * cmdfunc() both expect cmd_ctrl() to be populated,
4200 * so we need to check that that's the case
4201 */
4202 pr_err("chip.cmd_ctrl() callback is not provided");
4203 return -EINVAL;
4204 }
7aa65bfd 4205 /* Set the default functions */
29a198a1 4206 nand_set_defaults(chip);
7aa65bfd
TG		 4207
4208 /* Read the flash type */
7bb42799 4209 ret = nand_detect(chip, table);
4722c0e9 4210 if (ret) {
b1c6e6db 4211 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 4212 pr_warn("No NAND device found\n");
ace4dfee 4213 chip->select_chip(mtd, -1);
4722c0e9 4214 return ret;
1da177e4
LT		 4215 }
4216
7f501f0a
BB		 4217 nand_maf_id = chip->id.data[0];
4218 nand_dev_id = chip->id.data[1];
4219
07300164
HS		 4220 chip->select_chip(mtd, -1);
4221
7aa65bfd 4222 /* Check for a chip array */
e0c7d767 4223 for (i = 1; i < maxchips; i++) {
ef89a880 4224 /* See comment in nand_get_flash_type for reset */
73f907fd
BB		 4225 nand_reset(chip, i);
4226
4227 chip->select_chip(mtd, i);
1da177e4 4228 /* Send the command for reading device ID */
ace4dfee 4229 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 4230 /* Read manufacturer and device IDs */
ace4dfee 4231 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 4232 nand_dev_id != chip->read_byte(mtd)) {
4233 chip->select_chip(mtd, -1);
1da177e4 4234 break;
07300164
HS		 4235 }
4236 chip->select_chip(mtd, -1);
1da177e4
LT		 4237 }
4238 if (i > 1)
20171642 4239 pr_info("%d chips detected\n", i);
61b03bd7 4240
1da177e4 4241 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 4242 chip->numchips = i;
4243 mtd->size = i * chip->chipsize;
7aa65bfd 4244
3b85c321
DW		 4245 return 0;
4246}
7351d3a5 4247EXPORT_SYMBOL(nand_scan_ident);
3b85c321 4248
06f384c9
RM		 4249static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4250{
4251 struct nand_chip *chip = mtd_to_nand(mtd);
4252 struct nand_ecc_ctrl *ecc = &chip->ecc;
4253
e4225ae8 4254 if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
06f384c9
RM		 4255 return -EINVAL;
4256
4257 switch (ecc->algo) {
4258 case NAND_ECC_HAMMING:
4259 ecc->calculate = nand_calculate_ecc;
4260 ecc->correct = nand_correct_data;
4261 ecc->read_page = nand_read_page_swecc;
4262 ecc->read_subpage = nand_read_subpage;
4263 ecc->write_page = nand_write_page_swecc;
4264 ecc->read_page_raw = nand_read_page_raw;
4265 ecc->write_page_raw = nand_write_page_raw;
4266 ecc->read_oob = nand_read_oob_std;
4267 ecc->write_oob = nand_write_oob_std;
4268 if (!ecc->size)
4269 ecc->size = 256;
4270 ecc->bytes = 3;
4271 ecc->strength = 1;
4272 return 0;
4273 case NAND_ECC_BCH:
4274 if (!mtd_nand_has_bch()) {
4275 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4276 return -EINVAL;
4277 }
4278 ecc->calculate = nand_bch_calculate_ecc;
4279 ecc->correct = nand_bch_correct_data;
4280 ecc->read_page = nand_read_page_swecc;
4281 ecc->read_subpage = nand_read_subpage;
4282 ecc->write_page = nand_write_page_swecc;
4283 ecc->read_page_raw = nand_read_page_raw;
4284 ecc->write_page_raw = nand_write_page_raw;
4285 ecc->read_oob = nand_read_oob_std;
4286 ecc->write_oob = nand_write_oob_std;
8bbba481 4287
06f384c9
RM		 4288 /*
4289 * Board driver should supply ecc.size and ecc.strength
4290 * values to select how many bits are correctable.
4291 * Otherwise, default to 4 bits for large page devices.
4292 */
4293 if (!ecc->size && (mtd->oobsize >= 64)) {
4294 ecc->size = 512;
4295 ecc->strength = 4;
4296 }
4297
4298 /*
4299 * if no ecc placement scheme was provided pickup the default
4300 * large page one.
4301 */
4302 if (!mtd->ooblayout) {
4303 /* handle large page devices only */
4304 if (mtd->oobsize < 64) {
4305 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4306 return -EINVAL;
4307 }
4308
4309 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
8bbba481
BB		 4310
4311 }
4312
4313 /*
4314 * We can only maximize ECC config when the default layout is
4315 * used, otherwise we don't know how many bytes can really be
4316 * used.
4317 */
4318 if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
4319 ecc->options & NAND_ECC_MAXIMIZE) {
4320 int steps, bytes;
4321
4322 /* Always prefer 1k blocks over 512bytes ones */
4323 ecc->size = 1024;
4324 steps = mtd->writesize / ecc->size;
4325
4326 /* Reserve 2 bytes for the BBM */
4327 bytes = (mtd->oobsize - 2) / steps;
4328 ecc->strength = bytes * 8 / fls(8 * ecc->size);
06f384c9
RM		 4329 }
4330
4331 /* See nand_bch_init() for details. */
4332 ecc->bytes = 0;
4333 ecc->priv = nand_bch_init(mtd);
4334 if (!ecc->priv) {
4335 WARN(1, "BCH ECC initialization failed!\n");
4336 return -EINVAL;
4337 }
4338 return 0;
4339 default:
4340 WARN(1, "Unsupported ECC algorithm!\n");
4341 return -EINVAL;
4342 }
4343}
4344
2c8f8afa
MY		 4345/**
4346 * nand_check_ecc_caps - check the sanity of preset ECC settings
4347 * @chip: nand chip info structure
4348 * @caps: ECC caps info structure
4349 * @oobavail: OOB size that the ECC engine can use
4350 *
4351 * When ECC step size and strength are already set, check if they are supported
4352 * by the controller and the calculated ECC bytes fit within the chip's OOB.
4353 * On success, the calculated ECC bytes is set.
4354 */
4355int nand_check_ecc_caps(struct nand_chip *chip,
4356 const struct nand_ecc_caps *caps, int oobavail)
4357{
4358 struct mtd_info *mtd = nand_to_mtd(chip);
4359 const struct nand_ecc_step_info *stepinfo;
4360 int preset_step = chip->ecc.size;
4361 int preset_strength = chip->ecc.strength;
4362 int nsteps, ecc_bytes;
4363 int i, j;
4364
4365 if (WARN_ON(oobavail < 0))
4366 return -EINVAL;
4367
4368 if (!preset_step || !preset_strength)
4369 return -ENODATA;
4370
4371 nsteps = mtd->writesize / preset_step;
4372
4373 for (i = 0; i < caps->nstepinfos; i++) {
4374 stepinfo = &caps->stepinfos[i];
4375
4376 if (stepinfo->stepsize != preset_step)
4377 continue;
4378
4379 for (j = 0; j < stepinfo->nstrengths; j++) {
4380 if (stepinfo->strengths[j] != preset_strength)
4381 continue;
4382
4383 ecc_bytes = caps->calc_ecc_bytes(preset_step,
4384 preset_strength);
4385 if (WARN_ON_ONCE(ecc_bytes < 0))
4386 return ecc_bytes;
4387
4388 if (ecc_bytes * nsteps > oobavail) {
4389 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
4390 preset_step, preset_strength);
4391 return -ENOSPC;
4392 }
4393
4394 chip->ecc.bytes = ecc_bytes;
4395
4396 return 0;
4397 }
4398 }
4399
4400 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
4401 preset_step, preset_strength);
4402
4403 return -ENOTSUPP;
4404}
4405EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
4406
4407/**
4408 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
4409 * @chip: nand chip info structure
4410 * @caps: ECC engine caps info structure
4411 * @oobavail: OOB size that the ECC engine can use
4412 *
4413 * If a chip's ECC requirement is provided, try to meet it with the least
4414 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
4415 * On success, the chosen ECC settings are set.
4416 */
4417int nand_match_ecc_req(struct nand_chip *chip,
4418 const struct nand_ecc_caps *caps, int oobavail)
4419{
4420 struct mtd_info *mtd = nand_to_mtd(chip);
4421 const struct nand_ecc_step_info *stepinfo;
4422 int req_step = chip->ecc_step_ds;
4423 int req_strength = chip->ecc_strength_ds;
4424 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
4425 int best_step, best_strength, best_ecc_bytes;
4426 int best_ecc_bytes_total = INT_MAX;
4427 int i, j;
4428
4429 if (WARN_ON(oobavail < 0))
4430 return -EINVAL;
4431
4432 /* No information provided by the NAND chip */
4433 if (!req_step || !req_strength)
4434 return -ENOTSUPP;
4435
4436 /* number of correctable bits the chip requires in a page */
4437 req_corr = mtd->writesize / req_step * req_strength;
4438
4439 for (i = 0; i < caps->nstepinfos; i++) {
4440 stepinfo = &caps->stepinfos[i];
4441 step_size = stepinfo->stepsize;
4442
4443 for (j = 0; j < stepinfo->nstrengths; j++) {
4444 strength = stepinfo->strengths[j];
4445
4446 /*
4447 * If both step size and strength are smaller than the
4448 * chip's requirement, it is not easy to compare the
4449 * resulted reliability.
4450 */
4451 if (step_size < req_step && strength < req_strength)
4452 continue;
4453
4454 if (mtd->writesize % step_size)
4455 continue;
4456
4457 nsteps = mtd->writesize / step_size;
4458
4459 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4460 if (WARN_ON_ONCE(ecc_bytes < 0))
4461 continue;
4462 ecc_bytes_total = ecc_bytes * nsteps;
4463
4464 if (ecc_bytes_total > oobavail ||
4465 strength * nsteps < req_corr)
4466 continue;
4467
4468 /*
4469 * We assume the best is to meet the chip's requrement
4470 * with the least number of ECC bytes.
4471 */
4472 if (ecc_bytes_total < best_ecc_bytes_total) {
4473 best_ecc_bytes_total = ecc_bytes_total;
4474 best_step = step_size;
4475 best_strength = strength;
4476 best_ecc_bytes = ecc_bytes;
4477 }
4478 }
4479 }
4480
4481 if (best_ecc_bytes_total == INT_MAX)
4482 return -ENOTSUPP;
4483
4484 chip->ecc.size = best_step;
4485 chip->ecc.strength = best_strength;
4486 chip->ecc.bytes = best_ecc_bytes;
4487
4488 return 0;
4489}
4490EXPORT_SYMBOL_GPL(nand_match_ecc_req);
4491
4492/**
4493 * nand_maximize_ecc - choose the max ECC strength available
4494 * @chip: nand chip info structure
4495 * @caps: ECC engine caps info structure
4496 * @oobavail: OOB size that the ECC engine can use
4497 *
4498 * Choose the max ECC strength that is supported on the controller, and can fit
4499 * within the chip's OOB. On success, the chosen ECC settings are set.
4500 */
4501int nand_maximize_ecc(struct nand_chip *chip,
4502 const struct nand_ecc_caps *caps, int oobavail)
4503{
4504 struct mtd_info *mtd = nand_to_mtd(chip);
4505 const struct nand_ecc_step_info *stepinfo;
4506 int step_size, strength, nsteps, ecc_bytes, corr;
4507 int best_corr = 0;
4508 int best_step = 0;
4509 int best_strength, best_ecc_bytes;
4510 int i, j;
4511
4512 if (WARN_ON(oobavail < 0))
4513 return -EINVAL;
4514
4515 for (i = 0; i < caps->nstepinfos; i++) {
4516 stepinfo = &caps->stepinfos[i];
4517 step_size = stepinfo->stepsize;
4518
4519 /* If chip->ecc.size is already set, respect it */
4520 if (chip->ecc.size && step_size != chip->ecc.size)
4521 continue;
4522
4523 for (j = 0; j < stepinfo->nstrengths; j++) {
4524 strength = stepinfo->strengths[j];
4525
4526 if (mtd->writesize % step_size)
4527 continue;
4528
4529 nsteps = mtd->writesize / step_size;
4530
4531 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
4532 if (WARN_ON_ONCE(ecc_bytes < 0))
4533 continue;
4534
4535 if (ecc_bytes * nsteps > oobavail)
4536 continue;
4537
4538 corr = strength * nsteps;
4539
4540 /*
4541 * If the number of correctable bits is the same,
4542 * bigger step_size has more reliability.
4543 */
4544 if (corr > best_corr ||
4545 (corr == best_corr && step_size > best_step)) {
4546 best_corr = corr;
4547 best_step = step_size;
4548 best_strength = strength;
4549 best_ecc_bytes = ecc_bytes;
4550 }
4551 }
4552 }
4553
4554 if (!best_corr)
4555 return -ENOTSUPP;
4556
4557 chip->ecc.size = best_step;
4558 chip->ecc.strength = best_strength;
4559 chip->ecc.bytes = best_ecc_bytes;
4560
4561 return 0;
4562}
4563EXPORT_SYMBOL_GPL(nand_maximize_ecc);
4564
67a9ad9b
EG		 4565/*
4566 * Check if the chip configuration meet the datasheet requirements.
4567
4568 * If our configuration corrects A bits per B bytes and the minimum
4569 * required correction level is X bits per Y bytes, then we must ensure
4570 * both of the following are true:
4571 *
4572 * (1) A / B >= X / Y
4573 * (2) A >= X
4574 *
4575 * Requirement (1) ensures we can correct for the required bitflip density.
4576 * Requirement (2) ensures we can correct even when all bitflips are clumped
4577 * in the same sector.
4578 */
4579static bool nand_ecc_strength_good(struct mtd_info *mtd)
4580{
862eba51 4581 struct nand_chip *chip = mtd_to_nand(mtd);
67a9ad9b
EG		 4582 struct nand_ecc_ctrl *ecc = &chip->ecc;
4583 int corr, ds_corr;
4584
4585 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4586 /* Not enough information */
4587 return true;
4588
4589 /*
4590 * We get the number of corrected bits per page to compare
4591 * the correction density.
4592 */
4593 corr = (mtd->writesize * ecc->strength) / ecc->size;
4594 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4595
4596 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4597}
3b85c321 4598
3371d663
MG		 4599static bool invalid_ecc_page_accessors(struct nand_chip *chip)
4600{
4601 struct nand_ecc_ctrl *ecc = &chip->ecc;
4602
4603 if (nand_standard_page_accessors(ecc))
4604 return false;
4605
4606 /*
4607 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
4608 * controller driver implements all the page accessors because
4609 * default helpers are not suitable when the core does not
4610 * send the READ0/PAGEPROG commands.
4611 */
4612 return (!ecc->read_page || !ecc->write_page ||
4613 !ecc->read_page_raw || !ecc->write_page_raw ||
4614 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
4615 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
4616 ecc->hwctl && ecc->calculate));
4617}
4618
3b85c321
DW		 4619/**
4620 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 4621 * @mtd: MTD device structure
3b85c321 4622 *
8b6e50c9
BN		 4623 * This is the second phase of the normal nand_scan() function. It fills out
4624 * all the uninitialized function pointers with the defaults and scans for a
4625 * bad block table if appropriate.
3b85c321
DW		 4626 */
4627int nand_scan_tail(struct mtd_info *mtd)
4628{
862eba51 4629 struct nand_chip *chip = mtd_to_nand(mtd);
97de79e0 4630 struct nand_ecc_ctrl *ecc = &chip->ecc;
3deb9979 4631 struct nand_buffers *nbuf = NULL;
f84674b8 4632 int ret, i;
3b85c321 4633
e2414f4c 4634 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
11eaf6df 4635 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
78771049 4636 !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
f84674b8 4637 return -EINVAL;
78771049 4638 }
e2414f4c 4639
3371d663
MG		 4640 if (invalid_ecc_page_accessors(chip)) {
4641 pr_err("Invalid ECC page accessors setup\n");
f84674b8 4642 return -EINVAL;
3371d663
MG		 4643 }
4644
f02ea4e6 4645 if (!(chip->options & NAND_OWN_BUFFERS)) {
3deb9979 4646 nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL);
f84674b8
BB		 4647 if (!nbuf)
4648 return -ENOMEM;
3deb9979
MY		 4649
4650 nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL);
4651 if (!nbuf->ecccalc) {
4652 ret = -ENOMEM;
f84674b8 4653 goto err_free_nbuf;
3deb9979
MY		 4654 }
4655
4656 nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL);
4657 if (!nbuf->ecccode) {
4658 ret = -ENOMEM;
f84674b8 4659 goto err_free_nbuf;
3deb9979
MY		 4660 }
4661
4662 nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize,
4663 GFP_KERNEL);
4664 if (!nbuf->databuf) {
4665 ret = -ENOMEM;
f84674b8 4666 goto err_free_nbuf;
3deb9979 4667 }
f02ea4e6
HS		 4668
4669 chip->buffers = nbuf;
f84674b8
BB		 4670 } else if (!chip->buffers) {
4671 return -ENOMEM;
f02ea4e6 4672 }
4bf63fcb 4673
f84674b8
BB		 4674 /*
4675 * FIXME: some NAND manufacturer drivers expect the first die to be
4676 * selected when manufacturer->init() is called. They should be fixed
4677 * to explictly select the relevant die when interacting with the NAND
4678 * chip.
4679 */
4680 chip->select_chip(mtd, 0);
4681 ret = nand_manufacturer_init(chip);
4682 chip->select_chip(mtd, -1);
4683 if (ret)
4684 goto err_free_nbuf;
4685
7dcdcbef 4686 /* Set the internal oob buffer location, just after the page data */
784f4d5e 4687 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 4688
7aa65bfd 4689 /*
8b6e50c9 4690 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 4691 */
06f384c9 4692 if (!mtd->ooblayout &&
e4225ae8 4693 !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
61b03bd7 4694 switch (mtd->oobsize) {
1da177e4 4695 case 8:
1da177e4 4696 case 16:
41b207a7 4697 mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
1da177e4
LT		 4698 break;
4699 case 64:
81ec5364 4700 case 128:
6a623e07 4701 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops);
81ec5364 4702 break;
1da177e4 4703 default:
882fd157
MR		 4704 /*
4705 * Expose the whole OOB area to users if ECC_NONE
4706 * is passed. We could do that for all kind of
4707 * ->oobsize, but we must keep the old large/small
4708 * page with ECC layout when ->oobsize <= 128 for
4709 * compatibility reasons.
4710 */
4711 if (ecc->mode == NAND_ECC_NONE) {
4712 mtd_set_ooblayout(mtd,
4713 &nand_ooblayout_lp_ops);
4714 break;
4715 }
4716
11eaf6df
EG		 4717 WARN(1, "No oob scheme defined for oobsize %d\n",
4718 mtd->oobsize);
4719 ret = -EINVAL;
f84674b8 4720 goto err_nand_manuf_cleanup;
1da177e4
LT		 4721 }
4722 }
61b03bd7 4723
61b03bd7 4724 /*
8b6e50c9 4725 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 4726 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 4727 */
956e944c 4728
97de79e0 4729 switch (ecc->mode) {
6e0cb135
SN		 4730 case NAND_ECC_HW_OOB_FIRST:
4731 /* Similar to NAND_ECC_HW, but a separate read_page handle */
97de79e0 4732 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
11eaf6df
EG		 4733 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4734 ret = -EINVAL;
f84674b8 4735 goto err_nand_manuf_cleanup;
6e0cb135 4736 }
97de79e0
HS		 4737 if (!ecc->read_page)
4738 ecc->read_page = nand_read_page_hwecc_oob_first;
6e0cb135 4739
6dfc6d25 4740 case NAND_ECC_HW:
8b6e50c9 4741 /* Use standard hwecc read page function? */
97de79e0
HS		 4742 if (!ecc->read_page)
4743 ecc->read_page = nand_read_page_hwecc;
4744 if (!ecc->write_page)
4745 ecc->write_page = nand_write_page_hwecc;
4746 if (!ecc->read_page_raw)
4747 ecc->read_page_raw = nand_read_page_raw;
4748 if (!ecc->write_page_raw)
4749 ecc->write_page_raw = nand_write_page_raw;
4750 if (!ecc->read_oob)
4751 ecc->read_oob = nand_read_oob_std;
4752 if (!ecc->write_oob)
4753 ecc->write_oob = nand_write_oob_std;
4754 if (!ecc->read_subpage)
4755 ecc->read_subpage = nand_read_subpage;
44991b3d 4756 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
97de79e0 4757 ecc->write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4758
6dfc6d25 4759 case NAND_ECC_HW_SYNDROME:
97de79e0
HS		 4760 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4761 (!ecc->read_page ||
4762 ecc->read_page == nand_read_page_hwecc ||
4763 !ecc->write_page ||
4764 ecc->write_page == nand_write_page_hwecc)) {
11eaf6df
EG		 4765 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4766 ret = -EINVAL;
f84674b8 4767 goto err_nand_manuf_cleanup;
6dfc6d25 4768 }
8b6e50c9 4769 /* Use standard syndrome read/write page function? */
97de79e0
HS		 4770 if (!ecc->read_page)
4771 ecc->read_page = nand_read_page_syndrome;
4772 if (!ecc->write_page)
4773 ecc->write_page = nand_write_page_syndrome;
4774 if (!ecc->read_page_raw)
4775 ecc->read_page_raw = nand_read_page_raw_syndrome;
4776 if (!ecc->write_page_raw)
4777 ecc->write_page_raw = nand_write_page_raw_syndrome;
4778 if (!ecc->read_oob)
4779 ecc->read_oob = nand_read_oob_syndrome;
4780 if (!ecc->write_oob)
4781 ecc->write_oob = nand_write_oob_syndrome;
4782
4783 if (mtd->writesize >= ecc->size) {
4784 if (!ecc->strength) {
11eaf6df
EG		 4785 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4786 ret = -EINVAL;
f84674b8 4787 goto err_nand_manuf_cleanup;
e2788c98 4788 }
6dfc6d25 4789 break;
e2788c98 4790 }
2ac63d90
RM		 4791 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4792 ecc->size, mtd->writesize);
97de79e0 4793 ecc->mode = NAND_ECC_SOFT;
e9d4faed 4794 ecc->algo = NAND_ECC_HAMMING;
61b03bd7 4795
6dfc6d25 4796 case NAND_ECC_SOFT:
06f384c9
RM		 4797 ret = nand_set_ecc_soft_ops(mtd);
4798 if (ret) {
11eaf6df 4799 ret = -EINVAL;
f84674b8 4800 goto err_nand_manuf_cleanup;
193bd400
ID		 4801 }
4802 break;
4803
785818fa
TP		 4804 case NAND_ECC_ON_DIE:
4805 if (!ecc->read_page || !ecc->write_page) {
4806 WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
4807 ret = -EINVAL;
f84674b8 4808 goto err_nand_manuf_cleanup;
785818fa
TP		 4809 }
4810 if (!ecc->read_oob)
4811 ecc->read_oob = nand_read_oob_std;
4812 if (!ecc->write_oob)
4813 ecc->write_oob = nand_write_oob_std;
4814 break;
4815
61b03bd7 4816 case NAND_ECC_NONE:
2ac63d90 4817 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
97de79e0
HS		 4818 ecc->read_page = nand_read_page_raw;
4819 ecc->write_page = nand_write_page_raw;
4820 ecc->read_oob = nand_read_oob_std;
4821 ecc->read_page_raw = nand_read_page_raw;
4822 ecc->write_page_raw = nand_write_page_raw;
4823 ecc->write_oob = nand_write_oob_std;
4824 ecc->size = mtd->writesize;
4825 ecc->bytes = 0;
4826 ecc->strength = 0;
1da177e4 4827 break;
956e944c 4828
1da177e4 4829 default:
11eaf6df
EG		 4830 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4831 ret = -EINVAL;
f84674b8 4832 goto err_nand_manuf_cleanup;
1da177e4 4833 }
61b03bd7 4834
9ce244b3 4835 /* For many systems, the standard OOB write also works for raw */
97de79e0
HS		 4836 if (!ecc->read_oob_raw)
4837 ecc->read_oob_raw = ecc->read_oob;
4838 if (!ecc->write_oob_raw)
4839 ecc->write_oob_raw = ecc->write_oob;
9ce244b3 4840
846031d3 4841 /* propagate ecc info to mtd_info */
846031d3
BB		 4842 mtd->ecc_strength = ecc->strength;
4843 mtd->ecc_step_size = ecc->size;
67a9ad9b 4844
7aa65bfd
TG		 4845 /*
4846 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4847 * mode.
7aa65bfd 4848 */
97de79e0
HS		 4849 ecc->steps = mtd->writesize / ecc->size;
4850 if (ecc->steps * ecc->size != mtd->writesize) {
11eaf6df
EG		 4851 WARN(1, "Invalid ECC parameters\n");
4852 ret = -EINVAL;
f84674b8 4853 goto err_nand_manuf_cleanup;
1da177e4 4854 }
97de79e0 4855 ecc->total = ecc->steps * ecc->bytes;
79e0348c
MY		 4856 if (ecc->total > mtd->oobsize) {
4857 WARN(1, "Total number of ECC bytes exceeded oobsize\n");
4858 ret = -EINVAL;
f84674b8 4859 goto err_nand_manuf_cleanup;
79e0348c 4860 }
61b03bd7 4861
846031d3
BB		 4862 /*
4863 * The number of bytes available for a client to place data into
4864 * the out of band area.
4865 */
4866 ret = mtd_ooblayout_count_freebytes(mtd);
4867 if (ret < 0)
4868 ret = 0;
4869
4870 mtd->oobavail = ret;
4871
4872 /* ECC sanity check: warn if it's too weak */
4873 if (!nand_ecc_strength_good(mtd))
4874 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4875 mtd->name);
4876
8b6e50c9 4877 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
1d0ed69d 4878 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
97de79e0 4879 switch (ecc->steps) {
29072b96
TG		 4880 case 2:
4881 mtd->subpage_sft = 1;
4882 break;
4883 case 4:
4884 case 8:
81ec5364 4885 case 16:
29072b96
TG		 4886 mtd->subpage_sft = 2;
4887 break;
4888 }
4889 }
4890 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4891
04bbd0ea 4892 /* Initialize state */
ace4dfee 4893 chip->state = FL_READY;
1da177e4 4894
1da177e4 4895 /* Invalidate the pagebuffer reference */
ace4dfee 4896 chip->pagebuf = -1;
1da177e4 4897
a5ff4f10 4898 /* Large page NAND with SOFT_ECC should support subpage reads */
4007e2d1
RL		 4899 switch (ecc->mode) {
4900 case NAND_ECC_SOFT:
4007e2d1
RL		 4901 if (chip->page_shift > 9)
4902 chip->options |= NAND_SUBPAGE_READ;
4903 break;
4904
4905 default:
4906 break;
4907 }
a5ff4f10 4908
1da177e4 4909 /* Fill in remaining MTD driver data */
963d1c28 4910 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
93edbad6
ML		 4911 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4912 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4913 mtd->_erase = nand_erase;
4914 mtd->_point = NULL;
4915 mtd->_unpoint = NULL;
4916 mtd->_read = nand_read;
4917 mtd->_write = nand_write;
4918 mtd->_panic_write = panic_nand_write;
4919 mtd->_read_oob = nand_read_oob;
4920 mtd->_write_oob = nand_write_oob;
4921 mtd->_sync = nand_sync;
4922 mtd->_lock = NULL;
4923 mtd->_unlock = NULL;
4924 mtd->_suspend = nand_suspend;
4925 mtd->_resume = nand_resume;
72ea4036 4926 mtd->_reboot = nand_shutdown;
8471bb73 4927 mtd->_block_isreserved = nand_block_isreserved;
3c3c10bb
AB		 4928 mtd->_block_isbad = nand_block_isbad;
4929 mtd->_block_markbad = nand_block_markbad;
5671842f 4930 mtd->_max_bad_blocks = nand_max_bad_blocks;
cbcab65a 4931 mtd->writebufsize = mtd->writesize;
1da177e4 4932
ea3b2ea2
SL		 4933 /*
4934 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4935 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4936 * properly set.
4937 */
4938 if (!mtd->bitflip_threshold)
240181fd 4939 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
1da177e4 4940
f84674b8
BB		 4941 /* Initialize the ->data_interface field. */
4942 ret = nand_init_data_interface(chip);
4943 if (ret)
4944 goto err_nand_manuf_cleanup;
4945
4946 /* Enter fastest possible mode on all dies. */
4947 for (i = 0; i < chip->numchips; i++) {
4948 chip->select_chip(mtd, i);
4949 ret = nand_setup_data_interface(chip, i);
4950 chip->select_chip(mtd, -1);
4951
4952 if (ret)
4953 goto err_nand_data_iface_cleanup;
4954 }
4955
0040bf38 4956 /* Check, if we should skip the bad block table scan */
ace4dfee 4957 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4958 return 0;
1da177e4
LT		 4959
4960 /* Build bad block table */
44d4182e
BN		 4961 ret = chip->scan_bbt(mtd);
4962 if (ret)
f84674b8
BB		 4963 goto err_nand_data_iface_cleanup;
4964
44d4182e
BN		 4965 return 0;
4966
f84674b8
BB		 4967err_nand_data_iface_cleanup:
4968 nand_release_data_interface(chip);
4969
4970err_nand_manuf_cleanup:
4971 nand_manufacturer_cleanup(chip);
4972
4973err_free_nbuf:
3deb9979
MY		 4974 if (nbuf) {
4975 kfree(nbuf->databuf);
4976 kfree(nbuf->ecccode);
4977 kfree(nbuf->ecccalc);
4978 kfree(nbuf);
4979 }
78771049 4980
11eaf6df 4981 return ret;
1da177e4 4982}
7351d3a5 4983EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4984
8b6e50c9
BN		 4985/*
4986 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4987 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4988 * to call us from in-kernel code if the core NAND support is modular.
4989 */
3b85c321
DW		 4990#ifdef MODULE
4991#define caller_is_module() (1)
4992#else
4993#define caller_is_module() \
a6e6abd5 4994 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4995#endif
4996
4997/**
4998 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4999 * @mtd: MTD device structure
5000 * @maxchips: number of chips to scan for
3b85c321 5001 *
8b6e50c9
BN		 5002 * This fills out all the uninitialized function pointers with the defaults.
5003 * The flash ID is read and the mtd/chip structures are filled with the
20c07a5b 5004 * appropriate values.
3b85c321
DW		 5005 */
5006int nand_scan(struct mtd_info *mtd, int maxchips)
5007{
5008 int ret;
5009
5e81e88a 5010 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 5011 if (!ret)
5012 ret = nand_scan_tail(mtd);
5013 return ret;
5014}
7351d3a5 5015EXPORT_SYMBOL(nand_scan);
3b85c321 5016
1da177e4 5017/**
d44154f9
RW		 5018 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
5019 * @chip: NAND chip object
8b6e50c9 5020 */
d44154f9 5021void nand_cleanup(struct nand_chip *chip)
1da177e4 5022{
e4225ae8 5023 if (chip->ecc.mode == NAND_ECC_SOFT &&
06f384c9 5024 chip->ecc.algo == NAND_ECC_BCH)
193bd400
ID		 5025 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
5026
d8e725dd
BB		 5027 nand_release_data_interface(chip);
5028
fa671646 5029 /* Free bad block table memory */
ace4dfee 5030 kfree(chip->bbt);
3deb9979
MY		 5031 if (!(chip->options & NAND_OWN_BUFFERS) && chip->buffers) {
5032 kfree(chip->buffers->databuf);
5033 kfree(chip->buffers->ecccode);
5034 kfree(chip->buffers->ecccalc);
4bf63fcb 5035 kfree(chip->buffers);
3deb9979 5036 }
58373ff0
BN		 5037
5038 /* Free bad block descriptor memory */
5039 if (chip->badblock_pattern && chip->badblock_pattern->options
5040 & NAND_BBT_DYNAMICSTRUCT)
5041 kfree(chip->badblock_pattern);
abbe26d1
BB		 5042
5043 /* Free manufacturer priv data. */
5044 nand_manufacturer_cleanup(chip);
1da177e4 5045}
d44154f9
RW		 5046EXPORT_SYMBOL_GPL(nand_cleanup);
5047
5048/**
5049 * nand_release - [NAND Interface] Unregister the MTD device and free resources
5050 * held by the NAND device
5051 * @mtd: MTD device structure
5052 */
5053void nand_release(struct mtd_info *mtd)
5054{
5055 mtd_device_unregister(mtd);
5056 nand_cleanup(mtd_to_nand(mtd));
5057}
e0c7d767 5058EXPORT_SYMBOL_GPL(nand_release);
8fe833c1 5059
e0c7d767 5060MODULE_LICENSE("GPL");
7351d3a5
FF		 5061MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
5062MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 5063MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)