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mtd: nand: fsmc: update of OF support
[linux-2.6-block.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
38#include <linux/types.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/nand_ecc.h>
193bd400 42#include <linux/mtd/nand_bch.h>
1da177e4
LT		 43#include <linux/interrupt.h>
44#include <linux/bitops.h>
8fe833c1 45#include <linux/leds.h>
7351d3a5 46#include <linux/io.h>
1da177e4 47#include <linux/mtd/partitions.h>
1da177e4
LT		 48
49/* Define default oob placement schemes for large and small page devices */
5bd34c09 50static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 51 .eccbytes = 3,
52 .eccpos = {0, 1, 2},
5bd34c09
TG		 53 .oobfree = {
54 {.offset = 3,
55 .length = 2},
56 {.offset = 6,
f8ac0414 57 .length = 2} }
1da177e4
LT		 58};
59
5bd34c09 60static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 61 .eccbytes = 6,
62 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 63 .oobfree = {
64 {.offset = 8,
f8ac0414 65 . length = 8} }
1da177e4
LT		 66};
67
5bd34c09 68static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 69 .eccbytes = 24,
70 .eccpos = {
e0c7d767
DW		 71 40, 41, 42, 43, 44, 45, 46, 47,
72 48, 49, 50, 51, 52, 53, 54, 55,
73 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 74 .oobfree = {
75 {.offset = 2,
f8ac0414 76 .length = 38} }
1da177e4
LT		 77};
78
81ec5364
TG		 79static struct nand_ecclayout nand_oob_128 = {
80 .eccbytes = 48,
81 .eccpos = {
82 80, 81, 82, 83, 84, 85, 86, 87,
83 88, 89, 90, 91, 92, 93, 94, 95,
84 96, 97, 98, 99, 100, 101, 102, 103,
85 104, 105, 106, 107, 108, 109, 110, 111,
86 112, 113, 114, 115, 116, 117, 118, 119,
87 120, 121, 122, 123, 124, 125, 126, 127},
88 .oobfree = {
89 {.offset = 2,
f8ac0414 90 .length = 78} }
81ec5364
TG		 91};
92
6a8214aa 93static int nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 94
8593fbc6
TG		 95static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
96 struct mtd_oob_ops *ops);
97
d470a97c 98/*
8e87d782 99 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 100 * compiled away when LED support is disabled.
101 */
102DEFINE_LED_TRIGGER(nand_led_trigger);
103
6fe5a6ac
VS		 104static int check_offs_len(struct mtd_info *mtd,
105 loff_t ofs, uint64_t len)
106{
107 struct nand_chip *chip = mtd->priv;
108 int ret = 0;
109
110 /* Start address must align on block boundary */
111 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 112 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 113 ret = -EINVAL;
114 }
115
116 /* Length must align on block boundary */
117 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 118 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 119 ret = -EINVAL;
120 }
121
6fe5a6ac
VS		 122 return ret;
123}
124
1da177e4
LT		 125/**
126 * nand_release_device - [GENERIC] release chip
8b6e50c9 127 * @mtd: MTD device structure
61b03bd7 128 *
b0bb6903 129 * Release chip lock and wake up anyone waiting on the device.
1da177e4 130 */
e0c7d767 131static void nand_release_device(struct mtd_info *mtd)
1da177e4 132{
ace4dfee 133 struct nand_chip *chip = mtd->priv;
1da177e4 134
a36ed299 135 /* Release the controller and the chip */
ace4dfee
TG		 136 spin_lock(&chip->controller->lock);
137 chip->controller->active = NULL;
138 chip->state = FL_READY;
139 wake_up(&chip->controller->wq);
140 spin_unlock(&chip->controller->lock);
1da177e4
LT		 141}
142
143/**
144 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 145 * @mtd: MTD device structure
1da177e4 146 *
7854d3f7 147 * Default read function for 8bit buswidth
1da177e4 148 */
58dd8f2b 149static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 150{
ace4dfee
TG		 151 struct nand_chip *chip = mtd->priv;
152 return readb(chip->IO_ADDR_R);
1da177e4
LT		 153}
154
1da177e4 155/**
064a7694 156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
7854d3f7 157 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 158 * @mtd: MTD device structure
1da177e4 159 *
7854d3f7
BN		 160 * Default read function for 16bit buswidth with endianness conversion.
161 *
1da177e4 162 */
58dd8f2b 163static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 164{
ace4dfee
TG		 165 struct nand_chip *chip = mtd->priv;
166 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 167}
168
1da177e4
LT		 169/**
170 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 171 * @mtd: MTD device structure
1da177e4 172 *
7854d3f7 173 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 174 */
175static u16 nand_read_word(struct mtd_info *mtd)
176{
ace4dfee
TG		 177 struct nand_chip *chip = mtd->priv;
178 return readw(chip->IO_ADDR_R);
1da177e4
LT		 179}
180
1da177e4
LT		 181/**
182 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 183 * @mtd: MTD device structure
184 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 185 *
186 * Default select function for 1 chip devices.
187 */
ace4dfee 188static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 189{
ace4dfee
TG		 190 struct nand_chip *chip = mtd->priv;
191
192 switch (chipnr) {
1da177e4 193 case -1:
ace4dfee 194 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 195 break;
196 case 0:
1da177e4
LT		 197 break;
198
199 default:
200 BUG();
201 }
202}
203
204/**
205 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 206 * @mtd: MTD device structure
207 * @buf: data buffer
208 * @len: number of bytes to write
1da177e4 209 *
7854d3f7 210 * Default write function for 8bit buswidth.
1da177e4 211 */
58dd8f2b 212static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 213{
ace4dfee 214 struct nand_chip *chip = mtd->priv;
1da177e4 215
76413839 216 iowrite8_rep(chip->IO_ADDR_W, buf, len);
1da177e4
LT		 217}
218
219/**
61b03bd7 220 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 221 * @mtd: MTD device structure
222 * @buf: buffer to store date
223 * @len: number of bytes to read
1da177e4 224 *
7854d3f7 225 * Default read function for 8bit buswidth.
1da177e4 226 */
58dd8f2b 227static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 228{
ace4dfee 229 struct nand_chip *chip = mtd->priv;
1da177e4 230
76413839 231 ioread8_rep(chip->IO_ADDR_R, buf, len);
1da177e4
LT		 232}
233
1da177e4
LT		 234/**
235 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 236 * @mtd: MTD device structure
237 * @buf: data buffer
238 * @len: number of bytes to write
1da177e4 239 *
7854d3f7 240 * Default write function for 16bit buswidth.
1da177e4 241 */
58dd8f2b 242static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4 243{
ace4dfee 244 struct nand_chip *chip = mtd->priv;
1da177e4 245 u16 *p = (u16 *) buf;
61b03bd7 246
76413839 247 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
1da177e4
LT		 248}
249
250/**
61b03bd7 251 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 252 * @mtd: MTD device structure
253 * @buf: buffer to store date
254 * @len: number of bytes to read
1da177e4 255 *
7854d3f7 256 * Default read function for 16bit buswidth.
1da177e4 257 */
58dd8f2b 258static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4 259{
ace4dfee 260 struct nand_chip *chip = mtd->priv;
1da177e4 261 u16 *p = (u16 *) buf;
1da177e4 262
76413839 263 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
1da177e4
LT		 264}
265
1da177e4
LT		 266/**
267 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 268 * @mtd: MTD device structure
269 * @ofs: offset from device start
270 * @getchip: 0, if the chip is already selected
1da177e4 271 *
61b03bd7 272 * Check, if the block is bad.
1da177e4
LT		 273 */
274static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
275{
cdbec050 276 int page, chipnr, res = 0, i = 0;
ace4dfee 277 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 278 u16 bad;
279
5fb1549d 280 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 281 ofs += mtd->erasesize - mtd->writesize;
282
1a12f46a
TK		 283 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
284
1da177e4 285 if (getchip) {
ace4dfee 286 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 287
6a8214aa 288 nand_get_device(mtd, FL_READING);
1da177e4
LT		 289
290 /* Select the NAND device */
ace4dfee 291 chip->select_chip(mtd, chipnr);
1a12f46a 292 }
1da177e4 293
cdbec050
BN		 294 do {
295 if (chip->options & NAND_BUSWIDTH_16) {
296 chip->cmdfunc(mtd, NAND_CMD_READOOB,
297 chip->badblockpos & 0xFE, page);
298 bad = cpu_to_le16(chip->read_word(mtd));
299 if (chip->badblockpos & 0x1)
300 bad >>= 8;
301 else
302 bad &= 0xFF;
303 } else {
304 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
305 page);
306 bad = chip->read_byte(mtd);
307 }
308
309 if (likely(chip->badblockbits == 8))
310 res = bad != 0xFF;
e0b58d0a 311 else
cdbec050
BN		 312 res = hweight8(bad) < chip->badblockbits;
313 ofs += mtd->writesize;
314 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
315 i++;
316 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 317
b0bb6903
HS		 318 if (getchip) {
319 chip->select_chip(mtd, -1);
1da177e4 320 nand_release_device(mtd);
b0bb6903 321 }
61b03bd7 322
1da177e4
LT		 323 return res;
324}
325
326/**
327 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 328 * @mtd: MTD device structure
329 * @ofs: offset from device start
1da177e4 330 *
8b6e50c9 331 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 332 * specific driver. We try operations in the following order, according to our
333 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
334 * (1) erase the affected block, to allow OOB marker to be written cleanly
335 * (2) update in-memory BBT
336 * (3) write bad block marker to OOB area of affected block
337 * (4) update flash-based BBT
338 * Note that we retain the first error encountered in (3) or (4), finish the
339 * procedures, and dump the error in the end.
1da177e4
LT		 340*/
341static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
342{
ace4dfee 343 struct nand_chip *chip = mtd->priv;
58dd8f2b 344 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 345 int block, res, ret = 0, i = 0;
346 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 347
e2414f4c 348 if (write_oob) {
00918429
BN		 349 struct erase_info einfo;
350
351 /* Attempt erase before marking OOB */
352 memset(&einfo, 0, sizeof(einfo));
353 einfo.mtd = mtd;
354 einfo.addr = ofs;
355 einfo.len = 1 << chip->phys_erase_shift;
356 nand_erase_nand(mtd, &einfo, 0);
357 }
358
1da177e4 359 /* Get block number */
4226b510 360 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 361 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 362 if (chip->bbt)
363 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 364
e2414f4c
BN		 365 /* Write bad block marker to OOB */
366 if (write_oob) {
4a89ff88 367 struct mtd_oob_ops ops;
df698621 368 loff_t wr_ofs = ofs;
4a89ff88 369
6a8214aa 370 nand_get_device(mtd, FL_WRITING);
f1a28c02 371
4a89ff88
BN		 372 ops.datbuf = NULL;
373 ops.oobbuf = buf;
85443319
BN		 374 ops.ooboffs = chip->badblockpos;
375 if (chip->options & NAND_BUSWIDTH_16) {
376 ops.ooboffs &= ~0x01;
377 ops.len = ops.ooblen = 2;
378 } else {
379 ops.len = ops.ooblen = 1;
380 }
23b1a99b 381 ops.mode = MTD_OPS_PLACE_OOB;
df698621 382
e2414f4c 383 /* Write to first/last page(s) if necessary */
df698621
BN		 384 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
385 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 386 do {
e2414f4c
BN		 387 res = nand_do_write_oob(mtd, wr_ofs, &ops);
388 if (!ret)
389 ret = res;
02ed70bb 390
02ed70bb 391 i++;
df698621 392 wr_ofs += mtd->writesize;
e2414f4c 393 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 394
c0b8ba7b 395 nand_release_device(mtd);
f1a28c02 396 }
e2414f4c
BN		 397
398 /* Update flash-based bad block table */
399 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
400 res = nand_update_bbt(mtd, ofs);
401 if (!ret)
402 ret = res;
403 }
404
f1a28c02
TG		 405 if (!ret)
406 mtd->ecc_stats.badblocks++;
c0b8ba7b 407
f1a28c02 408 return ret;
1da177e4
LT		 409}
410
61b03bd7 411/**
1da177e4 412 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 413 * @mtd: MTD device structure
1da177e4 414 *
8b6e50c9
BN		 415 * Check, if the device is write protected. The function expects, that the
416 * device is already selected.
1da177e4 417 */
e0c7d767 418static int nand_check_wp(struct mtd_info *mtd)
1da177e4 419{
ace4dfee 420 struct nand_chip *chip = mtd->priv;
93edbad6 421
8b6e50c9 422 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 423 if (chip->options & NAND_BROKEN_XD)
424 return 0;
425
1da177e4 426 /* Check the WP bit */
ace4dfee
TG		 427 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
428 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 429}
430
431/**
432 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 433 * @mtd: MTD device structure
434 * @ofs: offset from device start
435 * @getchip: 0, if the chip is already selected
436 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 437 *
438 * Check, if the block is bad. Either by reading the bad block table or
439 * calling of the scan function.
440 */
2c0a2bed
TG		 441static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
442 int allowbbt)
1da177e4 443{
ace4dfee 444 struct nand_chip *chip = mtd->priv;
61b03bd7 445
ace4dfee
TG		 446 if (!chip->bbt)
447 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 448
1da177e4 449 /* Return info from the table */
e0c7d767 450 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 451}
452
2af7c653
SK		 453/**
454 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 455 * @mtd: MTD device structure
456 * @timeo: Timeout
2af7c653
SK		 457 *
458 * Helper function for nand_wait_ready used when needing to wait in interrupt
459 * context.
460 */
461static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
462{
463 struct nand_chip *chip = mtd->priv;
464 int i;
465
466 /* Wait for the device to get ready */
467 for (i = 0; i < timeo; i++) {
468 if (chip->dev_ready(mtd))
469 break;
470 touch_softlockup_watchdog();
471 mdelay(1);
472 }
473}
474
7854d3f7 475/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 476void nand_wait_ready(struct mtd_info *mtd)
3b88775c 477{
ace4dfee 478 struct nand_chip *chip = mtd->priv;
ca6a2489 479 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 480
2af7c653
SK		 481 /* 400ms timeout */
482 if (in_interrupt() || oops_in_progress)
483 return panic_nand_wait_ready(mtd, 400);
484
8fe833c1 485 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 486 /* Wait until command is processed or timeout occurs */
3b88775c 487 do {
ace4dfee 488 if (chip->dev_ready(mtd))
8fe833c1 489 break;
8446f1d3 490 touch_softlockup_watchdog();
61b03bd7 491 } while (time_before(jiffies, timeo));
8fe833c1 492 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 493}
4b648b02 494EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 495
1da177e4
LT		 496/**
497 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 498 * @mtd: MTD device structure
499 * @command: the command to be sent
500 * @column: the column address for this command, -1 if none
501 * @page_addr: the page address for this command, -1 if none
1da177e4 502 *
8b6e50c9 503 * Send command to NAND device. This function is used for small page devices
51148f1f 504 * (512 Bytes per page).
1da177e4 505 */
7abd3ef9
TG		 506static void nand_command(struct mtd_info *mtd, unsigned int command,
507 int column, int page_addr)
1da177e4 508{
ace4dfee 509 register struct nand_chip *chip = mtd->priv;
7abd3ef9 510 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 511
8b6e50c9 512 /* Write out the command to the device */
1da177e4
LT		 513 if (command == NAND_CMD_SEQIN) {
514 int readcmd;
515
28318776 516 if (column >= mtd->writesize) {
1da177e4 517 /* OOB area */
28318776 518 column -= mtd->writesize;
1da177e4
LT		 519 readcmd = NAND_CMD_READOOB;
520 } else if (column < 256) {
521 /* First 256 bytes --> READ0 */
522 readcmd = NAND_CMD_READ0;
523 } else {
524 column -= 256;
525 readcmd = NAND_CMD_READ1;
526 }
ace4dfee 527 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 528 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 529 }
ace4dfee 530 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 531
8b6e50c9 532 /* Address cycle, when necessary */
7abd3ef9
TG		 533 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
534 /* Serially input address */
535 if (column != -1) {
536 /* Adjust columns for 16 bit buswidth */
ace4dfee 537 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 538 column >>= 1;
ace4dfee 539 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 540 ctrl &= ~NAND_CTRL_CHANGE;
541 }
542 if (page_addr != -1) {
ace4dfee 543 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 544 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 545 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 546 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 547 if (chip->chipsize > (32 << 20))
548 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 549 }
ace4dfee 550 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 551
552 /*
8b6e50c9
BN		 553 * Program and erase have their own busy handlers status and sequential
554 * in needs no delay
e0c7d767 555 */
1da177e4 556 switch (command) {
61b03bd7 557
1da177e4
LT		 558 case NAND_CMD_PAGEPROG:
559 case NAND_CMD_ERASE1:
560 case NAND_CMD_ERASE2:
561 case NAND_CMD_SEQIN:
562 case NAND_CMD_STATUS:
563 return;
564
565 case NAND_CMD_RESET:
ace4dfee 566 if (chip->dev_ready)
1da177e4 567 break;
ace4dfee
TG		 568 udelay(chip->chip_delay);
569 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 570 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 571 chip->cmd_ctrl(mtd,
572 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 573 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
574 ;
1da177e4
LT		 575 return;
576
e0c7d767 577 /* This applies to read commands */
1da177e4 578 default:
61b03bd7 579 /*
1da177e4
LT		 580 * If we don't have access to the busy pin, we apply the given
581 * command delay
e0c7d767 582 */
ace4dfee
TG		 583 if (!chip->dev_ready) {
584 udelay(chip->chip_delay);
1da177e4 585 return;
61b03bd7 586 }
1da177e4 587 }
8b6e50c9
BN		 588 /*
589 * Apply this short delay always to ensure that we do wait tWB in
590 * any case on any machine.
591 */
e0c7d767 592 ndelay(100);
3b88775c
TG		 593
594 nand_wait_ready(mtd);
1da177e4
LT		 595}
596
597/**
598 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 599 * @mtd: MTD device structure
600 * @command: the command to be sent
601 * @column: the column address for this command, -1 if none
602 * @page_addr: the page address for this command, -1 if none
1da177e4 603 *
7abd3ef9 604 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 605 * devices. We don't have the separate regions as we have in the small page
606 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 607 */
7abd3ef9
TG		 608static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
609 int column, int page_addr)
1da177e4 610{
ace4dfee 611 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 612
613 /* Emulate NAND_CMD_READOOB */
614 if (command == NAND_CMD_READOOB) {
28318776 615 column += mtd->writesize;
1da177e4
LT		 616 command = NAND_CMD_READ0;
617 }
61b03bd7 618
7abd3ef9 619 /* Command latch cycle */
fb066ada 620 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 621
622 if (column != -1 || page_addr != -1) {
7abd3ef9 623 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 624
625 /* Serially input address */
626 if (column != -1) {
627 /* Adjust columns for 16 bit buswidth */
ace4dfee 628 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 629 column >>= 1;
ace4dfee 630 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 631 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 632 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 633 }
1da177e4 634 if (page_addr != -1) {
ace4dfee
TG		 635 chip->cmd_ctrl(mtd, page_addr, ctrl);
636 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 637 NAND_NCE | NAND_ALE);
1da177e4 638 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 639 if (chip->chipsize > (128 << 20))
640 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 641 NAND_NCE | NAND_ALE);
1da177e4 642 }
1da177e4 643 }
ace4dfee 644 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 645
646 /*
8b6e50c9
BN		 647 * Program and erase have their own busy handlers status, sequential
648 * in, and deplete1 need no delay.
30f464b7 649 */
1da177e4 650 switch (command) {
61b03bd7 651
1da177e4
LT		 652 case NAND_CMD_CACHEDPROG:
653 case NAND_CMD_PAGEPROG:
654 case NAND_CMD_ERASE1:
655 case NAND_CMD_ERASE2:
656 case NAND_CMD_SEQIN:
7bc3312b 657 case NAND_CMD_RNDIN:
1da177e4 658 case NAND_CMD_STATUS:
30f464b7 659 return;
1da177e4
LT		 660
661 case NAND_CMD_RESET:
ace4dfee 662 if (chip->dev_ready)
1da177e4 663 break;
ace4dfee 664 udelay(chip->chip_delay);
12efdde3
TG		 665 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
666 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
667 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
668 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 669 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
670 ;
1da177e4
LT		 671 return;
672
7bc3312b
TG		 673 case NAND_CMD_RNDOUT:
674 /* No ready / busy check necessary */
675 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
676 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
677 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
678 NAND_NCE | NAND_CTRL_CHANGE);
679 return;
680
1da177e4 681 case NAND_CMD_READ0:
12efdde3
TG		 682 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
683 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
684 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
685 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 686
e0c7d767 687 /* This applies to read commands */
1da177e4 688 default:
61b03bd7 689 /*
1da177e4 690 * If we don't have access to the busy pin, we apply the given
8b6e50c9 691 * command delay.
e0c7d767 692 */
ace4dfee
TG		 693 if (!chip->dev_ready) {
694 udelay(chip->chip_delay);
1da177e4 695 return;
61b03bd7 696 }
1da177e4 697 }
3b88775c 698
8b6e50c9
BN		 699 /*
700 * Apply this short delay always to ensure that we do wait tWB in
701 * any case on any machine.
702 */
e0c7d767 703 ndelay(100);
3b88775c
TG		 704
705 nand_wait_ready(mtd);
1da177e4
LT		 706}
707
2af7c653
SK		 708/**
709 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 710 * @chip: the nand chip descriptor
711 * @mtd: MTD device structure
712 * @new_state: the state which is requested
2af7c653
SK		 713 *
714 * Used when in panic, no locks are taken.
715 */
716static void panic_nand_get_device(struct nand_chip *chip,
717 struct mtd_info *mtd, int new_state)
718{
7854d3f7 719 /* Hardware controller shared among independent devices */
2af7c653
SK		 720 chip->controller->active = chip;
721 chip->state = new_state;
722}
723
1da177e4
LT		 724/**
725 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 726 * @mtd: MTD device structure
727 * @new_state: the state which is requested
1da177e4
LT		 728 *
729 * Get the device and lock it for exclusive access
730 */
2c0a2bed 731static int
6a8214aa 732nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 733{
6a8214aa 734 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 735 spinlock_t *lock = &chip->controller->lock;
736 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 737 DECLARE_WAITQUEUE(wait, current);
7351d3a5 738retry:
0dfc6246
TG		 739 spin_lock(lock);
740
b8b3ee9a 741 /* Hardware controller shared among independent devices */
ace4dfee
TG		 742 if (!chip->controller->active)
743 chip->controller->active = chip;
a36ed299 744
ace4dfee
TG		 745 if (chip->controller->active == chip && chip->state == FL_READY) {
746 chip->state = new_state;
0dfc6246 747 spin_unlock(lock);
962034f4
VW		 748 return 0;
749 }
750 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 751 if (chip->controller->active->state == FL_PM_SUSPENDED) {
752 chip->state = FL_PM_SUSPENDED;
753 spin_unlock(lock);
754 return 0;
6b0d9a84 755 }
0dfc6246
TG		 756 }
757 set_current_state(TASK_UNINTERRUPTIBLE);
758 add_wait_queue(wq, &wait);
759 spin_unlock(lock);
760 schedule();
761 remove_wait_queue(wq, &wait);
1da177e4
LT		 762 goto retry;
763}
764
2af7c653 765/**
8b6e50c9
BN		 766 * panic_nand_wait - [GENERIC] wait until the command is done
767 * @mtd: MTD device structure
768 * @chip: NAND chip structure
769 * @timeo: timeout
2af7c653
SK		 770 *
771 * Wait for command done. This is a helper function for nand_wait used when
772 * we are in interrupt context. May happen when in panic and trying to write
b595076a 773 * an oops through mtdoops.
2af7c653
SK		 774 */
775static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
776 unsigned long timeo)
777{
778 int i;
779 for (i = 0; i < timeo; i++) {
780 if (chip->dev_ready) {
781 if (chip->dev_ready(mtd))
782 break;
783 } else {
784 if (chip->read_byte(mtd) & NAND_STATUS_READY)
785 break;
786 }
787 mdelay(1);
f8ac0414 788 }
2af7c653
SK		 789}
790
1da177e4 791/**
8b6e50c9
BN		 792 * nand_wait - [DEFAULT] wait until the command is done
793 * @mtd: MTD device structure
794 * @chip: NAND chip structure
1da177e4 795 *
8b6e50c9
BN		 796 * Wait for command done. This applies to erase and program only. Erase can
797 * take up to 400ms and program up to 20ms according to general NAND and
798 * SmartMedia specs.
844d3b42 799 */
7bc3312b 800static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 801{
802
7bc3312b 803 int status, state = chip->state;
6d2559f8 804 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1da177e4 805
8fe833c1
RP		 806 led_trigger_event(nand_led_trigger, LED_FULL);
807
8b6e50c9
BN		 808 /*
809 * Apply this short delay always to ensure that we do wait tWB in any
810 * case on any machine.
811 */
e0c7d767 812 ndelay(100);
1da177e4 813
14c65786 814 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 815
2af7c653
SK		 816 if (in_interrupt() || oops_in_progress)
817 panic_nand_wait(mtd, chip, timeo);
818 else {
6d2559f8 819 timeo = jiffies + msecs_to_jiffies(timeo);
2af7c653
SK		 820 while (time_before(jiffies, timeo)) {
821 if (chip->dev_ready) {
822 if (chip->dev_ready(mtd))
823 break;
824 } else {
825 if (chip->read_byte(mtd) & NAND_STATUS_READY)
826 break;
827 }
828 cond_resched();
1da177e4 829 }
1da177e4 830 }
8fe833c1
RP		 831 led_trigger_event(nand_led_trigger, LED_OFF);
832
ace4dfee 833 status = (int)chip->read_byte(mtd);
f251b8df
MC		 834 /* This can happen if in case of timeout or buggy dev_ready */
835 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 836 return status;
837}
838
7d70f334 839/**
b6d676db 840 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 841 * @mtd: mtd info
842 * @ofs: offset to start unlock from
843 * @len: length to unlock
8b6e50c9
BN		 844 * @invert: when = 0, unlock the range of blocks within the lower and
845 * upper boundary address
846 * when = 1, unlock the range of blocks outside the boundaries
847 * of the lower and upper boundary address
7d70f334 848 *
8b6e50c9 849 * Returs unlock status.
7d70f334
VS		 850 */
851static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
852 uint64_t len, int invert)
853{
854 int ret = 0;
855 int status, page;
856 struct nand_chip *chip = mtd->priv;
857
858 /* Submit address of first page to unlock */
859 page = ofs >> chip->page_shift;
860 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
861
862 /* Submit address of last page to unlock */
863 page = (ofs + len) >> chip->page_shift;
864 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
865 (page | invert) & chip->pagemask);
866
867 /* Call wait ready function */
868 status = chip->waitfunc(mtd, chip);
7d70f334 869 /* See if device thinks it succeeded */
74830966 870 if (status & NAND_STATUS_FAIL) {
289c0522 871 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 872 __func__, status);
873 ret = -EIO;
874 }
875
876 return ret;
877}
878
879/**
b6d676db 880 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 881 * @mtd: mtd info
882 * @ofs: offset to start unlock from
883 * @len: length to unlock
7d70f334 884 *
8b6e50c9 885 * Returns unlock status.
7d70f334
VS		 886 */
887int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
888{
889 int ret = 0;
890 int chipnr;
891 struct nand_chip *chip = mtd->priv;
892
289c0522 893 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 894 __func__, (unsigned long long)ofs, len);
895
896 if (check_offs_len(mtd, ofs, len))
897 ret = -EINVAL;
898
899 /* Align to last block address if size addresses end of the device */
900 if (ofs + len == mtd->size)
901 len -= mtd->erasesize;
902
6a8214aa 903 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 904
905 /* Shift to get chip number */
906 chipnr = ofs >> chip->chip_shift;
907
908 chip->select_chip(mtd, chipnr);
909
910 /* Check, if it is write protected */
911 if (nand_check_wp(mtd)) {
289c0522 912 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 913 __func__);
914 ret = -EIO;
915 goto out;
916 }
917
918 ret = __nand_unlock(mtd, ofs, len, 0);
919
920out:
b0bb6903 921 chip->select_chip(mtd, -1);
7d70f334
VS		 922 nand_release_device(mtd);
923
924 return ret;
925}
7351d3a5 926EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 927
928/**
b6d676db 929 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 930 * @mtd: mtd info
931 * @ofs: offset to start unlock from
932 * @len: length to unlock
7d70f334 933 *
8b6e50c9
BN		 934 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
935 * have this feature, but it allows only to lock all blocks, not for specified
936 * range for block. Implementing 'lock' feature by making use of 'unlock', for
937 * now.
7d70f334 938 *
8b6e50c9 939 * Returns lock status.
7d70f334
VS		 940 */
941int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
942{
943 int ret = 0;
944 int chipnr, status, page;
945 struct nand_chip *chip = mtd->priv;
946
289c0522 947 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 948 __func__, (unsigned long long)ofs, len);
949
950 if (check_offs_len(mtd, ofs, len))
951 ret = -EINVAL;
952
6a8214aa 953 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 954
955 /* Shift to get chip number */
956 chipnr = ofs >> chip->chip_shift;
957
958 chip->select_chip(mtd, chipnr);
959
960 /* Check, if it is write protected */
961 if (nand_check_wp(mtd)) {
289c0522 962 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 963 __func__);
964 status = MTD_ERASE_FAILED;
965 ret = -EIO;
966 goto out;
967 }
968
969 /* Submit address of first page to lock */
970 page = ofs >> chip->page_shift;
971 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
972
973 /* Call wait ready function */
974 status = chip->waitfunc(mtd, chip);
7d70f334 975 /* See if device thinks it succeeded */
74830966 976 if (status & NAND_STATUS_FAIL) {
289c0522 977 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 978 __func__, status);
979 ret = -EIO;
980 goto out;
981 }
982
983 ret = __nand_unlock(mtd, ofs, len, 0x1);
984
985out:
b0bb6903 986 chip->select_chip(mtd, -1);
7d70f334
VS		 987 nand_release_device(mtd);
988
989 return ret;
990}
7351d3a5 991EXPORT_SYMBOL(nand_lock);
7d70f334 992
8593fbc6 993/**
7854d3f7 994 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 995 * @mtd: mtd info structure
996 * @chip: nand chip info structure
997 * @buf: buffer to store read data
1fbb938d 998 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 999 * @page: page number to read
52ff49df 1000 *
7854d3f7 1001 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1002 */
1003static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1004 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1005{
1006 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1007 if (oob_required)
1008 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1009 return 0;
1010}
1011
52ff49df 1012/**
7854d3f7 1013 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1014 * @mtd: mtd info structure
1015 * @chip: nand chip info structure
1016 * @buf: buffer to store read data
1fbb938d 1017 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1018 * @page: page number to read
52ff49df
DB		 1019 *
1020 * We need a special oob layout and handling even when OOB isn't used.
1021 */
7351d3a5 1022static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1023 struct nand_chip *chip, uint8_t *buf,
1024 int oob_required, int page)
52ff49df
DB		 1025{
1026 int eccsize = chip->ecc.size;
1027 int eccbytes = chip->ecc.bytes;
1028 uint8_t *oob = chip->oob_poi;
1029 int steps, size;
1030
1031 for (steps = chip->ecc.steps; steps > 0; steps--) {
1032 chip->read_buf(mtd, buf, eccsize);
1033 buf += eccsize;
1034
1035 if (chip->ecc.prepad) {
1036 chip->read_buf(mtd, oob, chip->ecc.prepad);
1037 oob += chip->ecc.prepad;
1038 }
1039
1040 chip->read_buf(mtd, oob, eccbytes);
1041 oob += eccbytes;
1042
1043 if (chip->ecc.postpad) {
1044 chip->read_buf(mtd, oob, chip->ecc.postpad);
1045 oob += chip->ecc.postpad;
1046 }
1047 }
1048
1049 size = mtd->oobsize - (oob - chip->oob_poi);
1050 if (size)
1051 chip->read_buf(mtd, oob, size);
1052
1053 return 0;
1054}
1055
1da177e4 1056/**
7854d3f7 1057 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1058 * @mtd: mtd info structure
1059 * @chip: nand chip info structure
1060 * @buf: buffer to store read data
1fbb938d 1061 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1062 * @page: page number to read
068e3c0a 1063 */
f5bbdacc 1064static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1065 uint8_t *buf, int oob_required, int page)
1da177e4 1066{
f5bbdacc
TG		 1067 int i, eccsize = chip->ecc.size;
1068 int eccbytes = chip->ecc.bytes;
1069 int eccsteps = chip->ecc.steps;
1070 uint8_t *p = buf;
4bf63fcb
DW		 1071 uint8_t *ecc_calc = chip->buffers->ecccalc;
1072 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1073 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1074 unsigned int max_bitflips = 0;
f5bbdacc 1075
1fbb938d 1076 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1077
1078 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1079 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1080
1081 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1082 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1083
1084 eccsteps = chip->ecc.steps;
1085 p = buf;
1086
1087 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1088 int stat;
1089
1090 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1091 if (stat < 0) {
f5bbdacc 1092 mtd->ecc_stats.failed++;
3f91e94f 1093 } else {
f5bbdacc 1094 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1095 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1096 }
f5bbdacc 1097 }
3f91e94f 1098 return max_bitflips;
22c60f5f 1099}
1da177e4 1100
3d459559 1101/**
837a6ba4 1102 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1103 * @mtd: mtd info structure
1104 * @chip: nand chip info structure
1105 * @data_offs: offset of requested data within the page
1106 * @readlen: data length
1107 * @bufpoi: buffer to store read data
3d459559 1108 */
7351d3a5
FF		 1109static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1110 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1111{
1112 int start_step, end_step, num_steps;
1113 uint32_t *eccpos = chip->ecc.layout->eccpos;
1114 uint8_t *p;
1115 int data_col_addr, i, gaps = 0;
1116 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1117 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1118 int index = 0;
3f91e94f 1119 unsigned int max_bitflips = 0;
3d459559 1120
7854d3f7 1121 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1122 start_step = data_offs / chip->ecc.size;
1123 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1124 num_steps = end_step - start_step + 1;
1125
8b6e50c9 1126 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1127 datafrag_len = num_steps * chip->ecc.size;
1128 eccfrag_len = num_steps * chip->ecc.bytes;
1129
1130 data_col_addr = start_step * chip->ecc.size;
1131 /* If we read not a page aligned data */
1132 if (data_col_addr != 0)
1133 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1134
1135 p = bufpoi + data_col_addr;
1136 chip->read_buf(mtd, p, datafrag_len);
1137
8b6e50c9 1138 /* Calculate ECC */
3d459559
AK		 1139 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1140 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1141
8b6e50c9
BN		 1142 /*
1143 * The performance is faster if we position offsets according to
7854d3f7 1144 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1145 */
3d459559
AK		 1146 for (i = 0; i < eccfrag_len - 1; i++) {
1147 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1148 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1149 gaps = 1;
1150 break;
1151 }
1152 }
1153 if (gaps) {
1154 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1155 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1156 } else {
8b6e50c9 1157 /*
7854d3f7 1158 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1159 * about buswidth alignment in read_buf.
1160 */
7351d3a5
FF		 1161 index = start_step * chip->ecc.bytes;
1162
1163 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1164 aligned_len = eccfrag_len;
7351d3a5 1165 if (eccpos[index] & (busw - 1))
3d459559 1166 aligned_len++;
7351d3a5 1167 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1168 aligned_len++;
1169
7351d3a5
FF		 1170 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1171 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1172 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1173 }
1174
1175 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1176 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1177
1178 p = bufpoi + data_col_addr;
1179 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1180 int stat;
1181
7351d3a5
FF		 1182 stat = chip->ecc.correct(mtd, p,
1183 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1184 if (stat < 0) {
3d459559 1185 mtd->ecc_stats.failed++;
3f91e94f 1186 } else {
3d459559 1187 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1188 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1189 }
3d459559 1190 }
3f91e94f 1191 return max_bitflips;
3d459559
AK		 1192}
1193
068e3c0a 1194/**
7854d3f7 1195 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1196 * @mtd: mtd info structure
1197 * @chip: nand chip info structure
1198 * @buf: buffer to store read data
1fbb938d 1199 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1200 * @page: page number to read
068e3c0a 1201 *
7854d3f7 1202 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1203 */
f5bbdacc 1204static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1205 uint8_t *buf, int oob_required, int page)
1da177e4 1206{
f5bbdacc
TG		 1207 int i, eccsize = chip->ecc.size;
1208 int eccbytes = chip->ecc.bytes;
1209 int eccsteps = chip->ecc.steps;
1210 uint8_t *p = buf;
4bf63fcb
DW		 1211 uint8_t *ecc_calc = chip->buffers->ecccalc;
1212 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1213 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1214 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1215
1216 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1217 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1218 chip->read_buf(mtd, p, eccsize);
1219 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1220 }
f75e5097 1221 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1222
f5bbdacc 1223 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1224 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1225
f5bbdacc
TG		 1226 eccsteps = chip->ecc.steps;
1227 p = buf;
61b03bd7 1228
f5bbdacc
TG		 1229 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1230 int stat;
1da177e4 1231
f5bbdacc 1232 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1233 if (stat < 0) {
f5bbdacc 1234 mtd->ecc_stats.failed++;
3f91e94f 1235 } else {
f5bbdacc 1236 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1237 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1238 }
f5bbdacc 1239 }
3f91e94f 1240 return max_bitflips;
f5bbdacc 1241}
1da177e4 1242
6e0cb135 1243/**
7854d3f7 1244 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1245 * @mtd: mtd info structure
1246 * @chip: nand chip info structure
1247 * @buf: buffer to store read data
1fbb938d 1248 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1249 * @page: page number to read
6e0cb135 1250 *
8b6e50c9
BN		 1251 * Hardware ECC for large page chips, require OOB to be read first. For this
1252 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1253 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1254 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1255 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1256 */
1257static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1258 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1259{
1260 int i, eccsize = chip->ecc.size;
1261 int eccbytes = chip->ecc.bytes;
1262 int eccsteps = chip->ecc.steps;
1263 uint8_t *p = buf;
1264 uint8_t *ecc_code = chip->buffers->ecccode;
1265 uint32_t *eccpos = chip->ecc.layout->eccpos;
1266 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1267 unsigned int max_bitflips = 0;
6e0cb135
SN		 1268
1269 /* Read the OOB area first */
1270 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1271 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1272 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1273
1274 for (i = 0; i < chip->ecc.total; i++)
1275 ecc_code[i] = chip->oob_poi[eccpos[i]];
1276
1277 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1278 int stat;
1279
1280 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1281 chip->read_buf(mtd, p, eccsize);
1282 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1283
1284 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1285 if (stat < 0) {
6e0cb135 1286 mtd->ecc_stats.failed++;
3f91e94f 1287 } else {
6e0cb135 1288 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1289 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1290 }
6e0cb135 1291 }
3f91e94f 1292 return max_bitflips;
6e0cb135
SN		 1293}
1294
f5bbdacc 1295/**
7854d3f7 1296 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1297 * @mtd: mtd info structure
1298 * @chip: nand chip info structure
1299 * @buf: buffer to store read data
1fbb938d 1300 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1301 * @page: page number to read
f5bbdacc 1302 *
8b6e50c9
BN		 1303 * The hw generator calculates the error syndrome automatically. Therefore we
1304 * need a special oob layout and handling.
f5bbdacc
TG		 1305 */
1306static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1307 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1308{
1309 int i, eccsize = chip->ecc.size;
1310 int eccbytes = chip->ecc.bytes;
1311 int eccsteps = chip->ecc.steps;
1312 uint8_t *p = buf;
f75e5097 1313 uint8_t *oob = chip->oob_poi;
3f91e94f 1314 unsigned int max_bitflips = 0;
1da177e4 1315
f5bbdacc
TG		 1316 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1317 int stat;
61b03bd7 1318
f5bbdacc
TG		 1319 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1320 chip->read_buf(mtd, p, eccsize);
1da177e4 1321
f5bbdacc
TG		 1322 if (chip->ecc.prepad) {
1323 chip->read_buf(mtd, oob, chip->ecc.prepad);
1324 oob += chip->ecc.prepad;
1325 }
1da177e4 1326
f5bbdacc
TG		 1327 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1328 chip->read_buf(mtd, oob, eccbytes);
1329 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1330
3f91e94f 1331 if (stat < 0) {
f5bbdacc 1332 mtd->ecc_stats.failed++;
3f91e94f 1333 } else {
f5bbdacc 1334 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1335 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1336 }
61b03bd7 1337
f5bbdacc 1338 oob += eccbytes;
1da177e4 1339
f5bbdacc
TG		 1340 if (chip->ecc.postpad) {
1341 chip->read_buf(mtd, oob, chip->ecc.postpad);
1342 oob += chip->ecc.postpad;
61b03bd7 1343 }
f5bbdacc 1344 }
1da177e4 1345
f5bbdacc 1346 /* Calculate remaining oob bytes */
7e4178f9 1347 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1348 if (i)
1349 chip->read_buf(mtd, oob, i);
61b03bd7 1350
3f91e94f 1351 return max_bitflips;
f5bbdacc 1352}
1da177e4 1353
f5bbdacc 1354/**
7854d3f7 1355 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1356 * @chip: nand chip structure
1357 * @oob: oob destination address
1358 * @ops: oob ops structure
1359 * @len: size of oob to transfer
8593fbc6
TG		 1360 */
1361static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1362 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1363{
f8ac0414 1364 switch (ops->mode) {
8593fbc6 1365
0612b9dd
BN		 1366 case MTD_OPS_PLACE_OOB:
1367 case MTD_OPS_RAW:
8593fbc6
TG		 1368 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1369 return oob + len;
1370
0612b9dd 1371 case MTD_OPS_AUTO_OOB: {
8593fbc6 1372 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1373 uint32_t boffs = 0, roffs = ops->ooboffs;
1374 size_t bytes = 0;
8593fbc6 1375
f8ac0414 1376 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1377 /* Read request not from offset 0? */
7bc3312b
TG		 1378 if (unlikely(roffs)) {
1379 if (roffs >= free->length) {
1380 roffs -= free->length;
1381 continue;
1382 }
1383 boffs = free->offset + roffs;
1384 bytes = min_t(size_t, len,
1385 (free->length - roffs));
1386 roffs = 0;
1387 } else {
1388 bytes = min_t(size_t, len, free->length);
1389 boffs = free->offset;
1390 }
1391 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1392 oob += bytes;
1393 }
1394 return oob;
1395 }
1396 default:
1397 BUG();
1398 }
1399 return NULL;
1400}
1401
1402/**
7854d3f7 1403 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1404 * @mtd: MTD device structure
1405 * @from: offset to read from
1406 * @ops: oob ops structure
f5bbdacc
TG		 1407 *
1408 * Internal function. Called with chip held.
1409 */
8593fbc6
TG		 1410static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1411 struct mtd_oob_ops *ops)
f5bbdacc 1412{
e47f3db4 1413 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1414 struct nand_chip *chip = mtd->priv;
1415 struct mtd_ecc_stats stats;
f5bbdacc 1416 int ret = 0;
8593fbc6 1417 uint32_t readlen = ops->len;
7014568b 1418 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1419 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1420 mtd->oobavail : mtd->oobsize;
1421
8593fbc6 1422 uint8_t *bufpoi, *oob, *buf;
edbc4540 1423 unsigned int max_bitflips = 0;
1da177e4 1424
f5bbdacc 1425 stats = mtd->ecc_stats;
1da177e4 1426
f5bbdacc
TG		 1427 chipnr = (int)(from >> chip->chip_shift);
1428 chip->select_chip(mtd, chipnr);
61b03bd7 1429
f5bbdacc
TG		 1430 realpage = (int)(from >> chip->page_shift);
1431 page = realpage & chip->pagemask;
1da177e4 1432
f5bbdacc 1433 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1434
8593fbc6
TG		 1435 buf = ops->datbuf;
1436 oob = ops->oobbuf;
e47f3db4 1437 oob_required = oob ? 1 : 0;
8593fbc6 1438
f8ac0414 1439 while (1) {
f5bbdacc
TG		 1440 bytes = min(mtd->writesize - col, readlen);
1441 aligned = (bytes == mtd->writesize);
61b03bd7 1442
8b6e50c9 1443 /* Is the current page in the buffer? */
8593fbc6 1444 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1445 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1446
c00a0991 1447 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1448
edbc4540
MD		 1449 /*
1450 * Now read the page into the buffer. Absent an error,
1451 * the read methods return max bitflips per ecc step.
1452 */
0612b9dd 1453 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1454 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1455 oob_required,
1456 page);
a5ff4f10
JW		 1457 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1458 !oob)
7351d3a5
FF		 1459 ret = chip->ecc.read_subpage(mtd, chip,
1460 col, bytes, bufpoi);
956e944c 1461 else
46a8cf2d 1462 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1463 oob_required, page);
6d77b9d0
BN		 1464 if (ret < 0) {
1465 if (!aligned)
1466 /* Invalidate page cache */
1467 chip->pagebuf = -1;
1da177e4 1468 break;
6d77b9d0 1469 }
f5bbdacc 1470
edbc4540
MD		 1471 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1472
f5bbdacc
TG		 1473 /* Transfer not aligned data */
1474 if (!aligned) {
a5ff4f10 1475 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1476 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1477 (ops->mode != MTD_OPS_RAW)) {
3d459559 1478 chip->pagebuf = realpage;
edbc4540
MD		 1479 chip->pagebuf_bitflips = ret;
1480 } else {
6d77b9d0
BN		 1481 /* Invalidate page cache */
1482 chip->pagebuf = -1;
edbc4540 1483 }
4bf63fcb 1484 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1485 }
1486
8593fbc6
TG		 1487 buf += bytes;
1488
1489 if (unlikely(oob)) {
b64d39d8
ML		 1490 int toread = min(oobreadlen, max_oobsize);
1491
1492 if (toread) {
1493 oob = nand_transfer_oob(chip,
1494 oob, ops, toread);
1495 oobreadlen -= toread;
1496 }
8593fbc6 1497 }
5bc7c33c
BN		 1498
1499 if (chip->options & NAND_NEED_READRDY) {
1500 /* Apply delay or wait for ready/busy pin */
1501 if (!chip->dev_ready)
1502 udelay(chip->chip_delay);
1503 else
1504 nand_wait_ready(mtd);
1505 }
8593fbc6 1506 } else {
4bf63fcb 1507 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1508 buf += bytes;
edbc4540
MD		 1509 max_bitflips = max_t(unsigned int, max_bitflips,
1510 chip->pagebuf_bitflips);
8593fbc6 1511 }
1da177e4 1512
f5bbdacc 1513 readlen -= bytes;
61b03bd7 1514
f5bbdacc 1515 if (!readlen)
61b03bd7 1516 break;
1da177e4 1517
8b6e50c9 1518 /* For subsequent reads align to page boundary */
1da177e4
LT		 1519 col = 0;
1520 /* Increment page address */
1521 realpage++;
1522
ace4dfee 1523 page = realpage & chip->pagemask;
1da177e4
LT		 1524 /* Check, if we cross a chip boundary */
1525 if (!page) {
1526 chipnr++;
ace4dfee
TG		 1527 chip->select_chip(mtd, -1);
1528 chip->select_chip(mtd, chipnr);
1da177e4 1529 }
1da177e4 1530 }
b0bb6903 1531 chip->select_chip(mtd, -1);
1da177e4 1532
8593fbc6 1533 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1534 if (oob)
1535 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1536
3f91e94f 1537 if (ret < 0)
f5bbdacc
TG		 1538 return ret;
1539
9a1fcdfd
TG		 1540 if (mtd->ecc_stats.failed - stats.failed)
1541 return -EBADMSG;
1542
edbc4540 1543 return max_bitflips;
f5bbdacc
TG		 1544}
1545
1546/**
25985edc 1547 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1548 * @mtd: MTD device structure
1549 * @from: offset to read from
1550 * @len: number of bytes to read
1551 * @retlen: pointer to variable to store the number of read bytes
1552 * @buf: the databuffer to put data
f5bbdacc 1553 *
8b6e50c9 1554 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1555 */
1556static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1557 size_t *retlen, uint8_t *buf)
1558{
4a89ff88 1559 struct mtd_oob_ops ops;
f5bbdacc
TG		 1560 int ret;
1561
6a8214aa 1562 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 1563 ops.len = len;
1564 ops.datbuf = buf;
1565 ops.oobbuf = NULL;
11041ae6 1566 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1567 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1568 *retlen = ops.retlen;
f5bbdacc 1569 nand_release_device(mtd);
f5bbdacc 1570 return ret;
1da177e4
LT		 1571}
1572
7bc3312b 1573/**
7854d3f7 1574 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1575 * @mtd: mtd info structure
1576 * @chip: nand chip info structure
1577 * @page: page number to read
7bc3312b
TG		 1578 */
1579static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1580 int page)
7bc3312b 1581{
5c2ffb11 1582 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1583 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1584 return 0;
7bc3312b
TG		 1585}
1586
1587/**
7854d3f7 1588 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1589 * with syndromes
8b6e50c9
BN		 1590 * @mtd: mtd info structure
1591 * @chip: nand chip info structure
1592 * @page: page number to read
7bc3312b
TG		 1593 */
1594static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1595 int page)
7bc3312b
TG		 1596{
1597 uint8_t *buf = chip->oob_poi;
1598 int length = mtd->oobsize;
1599 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1600 int eccsize = chip->ecc.size;
1601 uint8_t *bufpoi = buf;
1602 int i, toread, sndrnd = 0, pos;
1603
1604 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1605 for (i = 0; i < chip->ecc.steps; i++) {
1606 if (sndrnd) {
1607 pos = eccsize + i * (eccsize + chunk);
1608 if (mtd->writesize > 512)
1609 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1610 else
1611 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1612 } else
1613 sndrnd = 1;
1614 toread = min_t(int, length, chunk);
1615 chip->read_buf(mtd, bufpoi, toread);
1616 bufpoi += toread;
1617 length -= toread;
1618 }
1619 if (length > 0)
1620 chip->read_buf(mtd, bufpoi, length);
1621
5c2ffb11 1622 return 0;
7bc3312b
TG		 1623}
1624
1625/**
7854d3f7 1626 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1627 * @mtd: mtd info structure
1628 * @chip: nand chip info structure
1629 * @page: page number to write
7bc3312b
TG		 1630 */
1631static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1632 int page)
1633{
1634 int status = 0;
1635 const uint8_t *buf = chip->oob_poi;
1636 int length = mtd->oobsize;
1637
1638 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1639 chip->write_buf(mtd, buf, length);
1640 /* Send command to program the OOB data */
1641 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1642
1643 status = chip->waitfunc(mtd, chip);
1644
0d420f9d 1645 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1646}
1647
1648/**
7854d3f7 1649 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1650 * with syndrome - only for large page flash
1651 * @mtd: mtd info structure
1652 * @chip: nand chip info structure
1653 * @page: page number to write
7bc3312b
TG		 1654 */
1655static int nand_write_oob_syndrome(struct mtd_info *mtd,
1656 struct nand_chip *chip, int page)
1657{
1658 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1659 int eccsize = chip->ecc.size, length = mtd->oobsize;
1660 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1661 const uint8_t *bufpoi = chip->oob_poi;
1662
1663 /*
1664 * data-ecc-data-ecc ... ecc-oob
1665 * or
1666 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1667 */
1668 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1669 pos = steps * (eccsize + chunk);
1670 steps = 0;
1671 } else
8b0036ee 1672 pos = eccsize;
7bc3312b
TG		 1673
1674 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1675 for (i = 0; i < steps; i++) {
1676 if (sndcmd) {
1677 if (mtd->writesize <= 512) {
1678 uint32_t fill = 0xFFFFFFFF;
1679
1680 len = eccsize;
1681 while (len > 0) {
1682 int num = min_t(int, len, 4);
1683 chip->write_buf(mtd, (uint8_t *)&fill,
1684 num);
1685 len -= num;
1686 }
1687 } else {
1688 pos = eccsize + i * (eccsize + chunk);
1689 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1690 }
1691 } else
1692 sndcmd = 1;
1693 len = min_t(int, length, chunk);
1694 chip->write_buf(mtd, bufpoi, len);
1695 bufpoi += len;
1696 length -= len;
1697 }
1698 if (length > 0)
1699 chip->write_buf(mtd, bufpoi, length);
1700
1701 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1702 status = chip->waitfunc(mtd, chip);
1703
1704 return status & NAND_STATUS_FAIL ? -EIO : 0;
1705}
1706
1da177e4 1707/**
7854d3f7 1708 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1709 * @mtd: MTD device structure
1710 * @from: offset to read from
1711 * @ops: oob operations description structure
1da177e4 1712 *
8b6e50c9 1713 * NAND read out-of-band data from the spare area.
1da177e4 1714 */
8593fbc6
TG		 1715static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1716 struct mtd_oob_ops *ops)
1da177e4 1717{
c00a0991 1718 int page, realpage, chipnr;
ace4dfee 1719 struct nand_chip *chip = mtd->priv;
041e4575 1720 struct mtd_ecc_stats stats;
7014568b
VW		 1721 int readlen = ops->ooblen;
1722 int len;
7bc3312b 1723 uint8_t *buf = ops->oobbuf;
1951f2f7 1724 int ret = 0;
61b03bd7 1725
289c0522 1726 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1727 __func__, (unsigned long long)from, readlen);
1da177e4 1728
041e4575
BN		 1729 stats = mtd->ecc_stats;
1730
0612b9dd 1731 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1732 len = chip->ecc.layout->oobavail;
03736155
AH		 1733 else
1734 len = mtd->oobsize;
1735
1736 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1737 pr_debug("%s: attempt to start read outside oob\n",
1738 __func__);
03736155
AH		 1739 return -EINVAL;
1740 }
1741
1742 /* Do not allow reads past end of device */
1743 if (unlikely(from >= mtd->size ||
1744 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1745 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1746 pr_debug("%s: attempt to read beyond end of device\n",
1747 __func__);
03736155
AH		 1748 return -EINVAL;
1749 }
7014568b 1750
7314e9e7 1751 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1752 chip->select_chip(mtd, chipnr);
1da177e4 1753
7314e9e7
TG		 1754 /* Shift to get page */
1755 realpage = (int)(from >> chip->page_shift);
1756 page = realpage & chip->pagemask;
1da177e4 1757
f8ac0414 1758 while (1) {
0612b9dd 1759 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1760 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1761 else
1951f2f7
SL		 1762 ret = chip->ecc.read_oob(mtd, chip, page);
1763
1764 if (ret < 0)
1765 break;
7014568b
VW		 1766
1767 len = min(len, readlen);
1768 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1769
5bc7c33c
BN		 1770 if (chip->options & NAND_NEED_READRDY) {
1771 /* Apply delay or wait for ready/busy pin */
1772 if (!chip->dev_ready)
1773 udelay(chip->chip_delay);
1774 else
1775 nand_wait_ready(mtd);
1776 }
1777
7014568b 1778 readlen -= len;
0d420f9d
SZ		 1779 if (!readlen)
1780 break;
1781
7314e9e7
TG		 1782 /* Increment page address */
1783 realpage++;
1784
1785 page = realpage & chip->pagemask;
1786 /* Check, if we cross a chip boundary */
1787 if (!page) {
1788 chipnr++;
1789 chip->select_chip(mtd, -1);
1790 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1791 }
1792 }
b0bb6903 1793 chip->select_chip(mtd, -1);
1da177e4 1794
1951f2f7
SL		 1795 ops->oobretlen = ops->ooblen - readlen;
1796
1797 if (ret < 0)
1798 return ret;
041e4575
BN		 1799
1800 if (mtd->ecc_stats.failed - stats.failed)
1801 return -EBADMSG;
1802
1803 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1804}
1805
1806/**
8593fbc6 1807 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1808 * @mtd: MTD device structure
1809 * @from: offset to read from
1810 * @ops: oob operation description structure
1da177e4 1811 *
8b6e50c9 1812 * NAND read data and/or out-of-band data.
1da177e4 1813 */
8593fbc6
TG		 1814static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1815 struct mtd_oob_ops *ops)
1da177e4 1816{
8593fbc6
TG		 1817 int ret = -ENOTSUPP;
1818
1819 ops->retlen = 0;
1da177e4
LT		 1820
1821 /* Do not allow reads past end of device */
7014568b 1822 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1823 pr_debug("%s: attempt to read beyond end of device\n",
1824 __func__);
1da177e4
LT		 1825 return -EINVAL;
1826 }
1827
6a8214aa 1828 nand_get_device(mtd, FL_READING);
1da177e4 1829
f8ac0414 1830 switch (ops->mode) {
0612b9dd
BN		 1831 case MTD_OPS_PLACE_OOB:
1832 case MTD_OPS_AUTO_OOB:
1833 case MTD_OPS_RAW:
8593fbc6 1834 break;
1da177e4 1835
8593fbc6
TG		 1836 default:
1837 goto out;
1838 }
1da177e4 1839
8593fbc6
TG		 1840 if (!ops->datbuf)
1841 ret = nand_do_read_oob(mtd, from, ops);
1842 else
1843 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1844
7351d3a5 1845out:
8593fbc6
TG		 1846 nand_release_device(mtd);
1847 return ret;
1848}
61b03bd7 1849
1da177e4 1850
8593fbc6 1851/**
7854d3f7 1852 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1853 * @mtd: mtd info structure
1854 * @chip: nand chip info structure
1855 * @buf: data buffer
1fbb938d 1856 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1857 *
7854d3f7 1858 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1859 */
fdbad98d 1860static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1861 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1862{
1863 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1864 if (oob_required)
1865 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1866
1867 return 0;
1da177e4
LT		 1868}
1869
52ff49df 1870/**
7854d3f7 1871 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1872 * @mtd: mtd info structure
1873 * @chip: nand chip info structure
1874 * @buf: data buffer
1fbb938d 1875 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1876 *
1877 * We need a special oob layout and handling even when ECC isn't checked.
1878 */
fdbad98d 1879static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1880 struct nand_chip *chip,
1fbb938d 1881 const uint8_t *buf, int oob_required)
52ff49df
DB		 1882{
1883 int eccsize = chip->ecc.size;
1884 int eccbytes = chip->ecc.bytes;
1885 uint8_t *oob = chip->oob_poi;
1886 int steps, size;
1887
1888 for (steps = chip->ecc.steps; steps > 0; steps--) {
1889 chip->write_buf(mtd, buf, eccsize);
1890 buf += eccsize;
1891
1892 if (chip->ecc.prepad) {
1893 chip->write_buf(mtd, oob, chip->ecc.prepad);
1894 oob += chip->ecc.prepad;
1895 }
1896
1897 chip->read_buf(mtd, oob, eccbytes);
1898 oob += eccbytes;
1899
1900 if (chip->ecc.postpad) {
1901 chip->write_buf(mtd, oob, chip->ecc.postpad);
1902 oob += chip->ecc.postpad;
1903 }
1904 }
1905
1906 size = mtd->oobsize - (oob - chip->oob_poi);
1907 if (size)
1908 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 1909
1910 return 0;
52ff49df 1911}
9223a456 1912/**
7854d3f7 1913 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1914 * @mtd: mtd info structure
1915 * @chip: nand chip info structure
1916 * @buf: data buffer
1fbb938d 1917 * @oob_required: must write chip->oob_poi to OOB
9223a456 1918 */
fdbad98d 1919static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1920 const uint8_t *buf, int oob_required)
9223a456 1921{
f75e5097
TG		 1922 int i, eccsize = chip->ecc.size;
1923 int eccbytes = chip->ecc.bytes;
1924 int eccsteps = chip->ecc.steps;
4bf63fcb 1925 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1926 const uint8_t *p = buf;
8b099a39 1927 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1928
7854d3f7 1929 /* Software ECC calculation */
8593fbc6
TG		 1930 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1931 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1932
8593fbc6
TG		 1933 for (i = 0; i < chip->ecc.total; i++)
1934 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1935
fdbad98d 1936 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1937}
9223a456 1938
f75e5097 1939/**
7854d3f7 1940 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1941 * @mtd: mtd info structure
1942 * @chip: nand chip info structure
1943 * @buf: data buffer
1fbb938d 1944 * @oob_required: must write chip->oob_poi to OOB
f75e5097 1945 */
fdbad98d 1946static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1947 const uint8_t *buf, int oob_required)
f75e5097
TG		 1948{
1949 int i, eccsize = chip->ecc.size;
1950 int eccbytes = chip->ecc.bytes;
1951 int eccsteps = chip->ecc.steps;
4bf63fcb 1952 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1953 const uint8_t *p = buf;
8b099a39 1954 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1955
f75e5097
TG		 1956 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1957 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1958 chip->write_buf(mtd, p, eccsize);
f75e5097 1959 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1960 }
1961
f75e5097
TG		 1962 for (i = 0; i < chip->ecc.total; i++)
1963 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1964
1965 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1966
1967 return 0;
9223a456
TG		 1968}
1969
837a6ba4
GP		 1970
1971/**
1972 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1973 * @mtd: mtd info structure
1974 * @chip: nand chip info structure
1975 * @column: column address of subpage within the page
1976 * @data_len: data length
1977 * @oob_required: must write chip->oob_poi to OOB
1978 */
1979static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1980 struct nand_chip *chip, uint32_t offset,
1981 uint32_t data_len, const uint8_t *data_buf,
1982 int oob_required)
1983{
1984 uint8_t *oob_buf = chip->oob_poi;
1985 uint8_t *ecc_calc = chip->buffers->ecccalc;
1986 int ecc_size = chip->ecc.size;
1987 int ecc_bytes = chip->ecc.bytes;
1988 int ecc_steps = chip->ecc.steps;
1989 uint32_t *eccpos = chip->ecc.layout->eccpos;
1990 uint32_t start_step = offset / ecc_size;
1991 uint32_t end_step = (offset + data_len - 1) / ecc_size;
1992 int oob_bytes = mtd->oobsize / ecc_steps;
1993 int step, i;
1994
1995 for (step = 0; step < ecc_steps; step++) {
1996 /* configure controller for WRITE access */
1997 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1998
1999 /* write data (untouched subpages already masked by 0xFF) */
2000 chip->write_buf(mtd, data_buf, ecc_size);
2001
2002 /* mask ECC of un-touched subpages by padding 0xFF */
2003 if ((step < start_step) || (step > end_step))
2004 memset(ecc_calc, 0xff, ecc_bytes);
2005 else
2006 chip->ecc.calculate(mtd, data_buf, ecc_calc);
2007
2008 /* mask OOB of un-touched subpages by padding 0xFF */
2009 /* if oob_required, preserve OOB metadata of written subpage */
2010 if (!oob_required || (step < start_step) || (step > end_step))
2011 memset(oob_buf, 0xff, oob_bytes);
2012
2013 data_buf += ecc_size;
2014 ecc_calc += ecc_bytes;
2015 oob_buf += oob_bytes;
2016 }
2017
2018 /* copy calculated ECC for whole page to chip->buffer->oob */
2019 /* this include masked-value(0xFF) for unwritten subpages */
2020 ecc_calc = chip->buffers->ecccalc;
2021 for (i = 0; i < chip->ecc.total; i++)
2022 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2023
2024 /* write OOB buffer to NAND device */
2025 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2026
2027 return 0;
2028}
2029
2030
61b03bd7 2031/**
7854d3f7 2032 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2033 * @mtd: mtd info structure
2034 * @chip: nand chip info structure
2035 * @buf: data buffer
1fbb938d 2036 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2037 *
8b6e50c9
BN		 2038 * The hw generator calculates the error syndrome automatically. Therefore we
2039 * need a special oob layout and handling.
f75e5097 2040 */
fdbad98d 2041static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2042 struct nand_chip *chip,
2043 const uint8_t *buf, int oob_required)
1da177e4 2044{
f75e5097
TG		 2045 int i, eccsize = chip->ecc.size;
2046 int eccbytes = chip->ecc.bytes;
2047 int eccsteps = chip->ecc.steps;
2048 const uint8_t *p = buf;
2049 uint8_t *oob = chip->oob_poi;
1da177e4 2050
f75e5097 2051 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2052
f75e5097
TG		 2053 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2054 chip->write_buf(mtd, p, eccsize);
61b03bd7 2055
f75e5097
TG		 2056 if (chip->ecc.prepad) {
2057 chip->write_buf(mtd, oob, chip->ecc.prepad);
2058 oob += chip->ecc.prepad;
2059 }
2060
2061 chip->ecc.calculate(mtd, p, oob);
2062 chip->write_buf(mtd, oob, eccbytes);
2063 oob += eccbytes;
2064
2065 if (chip->ecc.postpad) {
2066 chip->write_buf(mtd, oob, chip->ecc.postpad);
2067 oob += chip->ecc.postpad;
1da177e4 2068 }
1da177e4 2069 }
f75e5097
TG		 2070
2071 /* Calculate remaining oob bytes */
7e4178f9 2072 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2073 if (i)
2074 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2075
2076 return 0;
f75e5097
TG		 2077}
2078
2079/**
956e944c 2080 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2081 * @mtd: MTD device structure
2082 * @chip: NAND chip descriptor
837a6ba4
GP		 2083 * @offset: address offset within the page
2084 * @data_len: length of actual data to be written
8b6e50c9 2085 * @buf: the data to write
1fbb938d 2086 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2087 * @page: page number to write
2088 * @cached: cached programming
2089 * @raw: use _raw version of write_page
f75e5097
TG		 2090 */
2091static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2092 uint32_t offset, int data_len, const uint8_t *buf,
2093 int oob_required, int page, int cached, int raw)
f75e5097 2094{
837a6ba4
GP		 2095 int status, subpage;
2096
2097 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2098 chip->ecc.write_subpage)
2099 subpage = offset || (data_len < mtd->writesize);
2100 else
2101 subpage = 0;
f75e5097
TG		 2102
2103 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2104
956e944c 2105 if (unlikely(raw))
837a6ba4
GP		 2106 status = chip->ecc.write_page_raw(mtd, chip, buf,
2107 oob_required);
2108 else if (subpage)
2109 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2110 buf, oob_required);
956e944c 2111 else
fdbad98d
JW		 2112 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2113
2114 if (status < 0)
2115 return status;
f75e5097
TG		 2116
2117 /*
7854d3f7 2118 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2119 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2120 */
2121 cached = 0;
2122
3239a6cd 2123 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2124
2125 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2126 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2127 /*
2128 * See if operation failed and additional status checks are
8b6e50c9 2129 * available.
f75e5097
TG		 2130 */
2131 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2132 status = chip->errstat(mtd, chip, FL_WRITING, status,
2133 page);
2134
2135 if (status & NAND_STATUS_FAIL)
2136 return -EIO;
2137 } else {
2138 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2139 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2140 }
2141
f75e5097 2142 return 0;
1da177e4
LT		 2143}
2144
8593fbc6 2145/**
7854d3f7 2146 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2147 * @mtd: MTD device structure
8b6e50c9
BN		 2148 * @oob: oob data buffer
2149 * @len: oob data write length
2150 * @ops: oob ops structure
8593fbc6 2151 */
f722013e
TAA		 2152static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2153 struct mtd_oob_ops *ops)
8593fbc6 2154{
f722013e
TAA		 2155 struct nand_chip *chip = mtd->priv;
2156
2157 /*
2158 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2159 * data from a previous OOB read.
2160 */
2161 memset(chip->oob_poi, 0xff, mtd->oobsize);
2162
f8ac0414 2163 switch (ops->mode) {
8593fbc6 2164
0612b9dd
BN		 2165 case MTD_OPS_PLACE_OOB:
2166 case MTD_OPS_RAW:
8593fbc6
TG		 2167 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2168 return oob + len;
2169
0612b9dd 2170 case MTD_OPS_AUTO_OOB: {
8593fbc6 2171 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2172 uint32_t boffs = 0, woffs = ops->ooboffs;
2173 size_t bytes = 0;
8593fbc6 2174
f8ac0414 2175 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2176 /* Write request not from offset 0? */
7bc3312b
TG		 2177 if (unlikely(woffs)) {
2178 if (woffs >= free->length) {
2179 woffs -= free->length;
2180 continue;
2181 }
2182 boffs = free->offset + woffs;
2183 bytes = min_t(size_t, len,
2184 (free->length - woffs));
2185 woffs = 0;
2186 } else {
2187 bytes = min_t(size_t, len, free->length);
2188 boffs = free->offset;
2189 }
8b0036ee 2190 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2191 oob += bytes;
2192 }
2193 return oob;
2194 }
2195 default:
2196 BUG();
2197 }
2198 return NULL;
2199}
2200
f8ac0414 2201#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2202
2203/**
7854d3f7 2204 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2205 * @mtd: MTD device structure
2206 * @to: offset to write to
2207 * @ops: oob operations description structure
1da177e4 2208 *
8b6e50c9 2209 * NAND write with ECC.
1da177e4 2210 */
8593fbc6
TG		 2211static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2212 struct mtd_oob_ops *ops)
1da177e4 2213{
29072b96 2214 int chipnr, realpage, page, blockmask, column;
ace4dfee 2215 struct nand_chip *chip = mtd->priv;
8593fbc6 2216 uint32_t writelen = ops->len;
782ce79a
ML		 2217
2218 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2219 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2220 mtd->oobavail : mtd->oobsize;
2221
8593fbc6
TG		 2222 uint8_t *oob = ops->oobbuf;
2223 uint8_t *buf = ops->datbuf;
837a6ba4 2224 int ret;
e47f3db4 2225 int oob_required = oob ? 1 : 0;
1da177e4 2226
8593fbc6 2227 ops->retlen = 0;
29072b96
TG		 2228 if (!writelen)
2229 return 0;
1da177e4 2230
8b6e50c9 2231 /* Reject writes, which are not page aligned */
8593fbc6 2232 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2233 pr_notice("%s: attempt to write non page aligned data\n",
2234 __func__);
1da177e4
LT		 2235 return -EINVAL;
2236 }
2237
29072b96 2238 column = to & (mtd->writesize - 1);
1da177e4 2239
6a930961
TG		 2240 chipnr = (int)(to >> chip->chip_shift);
2241 chip->select_chip(mtd, chipnr);
2242
1da177e4 2243 /* Check, if it is write protected */
b0bb6903
HS		 2244 if (nand_check_wp(mtd)) {
2245 ret = -EIO;
2246 goto err_out;
2247 }
1da177e4 2248
f75e5097
TG		 2249 realpage = (int)(to >> chip->page_shift);
2250 page = realpage & chip->pagemask;
2251 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2252
2253 /* Invalidate the page cache, when we write to the cached page */
2254 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2255 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2256 chip->pagebuf = -1;
61b03bd7 2257
782ce79a 2258 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2259 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2260 ret = -EINVAL;
2261 goto err_out;
2262 }
782ce79a 2263
f8ac0414 2264 while (1) {
29072b96 2265 int bytes = mtd->writesize;
f75e5097 2266 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2267 uint8_t *wbuf = buf;
2268
8b6e50c9 2269 /* Partial page write? */
29072b96
TG		 2270 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2271 cached = 0;
2272 bytes = min_t(int, bytes - column, (int) writelen);
2273 chip->pagebuf = -1;
2274 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2275 memcpy(&chip->buffers->databuf[column], buf, bytes);
2276 wbuf = chip->buffers->databuf;
2277 }
1da177e4 2278
782ce79a
ML		 2279 if (unlikely(oob)) {
2280 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2281 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2282 oobwritelen -= len;
f722013e
TAA		 2283 } else {
2284 /* We still need to erase leftover OOB data */
2285 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2286 }
837a6ba4
GP		 2287 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2288 oob_required, page, cached,
2289 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2290 if (ret)
2291 break;
2292
2293 writelen -= bytes;
2294 if (!writelen)
2295 break;
2296
29072b96 2297 column = 0;
f75e5097
TG		 2298 buf += bytes;
2299 realpage++;
2300
2301 page = realpage & chip->pagemask;
2302 /* Check, if we cross a chip boundary */
2303 if (!page) {
2304 chipnr++;
2305 chip->select_chip(mtd, -1);
2306 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2307 }
2308 }
8593fbc6 2309
8593fbc6 2310 ops->retlen = ops->len - writelen;
7014568b
VW		 2311 if (unlikely(oob))
2312 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 2313
2314err_out:
2315 chip->select_chip(mtd, -1);
1da177e4
LT		 2316 return ret;
2317}
2318
2af7c653
SK		 2319/**
2320 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2321 * @mtd: MTD device structure
2322 * @to: offset to write to
2323 * @len: number of bytes to write
2324 * @retlen: pointer to variable to store the number of written bytes
2325 * @buf: the data to write
2af7c653
SK		 2326 *
2327 * NAND write with ECC. Used when performing writes in interrupt context, this
2328 * may for example be called by mtdoops when writing an oops while in panic.
2329 */
2330static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2331 size_t *retlen, const uint8_t *buf)
2332{
2333 struct nand_chip *chip = mtd->priv;
4a89ff88 2334 struct mtd_oob_ops ops;
2af7c653
SK		 2335 int ret;
2336
8b6e50c9 2337 /* Wait for the device to get ready */
2af7c653
SK		 2338 panic_nand_wait(mtd, chip, 400);
2339
8b6e50c9 2340 /* Grab the device */
2af7c653
SK		 2341 panic_nand_get_device(chip, mtd, FL_WRITING);
2342
4a89ff88
BN		 2343 ops.len = len;
2344 ops.datbuf = (uint8_t *)buf;
2345 ops.oobbuf = NULL;
11041ae6 2346 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2347
4a89ff88 2348 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2349
4a89ff88 2350 *retlen = ops.retlen;
2af7c653
SK		 2351 return ret;
2352}
2353
f75e5097 2354/**
8593fbc6 2355 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2356 * @mtd: MTD device structure
2357 * @to: offset to write to
2358 * @len: number of bytes to write
2359 * @retlen: pointer to variable to store the number of written bytes
2360 * @buf: the data to write
f75e5097 2361 *
8b6e50c9 2362 * NAND write with ECC.
f75e5097 2363 */
8593fbc6
TG		 2364static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2365 size_t *retlen, const uint8_t *buf)
f75e5097 2366{
4a89ff88 2367 struct mtd_oob_ops ops;
f75e5097
TG		 2368 int ret;
2369
6a8214aa 2370 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 2371 ops.len = len;
2372 ops.datbuf = (uint8_t *)buf;
2373 ops.oobbuf = NULL;
11041ae6 2374 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2375 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2376 *retlen = ops.retlen;
f75e5097 2377 nand_release_device(mtd);
8593fbc6 2378 return ret;
f75e5097 2379}
7314e9e7 2380
1da177e4 2381/**
8593fbc6 2382 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2383 * @mtd: MTD device structure
2384 * @to: offset to write to
2385 * @ops: oob operation description structure
1da177e4 2386 *
8b6e50c9 2387 * NAND write out-of-band.
1da177e4 2388 */
8593fbc6
TG		 2389static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2390 struct mtd_oob_ops *ops)
1da177e4 2391{
03736155 2392 int chipnr, page, status, len;
ace4dfee 2393 struct nand_chip *chip = mtd->priv;
1da177e4 2394
289c0522 2395 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2396 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2397
0612b9dd 2398 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2399 len = chip->ecc.layout->oobavail;
2400 else
2401 len = mtd->oobsize;
2402
1da177e4 2403 /* Do not allow write past end of page */
03736155 2404 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2405 pr_debug("%s: attempt to write past end of page\n",
2406 __func__);
1da177e4
LT		 2407 return -EINVAL;
2408 }
2409
03736155 2410 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2411 pr_debug("%s: attempt to start write outside oob\n",
2412 __func__);
03736155
AH		 2413 return -EINVAL;
2414 }
2415
775adc3d 2416 /* Do not allow write past end of device */
03736155
AH		 2417 if (unlikely(to >= mtd->size ||
2418 ops->ooboffs + ops->ooblen >
2419 ((mtd->size >> chip->page_shift) -
2420 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2421 pr_debug("%s: attempt to write beyond end of device\n",
2422 __func__);
03736155
AH		 2423 return -EINVAL;
2424 }
2425
7314e9e7 2426 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2427 chip->select_chip(mtd, chipnr);
1da177e4 2428
7314e9e7
TG		 2429 /* Shift to get page */
2430 page = (int)(to >> chip->page_shift);
2431
2432 /*
2433 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2434 * of my DiskOnChip 2000 test units) will clear the whole data page too
2435 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2436 * it in the doc2000 driver in August 1999. dwmw2.
2437 */
ace4dfee 2438 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2439
2440 /* Check, if it is write protected */
b0bb6903
HS		 2441 if (nand_check_wp(mtd)) {
2442 chip->select_chip(mtd, -1);
8593fbc6 2443 return -EROFS;
b0bb6903 2444 }
61b03bd7 2445
1da177e4 2446 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2447 if (page == chip->pagebuf)
2448 chip->pagebuf = -1;
1da177e4 2449
f722013e 2450 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2451
0612b9dd 2452 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2453 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2454 else
2455 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2456
b0bb6903
HS		 2457 chip->select_chip(mtd, -1);
2458
7bc3312b
TG		 2459 if (status)
2460 return status;
1da177e4 2461
7014568b 2462 ops->oobretlen = ops->ooblen;
1da177e4 2463
7bc3312b 2464 return 0;
8593fbc6
TG		 2465}
2466
2467/**
2468 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2469 * @mtd: MTD device structure
2470 * @to: offset to write to
2471 * @ops: oob operation description structure
8593fbc6
TG		 2472 */
2473static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2474 struct mtd_oob_ops *ops)
2475{
8593fbc6
TG		 2476 int ret = -ENOTSUPP;
2477
2478 ops->retlen = 0;
2479
2480 /* Do not allow writes past end of device */
7014568b 2481 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2482 pr_debug("%s: attempt to write beyond end of device\n",
2483 __func__);
8593fbc6
TG		 2484 return -EINVAL;
2485 }
2486
6a8214aa 2487 nand_get_device(mtd, FL_WRITING);
8593fbc6 2488
f8ac0414 2489 switch (ops->mode) {
0612b9dd
BN		 2490 case MTD_OPS_PLACE_OOB:
2491 case MTD_OPS_AUTO_OOB:
2492 case MTD_OPS_RAW:
8593fbc6
TG		 2493 break;
2494
2495 default:
2496 goto out;
2497 }
2498
2499 if (!ops->datbuf)
2500 ret = nand_do_write_oob(mtd, to, ops);
2501 else
2502 ret = nand_do_write_ops(mtd, to, ops);
2503
7351d3a5 2504out:
1da177e4 2505 nand_release_device(mtd);
1da177e4
LT		 2506 return ret;
2507}
2508
1da177e4 2509/**
7854d3f7 2510 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2511 * @mtd: MTD device structure
2512 * @page: the page address of the block which will be erased
1da177e4 2513 *
8b6e50c9 2514 * Standard erase command for NAND chips.
1da177e4 2515 */
e0c7d767 2516static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2517{
ace4dfee 2518 struct nand_chip *chip = mtd->priv;
1da177e4 2519 /* Send commands to erase a block */
ace4dfee
TG		 2520 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2521 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2522}
2523
1da177e4
LT		 2524/**
2525 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2526 * @mtd: MTD device structure
2527 * @instr: erase instruction
1da177e4 2528 *
8b6e50c9 2529 * Erase one ore more blocks.
1da177e4 2530 */
e0c7d767 2531static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2532{
e0c7d767 2533 return nand_erase_nand(mtd, instr, 0);
1da177e4 2534}
61b03bd7 2535
1da177e4 2536/**
7854d3f7 2537 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2538 * @mtd: MTD device structure
2539 * @instr: erase instruction
2540 * @allowbbt: allow erasing the bbt area
1da177e4 2541 *
8b6e50c9 2542 * Erase one ore more blocks.
1da177e4 2543 */
ace4dfee
TG		 2544int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2545 int allowbbt)
1da177e4 2546{
69423d99 2547 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2548 struct nand_chip *chip = mtd->priv;
69423d99 2549 loff_t len;
1da177e4 2550
289c0522
BN		 2551 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2552 __func__, (unsigned long long)instr->addr,
2553 (unsigned long long)instr->len);
1da177e4 2554
6fe5a6ac 2555 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2556 return -EINVAL;
1da177e4 2557
1da177e4 2558 /* Grab the lock and see if the device is available */
6a8214aa 2559 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 2560
2561 /* Shift to get first page */
ace4dfee
TG		 2562 page = (int)(instr->addr >> chip->page_shift);
2563 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2564
2565 /* Calculate pages in each block */
ace4dfee 2566 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2567
2568 /* Select the NAND device */
ace4dfee 2569 chip->select_chip(mtd, chipnr);
1da177e4 2570
1da177e4
LT		 2571 /* Check, if it is write protected */
2572 if (nand_check_wp(mtd)) {
289c0522
BN		 2573 pr_debug("%s: device is write protected!\n",
2574 __func__);
1da177e4
LT		 2575 instr->state = MTD_ERASE_FAILED;
2576 goto erase_exit;
2577 }
2578
2579 /* Loop through the pages */
2580 len = instr->len;
2581
2582 instr->state = MTD_ERASING;
2583
2584 while (len) {
12183a20 2585 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2586 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2587 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2588 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2589 __func__, page);
1da177e4
LT		 2590 instr->state = MTD_ERASE_FAILED;
2591 goto erase_exit;
2592 }
61b03bd7 2593
ace4dfee
TG		 2594 /*
2595 * Invalidate the page cache, if we erase the block which
8b6e50c9 2596 * contains the current cached page.
ace4dfee
TG		 2597 */
2598 if (page <= chip->pagebuf && chip->pagebuf <
2599 (page + pages_per_block))
2600 chip->pagebuf = -1;
1da177e4 2601
ace4dfee 2602 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2603
7bc3312b 2604 status = chip->waitfunc(mtd, chip);
1da177e4 2605
ace4dfee
TG		 2606 /*
2607 * See if operation failed and additional status checks are
2608 * available
2609 */
2610 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2611 status = chip->errstat(mtd, chip, FL_ERASING,
2612 status, page);
068e3c0a 2613
1da177e4 2614 /* See if block erase succeeded */
a4ab4c5d 2615 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2616 pr_debug("%s: failed erase, page 0x%08x\n",
2617 __func__, page);
1da177e4 2618 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2619 instr->fail_addr =
2620 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2621 goto erase_exit;
2622 }
30f464b7 2623
1da177e4 2624 /* Increment page address and decrement length */
ace4dfee 2625 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2626 page += pages_per_block;
2627
2628 /* Check, if we cross a chip boundary */
ace4dfee 2629 if (len && !(page & chip->pagemask)) {
1da177e4 2630 chipnr++;
ace4dfee
TG		 2631 chip->select_chip(mtd, -1);
2632 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2633 }
2634 }
2635 instr->state = MTD_ERASE_DONE;
2636
7351d3a5 2637erase_exit:
1da177e4
LT		 2638
2639 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2640
2641 /* Deselect and wake up anyone waiting on the device */
b0bb6903 2642 chip->select_chip(mtd, -1);
1da177e4
LT		 2643 nand_release_device(mtd);
2644
49defc01
DW		 2645 /* Do call back function */
2646 if (!ret)
2647 mtd_erase_callback(instr);
2648
1da177e4
LT		 2649 /* Return more or less happy */
2650 return ret;
2651}
2652
2653/**
2654 * nand_sync - [MTD Interface] sync
8b6e50c9 2655 * @mtd: MTD device structure
1da177e4 2656 *
8b6e50c9 2657 * Sync is actually a wait for chip ready function.
1da177e4 2658 */
e0c7d767 2659static void nand_sync(struct mtd_info *mtd)
1da177e4 2660{
289c0522 2661 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2662
2663 /* Grab the lock and see if the device is available */
6a8214aa 2664 nand_get_device(mtd, FL_SYNCING);
1da177e4 2665 /* Release it and go back */
e0c7d767 2666 nand_release_device(mtd);
1da177e4
LT		 2667}
2668
1da177e4 2669/**
ace4dfee 2670 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2671 * @mtd: MTD device structure
2672 * @offs: offset relative to mtd start
1da177e4 2673 */
ace4dfee 2674static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2675{
ace4dfee 2676 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2677}
2678
2679/**
ace4dfee 2680 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2681 * @mtd: MTD device structure
2682 * @ofs: offset relative to mtd start
1da177e4 2683 */
e0c7d767 2684static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2685{
ace4dfee 2686 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2687 int ret;
2688
f8ac0414
FF		 2689 ret = nand_block_isbad(mtd, ofs);
2690 if (ret) {
8b6e50c9 2691 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2692 if (ret > 0)
2693 return 0;
e0c7d767
DW		 2694 return ret;
2695 }
1da177e4 2696
ace4dfee 2697 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2698}
2699
7db03ecc
HS		 2700/**
2701 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2702 * @mtd: MTD device structure
2703 * @chip: nand chip info structure
2704 * @addr: feature address.
2705 * @subfeature_param: the subfeature parameters, a four bytes array.
2706 */
2707static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2708 int addr, uint8_t *subfeature_param)
2709{
2710 int status;
2711
2712 if (!chip->onfi_version)
2713 return -EINVAL;
2714
2715 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2716 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2717 status = chip->waitfunc(mtd, chip);
2718 if (status & NAND_STATUS_FAIL)
2719 return -EIO;
2720 return 0;
2721}
2722
2723/**
2724 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2725 * @mtd: MTD device structure
2726 * @chip: nand chip info structure
2727 * @addr: feature address.
2728 * @subfeature_param: the subfeature parameters, a four bytes array.
2729 */
2730static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2731 int addr, uint8_t *subfeature_param)
2732{
2733 if (!chip->onfi_version)
2734 return -EINVAL;
2735
2736 /* clear the sub feature parameters */
2737 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2738
2739 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2740 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2741 return 0;
2742}
2743
962034f4
VW		 2744/**
2745 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2746 * @mtd: MTD device structure
962034f4
VW		 2747 */
2748static int nand_suspend(struct mtd_info *mtd)
2749{
6a8214aa 2750 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 2751}
2752
2753/**
2754 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2755 * @mtd: MTD device structure
962034f4
VW		 2756 */
2757static void nand_resume(struct mtd_info *mtd)
2758{
ace4dfee 2759 struct nand_chip *chip = mtd->priv;
962034f4 2760
ace4dfee 2761 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2762 nand_release_device(mtd);
2763 else
d0370219
BN		 2764 pr_err("%s called for a chip which is not in suspended state\n",
2765 __func__);
962034f4
VW		 2766}
2767
8b6e50c9 2768/* Set default functions */
ace4dfee 2769static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2770{
1da177e4 2771 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2772 if (!chip->chip_delay)
2773 chip->chip_delay = 20;
1da177e4
LT		 2774
2775 /* check, if a user supplied command function given */
ace4dfee
TG		 2776 if (chip->cmdfunc == NULL)
2777 chip->cmdfunc = nand_command;
1da177e4
LT		 2778
2779 /* check, if a user supplied wait function given */
ace4dfee
TG		 2780 if (chip->waitfunc == NULL)
2781 chip->waitfunc = nand_wait;
2782
2783 if (!chip->select_chip)
2784 chip->select_chip = nand_select_chip;
2785 if (!chip->read_byte)
2786 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2787 if (!chip->read_word)
2788 chip->read_word = nand_read_word;
2789 if (!chip->block_bad)
2790 chip->block_bad = nand_block_bad;
2791 if (!chip->block_markbad)
2792 chip->block_markbad = nand_default_block_markbad;
2793 if (!chip->write_buf)
2794 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2795 if (!chip->read_buf)
2796 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2797 if (!chip->scan_bbt)
2798 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2799
2800 if (!chip->controller) {
2801 chip->controller = &chip->hwcontrol;
2802 spin_lock_init(&chip->controller->lock);
2803 init_waitqueue_head(&chip->controller->wq);
2804 }
2805
7aa65bfd
TG		 2806}
2807
8b6e50c9 2808/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2809static void sanitize_string(uint8_t *s, size_t len)
2810{
2811 ssize_t i;
2812
8b6e50c9 2813 /* Null terminate */
d1e1f4e4
FF		 2814 s[len - 1] = 0;
2815
8b6e50c9 2816 /* Remove non printable chars */
d1e1f4e4
FF		 2817 for (i = 0; i < len - 1; i++) {
2818 if (s[i] < ' ' || s[i] > 127)
2819 s[i] = '?';
2820 }
2821
8b6e50c9 2822 /* Remove trailing spaces */
d1e1f4e4
FF		 2823 strim(s);
2824}
2825
2826static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2827{
2828 int i;
2829 while (len--) {
2830 crc ^= *p++ << 8;
2831 for (i = 0; i < 8; i++)
2832 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2833 }
2834
2835 return crc;
2836}
2837
6fb277ba 2838/*
8b6e50c9 2839 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2840 */
2841static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2842 int *busw)
6fb277ba
FF		 2843{
2844 struct nand_onfi_params *p = &chip->onfi_params;
2845 int i;
2846 int val;
2847
0ce82b7f
MC		 2848 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2849 if (chip->options & NAND_BUSWIDTH_16) {
2850 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2851 return 0;
2852 }
7854d3f7 2853 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2854 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2855 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2856 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2857 return 0;
2858
6fb277ba
FF		 2859 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2860 for (i = 0; i < 3; i++) {
2861 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2862 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2863 le16_to_cpu(p->crc)) {
9a4d4d69 2864 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2865 break;
2866 }
2867 }
2868
2869 if (i == 3)
2870 return 0;
2871
8b6e50c9 2872 /* Check version */
6fb277ba 2873 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2874 if (val & (1 << 5))
2875 chip->onfi_version = 23;
2876 else if (val & (1 << 4))
6fb277ba
FF		 2877 chip->onfi_version = 22;
2878 else if (val & (1 << 3))
2879 chip->onfi_version = 21;
2880 else if (val & (1 << 2))
2881 chip->onfi_version = 20;
b7b1a29d 2882 else if (val & (1 << 1))
6fb277ba 2883 chip->onfi_version = 10;
b7b1a29d
BN		 2884
2885 if (!chip->onfi_version) {
d0370219 2886 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2887 return 0;
2888 }
6fb277ba
FF		 2889
2890 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2891 sanitize_string(p->model, sizeof(p->model));
2892 if (!mtd->name)
2893 mtd->name = p->model;
2894 mtd->writesize = le32_to_cpu(p->byte_per_page);
2895 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2896 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2897 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2898 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2899 *busw = 0;
6fb277ba 2900 if (le16_to_cpu(p->features) & 1)
08c248fb 2901 *busw = NAND_BUSWIDTH_16;
6fb277ba 2902
d42b5de3 2903 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2904 return 1;
2905}
2906
e3b88bd6
BN		 2907/*
2908 * nand_id_has_period - Check if an ID string has a given wraparound period
2909 * @id_data: the ID string
2910 * @arrlen: the length of the @id_data array
2911 * @period: the period of repitition
2912 *
2913 * Check if an ID string is repeated within a given sequence of bytes at
2914 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 2915 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 2916 * if the repetition has a period of @period; otherwise, returns zero.
2917 */
2918static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2919{
2920 int i, j;
2921 for (i = 0; i < period; i++)
2922 for (j = i + period; j < arrlen; j += period)
2923 if (id_data[i] != id_data[j])
2924 return 0;
2925 return 1;
2926}
2927
2928/*
2929 * nand_id_len - Get the length of an ID string returned by CMD_READID
2930 * @id_data: the ID string
2931 * @arrlen: the length of the @id_data array
2932
2933 * Returns the length of the ID string, according to known wraparound/trailing
2934 * zero patterns. If no pattern exists, returns the length of the array.
2935 */
2936static int nand_id_len(u8 *id_data, int arrlen)
2937{
2938 int last_nonzero, period;
2939
2940 /* Find last non-zero byte */
2941 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2942 if (id_data[last_nonzero])
2943 break;
2944
2945 /* All zeros */
2946 if (last_nonzero < 0)
2947 return 0;
2948
2949 /* Calculate wraparound period */
2950 for (period = 1; period < arrlen; period++)
2951 if (nand_id_has_period(id_data, arrlen, period))
2952 break;
2953
2954 /* There's a repeated pattern */
2955 if (period < arrlen)
2956 return period;
2957
2958 /* There are trailing zeros */
2959 if (last_nonzero < arrlen - 1)
2960 return last_nonzero + 1;
2961
2962 /* No pattern detected */
2963 return arrlen;
2964}
2965
fc09bbc0
BN		 2966/*
2967 * Many new NAND share similar device ID codes, which represent the size of the
2968 * chip. The rest of the parameters must be decoded according to generic or
2969 * manufacturer-specific "extended ID" decoding patterns.
2970 */
2971static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2972 u8 id_data[8], int *busw)
2973{
e3b88bd6 2974 int extid, id_len;
fc09bbc0
BN		 2975 /* The 3rd id byte holds MLC / multichip data */
2976 chip->cellinfo = id_data[2];
2977 /* The 4th id byte is the important one */
2978 extid = id_data[3];
2979
e3b88bd6
BN		 2980 id_len = nand_id_len(id_data, 8);
2981
fc09bbc0
BN		 2982 /*
2983 * Field definitions are in the following datasheets:
2984 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 2985 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 2986 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 2987 *
af451af4
BN		 2988 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2989 * ID to decide what to do.
fc09bbc0 2990 */
af451af4 2991 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
6924d99f 2992 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
af451af4 2993 id_data[5] != 0x00) {
fc09bbc0
BN		 2994 /* Calc pagesize */
2995 mtd->writesize = 2048 << (extid & 0x03);
2996 extid >>= 2;
2997 /* Calc oobsize */
e2d3a35e 2998 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 2999 case 1:
3000 mtd->oobsize = 128;
3001 break;
3002 case 2:
3003 mtd->oobsize = 218;
3004 break;
3005 case 3:
3006 mtd->oobsize = 400;
3007 break;
e2d3a35e 3008 case 4:
fc09bbc0
BN		 3009 mtd->oobsize = 436;
3010 break;
e2d3a35e
BN		 3011 case 5:
3012 mtd->oobsize = 512;
3013 break;
3014 case 6:
3015 default: /* Other cases are "reserved" (unknown) */
3016 mtd->oobsize = 640;
3017 break;
fc09bbc0
BN		 3018 }
3019 extid >>= 2;
3020 /* Calc blocksize */
3021 mtd->erasesize = (128 * 1024) <<
3022 (((extid >> 1) & 0x04) | (extid & 0x03));
3023 *busw = 0;
73ca392f
BN		 3024 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3025 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3026 unsigned int tmp;
3027
3028 /* Calc pagesize */
3029 mtd->writesize = 2048 << (extid & 0x03);
3030 extid >>= 2;
3031 /* Calc oobsize */
3032 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3033 case 0:
3034 mtd->oobsize = 128;
3035 break;
3036 case 1:
3037 mtd->oobsize = 224;
3038 break;
3039 case 2:
3040 mtd->oobsize = 448;
3041 break;
3042 case 3:
3043 mtd->oobsize = 64;
3044 break;
3045 case 4:
3046 mtd->oobsize = 32;
3047 break;
3048 case 5:
3049 mtd->oobsize = 16;
3050 break;
3051 default:
3052 mtd->oobsize = 640;
3053 break;
3054 }
3055 extid >>= 2;
3056 /* Calc blocksize */
3057 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3058 if (tmp < 0x03)
3059 mtd->erasesize = (128 * 1024) << tmp;
3060 else if (tmp == 0x03)
3061 mtd->erasesize = 768 * 1024;
3062 else
3063 mtd->erasesize = (64 * 1024) << tmp;
3064 *busw = 0;
fc09bbc0
BN		 3065 } else {
3066 /* Calc pagesize */
3067 mtd->writesize = 1024 << (extid & 0x03);
3068 extid >>= 2;
3069 /* Calc oobsize */
3070 mtd->oobsize = (8 << (extid & 0x01)) *
3071 (mtd->writesize >> 9);
3072 extid >>= 2;
3073 /* Calc blocksize. Blocksize is multiples of 64KiB */
3074 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3075 extid >>= 2;
3076 /* Get buswidth information */
3077 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3078 }
3079}
3080
f23a481c
BN		 3081/*
3082 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3083 * decodes a matching ID table entry and assigns the MTD size parameters for
3084 * the chip.
3085 */
3086static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3087 struct nand_flash_dev *type, u8 id_data[8],
3088 int *busw)
3089{
3090 int maf_id = id_data[0];
3091
3092 mtd->erasesize = type->erasesize;
3093 mtd->writesize = type->pagesize;
3094 mtd->oobsize = mtd->writesize / 32;
3095 *busw = type->options & NAND_BUSWIDTH_16;
3096
3097 /*
3098 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3099 * some Spansion chips have erasesize that conflicts with size
3100 * listed in nand_ids table.
3101 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3102 */
3103 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3104 && id_data[6] == 0x00 && id_data[7] == 0x00
3105 && mtd->writesize == 512) {
3106 mtd->erasesize = 128 * 1024;
3107 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3108 }
3109}
3110
7e74c2d7
BN		 3111/*
3112 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3113 * heuristic patterns using various detected parameters (e.g., manufacturer,
3114 * page size, cell-type information).
3115 */
3116static void nand_decode_bbm_options(struct mtd_info *mtd,
3117 struct nand_chip *chip, u8 id_data[8])
3118{
3119 int maf_id = id_data[0];
3120
3121 /* Set the bad block position */
3122 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3123 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3124 else
3125 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3126
3127 /*
3128 * Bad block marker is stored in the last page of each block on Samsung
3129 * and Hynix MLC devices; stored in first two pages of each block on
3130 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3131 * AMD/Spansion, and Macronix. All others scan only the first page.
3132 */
3133 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3134 (maf_id == NAND_MFR_SAMSUNG ||
3135 maf_id == NAND_MFR_HYNIX))
3136 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3137 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3138 (maf_id == NAND_MFR_SAMSUNG ||
3139 maf_id == NAND_MFR_HYNIX ||
3140 maf_id == NAND_MFR_TOSHIBA ||
3141 maf_id == NAND_MFR_AMD ||
3142 maf_id == NAND_MFR_MACRONIX)) ||
3143 (mtd->writesize == 2048 &&
3144 maf_id == NAND_MFR_MICRON))
3145 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3146}
3147
ec6e87e3
HS		 3148static inline bool is_full_id_nand(struct nand_flash_dev *type)
3149{
3150 return type->id_len;
3151}
3152
3153static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3154 struct nand_flash_dev *type, u8 *id_data, int *busw)
3155{
3156 if (!strncmp(type->id, id_data, type->id_len)) {
3157 mtd->writesize = type->pagesize;
3158 mtd->erasesize = type->erasesize;
3159 mtd->oobsize = type->oobsize;
3160
3161 chip->cellinfo = id_data[2];
3162 chip->chipsize = (uint64_t)type->chipsize << 20;
3163 chip->options |= type->options;
3164
3165 *busw = type->options & NAND_BUSWIDTH_16;
3166
3167 return true;
3168 }
3169 return false;
3170}
3171
7aa65bfd 3172/*
8b6e50c9 3173 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3174 */
3175static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3176 struct nand_chip *chip,
7351d3a5
FF		 3177 int busw,
3178 int *maf_id, int *dev_id,
5e81e88a 3179 struct nand_flash_dev *type)
7aa65bfd 3180{
d1e1f4e4 3181 int i, maf_idx;
426c457a 3182 u8 id_data[8];
1da177e4
LT		 3183
3184 /* Select the device */
ace4dfee 3185 chip->select_chip(mtd, 0);
1da177e4 3186
ef89a880
KB		 3187 /*
3188 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3189 * after power-up.
ef89a880
KB		 3190 */
3191 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3192
1da177e4 3193 /* Send the command for reading device ID */
ace4dfee 3194 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3195
3196 /* Read manufacturer and device IDs */
ace4dfee 3197 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3198 *dev_id = chip->read_byte(mtd);
1da177e4 3199
8b6e50c9
BN		 3200 /*
3201 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3202 * interface concerns can cause random data which looks like a
3203 * possibly credible NAND flash to appear. If the two results do
3204 * not match, ignore the device completely.
3205 */
3206
3207 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3208
4aef9b78
BN		 3209 /* Read entire ID string */
3210 for (i = 0; i < 8; i++)
426c457a 3211 id_data[i] = chip->read_byte(mtd);
ed8165c7 3212
d1e1f4e4 3213 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 3214 pr_info("%s: second ID read did not match "
d0370219
BN		 3215 "%02x,%02x against %02x,%02x\n", __func__,
3216 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3217 return ERR_PTR(-ENODEV);
3218 }
3219
7aa65bfd 3220 if (!type)
5e81e88a
DW		 3221 type = nand_flash_ids;
3222
ec6e87e3
HS		 3223 for (; type->name != NULL; type++) {
3224 if (is_full_id_nand(type)) {
3225 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3226 goto ident_done;
3227 } else if (*dev_id == type->dev_id) {
3228 break;
3229 }
3230 }
5e81e88a 3231
d1e1f4e4
FF		 3232 chip->onfi_version = 0;
3233 if (!type->name || !type->pagesize) {
6fb277ba 3234 /* Check is chip is ONFI compliant */
47450b35 3235 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3236 goto ident_done;
d1e1f4e4
FF		 3237 }
3238
5e81e88a 3239 if (!type->name)
7aa65bfd
TG		 3240 return ERR_PTR(-ENODEV);
3241
ba0251fe
TG		 3242 if (!mtd->name)
3243 mtd->name = type->name;
3244
69423d99 3245 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3246
12a40a57 3247 if (!type->pagesize && chip->init_size) {
8b6e50c9 3248 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3249 busw = chip->init_size(mtd, chip, id_data);
3250 } else if (!type->pagesize) {
fc09bbc0
BN		 3251 /* Decode parameters from extended ID */
3252 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3253 } else {
f23a481c 3254 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3255 }
bf7a01bf
BN		 3256 /* Get chip options */
3257 chip->options |= type->options;
d1e1f4e4 3258
8b6e50c9
BN		 3259 /*
3260 * Check if chip is not a Samsung device. Do not clear the
3261 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3262 */
3263 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3264 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3265ident_done:
3266
7aa65bfd 3267 /* Try to identify manufacturer */
9a909867 3268 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3269 if (nand_manuf_ids[maf_idx].id == *maf_id)
3270 break;
3271 }
0ea4a755 3272
64b37b2a
MC		 3273 if (chip->options & NAND_BUSWIDTH_AUTO) {
3274 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3275 chip->options |= busw;
3276 nand_set_defaults(chip, busw);
3277 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3278 /*
3279 * Check, if buswidth is correct. Hardware drivers should set
3280 * chip correct!
3281 */
9a4d4d69 3282 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3283 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3284 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3285 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3286 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3287 busw ? 16 : 8);
7aa65bfd
TG		 3288 return ERR_PTR(-EINVAL);
3289 }
61b03bd7 3290
7e74c2d7
BN		 3291 nand_decode_bbm_options(mtd, chip, id_data);
3292
7aa65bfd 3293 /* Calculate the address shift from the page size */
ace4dfee 3294 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3295 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3296 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3297
ace4dfee 3298 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3299 ffs(mtd->erasesize) - 1;
69423d99
AH		 3300 if (chip->chipsize & 0xffffffff)
3301 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3302 else {
3303 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3304 chip->chip_shift += 32 - 1;
3305 }
1da177e4 3306
26d9be11 3307 chip->badblockbits = 8;
14c65786 3308 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3309
8b6e50c9 3310 /* Do not replace user supplied command function! */
ace4dfee
TG		 3311 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3312 chip->cmdfunc = nand_command_lp;
7aa65bfd 3313
886bd33d 3314 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
2fd71a29 3315 " %dMiB, page size: %d, OOB size: %d\n",
886bd33d
HS		 3316 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3317 chip->onfi_version ? chip->onfi_params.model : type->name,
2fd71a29 3318 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3319
3320 return type;
3321}
3322
7aa65bfd 3323/**
3b85c321 3324 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3325 * @mtd: MTD device structure
3326 * @maxchips: number of chips to scan for
3327 * @table: alternative NAND ID table
7aa65bfd 3328 *
8b6e50c9
BN		 3329 * This is the first phase of the normal nand_scan() function. It reads the
3330 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3331 *
3b85c321 3332 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3333 */
5e81e88a
DW		 3334int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3335 struct nand_flash_dev *table)
7aa65bfd 3336{
d1e1f4e4 3337 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3338 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3339 struct nand_flash_dev *type;
3340
7aa65bfd 3341 /* Get buswidth to select the correct functions */
ace4dfee 3342 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3343 /* Set the default functions */
ace4dfee 3344 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3345
3346 /* Read the flash type */
7351d3a5
FF		 3347 type = nand_get_flash_type(mtd, chip, busw,
3348 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3349
3350 if (IS_ERR(type)) {
b1c6e6db 3351 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3352 pr_warn("No NAND device found\n");
ace4dfee 3353 chip->select_chip(mtd, -1);
7aa65bfd 3354 return PTR_ERR(type);
1da177e4
LT		 3355 }
3356
07300164
HS		 3357 chip->select_chip(mtd, -1);
3358
7aa65bfd 3359 /* Check for a chip array */
e0c7d767 3360 for (i = 1; i < maxchips; i++) {
ace4dfee 3361 chip->select_chip(mtd, i);
ef89a880
KB		 3362 /* See comment in nand_get_flash_type for reset */
3363 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3364 /* Send the command for reading device ID */
ace4dfee 3365 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3366 /* Read manufacturer and device IDs */
ace4dfee 3367 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 3368 nand_dev_id != chip->read_byte(mtd)) {
3369 chip->select_chip(mtd, -1);
1da177e4 3370 break;
07300164
HS		 3371 }
3372 chip->select_chip(mtd, -1);
1da177e4
LT		 3373 }
3374 if (i > 1)
9a4d4d69 3375 pr_info("%d NAND chips detected\n", i);
61b03bd7 3376
1da177e4 3377 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3378 chip->numchips = i;
3379 mtd->size = i * chip->chipsize;
7aa65bfd 3380
3b85c321
DW		 3381 return 0;
3382}
7351d3a5 3383EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3384
3385
3386/**
3387 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3388 * @mtd: MTD device structure
3b85c321 3389 *
8b6e50c9
BN		 3390 * This is the second phase of the normal nand_scan() function. It fills out
3391 * all the uninitialized function pointers with the defaults and scans for a
3392 * bad block table if appropriate.
3b85c321
DW		 3393 */
3394int nand_scan_tail(struct mtd_info *mtd)
3395{
3396 int i;
3397 struct nand_chip *chip = mtd->priv;
3398
e2414f4c
BN		 3399 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3400 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3401 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3402
4bf63fcb
DW		 3403 if (!(chip->options & NAND_OWN_BUFFERS))
3404 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3405 if (!chip->buffers)
3406 return -ENOMEM;
3407
7dcdcbef 3408 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3409 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3410
7aa65bfd 3411 /*
8b6e50c9 3412 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3413 */
193bd400 3414 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3415 switch (mtd->oobsize) {
1da177e4 3416 case 8:
5bd34c09 3417 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3418 break;
3419 case 16:
5bd34c09 3420 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3421 break;
3422 case 64:
5bd34c09 3423 chip->ecc.layout = &nand_oob_64;
1da177e4 3424 break;
81ec5364
TG		 3425 case 128:
3426 chip->ecc.layout = &nand_oob_128;
3427 break;
1da177e4 3428 default:
d0370219
BN		 3429 pr_warn("No oob scheme defined for oobsize %d\n",
3430 mtd->oobsize);
1da177e4
LT		 3431 BUG();
3432 }
3433 }
61b03bd7 3434
956e944c
DW		 3435 if (!chip->write_page)
3436 chip->write_page = nand_write_page;
3437
7db03ecc
HS		 3438 /* set for ONFI nand */
3439 if (!chip->onfi_set_features)
3440 chip->onfi_set_features = nand_onfi_set_features;
3441 if (!chip->onfi_get_features)
3442 chip->onfi_get_features = nand_onfi_get_features;
3443
61b03bd7 3444 /*
8b6e50c9 3445 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3446 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3447 */
956e944c 3448
ace4dfee 3449 switch (chip->ecc.mode) {
6e0cb135
SN		 3450 case NAND_ECC_HW_OOB_FIRST:
3451 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3452 if (!chip->ecc.calculate || !chip->ecc.correct ||
3453 !chip->ecc.hwctl) {
9a4d4d69 3454 pr_warn("No ECC functions supplied; "
d0370219 3455 "hardware ECC not possible\n");
6e0cb135
SN		 3456 BUG();
3457 }
3458 if (!chip->ecc.read_page)
3459 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3460
6dfc6d25 3461 case NAND_ECC_HW:
8b6e50c9 3462 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3463 if (!chip->ecc.read_page)
3464 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3465 if (!chip->ecc.write_page)
3466 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3467 if (!chip->ecc.read_page_raw)
3468 chip->ecc.read_page_raw = nand_read_page_raw;
3469 if (!chip->ecc.write_page_raw)
3470 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3471 if (!chip->ecc.read_oob)
3472 chip->ecc.read_oob = nand_read_oob_std;
3473 if (!chip->ecc.write_oob)
3474 chip->ecc.write_oob = nand_write_oob_std;
837a6ba4
GP		 3475 if (!chip->ecc.read_subpage)
3476 chip->ecc.read_subpage = nand_read_subpage;
3477 if (!chip->ecc.write_subpage)
3478 chip->ecc.write_subpage = nand_write_subpage_hwecc;
f5bbdacc 3479
6dfc6d25 3480 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3481 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3482 !chip->ecc.hwctl) &&
3483 (!chip->ecc.read_page ||
1c45f604 3484 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3485 !chip->ecc.write_page ||
1c45f604 3486 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3487 pr_warn("No ECC functions supplied; "
d0370219 3488 "hardware ECC not possible\n");
6dfc6d25
TG		 3489 BUG();
3490 }
8b6e50c9 3491 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3492 if (!chip->ecc.read_page)
3493 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3494 if (!chip->ecc.write_page)
3495 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3496 if (!chip->ecc.read_page_raw)
3497 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3498 if (!chip->ecc.write_page_raw)
3499 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3500 if (!chip->ecc.read_oob)
3501 chip->ecc.read_oob = nand_read_oob_syndrome;
3502 if (!chip->ecc.write_oob)
3503 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3504
e2788c98
MD		 3505 if (mtd->writesize >= chip->ecc.size) {
3506 if (!chip->ecc.strength) {
3507 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3508 BUG();
3509 }
6dfc6d25 3510 break;
e2788c98 3511 }
9a4d4d69 3512 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3513 "%d byte page size, fallback to SW ECC\n",
3514 chip->ecc.size, mtd->writesize);
ace4dfee 3515 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3516
6dfc6d25 3517 case NAND_ECC_SOFT:
ace4dfee
TG		 3518 chip->ecc.calculate = nand_calculate_ecc;
3519 chip->ecc.correct = nand_correct_data;
f5bbdacc 3520 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3521 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3522 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3523 chip->ecc.read_page_raw = nand_read_page_raw;
3524 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3525 chip->ecc.read_oob = nand_read_oob_std;
3526 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3527 if (!chip->ecc.size)
3528 chip->ecc.size = 256;
ace4dfee 3529 chip->ecc.bytes = 3;
6a918bad 3530 chip->ecc.strength = 1;
1da177e4 3531 break;
61b03bd7 3532
193bd400
ID		 3533 case NAND_ECC_SOFT_BCH:
3534 if (!mtd_nand_has_bch()) {
9a4d4d69 3535 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3536 BUG();
3537 }
3538 chip->ecc.calculate = nand_bch_calculate_ecc;
3539 chip->ecc.correct = nand_bch_correct_data;
3540 chip->ecc.read_page = nand_read_page_swecc;
3541 chip->ecc.read_subpage = nand_read_subpage;
3542 chip->ecc.write_page = nand_write_page_swecc;
3543 chip->ecc.read_page_raw = nand_read_page_raw;
3544 chip->ecc.write_page_raw = nand_write_page_raw;
3545 chip->ecc.read_oob = nand_read_oob_std;
3546 chip->ecc.write_oob = nand_write_oob_std;
3547 /*
3548 * Board driver should supply ecc.size and ecc.bytes values to
3549 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3550 * for details. Otherwise, default to 4 bits for large page
3551 * devices.
193bd400
ID		 3552 */
3553 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3554 chip->ecc.size = 512;
3555 chip->ecc.bytes = 7;
3556 }
3557 chip->ecc.priv = nand_bch_init(mtd,
3558 chip->ecc.size,
3559 chip->ecc.bytes,
3560 &chip->ecc.layout);
3561 if (!chip->ecc.priv) {
9a4d4d69 3562 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3563 BUG();
3564 }
6a918bad 3565 chip->ecc.strength =
e2788c98 3566 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3567 break;
3568
61b03bd7 3569 case NAND_ECC_NONE:
9a4d4d69 3570 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3571 "This is not recommended!\n");
8593fbc6
TG		 3572 chip->ecc.read_page = nand_read_page_raw;
3573 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3574 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3575 chip->ecc.read_page_raw = nand_read_page_raw;
3576 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3577 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3578 chip->ecc.size = mtd->writesize;
3579 chip->ecc.bytes = 0;
6a918bad 3580 chip->ecc.strength = 0;
1da177e4 3581 break;
956e944c 3582
1da177e4 3583 default:
d0370219 3584 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3585 BUG();
1da177e4 3586 }
61b03bd7 3587
9ce244b3 3588 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3589 if (!chip->ecc.read_oob_raw)
3590 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3591 if (!chip->ecc.write_oob_raw)
3592 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3593
5bd34c09
TG		 3594 /*
3595 * The number of bytes available for a client to place data into
8b6e50c9 3596 * the out of band area.
5bd34c09
TG		 3597 */
3598 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3599 for (i = 0; chip->ecc.layout->oobfree[i].length
3600 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3601 chip->ecc.layout->oobavail +=
3602 chip->ecc.layout->oobfree[i].length;
1f92267c 3603 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3604
7aa65bfd
TG		 3605 /*
3606 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3607 * mode.
7aa65bfd 3608 */
ace4dfee 3609 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3610 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3611 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3612 BUG();
1da177e4 3613 }
f5bbdacc 3614 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3615
8b6e50c9 3616 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3617 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3618 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3619 switch (chip->ecc.steps) {
29072b96
TG		 3620 case 2:
3621 mtd->subpage_sft = 1;
3622 break;
3623 case 4:
3624 case 8:
81ec5364 3625 case 16:
29072b96
TG		 3626 mtd->subpage_sft = 2;
3627 break;
3628 }
3629 }
3630 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3631
04bbd0ea 3632 /* Initialize state */
ace4dfee 3633 chip->state = FL_READY;
1da177e4 3634
1da177e4 3635 /* Invalidate the pagebuffer reference */
ace4dfee 3636 chip->pagebuf = -1;
1da177e4 3637
a5ff4f10
JW		 3638 /* Large page NAND with SOFT_ECC should support subpage reads */
3639 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3640 chip->options |= NAND_SUBPAGE_READ;
3641
1da177e4
LT		 3642 /* Fill in remaining MTD driver data */
3643 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3644 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3645 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3646 mtd->_erase = nand_erase;
3647 mtd->_point = NULL;
3648 mtd->_unpoint = NULL;
3649 mtd->_read = nand_read;
3650 mtd->_write = nand_write;
3651 mtd->_panic_write = panic_nand_write;
3652 mtd->_read_oob = nand_read_oob;
3653 mtd->_write_oob = nand_write_oob;
3654 mtd->_sync = nand_sync;
3655 mtd->_lock = NULL;
3656 mtd->_unlock = NULL;
3657 mtd->_suspend = nand_suspend;
3658 mtd->_resume = nand_resume;
3659 mtd->_block_isbad = nand_block_isbad;
3660 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3661 mtd->writebufsize = mtd->writesize;
1da177e4 3662
6a918bad 3663 /* propagate ecc info to mtd_info */
5bd34c09 3664 mtd->ecclayout = chip->ecc.layout;
86c2072b 3665 mtd->ecc_strength = chip->ecc.strength;
ea3b2ea2
SL		 3666 /*
3667 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3668 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3669 * properly set.
3670 */
3671 if (!mtd->bitflip_threshold)
3672 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3673
0040bf38 3674 /* Check, if we should skip the bad block table scan */
ace4dfee 3675 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3676 return 0;
1da177e4
LT		 3677
3678 /* Build bad block table */
ace4dfee 3679 return chip->scan_bbt(mtd);
1da177e4 3680}
7351d3a5 3681EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3682
8b6e50c9
BN		 3683/*
3684 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3685 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3686 * to call us from in-kernel code if the core NAND support is modular.
3687 */
3b85c321
DW		 3688#ifdef MODULE
3689#define caller_is_module() (1)
3690#else
3691#define caller_is_module() \
a6e6abd5 3692 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3693#endif
3694
3695/**
3696 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3697 * @mtd: MTD device structure
3698 * @maxchips: number of chips to scan for
3b85c321 3699 *
8b6e50c9
BN		 3700 * This fills out all the uninitialized function pointers with the defaults.
3701 * The flash ID is read and the mtd/chip structures are filled with the
3702 * appropriate values. The mtd->owner field must be set to the module of the
3703 * caller.
3b85c321
DW		 3704 */
3705int nand_scan(struct mtd_info *mtd, int maxchips)
3706{
3707 int ret;
3708
3709 /* Many callers got this wrong, so check for it for a while... */
3710 if (!mtd->owner && caller_is_module()) {
d0370219 3711 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3712 BUG();
3713 }
3714
5e81e88a 3715 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3716 if (!ret)
3717 ret = nand_scan_tail(mtd);
3718 return ret;
3719}
7351d3a5 3720EXPORT_SYMBOL(nand_scan);
3b85c321 3721
1da177e4 3722/**
61b03bd7 3723 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3724 * @mtd: MTD device structure
3725 */
e0c7d767 3726void nand_release(struct mtd_info *mtd)
1da177e4 3727{
ace4dfee 3728 struct nand_chip *chip = mtd->priv;
1da177e4 3729
193bd400
ID		 3730 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3731 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3732
5ffcaf3d 3733 mtd_device_unregister(mtd);
1da177e4 3734
fa671646 3735 /* Free bad block table memory */
ace4dfee 3736 kfree(chip->bbt);
4bf63fcb
DW		 3737 if (!(chip->options & NAND_OWN_BUFFERS))
3738 kfree(chip->buffers);
58373ff0
BN		 3739
3740 /* Free bad block descriptor memory */
3741 if (chip->badblock_pattern && chip->badblock_pattern->options
3742 & NAND_BBT_DYNAMICSTRUCT)
3743 kfree(chip->badblock_pattern);
1da177e4 3744}
e0c7d767 3745EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3746
3747static int __init nand_base_init(void)
3748{
3749 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3750 return 0;
3751}
3752
3753static void __exit nand_base_exit(void)
3754{
3755 led_trigger_unregister_simple(nand_led_trigger);
3756}
3757
3758module_init(nand_base_init);
3759module_exit(nand_base_exit);
3760
e0c7d767 3761MODULE_LICENSE("GPL");
7351d3a5
FF		 3762MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3763MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3764MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)