Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
45 | #include <linux/mtd/compatmac.h> | |
46 | #include <linux/interrupt.h> | |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | ||
51 | #ifdef CONFIG_MTD_PARTITIONS | |
52 | #include <linux/mtd/partitions.h> | |
53 | #endif | |
54 | ||
55 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 56 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
57 | .eccbytes = 3, |
58 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
59 | .oobfree = { |
60 | {.offset = 3, | |
61 | .length = 2}, | |
62 | {.offset = 6, | |
63 | .length = 2}} | |
1da177e4 LT |
64 | }; |
65 | ||
5bd34c09 | 66 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
67 | .eccbytes = 6, |
68 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
69 | .oobfree = { |
70 | {.offset = 8, | |
71 | . length = 8}} | |
1da177e4 LT |
72 | }; |
73 | ||
5bd34c09 | 74 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
75 | .eccbytes = 24, |
76 | .eccpos = { | |
e0c7d767 DW |
77 | 40, 41, 42, 43, 44, 45, 46, 47, |
78 | 48, 49, 50, 51, 52, 53, 54, 55, | |
79 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
80 | .oobfree = { |
81 | {.offset = 2, | |
82 | .length = 38}} | |
1da177e4 LT |
83 | }; |
84 | ||
81ec5364 TG |
85 | static struct nand_ecclayout nand_oob_128 = { |
86 | .eccbytes = 48, | |
87 | .eccpos = { | |
88 | 80, 81, 82, 83, 84, 85, 86, 87, | |
89 | 88, 89, 90, 91, 92, 93, 94, 95, | |
90 | 96, 97, 98, 99, 100, 101, 102, 103, | |
91 | 104, 105, 106, 107, 108, 109, 110, 111, | |
92 | 112, 113, 114, 115, 116, 117, 118, 119, | |
93 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
94 | .oobfree = { | |
95 | {.offset = 2, | |
96 | .length = 78}} | |
97 | }; | |
98 | ||
ace4dfee | 99 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 100 | int new_state); |
1da177e4 | 101 | |
8593fbc6 TG |
102 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
103 | struct mtd_oob_ops *ops); | |
104 | ||
d470a97c | 105 | /* |
8e87d782 | 106 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
107 | * compiled away when LED support is disabled. |
108 | */ | |
109 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
110 | ||
6fe5a6ac VS |
111 | static int check_offs_len(struct mtd_info *mtd, |
112 | loff_t ofs, uint64_t len) | |
113 | { | |
114 | struct nand_chip *chip = mtd->priv; | |
115 | int ret = 0; | |
116 | ||
117 | /* Start address must align on block boundary */ | |
118 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
119 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); | |
120 | ret = -EINVAL; | |
121 | } | |
122 | ||
123 | /* Length must align on block boundary */ | |
124 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
125 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", | |
126 | __func__); | |
127 | ret = -EINVAL; | |
128 | } | |
129 | ||
130 | /* Do not allow past end of device */ | |
131 | if (ofs + len > mtd->size) { | |
132 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n", | |
133 | __func__); | |
134 | ret = -EINVAL; | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
1da177e4 LT |
140 | /** |
141 | * nand_release_device - [GENERIC] release chip | |
142 | * @mtd: MTD device structure | |
61b03bd7 TG |
143 | * |
144 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 145 | */ |
e0c7d767 | 146 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 147 | { |
ace4dfee | 148 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
149 | |
150 | /* De-select the NAND device */ | |
ace4dfee | 151 | chip->select_chip(mtd, -1); |
0dfc6246 | 152 | |
a36ed299 | 153 | /* Release the controller and the chip */ |
ace4dfee TG |
154 | spin_lock(&chip->controller->lock); |
155 | chip->controller->active = NULL; | |
156 | chip->state = FL_READY; | |
157 | wake_up(&chip->controller->wq); | |
158 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
159 | } |
160 | ||
161 | /** | |
162 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
163 | * @mtd: MTD device structure | |
164 | * | |
165 | * Default read function for 8bit buswith | |
166 | */ | |
58dd8f2b | 167 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 168 | { |
ace4dfee TG |
169 | struct nand_chip *chip = mtd->priv; |
170 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
171 | } |
172 | ||
1da177e4 LT |
173 | /** |
174 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
175 | * @mtd: MTD device structure | |
176 | * | |
61b03bd7 | 177 | * Default read function for 16bit buswith with |
1da177e4 LT |
178 | * endianess conversion |
179 | */ | |
58dd8f2b | 180 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 181 | { |
ace4dfee TG |
182 | struct nand_chip *chip = mtd->priv; |
183 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
184 | } |
185 | ||
1da177e4 LT |
186 | /** |
187 | * nand_read_word - [DEFAULT] read one word from the chip | |
188 | * @mtd: MTD device structure | |
189 | * | |
61b03bd7 | 190 | * Default read function for 16bit buswith without |
1da177e4 LT |
191 | * endianess conversion |
192 | */ | |
193 | static u16 nand_read_word(struct mtd_info *mtd) | |
194 | { | |
ace4dfee TG |
195 | struct nand_chip *chip = mtd->priv; |
196 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
197 | } |
198 | ||
1da177e4 LT |
199 | /** |
200 | * nand_select_chip - [DEFAULT] control CE line | |
201 | * @mtd: MTD device structure | |
844d3b42 | 202 | * @chipnr: chipnumber to select, -1 for deselect |
1da177e4 LT |
203 | * |
204 | * Default select function for 1 chip devices. | |
205 | */ | |
ace4dfee | 206 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 207 | { |
ace4dfee TG |
208 | struct nand_chip *chip = mtd->priv; |
209 | ||
210 | switch (chipnr) { | |
1da177e4 | 211 | case -1: |
ace4dfee | 212 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
213 | break; |
214 | case 0: | |
1da177e4 LT |
215 | break; |
216 | ||
217 | default: | |
218 | BUG(); | |
219 | } | |
220 | } | |
221 | ||
222 | /** | |
223 | * nand_write_buf - [DEFAULT] write buffer to chip | |
224 | * @mtd: MTD device structure | |
225 | * @buf: data buffer | |
226 | * @len: number of bytes to write | |
227 | * | |
228 | * Default write function for 8bit buswith | |
229 | */ | |
58dd8f2b | 230 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
231 | { |
232 | int i; | |
ace4dfee | 233 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 234 | |
e0c7d767 | 235 | for (i = 0; i < len; i++) |
ace4dfee | 236 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
237 | } |
238 | ||
239 | /** | |
61b03bd7 | 240 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
241 | * @mtd: MTD device structure |
242 | * @buf: buffer to store date | |
243 | * @len: number of bytes to read | |
244 | * | |
245 | * Default read function for 8bit buswith | |
246 | */ | |
58dd8f2b | 247 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
248 | { |
249 | int i; | |
ace4dfee | 250 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 251 | |
e0c7d767 | 252 | for (i = 0; i < len; i++) |
ace4dfee | 253 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
254 | } |
255 | ||
256 | /** | |
61b03bd7 | 257 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
258 | * @mtd: MTD device structure |
259 | * @buf: buffer containing the data to compare | |
260 | * @len: number of bytes to compare | |
261 | * | |
262 | * Default verify function for 8bit buswith | |
263 | */ | |
58dd8f2b | 264 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
265 | { |
266 | int i; | |
ace4dfee | 267 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 268 | |
e0c7d767 | 269 | for (i = 0; i < len; i++) |
ace4dfee | 270 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 271 | return -EFAULT; |
1da177e4 LT |
272 | return 0; |
273 | } | |
274 | ||
275 | /** | |
276 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
277 | * @mtd: MTD device structure | |
278 | * @buf: data buffer | |
279 | * @len: number of bytes to write | |
280 | * | |
281 | * Default write function for 16bit buswith | |
282 | */ | |
58dd8f2b | 283 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
284 | { |
285 | int i; | |
ace4dfee | 286 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
287 | u16 *p = (u16 *) buf; |
288 | len >>= 1; | |
61b03bd7 | 289 | |
e0c7d767 | 290 | for (i = 0; i < len; i++) |
ace4dfee | 291 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 292 | |
1da177e4 LT |
293 | } |
294 | ||
295 | /** | |
61b03bd7 | 296 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
297 | * @mtd: MTD device structure |
298 | * @buf: buffer to store date | |
299 | * @len: number of bytes to read | |
300 | * | |
301 | * Default read function for 16bit buswith | |
302 | */ | |
58dd8f2b | 303 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
304 | { |
305 | int i; | |
ace4dfee | 306 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
307 | u16 *p = (u16 *) buf; |
308 | len >>= 1; | |
309 | ||
e0c7d767 | 310 | for (i = 0; i < len; i++) |
ace4dfee | 311 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
312 | } |
313 | ||
314 | /** | |
61b03bd7 | 315 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
316 | * @mtd: MTD device structure |
317 | * @buf: buffer containing the data to compare | |
318 | * @len: number of bytes to compare | |
319 | * | |
320 | * Default verify function for 16bit buswith | |
321 | */ | |
58dd8f2b | 322 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
323 | { |
324 | int i; | |
ace4dfee | 325 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
326 | u16 *p = (u16 *) buf; |
327 | len >>= 1; | |
328 | ||
e0c7d767 | 329 | for (i = 0; i < len; i++) |
ace4dfee | 330 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
331 | return -EFAULT; |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | /** | |
337 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
338 | * @mtd: MTD device structure | |
339 | * @ofs: offset from device start | |
340 | * @getchip: 0, if the chip is already selected | |
341 | * | |
61b03bd7 | 342 | * Check, if the block is bad. |
1da177e4 LT |
343 | */ |
344 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
345 | { | |
346 | int page, chipnr, res = 0; | |
ace4dfee | 347 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
348 | u16 bad; |
349 | ||
1a12f46a TK |
350 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
351 | ||
1da177e4 | 352 | if (getchip) { |
ace4dfee | 353 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 354 | |
ace4dfee | 355 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
356 | |
357 | /* Select the NAND device */ | |
ace4dfee | 358 | chip->select_chip(mtd, chipnr); |
1a12f46a | 359 | } |
1da177e4 | 360 | |
ace4dfee TG |
361 | if (chip->options & NAND_BUSWIDTH_16) { |
362 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
1a12f46a | 363 | page); |
ace4dfee TG |
364 | bad = cpu_to_le16(chip->read_word(mtd)); |
365 | if (chip->badblockpos & 0x1) | |
49196f33 | 366 | bad >>= 8; |
e0b58d0a ML |
367 | else |
368 | bad &= 0xFF; | |
1da177e4 | 369 | } else { |
1a12f46a | 370 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
e0b58d0a | 371 | bad = chip->read_byte(mtd); |
1da177e4 | 372 | } |
61b03bd7 | 373 | |
e0b58d0a ML |
374 | if (likely(chip->badblockbits == 8)) |
375 | res = bad != 0xFF; | |
376 | else | |
377 | res = hweight8(bad) < chip->badblockbits; | |
378 | ||
ace4dfee | 379 | if (getchip) |
1da177e4 | 380 | nand_release_device(mtd); |
61b03bd7 | 381 | |
1da177e4 LT |
382 | return res; |
383 | } | |
384 | ||
385 | /** | |
386 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
387 | * @mtd: MTD device structure | |
388 | * @ofs: offset from device start | |
389 | * | |
390 | * This is the default implementation, which can be overridden by | |
391 | * a hardware specific driver. | |
392 | */ | |
393 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
394 | { | |
ace4dfee | 395 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 396 | uint8_t buf[2] = { 0, 0 }; |
f1a28c02 | 397 | int block, ret; |
61b03bd7 | 398 | |
1da177e4 | 399 | /* Get block number */ |
4226b510 | 400 | block = (int)(ofs >> chip->bbt_erase_shift); |
ace4dfee TG |
401 | if (chip->bbt) |
402 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
403 | |
404 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 405 | if (chip->options & NAND_USE_FLASH_BBT) |
f1a28c02 TG |
406 | ret = nand_update_bbt(mtd, ofs); |
407 | else { | |
408 | /* We write two bytes, so we dont have to mess with 16 bit | |
409 | * access | |
410 | */ | |
c0b8ba7b | 411 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 412 | ofs += mtd->oobsize; |
ff0dab64 | 413 | chip->ops.len = chip->ops.ooblen = 2; |
f1a28c02 TG |
414 | chip->ops.datbuf = NULL; |
415 | chip->ops.oobbuf = buf; | |
416 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
417 | ||
418 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); | |
c0b8ba7b | 419 | nand_release_device(mtd); |
f1a28c02 TG |
420 | } |
421 | if (!ret) | |
422 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 423 | |
f1a28c02 | 424 | return ret; |
1da177e4 LT |
425 | } |
426 | ||
61b03bd7 | 427 | /** |
1da177e4 LT |
428 | * nand_check_wp - [GENERIC] check if the chip is write protected |
429 | * @mtd: MTD device structure | |
61b03bd7 | 430 | * Check, if the device is write protected |
1da177e4 | 431 | * |
61b03bd7 | 432 | * The function expects, that the device is already selected |
1da177e4 | 433 | */ |
e0c7d767 | 434 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 435 | { |
ace4dfee | 436 | struct nand_chip *chip = mtd->priv; |
93edbad6 ML |
437 | |
438 | /* broken xD cards report WP despite being writable */ | |
439 | if (chip->options & NAND_BROKEN_XD) | |
440 | return 0; | |
441 | ||
1da177e4 | 442 | /* Check the WP bit */ |
ace4dfee TG |
443 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
444 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
445 | } |
446 | ||
447 | /** | |
448 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
449 | * @mtd: MTD device structure | |
450 | * @ofs: offset from device start | |
451 | * @getchip: 0, if the chip is already selected | |
452 | * @allowbbt: 1, if its allowed to access the bbt area | |
453 | * | |
454 | * Check, if the block is bad. Either by reading the bad block table or | |
455 | * calling of the scan function. | |
456 | */ | |
2c0a2bed TG |
457 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
458 | int allowbbt) | |
1da177e4 | 459 | { |
ace4dfee | 460 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 461 | |
ace4dfee TG |
462 | if (!chip->bbt) |
463 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 464 | |
1da177e4 | 465 | /* Return info from the table */ |
e0c7d767 | 466 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
467 | } |
468 | ||
2af7c653 SK |
469 | /** |
470 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
471 | * @mtd: MTD device structure | |
472 | * @timeo: Timeout | |
473 | * | |
474 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
475 | * context. | |
476 | */ | |
477 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
478 | { | |
479 | struct nand_chip *chip = mtd->priv; | |
480 | int i; | |
481 | ||
482 | /* Wait for the device to get ready */ | |
483 | for (i = 0; i < timeo; i++) { | |
484 | if (chip->dev_ready(mtd)) | |
485 | break; | |
486 | touch_softlockup_watchdog(); | |
487 | mdelay(1); | |
488 | } | |
489 | } | |
490 | ||
61b03bd7 | 491 | /* |
3b88775c TG |
492 | * Wait for the ready pin, after a command |
493 | * The timeout is catched later. | |
494 | */ | |
4b648b02 | 495 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 496 | { |
ace4dfee | 497 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 498 | unsigned long timeo = jiffies + 2; |
3b88775c | 499 | |
2af7c653 SK |
500 | /* 400ms timeout */ |
501 | if (in_interrupt() || oops_in_progress) | |
502 | return panic_nand_wait_ready(mtd, 400); | |
503 | ||
8fe833c1 | 504 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
505 | /* wait until command is processed or timeout occures */ |
506 | do { | |
ace4dfee | 507 | if (chip->dev_ready(mtd)) |
8fe833c1 | 508 | break; |
8446f1d3 | 509 | touch_softlockup_watchdog(); |
61b03bd7 | 510 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 511 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 512 | } |
4b648b02 | 513 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 514 | |
1da177e4 LT |
515 | /** |
516 | * nand_command - [DEFAULT] Send command to NAND device | |
517 | * @mtd: MTD device structure | |
518 | * @command: the command to be sent | |
519 | * @column: the column address for this command, -1 if none | |
520 | * @page_addr: the page address for this command, -1 if none | |
521 | * | |
522 | * Send command to NAND device. This function is used for small page | |
523 | * devices (256/512 Bytes per page) | |
524 | */ | |
7abd3ef9 TG |
525 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
526 | int column, int page_addr) | |
1da177e4 | 527 | { |
ace4dfee | 528 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 529 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 530 | |
1da177e4 LT |
531 | /* |
532 | * Write out the command to the device. | |
533 | */ | |
534 | if (command == NAND_CMD_SEQIN) { | |
535 | int readcmd; | |
536 | ||
28318776 | 537 | if (column >= mtd->writesize) { |
1da177e4 | 538 | /* OOB area */ |
28318776 | 539 | column -= mtd->writesize; |
1da177e4 LT |
540 | readcmd = NAND_CMD_READOOB; |
541 | } else if (column < 256) { | |
542 | /* First 256 bytes --> READ0 */ | |
543 | readcmd = NAND_CMD_READ0; | |
544 | } else { | |
545 | column -= 256; | |
546 | readcmd = NAND_CMD_READ1; | |
547 | } | |
ace4dfee | 548 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 549 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 550 | } |
ace4dfee | 551 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 552 | |
7abd3ef9 TG |
553 | /* |
554 | * Address cycle, when necessary | |
555 | */ | |
556 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
557 | /* Serially input address */ | |
558 | if (column != -1) { | |
559 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 560 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 561 | column >>= 1; |
ace4dfee | 562 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
563 | ctrl &= ~NAND_CTRL_CHANGE; |
564 | } | |
565 | if (page_addr != -1) { | |
ace4dfee | 566 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 567 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 568 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 569 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
570 | if (chip->chipsize > (32 << 20)) |
571 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 572 | } |
ace4dfee | 573 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
574 | |
575 | /* | |
576 | * program and erase have their own busy handlers | |
1da177e4 | 577 | * status and sequential in needs no delay |
e0c7d767 | 578 | */ |
1da177e4 | 579 | switch (command) { |
61b03bd7 | 580 | |
1da177e4 LT |
581 | case NAND_CMD_PAGEPROG: |
582 | case NAND_CMD_ERASE1: | |
583 | case NAND_CMD_ERASE2: | |
584 | case NAND_CMD_SEQIN: | |
585 | case NAND_CMD_STATUS: | |
586 | return; | |
587 | ||
588 | case NAND_CMD_RESET: | |
ace4dfee | 589 | if (chip->dev_ready) |
1da177e4 | 590 | break; |
ace4dfee TG |
591 | udelay(chip->chip_delay); |
592 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 593 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
594 | chip->cmd_ctrl(mtd, |
595 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 596 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
597 | return; |
598 | ||
e0c7d767 | 599 | /* This applies to read commands */ |
1da177e4 | 600 | default: |
61b03bd7 | 601 | /* |
1da177e4 LT |
602 | * If we don't have access to the busy pin, we apply the given |
603 | * command delay | |
e0c7d767 | 604 | */ |
ace4dfee TG |
605 | if (!chip->dev_ready) { |
606 | udelay(chip->chip_delay); | |
1da177e4 | 607 | return; |
61b03bd7 | 608 | } |
1da177e4 | 609 | } |
1da177e4 LT |
610 | /* Apply this short delay always to ensure that we do wait tWB in |
611 | * any case on any machine. */ | |
e0c7d767 | 612 | ndelay(100); |
3b88775c TG |
613 | |
614 | nand_wait_ready(mtd); | |
1da177e4 LT |
615 | } |
616 | ||
617 | /** | |
618 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
619 | * @mtd: MTD device structure | |
620 | * @command: the command to be sent | |
621 | * @column: the column address for this command, -1 if none | |
622 | * @page_addr: the page address for this command, -1 if none | |
623 | * | |
7abd3ef9 TG |
624 | * Send command to NAND device. This is the version for the new large page |
625 | * devices We dont have the separate regions as we have in the small page | |
626 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 627 | */ |
7abd3ef9 TG |
628 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
629 | int column, int page_addr) | |
1da177e4 | 630 | { |
ace4dfee | 631 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
632 | |
633 | /* Emulate NAND_CMD_READOOB */ | |
634 | if (command == NAND_CMD_READOOB) { | |
28318776 | 635 | column += mtd->writesize; |
1da177e4 LT |
636 | command = NAND_CMD_READ0; |
637 | } | |
61b03bd7 | 638 | |
7abd3ef9 | 639 | /* Command latch cycle */ |
ace4dfee | 640 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 641 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
642 | |
643 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 644 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
645 | |
646 | /* Serially input address */ | |
647 | if (column != -1) { | |
648 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 649 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 650 | column >>= 1; |
ace4dfee | 651 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 652 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 653 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 654 | } |
1da177e4 | 655 | if (page_addr != -1) { |
ace4dfee TG |
656 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
657 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 658 | NAND_NCE | NAND_ALE); |
1da177e4 | 659 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
660 | if (chip->chipsize > (128 << 20)) |
661 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 662 | NAND_NCE | NAND_ALE); |
1da177e4 | 663 | } |
1da177e4 | 664 | } |
ace4dfee | 665 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
666 | |
667 | /* | |
668 | * program and erase have their own busy handlers | |
30f464b7 DM |
669 | * status, sequential in, and deplete1 need no delay |
670 | */ | |
1da177e4 | 671 | switch (command) { |
61b03bd7 | 672 | |
1da177e4 LT |
673 | case NAND_CMD_CACHEDPROG: |
674 | case NAND_CMD_PAGEPROG: | |
675 | case NAND_CMD_ERASE1: | |
676 | case NAND_CMD_ERASE2: | |
677 | case NAND_CMD_SEQIN: | |
7bc3312b | 678 | case NAND_CMD_RNDIN: |
1da177e4 | 679 | case NAND_CMD_STATUS: |
30f464b7 | 680 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
681 | return; |
682 | ||
e0c7d767 DW |
683 | /* |
684 | * read error status commands require only a short delay | |
685 | */ | |
30f464b7 DM |
686 | case NAND_CMD_STATUS_ERROR: |
687 | case NAND_CMD_STATUS_ERROR0: | |
688 | case NAND_CMD_STATUS_ERROR1: | |
689 | case NAND_CMD_STATUS_ERROR2: | |
690 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 691 | udelay(chip->chip_delay); |
30f464b7 | 692 | return; |
1da177e4 LT |
693 | |
694 | case NAND_CMD_RESET: | |
ace4dfee | 695 | if (chip->dev_ready) |
1da177e4 | 696 | break; |
ace4dfee | 697 | udelay(chip->chip_delay); |
12efdde3 TG |
698 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
699 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
700 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
701 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 702 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
703 | return; |
704 | ||
7bc3312b TG |
705 | case NAND_CMD_RNDOUT: |
706 | /* No ready / busy check necessary */ | |
707 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
708 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
709 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
710 | NAND_NCE | NAND_CTRL_CHANGE); | |
711 | return; | |
712 | ||
1da177e4 | 713 | case NAND_CMD_READ0: |
12efdde3 TG |
714 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
715 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
716 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
717 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 718 | |
e0c7d767 | 719 | /* This applies to read commands */ |
1da177e4 | 720 | default: |
61b03bd7 | 721 | /* |
1da177e4 LT |
722 | * If we don't have access to the busy pin, we apply the given |
723 | * command delay | |
e0c7d767 | 724 | */ |
ace4dfee TG |
725 | if (!chip->dev_ready) { |
726 | udelay(chip->chip_delay); | |
1da177e4 | 727 | return; |
61b03bd7 | 728 | } |
1da177e4 | 729 | } |
3b88775c | 730 | |
1da177e4 LT |
731 | /* Apply this short delay always to ensure that we do wait tWB in |
732 | * any case on any machine. */ | |
e0c7d767 | 733 | ndelay(100); |
3b88775c TG |
734 | |
735 | nand_wait_ready(mtd); | |
1da177e4 LT |
736 | } |
737 | ||
2af7c653 SK |
738 | /** |
739 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
740 | * @chip: the nand chip descriptor | |
741 | * @mtd: MTD device structure | |
742 | * @new_state: the state which is requested | |
743 | * | |
744 | * Used when in panic, no locks are taken. | |
745 | */ | |
746 | static void panic_nand_get_device(struct nand_chip *chip, | |
747 | struct mtd_info *mtd, int new_state) | |
748 | { | |
749 | /* Hardware controller shared among independend devices */ | |
750 | chip->controller->active = chip; | |
751 | chip->state = new_state; | |
752 | } | |
753 | ||
1da177e4 LT |
754 | /** |
755 | * nand_get_device - [GENERIC] Get chip for selected access | |
844d3b42 | 756 | * @chip: the nand chip descriptor |
1da177e4 | 757 | * @mtd: MTD device structure |
61b03bd7 | 758 | * @new_state: the state which is requested |
1da177e4 LT |
759 | * |
760 | * Get the device and lock it for exclusive access | |
761 | */ | |
2c0a2bed | 762 | static int |
ace4dfee | 763 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 764 | { |
ace4dfee TG |
765 | spinlock_t *lock = &chip->controller->lock; |
766 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 767 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 768 | retry: |
0dfc6246 TG |
769 | spin_lock(lock); |
770 | ||
b8b3ee9a | 771 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
772 | if (!chip->controller->active) |
773 | chip->controller->active = chip; | |
a36ed299 | 774 | |
ace4dfee TG |
775 | if (chip->controller->active == chip && chip->state == FL_READY) { |
776 | chip->state = new_state; | |
0dfc6246 | 777 | spin_unlock(lock); |
962034f4 VW |
778 | return 0; |
779 | } | |
780 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
781 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
782 | chip->state = FL_PM_SUSPENDED; | |
783 | spin_unlock(lock); | |
784 | return 0; | |
6b0d9a84 | 785 | } |
0dfc6246 TG |
786 | } |
787 | set_current_state(TASK_UNINTERRUPTIBLE); | |
788 | add_wait_queue(wq, &wait); | |
789 | spin_unlock(lock); | |
790 | schedule(); | |
791 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
792 | goto retry; |
793 | } | |
794 | ||
2af7c653 SK |
795 | /** |
796 | * panic_nand_wait - [GENERIC] wait until the command is done | |
797 | * @mtd: MTD device structure | |
798 | * @chip: NAND chip structure | |
799 | * @timeo: Timeout | |
800 | * | |
801 | * Wait for command done. This is a helper function for nand_wait used when | |
802 | * we are in interrupt context. May happen when in panic and trying to write | |
803 | * an oops trough mtdoops. | |
804 | */ | |
805 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
806 | unsigned long timeo) | |
807 | { | |
808 | int i; | |
809 | for (i = 0; i < timeo; i++) { | |
810 | if (chip->dev_ready) { | |
811 | if (chip->dev_ready(mtd)) | |
812 | break; | |
813 | } else { | |
814 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
815 | break; | |
816 | } | |
817 | mdelay(1); | |
818 | } | |
819 | } | |
820 | ||
1da177e4 LT |
821 | /** |
822 | * nand_wait - [DEFAULT] wait until the command is done | |
823 | * @mtd: MTD device structure | |
844d3b42 | 824 | * @chip: NAND chip structure |
1da177e4 LT |
825 | * |
826 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 827 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 | 828 | * general NAND and SmartMedia specs |
844d3b42 | 829 | */ |
7bc3312b | 830 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
831 | { |
832 | ||
e0c7d767 | 833 | unsigned long timeo = jiffies; |
7bc3312b | 834 | int status, state = chip->state; |
61b03bd7 | 835 | |
1da177e4 | 836 | if (state == FL_ERASING) |
e0c7d767 | 837 | timeo += (HZ * 400) / 1000; |
1da177e4 | 838 | else |
e0c7d767 | 839 | timeo += (HZ * 20) / 1000; |
1da177e4 | 840 | |
8fe833c1 RP |
841 | led_trigger_event(nand_led_trigger, LED_FULL); |
842 | ||
1da177e4 LT |
843 | /* Apply this short delay always to ensure that we do wait tWB in |
844 | * any case on any machine. */ | |
e0c7d767 | 845 | ndelay(100); |
1da177e4 | 846 | |
ace4dfee TG |
847 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
848 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 849 | else |
ace4dfee | 850 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 851 | |
2af7c653 SK |
852 | if (in_interrupt() || oops_in_progress) |
853 | panic_nand_wait(mtd, chip, timeo); | |
854 | else { | |
855 | while (time_before(jiffies, timeo)) { | |
856 | if (chip->dev_ready) { | |
857 | if (chip->dev_ready(mtd)) | |
858 | break; | |
859 | } else { | |
860 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
861 | break; | |
862 | } | |
863 | cond_resched(); | |
1da177e4 | 864 | } |
1da177e4 | 865 | } |
8fe833c1 RP |
866 | led_trigger_event(nand_led_trigger, LED_OFF); |
867 | ||
ace4dfee | 868 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
869 | return status; |
870 | } | |
871 | ||
7d70f334 VS |
872 | /** |
873 | * __nand_unlock - [REPLACABLE] unlocks specified locked blockes | |
874 | * | |
875 | * @param mtd - mtd info | |
876 | * @param ofs - offset to start unlock from | |
877 | * @param len - length to unlock | |
878 | * @invert - when = 0, unlock the range of blocks within the lower and | |
879 | * upper boundary address | |
880 | * whne = 1, unlock the range of blocks outside the boundaries | |
881 | * of the lower and upper boundary address | |
882 | * | |
883 | * @return - unlock status | |
884 | */ | |
885 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
886 | uint64_t len, int invert) | |
887 | { | |
888 | int ret = 0; | |
889 | int status, page; | |
890 | struct nand_chip *chip = mtd->priv; | |
891 | ||
892 | /* Submit address of first page to unlock */ | |
893 | page = ofs >> chip->page_shift; | |
894 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
895 | ||
896 | /* Submit address of last page to unlock */ | |
897 | page = (ofs + len) >> chip->page_shift; | |
898 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
899 | (page | invert) & chip->pagemask); | |
900 | ||
901 | /* Call wait ready function */ | |
902 | status = chip->waitfunc(mtd, chip); | |
903 | udelay(1000); | |
904 | /* See if device thinks it succeeded */ | |
905 | if (status & 0x01) { | |
906 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
907 | __func__, status); | |
908 | ret = -EIO; | |
909 | } | |
910 | ||
911 | return ret; | |
912 | } | |
913 | ||
914 | /** | |
915 | * nand_unlock - [REPLACABLE] unlocks specified locked blockes | |
916 | * | |
917 | * @param mtd - mtd info | |
918 | * @param ofs - offset to start unlock from | |
919 | * @param len - length to unlock | |
920 | * | |
921 | * @return - unlock status | |
922 | */ | |
923 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
924 | { | |
925 | int ret = 0; | |
926 | int chipnr; | |
927 | struct nand_chip *chip = mtd->priv; | |
928 | ||
929 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
930 | __func__, (unsigned long long)ofs, len); | |
931 | ||
932 | if (check_offs_len(mtd, ofs, len)) | |
933 | ret = -EINVAL; | |
934 | ||
935 | /* Align to last block address if size addresses end of the device */ | |
936 | if (ofs + len == mtd->size) | |
937 | len -= mtd->erasesize; | |
938 | ||
939 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
940 | ||
941 | /* Shift to get chip number */ | |
942 | chipnr = ofs >> chip->chip_shift; | |
943 | ||
944 | chip->select_chip(mtd, chipnr); | |
945 | ||
946 | /* Check, if it is write protected */ | |
947 | if (nand_check_wp(mtd)) { | |
948 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
949 | __func__); | |
950 | ret = -EIO; | |
951 | goto out; | |
952 | } | |
953 | ||
954 | ret = __nand_unlock(mtd, ofs, len, 0); | |
955 | ||
956 | out: | |
957 | /* de-select the NAND device */ | |
958 | chip->select_chip(mtd, -1); | |
959 | ||
960 | nand_release_device(mtd); | |
961 | ||
962 | return ret; | |
963 | } | |
964 | ||
965 | /** | |
966 | * nand_lock - [REPLACABLE] locks all blockes present in the device | |
967 | * | |
968 | * @param mtd - mtd info | |
969 | * @param ofs - offset to start unlock from | |
970 | * @param len - length to unlock | |
971 | * | |
972 | * @return - lock status | |
973 | * | |
974 | * This feature is not support in many NAND parts. 'Micron' NAND parts | |
975 | * do have this feature, but it allows only to lock all blocks not for | |
976 | * specified range for block. | |
977 | * | |
978 | * Implementing 'lock' feature by making use of 'unlock', for now. | |
979 | */ | |
980 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
981 | { | |
982 | int ret = 0; | |
983 | int chipnr, status, page; | |
984 | struct nand_chip *chip = mtd->priv; | |
985 | ||
986 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
987 | __func__, (unsigned long long)ofs, len); | |
988 | ||
989 | if (check_offs_len(mtd, ofs, len)) | |
990 | ret = -EINVAL; | |
991 | ||
992 | nand_get_device(chip, mtd, FL_LOCKING); | |
993 | ||
994 | /* Shift to get chip number */ | |
995 | chipnr = ofs >> chip->chip_shift; | |
996 | ||
997 | chip->select_chip(mtd, chipnr); | |
998 | ||
999 | /* Check, if it is write protected */ | |
1000 | if (nand_check_wp(mtd)) { | |
1001 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
1002 | __func__); | |
1003 | status = MTD_ERASE_FAILED; | |
1004 | ret = -EIO; | |
1005 | goto out; | |
1006 | } | |
1007 | ||
1008 | /* Submit address of first page to lock */ | |
1009 | page = ofs >> chip->page_shift; | |
1010 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1011 | ||
1012 | /* Call wait ready function */ | |
1013 | status = chip->waitfunc(mtd, chip); | |
1014 | udelay(1000); | |
1015 | /* See if device thinks it succeeded */ | |
1016 | if (status & 0x01) { | |
1017 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
1018 | __func__, status); | |
1019 | ret = -EIO; | |
1020 | goto out; | |
1021 | } | |
1022 | ||
1023 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1024 | ||
1025 | out: | |
1026 | /* de-select the NAND device */ | |
1027 | chip->select_chip(mtd, -1); | |
1028 | ||
1029 | nand_release_device(mtd); | |
1030 | ||
1031 | return ret; | |
1032 | } | |
1033 | ||
8593fbc6 TG |
1034 | /** |
1035 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
1036 | * @mtd: mtd info structure | |
1037 | * @chip: nand chip info structure | |
1038 | * @buf: buffer to store read data | |
58475fb9 | 1039 | * @page: page number to read |
52ff49df DB |
1040 | * |
1041 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1042 | */ |
1043 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1044 | uint8_t *buf, int page) |
8593fbc6 TG |
1045 | { |
1046 | chip->read_buf(mtd, buf, mtd->writesize); | |
1047 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1048 | return 0; | |
1049 | } | |
1050 | ||
52ff49df DB |
1051 | /** |
1052 | * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc | |
1053 | * @mtd: mtd info structure | |
1054 | * @chip: nand chip info structure | |
1055 | * @buf: buffer to store read data | |
58475fb9 | 1056 | * @page: page number to read |
52ff49df DB |
1057 | * |
1058 | * We need a special oob layout and handling even when OOB isn't used. | |
1059 | */ | |
1060 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1061 | uint8_t *buf, int page) |
52ff49df DB |
1062 | { |
1063 | int eccsize = chip->ecc.size; | |
1064 | int eccbytes = chip->ecc.bytes; | |
1065 | uint8_t *oob = chip->oob_poi; | |
1066 | int steps, size; | |
1067 | ||
1068 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1069 | chip->read_buf(mtd, buf, eccsize); | |
1070 | buf += eccsize; | |
1071 | ||
1072 | if (chip->ecc.prepad) { | |
1073 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1074 | oob += chip->ecc.prepad; | |
1075 | } | |
1076 | ||
1077 | chip->read_buf(mtd, oob, eccbytes); | |
1078 | oob += eccbytes; | |
1079 | ||
1080 | if (chip->ecc.postpad) { | |
1081 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1082 | oob += chip->ecc.postpad; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1087 | if (size) | |
1088 | chip->read_buf(mtd, oob, size); | |
1089 | ||
1090 | return 0; | |
1091 | } | |
1092 | ||
1da177e4 | 1093 | /** |
d29ebdbe | 1094 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
f5bbdacc TG |
1095 | * @mtd: mtd info structure |
1096 | * @chip: nand chip info structure | |
1097 | * @buf: buffer to store read data | |
58475fb9 | 1098 | * @page: page number to read |
068e3c0a | 1099 | */ |
f5bbdacc | 1100 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1101 | uint8_t *buf, int page) |
1da177e4 | 1102 | { |
f5bbdacc TG |
1103 | int i, eccsize = chip->ecc.size; |
1104 | int eccbytes = chip->ecc.bytes; | |
1105 | int eccsteps = chip->ecc.steps; | |
1106 | uint8_t *p = buf; | |
4bf63fcb DW |
1107 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1108 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1109 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 1110 | |
46a8cf2d | 1111 | chip->ecc.read_page_raw(mtd, chip, buf, page); |
f5bbdacc TG |
1112 | |
1113 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1114 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1115 | ||
1116 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1117 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1118 | |
1119 | eccsteps = chip->ecc.steps; | |
1120 | p = buf; | |
1121 | ||
1122 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1123 | int stat; | |
1124 | ||
1125 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
c32b8dcc | 1126 | if (stat < 0) |
f5bbdacc TG |
1127 | mtd->ecc_stats.failed++; |
1128 | else | |
1129 | mtd->ecc_stats.corrected += stat; | |
1130 | } | |
1131 | return 0; | |
22c60f5f | 1132 | } |
1da177e4 | 1133 | |
3d459559 AK |
1134 | /** |
1135 | * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function | |
1136 | * @mtd: mtd info structure | |
1137 | * @chip: nand chip info structure | |
17c1d2be AK |
1138 | * @data_offs: offset of requested data within the page |
1139 | * @readlen: data length | |
1140 | * @bufpoi: buffer to store read data | |
3d459559 AK |
1141 | */ |
1142 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
1143 | { | |
1144 | int start_step, end_step, num_steps; | |
1145 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1146 | uint8_t *p; | |
1147 | int data_col_addr, i, gaps = 0; | |
1148 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1149 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
1150 | ||
1151 | /* Column address wihin the page aligned to ECC size (256bytes). */ | |
1152 | start_step = data_offs / chip->ecc.size; | |
1153 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1154 | num_steps = end_step - start_step + 1; | |
1155 | ||
1156 | /* Data size aligned to ECC ecc.size*/ | |
1157 | datafrag_len = num_steps * chip->ecc.size; | |
1158 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1159 | ||
1160 | data_col_addr = start_step * chip->ecc.size; | |
1161 | /* If we read not a page aligned data */ | |
1162 | if (data_col_addr != 0) | |
1163 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1164 | ||
1165 | p = bufpoi + data_col_addr; | |
1166 | chip->read_buf(mtd, p, datafrag_len); | |
1167 | ||
1168 | /* Calculate ECC */ | |
1169 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) | |
1170 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1171 | ||
1172 | /* The performance is faster if to position offsets | |
1173 | according to ecc.pos. Let make sure here that | |
1174 | there are no gaps in ecc positions */ | |
1175 | for (i = 0; i < eccfrag_len - 1; i++) { | |
1176 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1177 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1178 | gaps = 1; | |
1179 | break; | |
1180 | } | |
1181 | } | |
1182 | if (gaps) { | |
1183 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1184 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1185 | } else { | |
1186 | /* send the command to read the particular ecc bytes */ | |
1187 | /* take care about buswidth alignment in read_buf */ | |
1188 | aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1); | |
1189 | aligned_len = eccfrag_len; | |
1190 | if (eccpos[start_step * chip->ecc.bytes] & (busw - 1)) | |
1191 | aligned_len++; | |
1192 | if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1)) | |
1193 | aligned_len++; | |
1194 | ||
1195 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1); | |
1196 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); | |
1197 | } | |
1198 | ||
1199 | for (i = 0; i < eccfrag_len; i++) | |
1200 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]]; | |
1201 | ||
1202 | p = bufpoi + data_col_addr; | |
1203 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1204 | int stat; | |
1205 | ||
1206 | stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
1207 | if (stat == -1) | |
1208 | mtd->ecc_stats.failed++; | |
1209 | else | |
1210 | mtd->ecc_stats.corrected += stat; | |
1211 | } | |
1212 | return 0; | |
1213 | } | |
1214 | ||
068e3c0a | 1215 | /** |
d29ebdbe | 1216 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
f5bbdacc TG |
1217 | * @mtd: mtd info structure |
1218 | * @chip: nand chip info structure | |
1219 | * @buf: buffer to store read data | |
58475fb9 | 1220 | * @page: page number to read |
068e3c0a | 1221 | * |
f5bbdacc | 1222 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 1223 | */ |
f5bbdacc | 1224 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1225 | uint8_t *buf, int page) |
1da177e4 | 1226 | { |
f5bbdacc TG |
1227 | int i, eccsize = chip->ecc.size; |
1228 | int eccbytes = chip->ecc.bytes; | |
1229 | int eccsteps = chip->ecc.steps; | |
1230 | uint8_t *p = buf; | |
4bf63fcb DW |
1231 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1232 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1233 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
1234 | |
1235 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1236 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1237 | chip->read_buf(mtd, p, eccsize); | |
1238 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1239 | } |
f75e5097 | 1240 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1241 | |
f5bbdacc | 1242 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1243 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1244 | |
f5bbdacc TG |
1245 | eccsteps = chip->ecc.steps; |
1246 | p = buf; | |
61b03bd7 | 1247 | |
f5bbdacc TG |
1248 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1249 | int stat; | |
1da177e4 | 1250 | |
f5bbdacc | 1251 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
c32b8dcc | 1252 | if (stat < 0) |
f5bbdacc TG |
1253 | mtd->ecc_stats.failed++; |
1254 | else | |
1255 | mtd->ecc_stats.corrected += stat; | |
1256 | } | |
1257 | return 0; | |
1258 | } | |
1da177e4 | 1259 | |
6e0cb135 SN |
1260 | /** |
1261 | * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first | |
1262 | * @mtd: mtd info structure | |
1263 | * @chip: nand chip info structure | |
1264 | * @buf: buffer to store read data | |
58475fb9 | 1265 | * @page: page number to read |
6e0cb135 SN |
1266 | * |
1267 | * Hardware ECC for large page chips, require OOB to be read first. | |
1268 | * For this ECC mode, the write_page method is re-used from ECC_HW. | |
1269 | * These methods read/write ECC from the OOB area, unlike the | |
1270 | * ECC_HW_SYNDROME support with multiple ECC steps, follows the | |
1271 | * "infix ECC" scheme and reads/writes ECC from the data area, by | |
1272 | * overwriting the NAND manufacturer bad block markings. | |
1273 | */ | |
1274 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1275 | struct nand_chip *chip, uint8_t *buf, int page) | |
1276 | { | |
1277 | int i, eccsize = chip->ecc.size; | |
1278 | int eccbytes = chip->ecc.bytes; | |
1279 | int eccsteps = chip->ecc.steps; | |
1280 | uint8_t *p = buf; | |
1281 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1282 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1283 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1284 | ||
1285 | /* Read the OOB area first */ | |
1286 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1287 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1288 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1289 | ||
1290 | for (i = 0; i < chip->ecc.total; i++) | |
1291 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1292 | ||
1293 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1294 | int stat; | |
1295 | ||
1296 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1297 | chip->read_buf(mtd, p, eccsize); | |
1298 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1299 | ||
1300 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
1301 | if (stat < 0) | |
1302 | mtd->ecc_stats.failed++; | |
1303 | else | |
1304 | mtd->ecc_stats.corrected += stat; | |
1305 | } | |
1306 | return 0; | |
1307 | } | |
1308 | ||
f5bbdacc | 1309 | /** |
d29ebdbe | 1310 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
f5bbdacc TG |
1311 | * @mtd: mtd info structure |
1312 | * @chip: nand chip info structure | |
1313 | * @buf: buffer to store read data | |
58475fb9 | 1314 | * @page: page number to read |
f5bbdacc TG |
1315 | * |
1316 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 1317 | * we need a special oob layout and handling. |
f5bbdacc TG |
1318 | */ |
1319 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1320 | uint8_t *buf, int page) |
f5bbdacc TG |
1321 | { |
1322 | int i, eccsize = chip->ecc.size; | |
1323 | int eccbytes = chip->ecc.bytes; | |
1324 | int eccsteps = chip->ecc.steps; | |
1325 | uint8_t *p = buf; | |
f75e5097 | 1326 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 1327 | |
f5bbdacc TG |
1328 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1329 | int stat; | |
61b03bd7 | 1330 | |
f5bbdacc TG |
1331 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1332 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1333 | |
f5bbdacc TG |
1334 | if (chip->ecc.prepad) { |
1335 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1336 | oob += chip->ecc.prepad; | |
1337 | } | |
1da177e4 | 1338 | |
f5bbdacc TG |
1339 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1340 | chip->read_buf(mtd, oob, eccbytes); | |
1341 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1342 | |
c32b8dcc | 1343 | if (stat < 0) |
f5bbdacc | 1344 | mtd->ecc_stats.failed++; |
61b03bd7 | 1345 | else |
f5bbdacc | 1346 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 1347 | |
f5bbdacc | 1348 | oob += eccbytes; |
1da177e4 | 1349 | |
f5bbdacc TG |
1350 | if (chip->ecc.postpad) { |
1351 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1352 | oob += chip->ecc.postpad; | |
61b03bd7 | 1353 | } |
f5bbdacc | 1354 | } |
1da177e4 | 1355 | |
f5bbdacc | 1356 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1357 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1358 | if (i) |
1359 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1360 | |
f5bbdacc TG |
1361 | return 0; |
1362 | } | |
1da177e4 | 1363 | |
f5bbdacc | 1364 | /** |
8593fbc6 TG |
1365 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
1366 | * @chip: nand chip structure | |
844d3b42 | 1367 | * @oob: oob destination address |
8593fbc6 | 1368 | * @ops: oob ops structure |
7014568b | 1369 | * @len: size of oob to transfer |
8593fbc6 TG |
1370 | */ |
1371 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1372 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1373 | { |
8593fbc6 TG |
1374 | switch(ops->mode) { |
1375 | ||
1376 | case MTD_OOB_PLACE: | |
1377 | case MTD_OOB_RAW: | |
1378 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
1379 | return oob + len; | |
1380 | ||
1381 | case MTD_OOB_AUTO: { | |
1382 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
1383 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1384 | size_t bytes = 0; | |
8593fbc6 TG |
1385 | |
1386 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
1387 | /* Read request not from offset 0 ? */ |
1388 | if (unlikely(roffs)) { | |
1389 | if (roffs >= free->length) { | |
1390 | roffs -= free->length; | |
1391 | continue; | |
1392 | } | |
1393 | boffs = free->offset + roffs; | |
1394 | bytes = min_t(size_t, len, | |
1395 | (free->length - roffs)); | |
1396 | roffs = 0; | |
1397 | } else { | |
1398 | bytes = min_t(size_t, len, free->length); | |
1399 | boffs = free->offset; | |
1400 | } | |
1401 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1402 | oob += bytes; |
1403 | } | |
1404 | return oob; | |
1405 | } | |
1406 | default: | |
1407 | BUG(); | |
1408 | } | |
1409 | return NULL; | |
1410 | } | |
1411 | ||
1412 | /** | |
1413 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
1414 | * |
1415 | * @mtd: MTD device structure | |
1416 | * @from: offset to read from | |
844d3b42 | 1417 | * @ops: oob ops structure |
f5bbdacc TG |
1418 | * |
1419 | * Internal function. Called with chip held. | |
1420 | */ | |
8593fbc6 TG |
1421 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1422 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
1423 | { |
1424 | int chipnr, page, realpage, col, bytes, aligned; | |
1425 | struct nand_chip *chip = mtd->priv; | |
1426 | struct mtd_ecc_stats stats; | |
1427 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1428 | int sndcmd = 1; | |
1429 | int ret = 0; | |
8593fbc6 | 1430 | uint32_t readlen = ops->len; |
7014568b | 1431 | uint32_t oobreadlen = ops->ooblen; |
9aca334e ML |
1432 | uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ? |
1433 | mtd->oobavail : mtd->oobsize; | |
1434 | ||
8593fbc6 | 1435 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 1436 | |
f5bbdacc | 1437 | stats = mtd->ecc_stats; |
1da177e4 | 1438 | |
f5bbdacc TG |
1439 | chipnr = (int)(from >> chip->chip_shift); |
1440 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1441 | |
f5bbdacc TG |
1442 | realpage = (int)(from >> chip->page_shift); |
1443 | page = realpage & chip->pagemask; | |
1da177e4 | 1444 | |
f5bbdacc | 1445 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1446 | |
8593fbc6 TG |
1447 | buf = ops->datbuf; |
1448 | oob = ops->oobbuf; | |
1449 | ||
f5bbdacc TG |
1450 | while(1) { |
1451 | bytes = min(mtd->writesize - col, readlen); | |
1452 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1453 | |
f5bbdacc | 1454 | /* Is the current page in the buffer ? */ |
8593fbc6 | 1455 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1456 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1457 | |
f5bbdacc TG |
1458 | if (likely(sndcmd)) { |
1459 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1460 | sndcmd = 0; | |
1da177e4 | 1461 | } |
1da177e4 | 1462 | |
f5bbdacc | 1463 | /* Now read the page into the buffer */ |
956e944c | 1464 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
46a8cf2d SN |
1465 | ret = chip->ecc.read_page_raw(mtd, chip, |
1466 | bufpoi, page); | |
3d459559 AK |
1467 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
1468 | ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); | |
956e944c | 1469 | else |
46a8cf2d SN |
1470 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
1471 | page); | |
f5bbdacc | 1472 | if (ret < 0) |
1da177e4 | 1473 | break; |
f5bbdacc TG |
1474 | |
1475 | /* Transfer not aligned data */ | |
1476 | if (!aligned) { | |
3d459559 AK |
1477 | if (!NAND_SUBPAGE_READ(chip) && !oob) |
1478 | chip->pagebuf = realpage; | |
4bf63fcb | 1479 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1480 | } |
1481 | ||
8593fbc6 TG |
1482 | buf += bytes; |
1483 | ||
1484 | if (unlikely(oob)) { | |
9aca334e | 1485 | |
b64d39d8 ML |
1486 | int toread = min(oobreadlen, max_oobsize); |
1487 | ||
1488 | if (toread) { | |
1489 | oob = nand_transfer_oob(chip, | |
1490 | oob, ops, toread); | |
1491 | oobreadlen -= toread; | |
1492 | } | |
8593fbc6 TG |
1493 | } |
1494 | ||
f5bbdacc TG |
1495 | if (!(chip->options & NAND_NO_READRDY)) { |
1496 | /* | |
1497 | * Apply delay or wait for ready/busy pin. Do | |
1498 | * this before the AUTOINCR check, so no | |
1499 | * problems arise if a chip which does auto | |
1500 | * increment is marked as NOAUTOINCR by the | |
1501 | * board driver. | |
1502 | */ | |
1503 | if (!chip->dev_ready) | |
1504 | udelay(chip->chip_delay); | |
1505 | else | |
1506 | nand_wait_ready(mtd); | |
1da177e4 | 1507 | } |
8593fbc6 | 1508 | } else { |
4bf63fcb | 1509 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1510 | buf += bytes; |
1511 | } | |
1da177e4 | 1512 | |
f5bbdacc | 1513 | readlen -= bytes; |
61b03bd7 | 1514 | |
f5bbdacc | 1515 | if (!readlen) |
61b03bd7 | 1516 | break; |
1da177e4 LT |
1517 | |
1518 | /* For subsequent reads align to page boundary. */ | |
1519 | col = 0; | |
1520 | /* Increment page address */ | |
1521 | realpage++; | |
1522 | ||
ace4dfee | 1523 | page = realpage & chip->pagemask; |
1da177e4 LT |
1524 | /* Check, if we cross a chip boundary */ |
1525 | if (!page) { | |
1526 | chipnr++; | |
ace4dfee TG |
1527 | chip->select_chip(mtd, -1); |
1528 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1529 | } |
f5bbdacc | 1530 | |
61b03bd7 TG |
1531 | /* Check, if the chip supports auto page increment |
1532 | * or if we have hit a block boundary. | |
e0c7d767 | 1533 | */ |
f5bbdacc | 1534 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1535 | sndcmd = 1; |
1da177e4 LT |
1536 | } |
1537 | ||
8593fbc6 | 1538 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1539 | if (oob) |
1540 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1541 | |
f5bbdacc TG |
1542 | if (ret) |
1543 | return ret; | |
1544 | ||
9a1fcdfd TG |
1545 | if (mtd->ecc_stats.failed - stats.failed) |
1546 | return -EBADMSG; | |
1547 | ||
1548 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1549 | } |
1550 | ||
1551 | /** | |
1552 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
1553 | * @mtd: MTD device structure | |
1554 | * @from: offset to read from | |
1555 | * @len: number of bytes to read | |
1556 | * @retlen: pointer to variable to store the number of read bytes | |
1557 | * @buf: the databuffer to put data | |
1558 | * | |
1559 | * Get hold of the chip and call nand_do_read | |
1560 | */ | |
1561 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1562 | size_t *retlen, uint8_t *buf) | |
1563 | { | |
8593fbc6 | 1564 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1565 | int ret; |
1566 | ||
f5bbdacc TG |
1567 | /* Do not allow reads past end of device */ |
1568 | if ((from + len) > mtd->size) | |
1569 | return -EINVAL; | |
1570 | if (!len) | |
1571 | return 0; | |
1572 | ||
8593fbc6 | 1573 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1574 | |
8593fbc6 TG |
1575 | chip->ops.len = len; |
1576 | chip->ops.datbuf = buf; | |
1577 | chip->ops.oobbuf = NULL; | |
1578 | ||
1579 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc | 1580 | |
7fd5aecc RP |
1581 | *retlen = chip->ops.retlen; |
1582 | ||
f5bbdacc TG |
1583 | nand_release_device(mtd); |
1584 | ||
1585 | return ret; | |
1da177e4 LT |
1586 | } |
1587 | ||
7bc3312b TG |
1588 | /** |
1589 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function | |
1590 | * @mtd: mtd info structure | |
1591 | * @chip: nand chip info structure | |
1592 | * @page: page number to read | |
1593 | * @sndcmd: flag whether to issue read command or not | |
1594 | */ | |
1595 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1596 | int page, int sndcmd) | |
1597 | { | |
1598 | if (sndcmd) { | |
1599 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1600 | sndcmd = 0; | |
1601 | } | |
1602 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1603 | return sndcmd; | |
1604 | } | |
1605 | ||
1606 | /** | |
1607 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC | |
1608 | * with syndromes | |
1609 | * @mtd: mtd info structure | |
1610 | * @chip: nand chip info structure | |
1611 | * @page: page number to read | |
1612 | * @sndcmd: flag whether to issue read command or not | |
1613 | */ | |
1614 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1615 | int page, int sndcmd) | |
1616 | { | |
1617 | uint8_t *buf = chip->oob_poi; | |
1618 | int length = mtd->oobsize; | |
1619 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1620 | int eccsize = chip->ecc.size; | |
1621 | uint8_t *bufpoi = buf; | |
1622 | int i, toread, sndrnd = 0, pos; | |
1623 | ||
1624 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1625 | for (i = 0; i < chip->ecc.steps; i++) { | |
1626 | if (sndrnd) { | |
1627 | pos = eccsize + i * (eccsize + chunk); | |
1628 | if (mtd->writesize > 512) | |
1629 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1630 | else | |
1631 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1632 | } else | |
1633 | sndrnd = 1; | |
1634 | toread = min_t(int, length, chunk); | |
1635 | chip->read_buf(mtd, bufpoi, toread); | |
1636 | bufpoi += toread; | |
1637 | length -= toread; | |
1638 | } | |
1639 | if (length > 0) | |
1640 | chip->read_buf(mtd, bufpoi, length); | |
1641 | ||
1642 | return 1; | |
1643 | } | |
1644 | ||
1645 | /** | |
1646 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function | |
1647 | * @mtd: mtd info structure | |
1648 | * @chip: nand chip info structure | |
1649 | * @page: page number to write | |
1650 | */ | |
1651 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1652 | int page) | |
1653 | { | |
1654 | int status = 0; | |
1655 | const uint8_t *buf = chip->oob_poi; | |
1656 | int length = mtd->oobsize; | |
1657 | ||
1658 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1659 | chip->write_buf(mtd, buf, length); | |
1660 | /* Send command to program the OOB data */ | |
1661 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1662 | ||
1663 | status = chip->waitfunc(mtd, chip); | |
1664 | ||
0d420f9d | 1665 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1666 | } |
1667 | ||
1668 | /** | |
1669 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC | |
1670 | * with syndrome - only for large page flash ! | |
1671 | * @mtd: mtd info structure | |
1672 | * @chip: nand chip info structure | |
1673 | * @page: page number to write | |
1674 | */ | |
1675 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1676 | struct nand_chip *chip, int page) | |
1677 | { | |
1678 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1679 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1680 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1681 | const uint8_t *bufpoi = chip->oob_poi; | |
1682 | ||
1683 | /* | |
1684 | * data-ecc-data-ecc ... ecc-oob | |
1685 | * or | |
1686 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1687 | */ | |
1688 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1689 | pos = steps * (eccsize + chunk); | |
1690 | steps = 0; | |
1691 | } else | |
8b0036ee | 1692 | pos = eccsize; |
7bc3312b TG |
1693 | |
1694 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1695 | for (i = 0; i < steps; i++) { | |
1696 | if (sndcmd) { | |
1697 | if (mtd->writesize <= 512) { | |
1698 | uint32_t fill = 0xFFFFFFFF; | |
1699 | ||
1700 | len = eccsize; | |
1701 | while (len > 0) { | |
1702 | int num = min_t(int, len, 4); | |
1703 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1704 | num); | |
1705 | len -= num; | |
1706 | } | |
1707 | } else { | |
1708 | pos = eccsize + i * (eccsize + chunk); | |
1709 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1710 | } | |
1711 | } else | |
1712 | sndcmd = 1; | |
1713 | len = min_t(int, length, chunk); | |
1714 | chip->write_buf(mtd, bufpoi, len); | |
1715 | bufpoi += len; | |
1716 | length -= len; | |
1717 | } | |
1718 | if (length > 0) | |
1719 | chip->write_buf(mtd, bufpoi, length); | |
1720 | ||
1721 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1722 | status = chip->waitfunc(mtd, chip); | |
1723 | ||
1724 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1725 | } | |
1726 | ||
1da177e4 | 1727 | /** |
8593fbc6 | 1728 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1729 | * @mtd: MTD device structure |
1730 | * @from: offset to read from | |
8593fbc6 | 1731 | * @ops: oob operations description structure |
1da177e4 LT |
1732 | * |
1733 | * NAND read out-of-band data from the spare area | |
1734 | */ | |
8593fbc6 TG |
1735 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1736 | struct mtd_oob_ops *ops) | |
1da177e4 | 1737 | { |
7bc3312b | 1738 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1739 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1740 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1741 | int readlen = ops->ooblen; |
1742 | int len; | |
7bc3312b | 1743 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1744 | |
20d8e248 | 1745 | DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", |
1746 | __func__, (unsigned long long)from, readlen); | |
1da177e4 | 1747 | |
03736155 | 1748 | if (ops->mode == MTD_OOB_AUTO) |
7014568b | 1749 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1750 | else |
1751 | len = mtd->oobsize; | |
1752 | ||
1753 | if (unlikely(ops->ooboffs >= len)) { | |
20d8e248 | 1754 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " |
1755 | "outside oob\n", __func__); | |
03736155 AH |
1756 | return -EINVAL; |
1757 | } | |
1758 | ||
1759 | /* Do not allow reads past end of device */ | |
1760 | if (unlikely(from >= mtd->size || | |
1761 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1762 | (from >> chip->page_shift)) * len)) { | |
20d8e248 | 1763 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " |
1764 | "of device\n", __func__); | |
03736155 AH |
1765 | return -EINVAL; |
1766 | } | |
7014568b | 1767 | |
7314e9e7 | 1768 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1769 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1770 | |
7314e9e7 TG |
1771 | /* Shift to get page */ |
1772 | realpage = (int)(from >> chip->page_shift); | |
1773 | page = realpage & chip->pagemask; | |
1da177e4 | 1774 | |
7314e9e7 | 1775 | while(1) { |
7bc3312b | 1776 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
7014568b VW |
1777 | |
1778 | len = min(len, readlen); | |
1779 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1780 | |
7314e9e7 TG |
1781 | if (!(chip->options & NAND_NO_READRDY)) { |
1782 | /* | |
1783 | * Apply delay or wait for ready/busy pin. Do this | |
1784 | * before the AUTOINCR check, so no problems arise if a | |
1785 | * chip which does auto increment is marked as | |
1786 | * NOAUTOINCR by the board driver. | |
19870da7 | 1787 | */ |
ace4dfee TG |
1788 | if (!chip->dev_ready) |
1789 | udelay(chip->chip_delay); | |
19870da7 TG |
1790 | else |
1791 | nand_wait_ready(mtd); | |
7314e9e7 | 1792 | } |
19870da7 | 1793 | |
7014568b | 1794 | readlen -= len; |
0d420f9d SZ |
1795 | if (!readlen) |
1796 | break; | |
1797 | ||
7314e9e7 TG |
1798 | /* Increment page address */ |
1799 | realpage++; | |
1800 | ||
1801 | page = realpage & chip->pagemask; | |
1802 | /* Check, if we cross a chip boundary */ | |
1803 | if (!page) { | |
1804 | chipnr++; | |
1805 | chip->select_chip(mtd, -1); | |
1806 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1807 | } |
7314e9e7 TG |
1808 | |
1809 | /* Check, if the chip supports auto page increment | |
1810 | * or if we have hit a block boundary. | |
1811 | */ | |
1812 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1813 | sndcmd = 1; | |
1da177e4 LT |
1814 | } |
1815 | ||
7014568b | 1816 | ops->oobretlen = ops->ooblen; |
1da177e4 LT |
1817 | return 0; |
1818 | } | |
1819 | ||
1820 | /** | |
8593fbc6 | 1821 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1822 | * @mtd: MTD device structure |
1da177e4 | 1823 | * @from: offset to read from |
8593fbc6 | 1824 | * @ops: oob operation description structure |
1da177e4 | 1825 | * |
8593fbc6 | 1826 | * NAND read data and/or out-of-band data |
1da177e4 | 1827 | */ |
8593fbc6 TG |
1828 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1829 | struct mtd_oob_ops *ops) | |
1da177e4 | 1830 | { |
ace4dfee | 1831 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1832 | int ret = -ENOTSUPP; |
1833 | ||
1834 | ops->retlen = 0; | |
1da177e4 LT |
1835 | |
1836 | /* Do not allow reads past end of device */ | |
7014568b | 1837 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
20d8e248 | 1838 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " |
1839 | "beyond end of device\n", __func__); | |
1da177e4 LT |
1840 | return -EINVAL; |
1841 | } | |
1842 | ||
ace4dfee | 1843 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1844 | |
8593fbc6 TG |
1845 | switch(ops->mode) { |
1846 | case MTD_OOB_PLACE: | |
1847 | case MTD_OOB_AUTO: | |
8593fbc6 | 1848 | case MTD_OOB_RAW: |
8593fbc6 | 1849 | break; |
1da177e4 | 1850 | |
8593fbc6 TG |
1851 | default: |
1852 | goto out; | |
1853 | } | |
1da177e4 | 1854 | |
8593fbc6 TG |
1855 | if (!ops->datbuf) |
1856 | ret = nand_do_read_oob(mtd, from, ops); | |
1857 | else | |
1858 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1859 | |
8593fbc6 TG |
1860 | out: |
1861 | nand_release_device(mtd); | |
1862 | return ret; | |
1863 | } | |
61b03bd7 | 1864 | |
1da177e4 | 1865 | |
8593fbc6 TG |
1866 | /** |
1867 | * nand_write_page_raw - [Intern] raw page write function | |
1868 | * @mtd: mtd info structure | |
1869 | * @chip: nand chip info structure | |
1870 | * @buf: data buffer | |
52ff49df DB |
1871 | * |
1872 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1873 | */ |
1874 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1875 | const uint8_t *buf) | |
1876 | { | |
1877 | chip->write_buf(mtd, buf, mtd->writesize); | |
1878 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1879 | } |
1880 | ||
52ff49df DB |
1881 | /** |
1882 | * nand_write_page_raw_syndrome - [Intern] raw page write function | |
1883 | * @mtd: mtd info structure | |
1884 | * @chip: nand chip info structure | |
1885 | * @buf: data buffer | |
1886 | * | |
1887 | * We need a special oob layout and handling even when ECC isn't checked. | |
1888 | */ | |
1889 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1890 | const uint8_t *buf) | |
1891 | { | |
1892 | int eccsize = chip->ecc.size; | |
1893 | int eccbytes = chip->ecc.bytes; | |
1894 | uint8_t *oob = chip->oob_poi; | |
1895 | int steps, size; | |
1896 | ||
1897 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1898 | chip->write_buf(mtd, buf, eccsize); | |
1899 | buf += eccsize; | |
1900 | ||
1901 | if (chip->ecc.prepad) { | |
1902 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1903 | oob += chip->ecc.prepad; | |
1904 | } | |
1905 | ||
1906 | chip->read_buf(mtd, oob, eccbytes); | |
1907 | oob += eccbytes; | |
1908 | ||
1909 | if (chip->ecc.postpad) { | |
1910 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1911 | oob += chip->ecc.postpad; | |
1912 | } | |
1913 | } | |
1914 | ||
1915 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1916 | if (size) | |
1917 | chip->write_buf(mtd, oob, size); | |
1918 | } | |
9223a456 | 1919 | /** |
d29ebdbe | 1920 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
f75e5097 TG |
1921 | * @mtd: mtd info structure |
1922 | * @chip: nand chip info structure | |
1923 | * @buf: data buffer | |
9223a456 | 1924 | */ |
f75e5097 TG |
1925 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1926 | const uint8_t *buf) | |
9223a456 | 1927 | { |
f75e5097 TG |
1928 | int i, eccsize = chip->ecc.size; |
1929 | int eccbytes = chip->ecc.bytes; | |
1930 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1931 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1932 | const uint8_t *p = buf; |
8b099a39 | 1933 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1934 | |
8593fbc6 TG |
1935 | /* Software ecc calculation */ |
1936 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1937 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1938 | |
8593fbc6 TG |
1939 | for (i = 0; i < chip->ecc.total; i++) |
1940 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1941 | |
90424de8 | 1942 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1943 | } |
9223a456 | 1944 | |
f75e5097 | 1945 | /** |
d29ebdbe | 1946 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
f75e5097 TG |
1947 | * @mtd: mtd info structure |
1948 | * @chip: nand chip info structure | |
1949 | * @buf: data buffer | |
1950 | */ | |
1951 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1952 | const uint8_t *buf) | |
1953 | { | |
1954 | int i, eccsize = chip->ecc.size; | |
1955 | int eccbytes = chip->ecc.bytes; | |
1956 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1957 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1958 | const uint8_t *p = buf; |
8b099a39 | 1959 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1960 | |
f75e5097 TG |
1961 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1962 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1963 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1964 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1965 | } |
1966 | ||
f75e5097 TG |
1967 | for (i = 0; i < chip->ecc.total; i++) |
1968 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1969 | ||
1970 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1971 | } |
1972 | ||
61b03bd7 | 1973 | /** |
d29ebdbe | 1974 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
f75e5097 TG |
1975 | * @mtd: mtd info structure |
1976 | * @chip: nand chip info structure | |
1977 | * @buf: data buffer | |
1da177e4 | 1978 | * |
f75e5097 TG |
1979 | * The hw generator calculates the error syndrome automatically. Therefor |
1980 | * we need a special oob layout and handling. | |
1981 | */ | |
1982 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1983 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1984 | { |
f75e5097 TG |
1985 | int i, eccsize = chip->ecc.size; |
1986 | int eccbytes = chip->ecc.bytes; | |
1987 | int eccsteps = chip->ecc.steps; | |
1988 | const uint8_t *p = buf; | |
1989 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1990 | |
f75e5097 | 1991 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1992 | |
f75e5097 TG |
1993 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1994 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 1995 | |
f75e5097 TG |
1996 | if (chip->ecc.prepad) { |
1997 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1998 | oob += chip->ecc.prepad; | |
1999 | } | |
2000 | ||
2001 | chip->ecc.calculate(mtd, p, oob); | |
2002 | chip->write_buf(mtd, oob, eccbytes); | |
2003 | oob += eccbytes; | |
2004 | ||
2005 | if (chip->ecc.postpad) { | |
2006 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2007 | oob += chip->ecc.postpad; | |
1da177e4 | 2008 | } |
1da177e4 | 2009 | } |
f75e5097 TG |
2010 | |
2011 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2012 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2013 | if (i) |
2014 | chip->write_buf(mtd, oob, i); | |
2015 | } | |
2016 | ||
2017 | /** | |
956e944c | 2018 | * nand_write_page - [REPLACEABLE] write one page |
f75e5097 TG |
2019 | * @mtd: MTD device structure |
2020 | * @chip: NAND chip descriptor | |
2021 | * @buf: the data to write | |
2022 | * @page: page number to write | |
2023 | * @cached: cached programming | |
efbfe96c | 2024 | * @raw: use _raw version of write_page |
f75e5097 TG |
2025 | */ |
2026 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 2027 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
2028 | { |
2029 | int status; | |
2030 | ||
2031 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2032 | ||
956e944c DW |
2033 | if (unlikely(raw)) |
2034 | chip->ecc.write_page_raw(mtd, chip, buf); | |
2035 | else | |
2036 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
2037 | |
2038 | /* | |
2039 | * Cached progamming disabled for now, Not sure if its worth the | |
2040 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
2041 | */ | |
2042 | cached = 0; | |
2043 | ||
2044 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2045 | ||
2046 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2047 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2048 | /* |
2049 | * See if operation failed and additional status checks are | |
2050 | * available | |
2051 | */ | |
2052 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2053 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2054 | page); | |
2055 | ||
2056 | if (status & NAND_STATUS_FAIL) | |
2057 | return -EIO; | |
2058 | } else { | |
2059 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2060 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2061 | } |
2062 | ||
2063 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
2064 | /* Send command to read back the data */ | |
2065 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
2066 | ||
2067 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
2068 | return -EIO; | |
2069 | #endif | |
2070 | return 0; | |
1da177e4 LT |
2071 | } |
2072 | ||
8593fbc6 TG |
2073 | /** |
2074 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
2075 | * @chip: nand chip structure | |
2076 | * @oob: oob data buffer | |
2077 | * @ops: oob ops structure | |
2078 | */ | |
782ce79a ML |
2079 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, |
2080 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2081 | { |
8593fbc6 TG |
2082 | switch(ops->mode) { |
2083 | ||
2084 | case MTD_OOB_PLACE: | |
2085 | case MTD_OOB_RAW: | |
2086 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
2087 | return oob + len; | |
2088 | ||
2089 | case MTD_OOB_AUTO: { | |
2090 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
2091 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2092 | size_t bytes = 0; | |
8593fbc6 TG |
2093 | |
2094 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
2095 | /* Write request not from offset 0 ? */ |
2096 | if (unlikely(woffs)) { | |
2097 | if (woffs >= free->length) { | |
2098 | woffs -= free->length; | |
2099 | continue; | |
2100 | } | |
2101 | boffs = free->offset + woffs; | |
2102 | bytes = min_t(size_t, len, | |
2103 | (free->length - woffs)); | |
2104 | woffs = 0; | |
2105 | } else { | |
2106 | bytes = min_t(size_t, len, free->length); | |
2107 | boffs = free->offset; | |
2108 | } | |
8b0036ee | 2109 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2110 | oob += bytes; |
2111 | } | |
2112 | return oob; | |
2113 | } | |
2114 | default: | |
2115 | BUG(); | |
2116 | } | |
2117 | return NULL; | |
2118 | } | |
2119 | ||
29072b96 | 2120 | #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 |
1da177e4 LT |
2121 | |
2122 | /** | |
8593fbc6 | 2123 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
2124 | * @mtd: MTD device structure |
2125 | * @to: offset to write to | |
8593fbc6 | 2126 | * @ops: oob operations description structure |
1da177e4 LT |
2127 | * |
2128 | * NAND write with ECC | |
2129 | */ | |
8593fbc6 TG |
2130 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2131 | struct mtd_oob_ops *ops) | |
1da177e4 | 2132 | { |
29072b96 | 2133 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2134 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2135 | uint32_t writelen = ops->len; |
782ce79a ML |
2136 | |
2137 | uint32_t oobwritelen = ops->ooblen; | |
2138 | uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ? | |
2139 | mtd->oobavail : mtd->oobsize; | |
2140 | ||
8593fbc6 TG |
2141 | uint8_t *oob = ops->oobbuf; |
2142 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2143 | int ret, subpage; |
1da177e4 | 2144 | |
8593fbc6 | 2145 | ops->retlen = 0; |
29072b96 TG |
2146 | if (!writelen) |
2147 | return 0; | |
1da177e4 | 2148 | |
61b03bd7 | 2149 | /* reject writes, which are not page aligned */ |
8593fbc6 | 2150 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
20d8e248 | 2151 | printk(KERN_NOTICE "%s: Attempt to write not " |
2152 | "page aligned data\n", __func__); | |
1da177e4 LT |
2153 | return -EINVAL; |
2154 | } | |
2155 | ||
29072b96 TG |
2156 | column = to & (mtd->writesize - 1); |
2157 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2158 | ||
2159 | if (subpage && oob) | |
2160 | return -EINVAL; | |
1da177e4 | 2161 | |
6a930961 TG |
2162 | chipnr = (int)(to >> chip->chip_shift); |
2163 | chip->select_chip(mtd, chipnr); | |
2164 | ||
1da177e4 LT |
2165 | /* Check, if it is write protected */ |
2166 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2167 | return -EIO; |
1da177e4 | 2168 | |
f75e5097 TG |
2169 | realpage = (int)(to >> chip->page_shift); |
2170 | page = realpage & chip->pagemask; | |
2171 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2172 | ||
2173 | /* Invalidate the page cache, when we write to the cached page */ | |
2174 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2175 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2176 | chip->pagebuf = -1; |
61b03bd7 | 2177 | |
7dcdcbef DW |
2178 | /* If we're not given explicit OOB data, let it be 0xFF */ |
2179 | if (likely(!oob)) | |
2180 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
61b03bd7 | 2181 | |
782ce79a ML |
2182 | /* Don't allow multipage oob writes with offset */ |
2183 | if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) | |
2184 | return -EINVAL; | |
2185 | ||
f75e5097 | 2186 | while(1) { |
29072b96 | 2187 | int bytes = mtd->writesize; |
f75e5097 | 2188 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2189 | uint8_t *wbuf = buf; |
2190 | ||
2191 | /* Partial page write ? */ | |
2192 | if (unlikely(column || writelen < (mtd->writesize - 1))) { | |
2193 | cached = 0; | |
2194 | bytes = min_t(int, bytes - column, (int) writelen); | |
2195 | chip->pagebuf = -1; | |
2196 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2197 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2198 | wbuf = chip->buffers->databuf; | |
2199 | } | |
1da177e4 | 2200 | |
782ce79a ML |
2201 | if (unlikely(oob)) { |
2202 | size_t len = min(oobwritelen, oobmaxlen); | |
2203 | oob = nand_fill_oob(chip, oob, len, ops); | |
2204 | oobwritelen -= len; | |
2205 | } | |
8593fbc6 | 2206 | |
29072b96 | 2207 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
956e944c | 2208 | (ops->mode == MTD_OOB_RAW)); |
f75e5097 TG |
2209 | if (ret) |
2210 | break; | |
2211 | ||
2212 | writelen -= bytes; | |
2213 | if (!writelen) | |
2214 | break; | |
2215 | ||
29072b96 | 2216 | column = 0; |
f75e5097 TG |
2217 | buf += bytes; |
2218 | realpage++; | |
2219 | ||
2220 | page = realpage & chip->pagemask; | |
2221 | /* Check, if we cross a chip boundary */ | |
2222 | if (!page) { | |
2223 | chipnr++; | |
2224 | chip->select_chip(mtd, -1); | |
2225 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2226 | } |
2227 | } | |
8593fbc6 | 2228 | |
8593fbc6 | 2229 | ops->retlen = ops->len - writelen; |
7014568b VW |
2230 | if (unlikely(oob)) |
2231 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
2232 | return ret; |
2233 | } | |
2234 | ||
2af7c653 SK |
2235 | /** |
2236 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
2237 | * @mtd: MTD device structure | |
2238 | * @to: offset to write to | |
2239 | * @len: number of bytes to write | |
2240 | * @retlen: pointer to variable to store the number of written bytes | |
2241 | * @buf: the data to write | |
2242 | * | |
2243 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2244 | * may for example be called by mtdoops when writing an oops while in panic. | |
2245 | */ | |
2246 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2247 | size_t *retlen, const uint8_t *buf) | |
2248 | { | |
2249 | struct nand_chip *chip = mtd->priv; | |
2250 | int ret; | |
2251 | ||
2252 | /* Do not allow reads past end of device */ | |
2253 | if ((to + len) > mtd->size) | |
2254 | return -EINVAL; | |
2255 | if (!len) | |
2256 | return 0; | |
2257 | ||
2258 | /* Wait for the device to get ready. */ | |
2259 | panic_nand_wait(mtd, chip, 400); | |
2260 | ||
2261 | /* Grab the device. */ | |
2262 | panic_nand_get_device(chip, mtd, FL_WRITING); | |
2263 | ||
2264 | chip->ops.len = len; | |
2265 | chip->ops.datbuf = (uint8_t *)buf; | |
2266 | chip->ops.oobbuf = NULL; | |
2267 | ||
2268 | ret = nand_do_write_ops(mtd, to, &chip->ops); | |
2269 | ||
2270 | *retlen = chip->ops.retlen; | |
2271 | return ret; | |
2272 | } | |
2273 | ||
f75e5097 | 2274 | /** |
8593fbc6 | 2275 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 2276 | * @mtd: MTD device structure |
f75e5097 TG |
2277 | * @to: offset to write to |
2278 | * @len: number of bytes to write | |
8593fbc6 TG |
2279 | * @retlen: pointer to variable to store the number of written bytes |
2280 | * @buf: the data to write | |
f75e5097 | 2281 | * |
8593fbc6 | 2282 | * NAND write with ECC |
f75e5097 | 2283 | */ |
8593fbc6 TG |
2284 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2285 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2286 | { |
2287 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
2288 | int ret; |
2289 | ||
8593fbc6 TG |
2290 | /* Do not allow reads past end of device */ |
2291 | if ((to + len) > mtd->size) | |
f75e5097 | 2292 | return -EINVAL; |
8593fbc6 TG |
2293 | if (!len) |
2294 | return 0; | |
f75e5097 | 2295 | |
7bc3312b | 2296 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 2297 | |
8593fbc6 TG |
2298 | chip->ops.len = len; |
2299 | chip->ops.datbuf = (uint8_t *)buf; | |
2300 | chip->ops.oobbuf = NULL; | |
f75e5097 | 2301 | |
8593fbc6 | 2302 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 2303 | |
7fd5aecc RP |
2304 | *retlen = chip->ops.retlen; |
2305 | ||
f75e5097 | 2306 | nand_release_device(mtd); |
8593fbc6 | 2307 | |
8593fbc6 | 2308 | return ret; |
f75e5097 | 2309 | } |
7314e9e7 | 2310 | |
1da177e4 | 2311 | /** |
8593fbc6 | 2312 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
2313 | * @mtd: MTD device structure |
2314 | * @to: offset to write to | |
8593fbc6 | 2315 | * @ops: oob operation description structure |
1da177e4 LT |
2316 | * |
2317 | * NAND write out-of-band | |
2318 | */ | |
8593fbc6 TG |
2319 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2320 | struct mtd_oob_ops *ops) | |
1da177e4 | 2321 | { |
03736155 | 2322 | int chipnr, page, status, len; |
ace4dfee | 2323 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2324 | |
20d8e248 | 2325 | DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", |
2326 | __func__, (unsigned int)to, (int)ops->ooblen); | |
1da177e4 | 2327 | |
03736155 AH |
2328 | if (ops->mode == MTD_OOB_AUTO) |
2329 | len = chip->ecc.layout->oobavail; | |
2330 | else | |
2331 | len = mtd->oobsize; | |
2332 | ||
1da177e4 | 2333 | /* Do not allow write past end of page */ |
03736155 | 2334 | if ((ops->ooboffs + ops->ooblen) > len) { |
20d8e248 | 2335 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " |
2336 | "past end of page\n", __func__); | |
1da177e4 LT |
2337 | return -EINVAL; |
2338 | } | |
2339 | ||
03736155 | 2340 | if (unlikely(ops->ooboffs >= len)) { |
20d8e248 | 2341 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " |
2342 | "write outside oob\n", __func__); | |
03736155 AH |
2343 | return -EINVAL; |
2344 | } | |
2345 | ||
2346 | /* Do not allow reads past end of device */ | |
2347 | if (unlikely(to >= mtd->size || | |
2348 | ops->ooboffs + ops->ooblen > | |
2349 | ((mtd->size >> chip->page_shift) - | |
2350 | (to >> chip->page_shift)) * len)) { | |
20d8e248 | 2351 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2352 | "end of device\n", __func__); | |
03736155 AH |
2353 | return -EINVAL; |
2354 | } | |
2355 | ||
7314e9e7 | 2356 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2357 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2358 | |
7314e9e7 TG |
2359 | /* Shift to get page */ |
2360 | page = (int)(to >> chip->page_shift); | |
2361 | ||
2362 | /* | |
2363 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2364 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2365 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2366 | * it in the doc2000 driver in August 1999. dwmw2. | |
2367 | */ | |
ace4dfee | 2368 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2369 | |
2370 | /* Check, if it is write protected */ | |
2371 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2372 | return -EROFS; |
61b03bd7 | 2373 | |
1da177e4 | 2374 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2375 | if (page == chip->pagebuf) |
2376 | chip->pagebuf = -1; | |
1da177e4 | 2377 | |
7bc3312b | 2378 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
782ce79a | 2379 | nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); |
7bc3312b TG |
2380 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); |
2381 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 2382 | |
7bc3312b TG |
2383 | if (status) |
2384 | return status; | |
1da177e4 | 2385 | |
7014568b | 2386 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2387 | |
7bc3312b | 2388 | return 0; |
8593fbc6 TG |
2389 | } |
2390 | ||
2391 | /** | |
2392 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
2393 | * @mtd: MTD device structure | |
844d3b42 | 2394 | * @to: offset to write to |
8593fbc6 TG |
2395 | * @ops: oob operation description structure |
2396 | */ | |
2397 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2398 | struct mtd_oob_ops *ops) | |
2399 | { | |
8593fbc6 TG |
2400 | struct nand_chip *chip = mtd->priv; |
2401 | int ret = -ENOTSUPP; | |
2402 | ||
2403 | ops->retlen = 0; | |
2404 | ||
2405 | /* Do not allow writes past end of device */ | |
7014568b | 2406 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
20d8e248 | 2407 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2408 | "end of device\n", __func__); | |
8593fbc6 TG |
2409 | return -EINVAL; |
2410 | } | |
2411 | ||
7bc3312b | 2412 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 TG |
2413 | |
2414 | switch(ops->mode) { | |
2415 | case MTD_OOB_PLACE: | |
2416 | case MTD_OOB_AUTO: | |
8593fbc6 | 2417 | case MTD_OOB_RAW: |
8593fbc6 TG |
2418 | break; |
2419 | ||
2420 | default: | |
2421 | goto out; | |
2422 | } | |
2423 | ||
2424 | if (!ops->datbuf) | |
2425 | ret = nand_do_write_oob(mtd, to, ops); | |
2426 | else | |
2427 | ret = nand_do_write_ops(mtd, to, ops); | |
2428 | ||
e0c7d767 | 2429 | out: |
1da177e4 | 2430 | nand_release_device(mtd); |
1da177e4 LT |
2431 | return ret; |
2432 | } | |
2433 | ||
1da177e4 LT |
2434 | /** |
2435 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
2436 | * @mtd: MTD device structure | |
2437 | * @page: the page address of the block which will be erased | |
2438 | * | |
2439 | * Standard erase command for NAND chips | |
2440 | */ | |
e0c7d767 | 2441 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2442 | { |
ace4dfee | 2443 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2444 | /* Send commands to erase a block */ |
ace4dfee TG |
2445 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2446 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2447 | } |
2448 | ||
2449 | /** | |
2450 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
2451 | * @mtd: MTD device structure | |
2452 | * @page: the page address of the block which will be erased | |
2453 | * | |
2454 | * AND multi block erase command function | |
2455 | * Erase 4 consecutive blocks | |
2456 | */ | |
e0c7d767 | 2457 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2458 | { |
ace4dfee | 2459 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2460 | /* Send commands to erase a block */ |
ace4dfee TG |
2461 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2462 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2463 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2464 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2465 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2466 | } |
2467 | ||
2468 | /** | |
2469 | * nand_erase - [MTD Interface] erase block(s) | |
2470 | * @mtd: MTD device structure | |
2471 | * @instr: erase instruction | |
2472 | * | |
2473 | * Erase one ore more blocks | |
2474 | */ | |
e0c7d767 | 2475 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2476 | { |
e0c7d767 | 2477 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2478 | } |
61b03bd7 | 2479 | |
30f464b7 | 2480 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2481 | /** |
ace4dfee | 2482 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
2483 | * @mtd: MTD device structure |
2484 | * @instr: erase instruction | |
2485 | * @allowbbt: allow erasing the bbt area | |
2486 | * | |
2487 | * Erase one ore more blocks | |
2488 | */ | |
ace4dfee TG |
2489 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2490 | int allowbbt) | |
1da177e4 | 2491 | { |
69423d99 | 2492 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2493 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2494 | loff_t rewrite_bbt[NAND_MAX_CHIPS]={0}; |
ace4dfee | 2495 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2496 | loff_t len; |
1da177e4 | 2497 | |
20d8e248 | 2498 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", |
2499 | __func__, (unsigned long long)instr->addr, | |
2500 | (unsigned long long)instr->len); | |
1da177e4 | 2501 | |
6fe5a6ac | 2502 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2503 | return -EINVAL; |
1da177e4 | 2504 | |
bb0eb217 | 2505 | instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; |
1da177e4 LT |
2506 | |
2507 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2508 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2509 | |
2510 | /* Shift to get first page */ | |
ace4dfee TG |
2511 | page = (int)(instr->addr >> chip->page_shift); |
2512 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2513 | |
2514 | /* Calculate pages in each block */ | |
ace4dfee | 2515 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2516 | |
2517 | /* Select the NAND device */ | |
ace4dfee | 2518 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2519 | |
1da177e4 LT |
2520 | /* Check, if it is write protected */ |
2521 | if (nand_check_wp(mtd)) { | |
20d8e248 | 2522 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", |
2523 | __func__); | |
1da177e4 LT |
2524 | instr->state = MTD_ERASE_FAILED; |
2525 | goto erase_exit; | |
2526 | } | |
2527 | ||
ace4dfee TG |
2528 | /* |
2529 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2530 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2531 | * can not be matched. This is also done when the bbt is actually | |
2532 | * erased to avoid recusrsive updates | |
2533 | */ | |
2534 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2535 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2536 | |
1da177e4 LT |
2537 | /* Loop through the pages */ |
2538 | len = instr->len; | |
2539 | ||
2540 | instr->state = MTD_ERASING; | |
2541 | ||
2542 | while (len) { | |
ace4dfee TG |
2543 | /* |
2544 | * heck if we have a bad block, we do not erase bad blocks ! | |
2545 | */ | |
2546 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
2547 | chip->page_shift, 0, allowbbt)) { | |
20d8e248 | 2548 | printk(KERN_WARNING "%s: attempt to erase a bad block " |
2549 | "at page 0x%08x\n", __func__, page); | |
1da177e4 LT |
2550 | instr->state = MTD_ERASE_FAILED; |
2551 | goto erase_exit; | |
2552 | } | |
61b03bd7 | 2553 | |
ace4dfee TG |
2554 | /* |
2555 | * Invalidate the page cache, if we erase the block which | |
2556 | * contains the current cached page | |
2557 | */ | |
2558 | if (page <= chip->pagebuf && chip->pagebuf < | |
2559 | (page + pages_per_block)) | |
2560 | chip->pagebuf = -1; | |
1da177e4 | 2561 | |
ace4dfee | 2562 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2563 | |
7bc3312b | 2564 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2565 | |
ace4dfee TG |
2566 | /* |
2567 | * See if operation failed and additional status checks are | |
2568 | * available | |
2569 | */ | |
2570 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2571 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2572 | status, page); | |
068e3c0a | 2573 | |
1da177e4 | 2574 | /* See if block erase succeeded */ |
a4ab4c5d | 2575 | if (status & NAND_STATUS_FAIL) { |
20d8e248 | 2576 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " |
2577 | "page 0x%08x\n", __func__, page); | |
1da177e4 | 2578 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2579 | instr->fail_addr = |
2580 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2581 | goto erase_exit; |
2582 | } | |
30f464b7 | 2583 | |
ace4dfee TG |
2584 | /* |
2585 | * If BBT requires refresh, set the BBT rewrite flag to the | |
2586 | * page being erased | |
2587 | */ | |
2588 | if (bbt_masked_page != 0xffffffff && | |
2589 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2590 | rewrite_bbt[chipnr] = |
2591 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2592 | |
1da177e4 | 2593 | /* Increment page address and decrement length */ |
ace4dfee | 2594 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2595 | page += pages_per_block; |
2596 | ||
2597 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2598 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2599 | chipnr++; |
ace4dfee TG |
2600 | chip->select_chip(mtd, -1); |
2601 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2602 | |
ace4dfee TG |
2603 | /* |
2604 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
2605 | * page mask to see if this BBT should be rewritten | |
2606 | */ | |
2607 | if (bbt_masked_page != 0xffffffff && | |
2608 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2609 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2610 | BBT_PAGE_MASK; | |
1da177e4 LT |
2611 | } |
2612 | } | |
2613 | instr->state = MTD_ERASE_DONE; | |
2614 | ||
e0c7d767 | 2615 | erase_exit: |
1da177e4 LT |
2616 | |
2617 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2618 | |
2619 | /* Deselect and wake up anyone waiting on the device */ | |
2620 | nand_release_device(mtd); | |
2621 | ||
49defc01 DW |
2622 | /* Do call back function */ |
2623 | if (!ret) | |
2624 | mtd_erase_callback(instr); | |
2625 | ||
ace4dfee TG |
2626 | /* |
2627 | * If BBT requires refresh and erase was successful, rewrite any | |
2628 | * selected bad block tables | |
2629 | */ | |
2630 | if (bbt_masked_page == 0xffffffff || ret) | |
2631 | return ret; | |
2632 | ||
2633 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2634 | if (!rewrite_bbt[chipnr]) | |
2635 | continue; | |
2636 | /* update the BBT for chip */ | |
20d8e248 | 2637 | DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " |
2638 | "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, | |
2639 | rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2640 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2641 | } |
2642 | ||
1da177e4 LT |
2643 | /* Return more or less happy */ |
2644 | return ret; | |
2645 | } | |
2646 | ||
2647 | /** | |
2648 | * nand_sync - [MTD Interface] sync | |
2649 | * @mtd: MTD device structure | |
2650 | * | |
2651 | * Sync is actually a wait for chip ready function | |
2652 | */ | |
e0c7d767 | 2653 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2654 | { |
ace4dfee | 2655 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2656 | |
20d8e248 | 2657 | DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); |
1da177e4 LT |
2658 | |
2659 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2660 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2661 | /* Release it and go back */ |
e0c7d767 | 2662 | nand_release_device(mtd); |
1da177e4 LT |
2663 | } |
2664 | ||
1da177e4 | 2665 | /** |
ace4dfee | 2666 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 | 2667 | * @mtd: MTD device structure |
844d3b42 | 2668 | * @offs: offset relative to mtd start |
1da177e4 | 2669 | */ |
ace4dfee | 2670 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2671 | { |
2672 | /* Check for invalid offset */ | |
ace4dfee | 2673 | if (offs > mtd->size) |
1da177e4 | 2674 | return -EINVAL; |
61b03bd7 | 2675 | |
ace4dfee | 2676 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2677 | } |
2678 | ||
2679 | /** | |
ace4dfee | 2680 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
2681 | * @mtd: MTD device structure |
2682 | * @ofs: offset relative to mtd start | |
2683 | */ | |
e0c7d767 | 2684 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2685 | { |
ace4dfee | 2686 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2687 | int ret; |
2688 | ||
e0c7d767 DW |
2689 | if ((ret = nand_block_isbad(mtd, ofs))) { |
2690 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
2691 | if (ret > 0) |
2692 | return 0; | |
e0c7d767 DW |
2693 | return ret; |
2694 | } | |
1da177e4 | 2695 | |
ace4dfee | 2696 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2697 | } |
2698 | ||
962034f4 VW |
2699 | /** |
2700 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
2701 | * @mtd: MTD device structure | |
2702 | */ | |
2703 | static int nand_suspend(struct mtd_info *mtd) | |
2704 | { | |
ace4dfee | 2705 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2706 | |
ace4dfee | 2707 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2708 | } |
2709 | ||
2710 | /** | |
2711 | * nand_resume - [MTD Interface] Resume the NAND flash | |
2712 | * @mtd: MTD device structure | |
2713 | */ | |
2714 | static void nand_resume(struct mtd_info *mtd) | |
2715 | { | |
ace4dfee | 2716 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2717 | |
ace4dfee | 2718 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2719 | nand_release_device(mtd); |
2720 | else | |
20d8e248 | 2721 | printk(KERN_ERR "%s called for a chip which is not " |
2722 | "in suspended state\n", __func__); | |
962034f4 VW |
2723 | } |
2724 | ||
7aa65bfd TG |
2725 | /* |
2726 | * Set default functions | |
2727 | */ | |
ace4dfee | 2728 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2729 | { |
1da177e4 | 2730 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2731 | if (!chip->chip_delay) |
2732 | chip->chip_delay = 20; | |
1da177e4 LT |
2733 | |
2734 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2735 | if (chip->cmdfunc == NULL) |
2736 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2737 | |
2738 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2739 | if (chip->waitfunc == NULL) |
2740 | chip->waitfunc = nand_wait; | |
2741 | ||
2742 | if (!chip->select_chip) | |
2743 | chip->select_chip = nand_select_chip; | |
2744 | if (!chip->read_byte) | |
2745 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2746 | if (!chip->read_word) | |
2747 | chip->read_word = nand_read_word; | |
2748 | if (!chip->block_bad) | |
2749 | chip->block_bad = nand_block_bad; | |
2750 | if (!chip->block_markbad) | |
2751 | chip->block_markbad = nand_default_block_markbad; | |
2752 | if (!chip->write_buf) | |
2753 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2754 | if (!chip->read_buf) | |
2755 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2756 | if (!chip->verify_buf) | |
2757 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2758 | if (!chip->scan_bbt) | |
2759 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2760 | |
2761 | if (!chip->controller) { | |
2762 | chip->controller = &chip->hwcontrol; | |
2763 | spin_lock_init(&chip->controller->lock); | |
2764 | init_waitqueue_head(&chip->controller->wq); | |
2765 | } | |
2766 | ||
7aa65bfd TG |
2767 | } |
2768 | ||
2769 | /* | |
ace4dfee | 2770 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2771 | */ |
2772 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2773 | struct nand_chip *chip, |
5e81e88a DW |
2774 | int busw, int *maf_id, |
2775 | struct nand_flash_dev *type) | |
7aa65bfd | 2776 | { |
426c457a KC |
2777 | int i, dev_id, maf_idx; |
2778 | u8 id_data[8]; | |
1da177e4 LT |
2779 | |
2780 | /* Select the device */ | |
ace4dfee | 2781 | chip->select_chip(mtd, 0); |
1da177e4 | 2782 | |
ef89a880 KB |
2783 | /* |
2784 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
2785 | * after power-up | |
2786 | */ | |
2787 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
2788 | ||
1da177e4 | 2789 | /* Send the command for reading device ID */ |
ace4dfee | 2790 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2791 | |
2792 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
2793 | *maf_id = chip->read_byte(mtd); |
2794 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 2795 | |
ed8165c7 BD |
2796 | /* Try again to make sure, as some systems the bus-hold or other |
2797 | * interface concerns can cause random data which looks like a | |
2798 | * possibly credible NAND flash to appear. If the two results do | |
2799 | * not match, ignore the device completely. | |
2800 | */ | |
2801 | ||
2802 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2803 | ||
426c457a | 2804 | /* Read entire ID string */ |
ed8165c7 | 2805 | |
426c457a KC |
2806 | for (i = 0; i < 8; i++) |
2807 | id_data[i] = chip->read_byte(mtd); | |
ed8165c7 | 2808 | |
426c457a | 2809 | if (id_data[0] != *maf_id || id_data[1] != dev_id) { |
ed8165c7 BD |
2810 | printk(KERN_INFO "%s: second ID read did not match " |
2811 | "%02x,%02x against %02x,%02x\n", __func__, | |
426c457a | 2812 | *maf_id, dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
2813 | return ERR_PTR(-ENODEV); |
2814 | } | |
2815 | ||
7aa65bfd | 2816 | if (!type) |
5e81e88a DW |
2817 | type = nand_flash_ids; |
2818 | ||
2819 | for (; type->name != NULL; type++) | |
2820 | if (dev_id == type->id) | |
2821 | break; | |
2822 | ||
2823 | if (!type->name) | |
7aa65bfd TG |
2824 | return ERR_PTR(-ENODEV); |
2825 | ||
ba0251fe TG |
2826 | if (!mtd->name) |
2827 | mtd->name = type->name; | |
2828 | ||
69423d99 | 2829 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd TG |
2830 | |
2831 | /* Newer devices have all the information in additional id bytes */ | |
ba0251fe | 2832 | if (!type->pagesize) { |
7aa65bfd | 2833 | int extid; |
29072b96 | 2834 | /* The 3rd id byte holds MLC / multichip data */ |
426c457a | 2835 | chip->cellinfo = id_data[2]; |
7aa65bfd | 2836 | /* The 4th id byte is the important one */ |
426c457a | 2837 | extid = id_data[3]; |
61b03bd7 | 2838 | |
426c457a KC |
2839 | /* |
2840 | * Field definitions are in the following datasheets: | |
2841 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
2842 | * New style (6 byte ID): Samsung K9GAG08U0D (p.40) | |
2843 | * | |
2844 | * Check for wraparound + Samsung ID + nonzero 6th byte | |
2845 | * to decide what to do. | |
2846 | */ | |
2847 | if (id_data[0] == id_data[6] && id_data[1] == id_data[7] && | |
2848 | id_data[0] == NAND_MFR_SAMSUNG && | |
2849 | id_data[5] != 0x00) { | |
2850 | /* Calc pagesize */ | |
2851 | mtd->writesize = 2048 << (extid & 0x03); | |
2852 | extid >>= 2; | |
2853 | /* Calc oobsize */ | |
2854 | mtd->oobsize = (extid & 0x03) == 0x01 ? 128 : 218; | |
2855 | extid >>= 2; | |
2856 | /* Calc blocksize */ | |
2857 | mtd->erasesize = (128 * 1024) << | |
2858 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
2859 | busw = 0; | |
2860 | } else { | |
2861 | /* Calc pagesize */ | |
2862 | mtd->writesize = 1024 << (extid & 0x03); | |
2863 | extid >>= 2; | |
2864 | /* Calc oobsize */ | |
2865 | mtd->oobsize = (8 << (extid & 0x01)) * | |
2866 | (mtd->writesize >> 9); | |
2867 | extid >>= 2; | |
2868 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
2869 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
2870 | extid >>= 2; | |
2871 | /* Get buswidth information */ | |
2872 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
2873 | } | |
7aa65bfd TG |
2874 | } else { |
2875 | /* | |
ace4dfee | 2876 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 2877 | */ |
ba0251fe TG |
2878 | mtd->erasesize = type->erasesize; |
2879 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 2880 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 2881 | busw = type->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2882 | } |
1da177e4 | 2883 | |
7aa65bfd | 2884 | /* Try to identify manufacturer */ |
9a909867 | 2885 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
2886 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
2887 | break; | |
2888 | } | |
0ea4a755 | 2889 | |
7aa65bfd TG |
2890 | /* |
2891 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 2892 | * chip correct ! |
7aa65bfd | 2893 | */ |
ace4dfee | 2894 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2895 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2896 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2897 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2898 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2899 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2900 | busw ? 16 : 8); |
2901 | return ERR_PTR(-EINVAL); | |
2902 | } | |
61b03bd7 | 2903 | |
7aa65bfd | 2904 | /* Calculate the address shift from the page size */ |
ace4dfee | 2905 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2906 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2907 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2908 | |
ace4dfee | 2909 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2910 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
2911 | if (chip->chipsize & 0xffffffff) |
2912 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
2913 | else | |
2914 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1; | |
1da177e4 | 2915 | |
7aa65bfd | 2916 | /* Set the bad block position */ |
ace4dfee | 2917 | chip->badblockpos = mtd->writesize > 512 ? |
7aa65bfd | 2918 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
e0b58d0a | 2919 | chip->badblockbits = 8; |
61b03bd7 | 2920 | |
7aa65bfd | 2921 | /* Get chip options, preserve non chip based options */ |
ace4dfee | 2922 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
ba0251fe | 2923 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
7aa65bfd TG |
2924 | |
2925 | /* | |
ace4dfee | 2926 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2927 | */ |
ace4dfee | 2928 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2929 | |
ace4dfee | 2930 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2931 | * options for chips which are not having an extended id. |
2932 | */ | |
ba0251fe | 2933 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
ace4dfee | 2934 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd TG |
2935 | |
2936 | /* Check for AND chips with 4 page planes */ | |
ace4dfee TG |
2937 | if (chip->options & NAND_4PAGE_ARRAY) |
2938 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2939 | else |
ace4dfee | 2940 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2941 | |
2942 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2943 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2944 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2945 | |
2946 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2947 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2948 | nand_manuf_ids[maf_idx].name, type->name); | |
2949 | ||
2950 | return type; | |
2951 | } | |
2952 | ||
7aa65bfd | 2953 | /** |
3b85c321 DW |
2954 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
2955 | * @mtd: MTD device structure | |
2956 | * @maxchips: Number of chips to scan for | |
5e81e88a | 2957 | * @table: Alternative NAND ID table |
7aa65bfd | 2958 | * |
3b85c321 DW |
2959 | * This is the first phase of the normal nand_scan() function. It |
2960 | * reads the flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 2961 | * |
3b85c321 | 2962 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 2963 | */ |
5e81e88a DW |
2964 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
2965 | struct nand_flash_dev *table) | |
7aa65bfd TG |
2966 | { |
2967 | int i, busw, nand_maf_id; | |
ace4dfee | 2968 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
2969 | struct nand_flash_dev *type; |
2970 | ||
7aa65bfd | 2971 | /* Get buswidth to select the correct functions */ |
ace4dfee | 2972 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2973 | /* Set the default functions */ |
ace4dfee | 2974 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
2975 | |
2976 | /* Read the flash type */ | |
5e81e88a | 2977 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table); |
7aa65bfd TG |
2978 | |
2979 | if (IS_ERR(type)) { | |
b1c6e6db BD |
2980 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
2981 | printk(KERN_WARNING "No NAND device found.\n"); | |
ace4dfee | 2982 | chip->select_chip(mtd, -1); |
7aa65bfd | 2983 | return PTR_ERR(type); |
1da177e4 LT |
2984 | } |
2985 | ||
7aa65bfd | 2986 | /* Check for a chip array */ |
e0c7d767 | 2987 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 2988 | chip->select_chip(mtd, i); |
ef89a880 KB |
2989 | /* See comment in nand_get_flash_type for reset */ |
2990 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 2991 | /* Send the command for reading device ID */ |
ace4dfee | 2992 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 2993 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
2994 | if (nand_maf_id != chip->read_byte(mtd) || |
2995 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
2996 | break; |
2997 | } | |
2998 | if (i > 1) | |
2999 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 3000 | |
1da177e4 | 3001 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3002 | chip->numchips = i; |
3003 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3004 | |
3b85c321 DW |
3005 | return 0; |
3006 | } | |
3007 | ||
3008 | ||
3009 | /** | |
3010 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
3011 | * @mtd: MTD device structure | |
3b85c321 DW |
3012 | * |
3013 | * This is the second phase of the normal nand_scan() function. It | |
3014 | * fills out all the uninitialized function pointers with the defaults | |
3015 | * and scans for a bad block table if appropriate. | |
3016 | */ | |
3017 | int nand_scan_tail(struct mtd_info *mtd) | |
3018 | { | |
3019 | int i; | |
3020 | struct nand_chip *chip = mtd->priv; | |
3021 | ||
4bf63fcb DW |
3022 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3023 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3024 | if (!chip->buffers) | |
3025 | return -ENOMEM; | |
3026 | ||
7dcdcbef | 3027 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3028 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3029 | |
7aa65bfd TG |
3030 | /* |
3031 | * If no default placement scheme is given, select an appropriate one | |
3032 | */ | |
5bd34c09 | 3033 | if (!chip->ecc.layout) { |
61b03bd7 | 3034 | switch (mtd->oobsize) { |
1da177e4 | 3035 | case 8: |
5bd34c09 | 3036 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3037 | break; |
3038 | case 16: | |
5bd34c09 | 3039 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3040 | break; |
3041 | case 64: | |
5bd34c09 | 3042 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3043 | break; |
81ec5364 TG |
3044 | case 128: |
3045 | chip->ecc.layout = &nand_oob_128; | |
3046 | break; | |
1da177e4 | 3047 | default: |
7aa65bfd TG |
3048 | printk(KERN_WARNING "No oob scheme defined for " |
3049 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
3050 | BUG(); |
3051 | } | |
3052 | } | |
61b03bd7 | 3053 | |
956e944c DW |
3054 | if (!chip->write_page) |
3055 | chip->write_page = nand_write_page; | |
3056 | ||
61b03bd7 | 3057 | /* |
7aa65bfd TG |
3058 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
3059 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 3060 | */ |
956e944c | 3061 | |
ace4dfee | 3062 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3063 | case NAND_ECC_HW_OOB_FIRST: |
3064 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3065 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3066 | !chip->ecc.hwctl) { | |
3067 | printk(KERN_WARNING "No ECC functions supplied; " | |
3068 | "Hardware ECC not possible\n"); | |
3069 | BUG(); | |
3070 | } | |
3071 | if (!chip->ecc.read_page) | |
3072 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3073 | ||
6dfc6d25 | 3074 | case NAND_ECC_HW: |
f5bbdacc TG |
3075 | /* Use standard hwecc read page function ? */ |
3076 | if (!chip->ecc.read_page) | |
3077 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3078 | if (!chip->ecc.write_page) |
3079 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3080 | if (!chip->ecc.read_page_raw) |
3081 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3082 | if (!chip->ecc.write_page_raw) | |
3083 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3084 | if (!chip->ecc.read_oob) |
3085 | chip->ecc.read_oob = nand_read_oob_std; | |
3086 | if (!chip->ecc.write_oob) | |
3087 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3088 | |
6dfc6d25 | 3089 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3090 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3091 | !chip->ecc.hwctl) && | |
3092 | (!chip->ecc.read_page || | |
1c45f604 | 3093 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3094 | !chip->ecc.write_page || |
1c45f604 | 3095 | chip->ecc.write_page == nand_write_page_hwecc)) { |
6e0cb135 | 3096 | printk(KERN_WARNING "No ECC functions supplied; " |
6dfc6d25 TG |
3097 | "Hardware ECC not possible\n"); |
3098 | BUG(); | |
3099 | } | |
f75e5097 | 3100 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
3101 | if (!chip->ecc.read_page) |
3102 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3103 | if (!chip->ecc.write_page) |
3104 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3105 | if (!chip->ecc.read_page_raw) |
3106 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3107 | if (!chip->ecc.write_page_raw) | |
3108 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3109 | if (!chip->ecc.read_oob) |
3110 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3111 | if (!chip->ecc.write_oob) | |
3112 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3113 | |
ace4dfee | 3114 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
3115 | break; |
3116 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
3117 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
3118 | chip->ecc.size, mtd->writesize); |
3119 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 3120 | |
6dfc6d25 | 3121 | case NAND_ECC_SOFT: |
ace4dfee TG |
3122 | chip->ecc.calculate = nand_calculate_ecc; |
3123 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3124 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3125 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3126 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3127 | chip->ecc.read_page_raw = nand_read_page_raw; |
3128 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3129 | chip->ecc.read_oob = nand_read_oob_std; |
3130 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3131 | if (!chip->ecc.size) |
3132 | chip->ecc.size = 256; | |
ace4dfee | 3133 | chip->ecc.bytes = 3; |
1da177e4 | 3134 | break; |
61b03bd7 TG |
3135 | |
3136 | case NAND_ECC_NONE: | |
7aa65bfd TG |
3137 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
3138 | "This is not recommended !!\n"); | |
8593fbc6 TG |
3139 | chip->ecc.read_page = nand_read_page_raw; |
3140 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3141 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3142 | chip->ecc.read_page_raw = nand_read_page_raw; |
3143 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3144 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3145 | chip->ecc.size = mtd->writesize; |
3146 | chip->ecc.bytes = 0; | |
1da177e4 | 3147 | break; |
956e944c | 3148 | |
1da177e4 | 3149 | default: |
7aa65bfd | 3150 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 3151 | chip->ecc.mode); |
61b03bd7 | 3152 | BUG(); |
1da177e4 | 3153 | } |
61b03bd7 | 3154 | |
5bd34c09 TG |
3155 | /* |
3156 | * The number of bytes available for a client to place data into | |
3157 | * the out of band area | |
3158 | */ | |
3159 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3160 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3161 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3162 | chip->ecc.layout->oobavail += |
3163 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3164 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3165 | |
7aa65bfd TG |
3166 | /* |
3167 | * Set the number of read / write steps for one page depending on ECC | |
3168 | * mode | |
3169 | */ | |
ace4dfee TG |
3170 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
3171 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
3172 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
3173 | BUG(); | |
1da177e4 | 3174 | } |
f5bbdacc | 3175 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3176 | |
29072b96 TG |
3177 | /* |
3178 | * Allow subpage writes up to ecc.steps. Not possible for MLC | |
3179 | * FLASH. | |
3180 | */ | |
3181 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
3182 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
3183 | switch(chip->ecc.steps) { | |
3184 | case 2: | |
3185 | mtd->subpage_sft = 1; | |
3186 | break; | |
3187 | case 4: | |
3188 | case 8: | |
81ec5364 | 3189 | case 16: |
29072b96 TG |
3190 | mtd->subpage_sft = 2; |
3191 | break; | |
3192 | } | |
3193 | } | |
3194 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3195 | ||
04bbd0ea | 3196 | /* Initialize state */ |
ace4dfee | 3197 | chip->state = FL_READY; |
1da177e4 LT |
3198 | |
3199 | /* De-select the device */ | |
ace4dfee | 3200 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3201 | |
3202 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 3203 | chip->pagebuf = -1; |
1da177e4 LT |
3204 | |
3205 | /* Fill in remaining MTD driver data */ | |
3206 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3207 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3208 | MTD_CAP_NANDFLASH; | |
1da177e4 LT |
3209 | mtd->erase = nand_erase; |
3210 | mtd->point = NULL; | |
3211 | mtd->unpoint = NULL; | |
3212 | mtd->read = nand_read; | |
3213 | mtd->write = nand_write; | |
2af7c653 | 3214 | mtd->panic_write = panic_nand_write; |
1da177e4 LT |
3215 | mtd->read_oob = nand_read_oob; |
3216 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
3217 | mtd->sync = nand_sync; |
3218 | mtd->lock = NULL; | |
3219 | mtd->unlock = NULL; | |
962034f4 VW |
3220 | mtd->suspend = nand_suspend; |
3221 | mtd->resume = nand_resume; | |
1da177e4 LT |
3222 | mtd->block_isbad = nand_block_isbad; |
3223 | mtd->block_markbad = nand_block_markbad; | |
3224 | ||
5bd34c09 TG |
3225 | /* propagate ecc.layout to mtd_info */ |
3226 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 3227 | |
0040bf38 | 3228 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3229 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3230 | return 0; |
1da177e4 LT |
3231 | |
3232 | /* Build bad block table */ | |
ace4dfee | 3233 | return chip->scan_bbt(mtd); |
1da177e4 LT |
3234 | } |
3235 | ||
a6e6abd5 | 3236 | /* is_module_text_address() isn't exported, and it's mostly a pointless |
3b85c321 DW |
3237 | test if this is a module _anyway_ -- they'd have to try _really_ hard |
3238 | to call us from in-kernel code if the core NAND support is modular. */ | |
3239 | #ifdef MODULE | |
3240 | #define caller_is_module() (1) | |
3241 | #else | |
3242 | #define caller_is_module() \ | |
a6e6abd5 | 3243 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3244 | #endif |
3245 | ||
3246 | /** | |
3247 | * nand_scan - [NAND Interface] Scan for the NAND device | |
3248 | * @mtd: MTD device structure | |
3249 | * @maxchips: Number of chips to scan for | |
3250 | * | |
3251 | * This fills out all the uninitialized function pointers | |
3252 | * with the defaults. | |
3253 | * The flash ID is read and the mtd/chip structures are | |
3254 | * filled with the appropriate values. | |
3255 | * The mtd->owner field must be set to the module of the caller | |
3256 | * | |
3257 | */ | |
3258 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3259 | { | |
3260 | int ret; | |
3261 | ||
3262 | /* Many callers got this wrong, so check for it for a while... */ | |
3263 | if (!mtd->owner && caller_is_module()) { | |
20d8e248 | 3264 | printk(KERN_CRIT "%s called with NULL mtd->owner!\n", |
3265 | __func__); | |
3b85c321 DW |
3266 | BUG(); |
3267 | } | |
3268 | ||
5e81e88a | 3269 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3270 | if (!ret) |
3271 | ret = nand_scan_tail(mtd); | |
3272 | return ret; | |
3273 | } | |
3274 | ||
1da177e4 | 3275 | /** |
61b03bd7 | 3276 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
3277 | * @mtd: MTD device structure |
3278 | */ | |
e0c7d767 | 3279 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3280 | { |
ace4dfee | 3281 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
3282 | |
3283 | #ifdef CONFIG_MTD_PARTITIONS | |
3284 | /* Deregister partitions */ | |
e0c7d767 | 3285 | del_mtd_partitions(mtd); |
1da177e4 LT |
3286 | #endif |
3287 | /* Deregister the device */ | |
e0c7d767 | 3288 | del_mtd_device(mtd); |
1da177e4 | 3289 | |
fa671646 | 3290 | /* Free bad block table memory */ |
ace4dfee | 3291 | kfree(chip->bbt); |
4bf63fcb DW |
3292 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3293 | kfree(chip->buffers); | |
1da177e4 LT |
3294 | } |
3295 | ||
7d70f334 VS |
3296 | EXPORT_SYMBOL_GPL(nand_lock); |
3297 | EXPORT_SYMBOL_GPL(nand_unlock); | |
e0c7d767 | 3298 | EXPORT_SYMBOL_GPL(nand_scan); |
3b85c321 DW |
3299 | EXPORT_SYMBOL_GPL(nand_scan_ident); |
3300 | EXPORT_SYMBOL_GPL(nand_scan_tail); | |
e0c7d767 | 3301 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3302 | |
3303 | static int __init nand_base_init(void) | |
3304 | { | |
3305 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3306 | return 0; | |
3307 | } | |
3308 | ||
3309 | static void __exit nand_base_exit(void) | |
3310 | { | |
3311 | led_trigger_unregister_simple(nand_led_trigger); | |
3312 | } | |
3313 | ||
3314 | module_init(nand_base_init); | |
3315 | module_exit(nand_base_exit); | |
3316 | ||
e0c7d767 DW |
3317 | MODULE_LICENSE("GPL"); |
3318 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
3319 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |