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Fix common misspellings
[linux-block.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4
LT		 50
51#ifdef CONFIG_MTD_PARTITIONS
52#include <linux/mtd/partitions.h>
53#endif
54
55/* Define default oob placement schemes for large and small page devices */
5bd34c09 56static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
5bd34c09
TG		 59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
f8ac0414 63 .length = 2} }
1da177e4
LT		 64};
65
5bd34c09 66static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 69 .oobfree = {
70 {.offset = 8,
f8ac0414 71 . length = 8} }
1da177e4
LT		 72};
73
5bd34c09 74static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 75 .eccbytes = 24,
76 .eccpos = {
e0c7d767
DW		 77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 80 .oobfree = {
81 {.offset = 2,
f8ac0414 82 .length = 38} }
1da177e4
LT		 83};
84
81ec5364
TG		 85static struct nand_ecclayout nand_oob_128 = {
86 .eccbytes = 48,
87 .eccpos = {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
94 .oobfree = {
95 {.offset = 2,
f8ac0414 96 .length = 78} }
81ec5364
TG		 97};
98
ace4dfee 99static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 100 int new_state);
1da177e4 101
8593fbc6
TG		 102static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103 struct mtd_oob_ops *ops);
104
d470a97c 105/*
8e87d782 106 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 107 * compiled away when LED support is disabled.
108 */
109DEFINE_LED_TRIGGER(nand_led_trigger);
110
6fe5a6ac
VS		 111static int check_offs_len(struct mtd_info *mtd,
112 loff_t ofs, uint64_t len)
113{
114 struct nand_chip *chip = mtd->priv;
115 int ret = 0;
116
117 /* Start address must align on block boundary */
118 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
119 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
120 ret = -EINVAL;
121 }
122
123 /* Length must align on block boundary */
124 if (len & ((1 << chip->phys_erase_shift) - 1)) {
125 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
126 __func__);
127 ret = -EINVAL;
128 }
129
130 /* Do not allow past end of device */
131 if (ofs + len > mtd->size) {
132 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
133 __func__);
134 ret = -EINVAL;
135 }
136
137 return ret;
138}
139
1da177e4
LT		 140/**
141 * nand_release_device - [GENERIC] release chip
142 * @mtd: MTD device structure
61b03bd7
TG		 143 *
144 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 145 */
e0c7d767 146static void nand_release_device(struct mtd_info *mtd)
1da177e4 147{
ace4dfee 148 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 149
150 /* De-select the NAND device */
ace4dfee 151 chip->select_chip(mtd, -1);
0dfc6246 152
a36ed299 153 /* Release the controller and the chip */
ace4dfee
TG		 154 spin_lock(&chip->controller->lock);
155 chip->controller->active = NULL;
156 chip->state = FL_READY;
157 wake_up(&chip->controller->wq);
158 spin_unlock(&chip->controller->lock);
1da177e4
LT		 159}
160
161/**
162 * nand_read_byte - [DEFAULT] read one byte from the chip
163 * @mtd: MTD device structure
164 *
165 * Default read function for 8bit buswith
166 */
58dd8f2b 167static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 168{
ace4dfee
TG		 169 struct nand_chip *chip = mtd->priv;
170 return readb(chip->IO_ADDR_R);
1da177e4
LT		 171}
172
1da177e4
LT		 173/**
174 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
175 * @mtd: MTD device structure
176 *
61b03bd7 177 * Default read function for 16bit buswith with
1da177e4
LT		 178 * endianess conversion
179 */
58dd8f2b 180static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 181{
ace4dfee
TG		 182 struct nand_chip *chip = mtd->priv;
183 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 184}
185
1da177e4
LT		 186/**
187 * nand_read_word - [DEFAULT] read one word from the chip
188 * @mtd: MTD device structure
189 *
61b03bd7 190 * Default read function for 16bit buswith without
1da177e4
LT		 191 * endianess conversion
192 */
193static u16 nand_read_word(struct mtd_info *mtd)
194{
ace4dfee
TG		 195 struct nand_chip *chip = mtd->priv;
196 return readw(chip->IO_ADDR_R);
1da177e4
LT		 197}
198
1da177e4
LT		 199/**
200 * nand_select_chip - [DEFAULT] control CE line
201 * @mtd: MTD device structure
844d3b42 202 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 203 *
204 * Default select function for 1 chip devices.
205 */
ace4dfee 206static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 207{
ace4dfee
TG		 208 struct nand_chip *chip = mtd->priv;
209
210 switch (chipnr) {
1da177e4 211 case -1:
ace4dfee 212 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 213 break;
214 case 0:
1da177e4
LT		 215 break;
216
217 default:
218 BUG();
219 }
220}
221
222/**
223 * nand_write_buf - [DEFAULT] write buffer to chip
224 * @mtd: MTD device structure
225 * @buf: data buffer
226 * @len: number of bytes to write
227 *
228 * Default write function for 8bit buswith
229 */
58dd8f2b 230static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 231{
232 int i;
ace4dfee 233 struct nand_chip *chip = mtd->priv;
1da177e4 234
e0c7d767 235 for (i = 0; i < len; i++)
ace4dfee 236 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 237}
238
239/**
61b03bd7 240 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 241 * @mtd: MTD device structure
242 * @buf: buffer to store date
243 * @len: number of bytes to read
244 *
245 * Default read function for 8bit buswith
246 */
58dd8f2b 247static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 248{
249 int i;
ace4dfee 250 struct nand_chip *chip = mtd->priv;
1da177e4 251
e0c7d767 252 for (i = 0; i < len; i++)
ace4dfee 253 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 254}
255
256/**
61b03bd7 257 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 258 * @mtd: MTD device structure
259 * @buf: buffer containing the data to compare
260 * @len: number of bytes to compare
261 *
262 * Default verify function for 8bit buswith
263 */
58dd8f2b 264static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 265{
266 int i;
ace4dfee 267 struct nand_chip *chip = mtd->priv;
1da177e4 268
e0c7d767 269 for (i = 0; i < len; i++)
ace4dfee 270 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 271 return -EFAULT;
1da177e4
LT		 272 return 0;
273}
274
275/**
276 * nand_write_buf16 - [DEFAULT] write buffer to chip
277 * @mtd: MTD device structure
278 * @buf: data buffer
279 * @len: number of bytes to write
280 *
281 * Default write function for 16bit buswith
282 */
58dd8f2b 283static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 284{
285 int i;
ace4dfee 286 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 287 u16 *p = (u16 *) buf;
288 len >>= 1;
61b03bd7 289
e0c7d767 290 for (i = 0; i < len; i++)
ace4dfee 291 writew(p[i], chip->IO_ADDR_W);
61b03bd7 292
1da177e4
LT		 293}
294
295/**
61b03bd7 296 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 297 * @mtd: MTD device structure
298 * @buf: buffer to store date
299 * @len: number of bytes to read
300 *
301 * Default read function for 16bit buswith
302 */
58dd8f2b 303static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 304{
305 int i;
ace4dfee 306 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 307 u16 *p = (u16 *) buf;
308 len >>= 1;
309
e0c7d767 310 for (i = 0; i < len; i++)
ace4dfee 311 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 312}
313
314/**
61b03bd7 315 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 316 * @mtd: MTD device structure
317 * @buf: buffer containing the data to compare
318 * @len: number of bytes to compare
319 *
320 * Default verify function for 16bit buswith
321 */
58dd8f2b 322static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 323{
324 int i;
ace4dfee 325 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 326 u16 *p = (u16 *) buf;
327 len >>= 1;
328
e0c7d767 329 for (i = 0; i < len; i++)
ace4dfee 330 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 331 return -EFAULT;
332
333 return 0;
334}
335
336/**
337 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
338 * @mtd: MTD device structure
339 * @ofs: offset from device start
340 * @getchip: 0, if the chip is already selected
341 *
61b03bd7 342 * Check, if the block is bad.
1da177e4
LT		 343 */
344static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
345{
346 int page, chipnr, res = 0;
ace4dfee 347 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 348 u16 bad;
349
30fe8115 350 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 351 ofs += mtd->erasesize - mtd->writesize;
352
1a12f46a
TK		 353 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
354
1da177e4 355 if (getchip) {
ace4dfee 356 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 357
ace4dfee 358 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 359
360 /* Select the NAND device */
ace4dfee 361 chip->select_chip(mtd, chipnr);
1a12f46a 362 }
1da177e4 363
ace4dfee
TG		 364 if (chip->options & NAND_BUSWIDTH_16) {
365 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 366 page);
ace4dfee
TG		 367 bad = cpu_to_le16(chip->read_word(mtd));
368 if (chip->badblockpos & 0x1)
49196f33 369 bad >>= 8;
e0b58d0a
ML		 370 else
371 bad &= 0xFF;
1da177e4 372 } else {
1a12f46a 373 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 374 bad = chip->read_byte(mtd);
1da177e4 375 }
61b03bd7 376
e0b58d0a
ML		 377 if (likely(chip->badblockbits == 8))
378 res = bad != 0xFF;
379 else
380 res = hweight8(bad) < chip->badblockbits;
381
ace4dfee 382 if (getchip)
1da177e4 383 nand_release_device(mtd);
61b03bd7 384
1da177e4
LT		 385 return res;
386}
387
388/**
389 * nand_default_block_markbad - [DEFAULT] mark a block bad
390 * @mtd: MTD device structure
391 * @ofs: offset from device start
392 *
393 * This is the default implementation, which can be overridden by
394 * a hardware specific driver.
395*/
396static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
397{
ace4dfee 398 struct nand_chip *chip = mtd->priv;
58dd8f2b 399 uint8_t buf[2] = { 0, 0 };
02ed70bb 400 int block, ret, i = 0;
61b03bd7 401
30fe8115 402 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 403 ofs += mtd->erasesize - mtd->writesize;
404
1da177e4 405 /* Get block number */
4226b510 406 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 407 if (chip->bbt)
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 409
410 /* Do we have a flash based bad block table ? */
ace4dfee 411 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 412 ret = nand_update_bbt(mtd, ofs);
413 else {
c0b8ba7b 414 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 415
02ed70bb
BN		 416 /* Write to first two pages and to byte 1 and 6 if necessary.
417 * If we write to more than one location, the first error
418 * encountered quits the procedure. We write two bytes per
419 * location, so we dont have to mess with 16 bit access.
420 */
421 do {
422 chip->ops.len = chip->ops.ooblen = 2;
423 chip->ops.datbuf = NULL;
424 chip->ops.oobbuf = buf;
425 chip->ops.ooboffs = chip->badblockpos & ~0x01;
426
427 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
428
429 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
430 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
431 & ~0x01;
432 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
433 }
434 i++;
435 ofs += mtd->writesize;
436 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
437 i < 2);
438
c0b8ba7b 439 nand_release_device(mtd);
f1a28c02
TG		 440 }
441 if (!ret)
442 mtd->ecc_stats.badblocks++;
c0b8ba7b 443
f1a28c02 444 return ret;
1da177e4
LT		 445}
446
61b03bd7 447/**
1da177e4
LT		 448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
61b03bd7 450 * Check, if the device is write protected
1da177e4 451 *
61b03bd7 452 * The function expects, that the device is already selected
1da177e4 453 */
e0c7d767 454static int nand_check_wp(struct mtd_info *mtd)
1da177e4 455{
ace4dfee 456 struct nand_chip *chip = mtd->priv;
93edbad6
ML		 457
458 /* broken xD cards report WP despite being writable */
459 if (chip->options & NAND_BROKEN_XD)
460 return 0;
461
1da177e4 462 /* Check the WP bit */
ace4dfee
TG		 463 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
464 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 465}
466
467/**
468 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
469 * @mtd: MTD device structure
470 * @ofs: offset from device start
471 * @getchip: 0, if the chip is already selected
472 * @allowbbt: 1, if its allowed to access the bbt area
473 *
474 * Check, if the block is bad. Either by reading the bad block table or
475 * calling of the scan function.
476 */
2c0a2bed
TG		 477static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
478 int allowbbt)
1da177e4 479{
ace4dfee 480 struct nand_chip *chip = mtd->priv;
61b03bd7 481
ace4dfee
TG		 482 if (!chip->bbt)
483 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 484
1da177e4 485 /* Return info from the table */
e0c7d767 486 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 487}
488
2af7c653
SK		 489/**
490 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
491 * @mtd: MTD device structure
492 * @timeo: Timeout
493 *
494 * Helper function for nand_wait_ready used when needing to wait in interrupt
495 * context.
496 */
497static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
498{
499 struct nand_chip *chip = mtd->priv;
500 int i;
501
502 /* Wait for the device to get ready */
503 for (i = 0; i < timeo; i++) {
504 if (chip->dev_ready(mtd))
505 break;
506 touch_softlockup_watchdog();
507 mdelay(1);
508 }
509}
510
61b03bd7 511/*
3b88775c
TG		 512 * Wait for the ready pin, after a command
513 * The timeout is catched later.
514 */
4b648b02 515void nand_wait_ready(struct mtd_info *mtd)
3b88775c 516{
ace4dfee 517 struct nand_chip *chip = mtd->priv;
e0c7d767 518 unsigned long timeo = jiffies + 2;
3b88775c 519
2af7c653
SK		 520 /* 400ms timeout */
521 if (in_interrupt() || oops_in_progress)
522 return panic_nand_wait_ready(mtd, 400);
523
8fe833c1 524 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 525 /* wait until command is processed or timeout occures */
526 do {
ace4dfee 527 if (chip->dev_ready(mtd))
8fe833c1 528 break;
8446f1d3 529 touch_softlockup_watchdog();
61b03bd7 530 } while (time_before(jiffies, timeo));
8fe833c1 531 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 532}
4b648b02 533EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 534
1da177e4
LT		 535/**
536 * nand_command - [DEFAULT] Send command to NAND device
537 * @mtd: MTD device structure
538 * @command: the command to be sent
539 * @column: the column address for this command, -1 if none
540 * @page_addr: the page address for this command, -1 if none
541 *
542 * Send command to NAND device. This function is used for small page
543 * devices (256/512 Bytes per page)
544 */
7abd3ef9
TG		 545static void nand_command(struct mtd_info *mtd, unsigned int command,
546 int column, int page_addr)
1da177e4 547{
ace4dfee 548 register struct nand_chip *chip = mtd->priv;
7abd3ef9 549 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 550
1da177e4
LT		 551 /*
552 * Write out the command to the device.
553 */
554 if (command == NAND_CMD_SEQIN) {
555 int readcmd;
556
28318776 557 if (column >= mtd->writesize) {
1da177e4 558 /* OOB area */
28318776 559 column -= mtd->writesize;
1da177e4
LT		 560 readcmd = NAND_CMD_READOOB;
561 } else if (column < 256) {
562 /* First 256 bytes --> READ0 */
563 readcmd = NAND_CMD_READ0;
564 } else {
565 column -= 256;
566 readcmd = NAND_CMD_READ1;
567 }
ace4dfee 568 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 569 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 570 }
ace4dfee 571 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 572
7abd3ef9
TG		 573 /*
574 * Address cycle, when necessary
575 */
576 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
577 /* Serially input address */
578 if (column != -1) {
579 /* Adjust columns for 16 bit buswidth */
ace4dfee 580 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 581 column >>= 1;
ace4dfee 582 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 583 ctrl &= ~NAND_CTRL_CHANGE;
584 }
585 if (page_addr != -1) {
ace4dfee 586 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 587 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 588 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 589 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 590 if (chip->chipsize > (32 << 20))
591 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 592 }
ace4dfee 593 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 594
595 /*
596 * program and erase have their own busy handlers
1da177e4 597 * status and sequential in needs no delay
e0c7d767 598 */
1da177e4 599 switch (command) {
61b03bd7 600
1da177e4
LT		 601 case NAND_CMD_PAGEPROG:
602 case NAND_CMD_ERASE1:
603 case NAND_CMD_ERASE2:
604 case NAND_CMD_SEQIN:
605 case NAND_CMD_STATUS:
606 return;
607
608 case NAND_CMD_RESET:
ace4dfee 609 if (chip->dev_ready)
1da177e4 610 break;
ace4dfee
TG		 611 udelay(chip->chip_delay);
612 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 613 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 614 chip->cmd_ctrl(mtd,
615 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 616 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
617 ;
1da177e4
LT		 618 return;
619
e0c7d767 620 /* This applies to read commands */
1da177e4 621 default:
61b03bd7 622 /*
1da177e4
LT		 623 * If we don't have access to the busy pin, we apply the given
624 * command delay
e0c7d767 625 */
ace4dfee
TG		 626 if (!chip->dev_ready) {
627 udelay(chip->chip_delay);
1da177e4 628 return;
61b03bd7 629 }
1da177e4 630 }
1da177e4
LT		 631 /* Apply this short delay always to ensure that we do wait tWB in
632 * any case on any machine. */
e0c7d767 633 ndelay(100);
3b88775c
TG		 634
635 nand_wait_ready(mtd);
1da177e4
LT		 636}
637
638/**
639 * nand_command_lp - [DEFAULT] Send command to NAND large page device
640 * @mtd: MTD device structure
641 * @command: the command to be sent
642 * @column: the column address for this command, -1 if none
643 * @page_addr: the page address for this command, -1 if none
644 *
7abd3ef9
TG		 645 * Send command to NAND device. This is the version for the new large page
646 * devices We dont have the separate regions as we have in the small page
647 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 648 */
7abd3ef9
TG		 649static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
650 int column, int page_addr)
1da177e4 651{
ace4dfee 652 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 653
654 /* Emulate NAND_CMD_READOOB */
655 if (command == NAND_CMD_READOOB) {
28318776 656 column += mtd->writesize;
1da177e4
LT		 657 command = NAND_CMD_READ0;
658 }
61b03bd7 659
7abd3ef9 660 /* Command latch cycle */
ace4dfee 661 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 662 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 663
664 if (column != -1 || page_addr != -1) {
7abd3ef9 665 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 666
667 /* Serially input address */
668 if (column != -1) {
669 /* Adjust columns for 16 bit buswidth */
ace4dfee 670 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 671 column >>= 1;
ace4dfee 672 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 673 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 674 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 675 }
1da177e4 676 if (page_addr != -1) {
ace4dfee
TG		 677 chip->cmd_ctrl(mtd, page_addr, ctrl);
678 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 679 NAND_NCE | NAND_ALE);
1da177e4 680 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 681 if (chip->chipsize > (128 << 20))
682 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 683 NAND_NCE | NAND_ALE);
1da177e4 684 }
1da177e4 685 }
ace4dfee 686 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 687
688 /*
689 * program and erase have their own busy handlers
30f464b7
DM		 690 * status, sequential in, and deplete1 need no delay
691 */
1da177e4 692 switch (command) {
61b03bd7 693
1da177e4
LT		 694 case NAND_CMD_CACHEDPROG:
695 case NAND_CMD_PAGEPROG:
696 case NAND_CMD_ERASE1:
697 case NAND_CMD_ERASE2:
698 case NAND_CMD_SEQIN:
7bc3312b 699 case NAND_CMD_RNDIN:
1da177e4 700 case NAND_CMD_STATUS:
30f464b7 701 case NAND_CMD_DEPLETE1:
1da177e4
LT		 702 return;
703
e0c7d767
DW		 704 /*
705 * read error status commands require only a short delay
706 */
30f464b7
DM		 707 case NAND_CMD_STATUS_ERROR:
708 case NAND_CMD_STATUS_ERROR0:
709 case NAND_CMD_STATUS_ERROR1:
710 case NAND_CMD_STATUS_ERROR2:
711 case NAND_CMD_STATUS_ERROR3:
ace4dfee 712 udelay(chip->chip_delay);
30f464b7 713 return;
1da177e4
LT		 714
715 case NAND_CMD_RESET:
ace4dfee 716 if (chip->dev_ready)
1da177e4 717 break;
ace4dfee 718 udelay(chip->chip_delay);
12efdde3
TG		 719 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
720 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
721 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
722 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 723 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
724 ;
1da177e4
LT		 725 return;
726
7bc3312b
TG		 727 case NAND_CMD_RNDOUT:
728 /* No ready / busy check necessary */
729 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
730 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
731 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
732 NAND_NCE | NAND_CTRL_CHANGE);
733 return;
734
1da177e4 735 case NAND_CMD_READ0:
12efdde3
TG		 736 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
737 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
738 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
739 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 740
e0c7d767 741 /* This applies to read commands */
1da177e4 742 default:
61b03bd7 743 /*
1da177e4
LT		 744 * If we don't have access to the busy pin, we apply the given
745 * command delay
e0c7d767 746 */
ace4dfee
TG		 747 if (!chip->dev_ready) {
748 udelay(chip->chip_delay);
1da177e4 749 return;
61b03bd7 750 }
1da177e4 751 }
3b88775c 752
1da177e4
LT		 753 /* Apply this short delay always to ensure that we do wait tWB in
754 * any case on any machine. */
e0c7d767 755 ndelay(100);
3b88775c
TG		 756
757 nand_wait_ready(mtd);
1da177e4
LT		 758}
759
2af7c653
SK		 760/**
761 * panic_nand_get_device - [GENERIC] Get chip for selected access
762 * @chip: the nand chip descriptor
763 * @mtd: MTD device structure
764 * @new_state: the state which is requested
765 *
766 * Used when in panic, no locks are taken.
767 */
768static void panic_nand_get_device(struct nand_chip *chip,
769 struct mtd_info *mtd, int new_state)
770{
771 /* Hardware controller shared among independend devices */
772 chip->controller->active = chip;
773 chip->state = new_state;
774}
775
1da177e4
LT		 776/**
777 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 778 * @chip: the nand chip descriptor
1da177e4 779 * @mtd: MTD device structure
61b03bd7 780 * @new_state: the state which is requested
1da177e4
LT		 781 *
782 * Get the device and lock it for exclusive access
783 */
2c0a2bed 784static int
ace4dfee 785nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 786{
ace4dfee
TG		 787 spinlock_t *lock = &chip->controller->lock;
788 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 789 DECLARE_WAITQUEUE(wait, current);
7351d3a5 790retry:
0dfc6246
TG		 791 spin_lock(lock);
792
b8b3ee9a 793 /* Hardware controller shared among independent devices */
ace4dfee
TG		 794 if (!chip->controller->active)
795 chip->controller->active = chip;
a36ed299 796
ace4dfee
TG		 797 if (chip->controller->active == chip && chip->state == FL_READY) {
798 chip->state = new_state;
0dfc6246 799 spin_unlock(lock);
962034f4
VW		 800 return 0;
801 }
802 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 803 if (chip->controller->active->state == FL_PM_SUSPENDED) {
804 chip->state = FL_PM_SUSPENDED;
805 spin_unlock(lock);
806 return 0;
6b0d9a84 807 }
0dfc6246
TG		 808 }
809 set_current_state(TASK_UNINTERRUPTIBLE);
810 add_wait_queue(wq, &wait);
811 spin_unlock(lock);
812 schedule();
813 remove_wait_queue(wq, &wait);
1da177e4
LT		 814 goto retry;
815}
816
2af7c653
SK		 817/**
818 * panic_nand_wait - [GENERIC] wait until the command is done
819 * @mtd: MTD device structure
820 * @chip: NAND chip structure
821 * @timeo: Timeout
822 *
823 * Wait for command done. This is a helper function for nand_wait used when
824 * we are in interrupt context. May happen when in panic and trying to write
b595076a 825 * an oops through mtdoops.
2af7c653
SK		 826 */
827static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
828 unsigned long timeo)
829{
830 int i;
831 for (i = 0; i < timeo; i++) {
832 if (chip->dev_ready) {
833 if (chip->dev_ready(mtd))
834 break;
835 } else {
836 if (chip->read_byte(mtd) & NAND_STATUS_READY)
837 break;
838 }
839 mdelay(1);
f8ac0414 840 }
2af7c653
SK		 841}
842
1da177e4
LT		 843/**
844 * nand_wait - [DEFAULT] wait until the command is done
845 * @mtd: MTD device structure
844d3b42 846 * @chip: NAND chip structure
1da177e4
LT		 847 *
848 * Wait for command done. This applies to erase and program only
61b03bd7 849 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 850 * general NAND and SmartMedia specs
844d3b42 851 */
7bc3312b 852static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 853{
854
e0c7d767 855 unsigned long timeo = jiffies;
7bc3312b 856 int status, state = chip->state;
61b03bd7 857
1da177e4 858 if (state == FL_ERASING)
e0c7d767 859 timeo += (HZ * 400) / 1000;
1da177e4 860 else
e0c7d767 861 timeo += (HZ * 20) / 1000;
1da177e4 862
8fe833c1
RP		 863 led_trigger_event(nand_led_trigger, LED_FULL);
864
1da177e4
LT		 865 /* Apply this short delay always to ensure that we do wait tWB in
866 * any case on any machine. */
e0c7d767 867 ndelay(100);
1da177e4 868
ace4dfee
TG		 869 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
870 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 871 else
ace4dfee 872 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 873
2af7c653
SK		 874 if (in_interrupt() || oops_in_progress)
875 panic_nand_wait(mtd, chip, timeo);
876 else {
877 while (time_before(jiffies, timeo)) {
878 if (chip->dev_ready) {
879 if (chip->dev_ready(mtd))
880 break;
881 } else {
882 if (chip->read_byte(mtd) & NAND_STATUS_READY)
883 break;
884 }
885 cond_resched();
1da177e4 886 }
1da177e4 887 }
8fe833c1
RP		 888 led_trigger_event(nand_led_trigger, LED_OFF);
889
ace4dfee 890 status = (int)chip->read_byte(mtd);
1da177e4
LT		 891 return status;
892}
893
7d70f334 894/**
b6d676db 895 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 896 *
b6d676db
RD		 897 * @mtd: mtd info
898 * @ofs: offset to start unlock from
899 * @len: length to unlock
900 * @invert: when = 0, unlock the range of blocks within the lower and
7d70f334 901 * upper boundary address
b6d676db 902 * when = 1, unlock the range of blocks outside the boundaries
7d70f334
VS		 903 * of the lower and upper boundary address
904 *
b6d676db 905 * return - unlock status
7d70f334
VS		 906 */
907static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
908 uint64_t len, int invert)
909{
910 int ret = 0;
911 int status, page;
912 struct nand_chip *chip = mtd->priv;
913
914 /* Submit address of first page to unlock */
915 page = ofs >> chip->page_shift;
916 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
917
918 /* Submit address of last page to unlock */
919 page = (ofs + len) >> chip->page_shift;
920 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
921 (page | invert) & chip->pagemask);
922
923 /* Call wait ready function */
924 status = chip->waitfunc(mtd, chip);
925 udelay(1000);
926 /* See if device thinks it succeeded */
927 if (status & 0x01) {
928 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
929 __func__, status);
930 ret = -EIO;
931 }
932
933 return ret;
934}
935
936/**
b6d676db 937 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 938 *
b6d676db
RD		 939 * @mtd: mtd info
940 * @ofs: offset to start unlock from
941 * @len: length to unlock
7d70f334 942 *
b6d676db 943 * return - unlock status
7d70f334
VS		 944 */
945int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
946{
947 int ret = 0;
948 int chipnr;
949 struct nand_chip *chip = mtd->priv;
950
951 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
952 __func__, (unsigned long long)ofs, len);
953
954 if (check_offs_len(mtd, ofs, len))
955 ret = -EINVAL;
956
957 /* Align to last block address if size addresses end of the device */
958 if (ofs + len == mtd->size)
959 len -= mtd->erasesize;
960
961 nand_get_device(chip, mtd, FL_UNLOCKING);
962
963 /* Shift to get chip number */
964 chipnr = ofs >> chip->chip_shift;
965
966 chip->select_chip(mtd, chipnr);
967
968 /* Check, if it is write protected */
969 if (nand_check_wp(mtd)) {
970 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
971 __func__);
972 ret = -EIO;
973 goto out;
974 }
975
976 ret = __nand_unlock(mtd, ofs, len, 0);
977
978out:
979 /* de-select the NAND device */
980 chip->select_chip(mtd, -1);
981
982 nand_release_device(mtd);
983
984 return ret;
985}
7351d3a5 986EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 987
988/**
b6d676db 989 * nand_lock - [REPLACEABLE] locks all blocks present in the device
7d70f334 990 *
b6d676db
RD		 991 * @mtd: mtd info
992 * @ofs: offset to start unlock from
993 * @len: length to unlock
7d70f334 994 *
b6d676db 995 * return - lock status
7d70f334 996 *
b6d676db
RD		 997 * This feature is not supported in many NAND parts. 'Micron' NAND parts
998 * do have this feature, but it allows only to lock all blocks, not for
7d70f334
VS		 999 * specified range for block.
1000 *
1001 * Implementing 'lock' feature by making use of 'unlock', for now.
1002 */
1003int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1004{
1005 int ret = 0;
1006 int chipnr, status, page;
1007 struct nand_chip *chip = mtd->priv;
1008
1009 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1010 __func__, (unsigned long long)ofs, len);
1011
1012 if (check_offs_len(mtd, ofs, len))
1013 ret = -EINVAL;
1014
1015 nand_get_device(chip, mtd, FL_LOCKING);
1016
1017 /* Shift to get chip number */
1018 chipnr = ofs >> chip->chip_shift;
1019
1020 chip->select_chip(mtd, chipnr);
1021
1022 /* Check, if it is write protected */
1023 if (nand_check_wp(mtd)) {
1024 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1025 __func__);
1026 status = MTD_ERASE_FAILED;
1027 ret = -EIO;
1028 goto out;
1029 }
1030
1031 /* Submit address of first page to lock */
1032 page = ofs >> chip->page_shift;
1033 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1034
1035 /* Call wait ready function */
1036 status = chip->waitfunc(mtd, chip);
1037 udelay(1000);
1038 /* See if device thinks it succeeded */
1039 if (status & 0x01) {
1040 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1041 __func__, status);
1042 ret = -EIO;
1043 goto out;
1044 }
1045
1046 ret = __nand_unlock(mtd, ofs, len, 0x1);
1047
1048out:
1049 /* de-select the NAND device */
1050 chip->select_chip(mtd, -1);
1051
1052 nand_release_device(mtd);
1053
1054 return ret;
1055}
7351d3a5 1056EXPORT_SYMBOL(nand_lock);
7d70f334 1057
8593fbc6
TG		 1058/**
1059 * nand_read_page_raw - [Intern] read raw page data without ecc
1060 * @mtd: mtd info structure
1061 * @chip: nand chip info structure
1062 * @buf: buffer to store read data
58475fb9 1063 * @page: page number to read
52ff49df
DB		 1064 *
1065 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1066 */
1067static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1068 uint8_t *buf, int page)
8593fbc6
TG		 1069{
1070 chip->read_buf(mtd, buf, mtd->writesize);
1071 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1072 return 0;
1073}
1074
52ff49df
DB		 1075/**
1076 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1077 * @mtd: mtd info structure
1078 * @chip: nand chip info structure
1079 * @buf: buffer to store read data
58475fb9 1080 * @page: page number to read
52ff49df
DB		 1081 *
1082 * We need a special oob layout and handling even when OOB isn't used.
1083 */
7351d3a5
FF		 1084static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1085 struct nand_chip *chip,
1086 uint8_t *buf, int page)
52ff49df
DB		 1087{
1088 int eccsize = chip->ecc.size;
1089 int eccbytes = chip->ecc.bytes;
1090 uint8_t *oob = chip->oob_poi;
1091 int steps, size;
1092
1093 for (steps = chip->ecc.steps; steps > 0; steps--) {
1094 chip->read_buf(mtd, buf, eccsize);
1095 buf += eccsize;
1096
1097 if (chip->ecc.prepad) {
1098 chip->read_buf(mtd, oob, chip->ecc.prepad);
1099 oob += chip->ecc.prepad;
1100 }
1101
1102 chip->read_buf(mtd, oob, eccbytes);
1103 oob += eccbytes;
1104
1105 if (chip->ecc.postpad) {
1106 chip->read_buf(mtd, oob, chip->ecc.postpad);
1107 oob += chip->ecc.postpad;
1108 }
1109 }
1110
1111 size = mtd->oobsize - (oob - chip->oob_poi);
1112 if (size)
1113 chip->read_buf(mtd, oob, size);
1114
1115 return 0;
1116}
1117
1da177e4 1118/**
d29ebdbe 1119 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 1120 * @mtd: mtd info structure
1121 * @chip: nand chip info structure
1122 * @buf: buffer to store read data
58475fb9 1123 * @page: page number to read
068e3c0a 1124 */
f5bbdacc 1125static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1126 uint8_t *buf, int page)
1da177e4 1127{
f5bbdacc
TG		 1128 int i, eccsize = chip->ecc.size;
1129 int eccbytes = chip->ecc.bytes;
1130 int eccsteps = chip->ecc.steps;
1131 uint8_t *p = buf;
4bf63fcb
DW		 1132 uint8_t *ecc_calc = chip->buffers->ecccalc;
1133 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1134 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1135
46a8cf2d 1136 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1137
1138 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1139 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1140
1141 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1142 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1143
1144 eccsteps = chip->ecc.steps;
1145 p = buf;
1146
1147 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1148 int stat;
1149
1150 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1151 if (stat < 0)
f5bbdacc
TG		 1152 mtd->ecc_stats.failed++;
1153 else
1154 mtd->ecc_stats.corrected += stat;
1155 }
1156 return 0;
22c60f5f 1157}
1da177e4 1158
3d459559
AK		 1159/**
1160 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1161 * @mtd: mtd info structure
1162 * @chip: nand chip info structure
17c1d2be
AK		 1163 * @data_offs: offset of requested data within the page
1164 * @readlen: data length
1165 * @bufpoi: buffer to store read data
3d459559 1166 */
7351d3a5
FF		 1167static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1168 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1169{
1170 int start_step, end_step, num_steps;
1171 uint32_t *eccpos = chip->ecc.layout->eccpos;
1172 uint8_t *p;
1173 int data_col_addr, i, gaps = 0;
1174 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1175 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1176 int index = 0;
3d459559
AK		 1177
1178 /* Column address wihin the page aligned to ECC size (256bytes). */
1179 start_step = data_offs / chip->ecc.size;
1180 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1181 num_steps = end_step - start_step + 1;
1182
1183 /* Data size aligned to ECC ecc.size*/
1184 datafrag_len = num_steps * chip->ecc.size;
1185 eccfrag_len = num_steps * chip->ecc.bytes;
1186
1187 data_col_addr = start_step * chip->ecc.size;
1188 /* If we read not a page aligned data */
1189 if (data_col_addr != 0)
1190 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1191
1192 p = bufpoi + data_col_addr;
1193 chip->read_buf(mtd, p, datafrag_len);
1194
1195 /* Calculate ECC */
1196 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1197 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1198
1199 /* The performance is faster if to position offsets
1200 according to ecc.pos. Let make sure here that
1201 there are no gaps in ecc positions */
1202 for (i = 0; i < eccfrag_len - 1; i++) {
1203 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1204 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1205 gaps = 1;
1206 break;
1207 }
1208 }
1209 if (gaps) {
1210 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1211 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1212 } else {
1213 /* send the command to read the particular ecc bytes */
1214 /* take care about buswidth alignment in read_buf */
7351d3a5
FF		 1215 index = start_step * chip->ecc.bytes;
1216
1217 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1218 aligned_len = eccfrag_len;
7351d3a5 1219 if (eccpos[index] & (busw - 1))
3d459559 1220 aligned_len++;
7351d3a5 1221 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1222 aligned_len++;
1223
7351d3a5
FF		 1224 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1225 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1226 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1227 }
1228
1229 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1230 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1231
1232 p = bufpoi + data_col_addr;
1233 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1234 int stat;
1235
7351d3a5
FF		 1236 stat = chip->ecc.correct(mtd, p,
1237 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1238 if (stat < 0)
3d459559
AK		 1239 mtd->ecc_stats.failed++;
1240 else
1241 mtd->ecc_stats.corrected += stat;
1242 }
1243 return 0;
1244}
1245
068e3c0a 1246/**
d29ebdbe 1247 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1248 * @mtd: mtd info structure
1249 * @chip: nand chip info structure
1250 * @buf: buffer to store read data
58475fb9 1251 * @page: page number to read
068e3c0a 1252 *
f5bbdacc 1253 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1254 */
f5bbdacc 1255static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1256 uint8_t *buf, int page)
1da177e4 1257{
f5bbdacc
TG		 1258 int i, eccsize = chip->ecc.size;
1259 int eccbytes = chip->ecc.bytes;
1260 int eccsteps = chip->ecc.steps;
1261 uint8_t *p = buf;
4bf63fcb
DW		 1262 uint8_t *ecc_calc = chip->buffers->ecccalc;
1263 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1264 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1265
1266 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1267 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1268 chip->read_buf(mtd, p, eccsize);
1269 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1270 }
f75e5097 1271 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1272
f5bbdacc 1273 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1274 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1275
f5bbdacc
TG		 1276 eccsteps = chip->ecc.steps;
1277 p = buf;
61b03bd7 1278
f5bbdacc
TG		 1279 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1280 int stat;
1da177e4 1281
f5bbdacc 1282 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1283 if (stat < 0)
f5bbdacc
TG		 1284 mtd->ecc_stats.failed++;
1285 else
1286 mtd->ecc_stats.corrected += stat;
1287 }
1288 return 0;
1289}
1da177e4 1290
6e0cb135
SN		 1291/**
1292 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1293 * @mtd: mtd info structure
1294 * @chip: nand chip info structure
1295 * @buf: buffer to store read data
58475fb9 1296 * @page: page number to read
6e0cb135
SN		 1297 *
1298 * Hardware ECC for large page chips, require OOB to be read first.
1299 * For this ECC mode, the write_page method is re-used from ECC_HW.
1300 * These methods read/write ECC from the OOB area, unlike the
1301 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1302 * "infix ECC" scheme and reads/writes ECC from the data area, by
1303 * overwriting the NAND manufacturer bad block markings.
1304 */
1305static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1306 struct nand_chip *chip, uint8_t *buf, int page)
1307{
1308 int i, eccsize = chip->ecc.size;
1309 int eccbytes = chip->ecc.bytes;
1310 int eccsteps = chip->ecc.steps;
1311 uint8_t *p = buf;
1312 uint8_t *ecc_code = chip->buffers->ecccode;
1313 uint32_t *eccpos = chip->ecc.layout->eccpos;
1314 uint8_t *ecc_calc = chip->buffers->ecccalc;
1315
1316 /* Read the OOB area first */
1317 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1318 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1319 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1320
1321 for (i = 0; i < chip->ecc.total; i++)
1322 ecc_code[i] = chip->oob_poi[eccpos[i]];
1323
1324 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1325 int stat;
1326
1327 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1328 chip->read_buf(mtd, p, eccsize);
1329 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1330
1331 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1332 if (stat < 0)
1333 mtd->ecc_stats.failed++;
1334 else
1335 mtd->ecc_stats.corrected += stat;
1336 }
1337 return 0;
1338}
1339
f5bbdacc 1340/**
d29ebdbe 1341 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1342 * @mtd: mtd info structure
1343 * @chip: nand chip info structure
1344 * @buf: buffer to store read data
58475fb9 1345 * @page: page number to read
f5bbdacc
TG		 1346 *
1347 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1348 * we need a special oob layout and handling.
f5bbdacc
TG		 1349 */
1350static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1351 uint8_t *buf, int page)
f5bbdacc
TG		 1352{
1353 int i, eccsize = chip->ecc.size;
1354 int eccbytes = chip->ecc.bytes;
1355 int eccsteps = chip->ecc.steps;
1356 uint8_t *p = buf;
f75e5097 1357 uint8_t *oob = chip->oob_poi;
1da177e4 1358
f5bbdacc
TG		 1359 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1360 int stat;
61b03bd7 1361
f5bbdacc
TG		 1362 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1363 chip->read_buf(mtd, p, eccsize);
1da177e4 1364
f5bbdacc
TG		 1365 if (chip->ecc.prepad) {
1366 chip->read_buf(mtd, oob, chip->ecc.prepad);
1367 oob += chip->ecc.prepad;
1368 }
1da177e4 1369
f5bbdacc
TG		 1370 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1371 chip->read_buf(mtd, oob, eccbytes);
1372 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1373
c32b8dcc 1374 if (stat < 0)
f5bbdacc 1375 mtd->ecc_stats.failed++;
61b03bd7 1376 else
f5bbdacc 1377 mtd->ecc_stats.corrected += stat;
61b03bd7 1378
f5bbdacc 1379 oob += eccbytes;
1da177e4 1380
f5bbdacc
TG		 1381 if (chip->ecc.postpad) {
1382 chip->read_buf(mtd, oob, chip->ecc.postpad);
1383 oob += chip->ecc.postpad;
61b03bd7 1384 }
f5bbdacc 1385 }
1da177e4 1386
f5bbdacc 1387 /* Calculate remaining oob bytes */
7e4178f9 1388 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1389 if (i)
1390 chip->read_buf(mtd, oob, i);
61b03bd7 1391
f5bbdacc
TG		 1392 return 0;
1393}
1da177e4 1394
f5bbdacc 1395/**
8593fbc6
TG		 1396 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1397 * @chip: nand chip structure
844d3b42 1398 * @oob: oob destination address
8593fbc6 1399 * @ops: oob ops structure
7014568b 1400 * @len: size of oob to transfer
8593fbc6
TG		 1401 */
1402static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1403 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1404{
f8ac0414 1405 switch (ops->mode) {
8593fbc6
TG		 1406
1407 case MTD_OOB_PLACE:
1408 case MTD_OOB_RAW:
1409 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1410 return oob + len;
1411
1412 case MTD_OOB_AUTO: {
1413 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1414 uint32_t boffs = 0, roffs = ops->ooboffs;
1415 size_t bytes = 0;
8593fbc6 1416
f8ac0414 1417 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1418 /* Read request not from offset 0 ? */
1419 if (unlikely(roffs)) {
1420 if (roffs >= free->length) {
1421 roffs -= free->length;
1422 continue;
1423 }
1424 boffs = free->offset + roffs;
1425 bytes = min_t(size_t, len,
1426 (free->length - roffs));
1427 roffs = 0;
1428 } else {
1429 bytes = min_t(size_t, len, free->length);
1430 boffs = free->offset;
1431 }
1432 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1433 oob += bytes;
1434 }
1435 return oob;
1436 }
1437 default:
1438 BUG();
1439 }
1440 return NULL;
1441}
1442
1443/**
1444 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1445 *
1446 * @mtd: MTD device structure
1447 * @from: offset to read from
844d3b42 1448 * @ops: oob ops structure
f5bbdacc
TG		 1449 *
1450 * Internal function. Called with chip held.
1451 */
8593fbc6
TG		 1452static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1453 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1454{
1455 int chipnr, page, realpage, col, bytes, aligned;
1456 struct nand_chip *chip = mtd->priv;
1457 struct mtd_ecc_stats stats;
1458 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1459 int sndcmd = 1;
1460 int ret = 0;
8593fbc6 1461 uint32_t readlen = ops->len;
7014568b 1462 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1463 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1464 mtd->oobavail : mtd->oobsize;
1465
8593fbc6 1466 uint8_t *bufpoi, *oob, *buf;
1da177e4 1467
f5bbdacc 1468 stats = mtd->ecc_stats;
1da177e4 1469
f5bbdacc
TG		 1470 chipnr = (int)(from >> chip->chip_shift);
1471 chip->select_chip(mtd, chipnr);
61b03bd7 1472
f5bbdacc
TG		 1473 realpage = (int)(from >> chip->page_shift);
1474 page = realpage & chip->pagemask;
1da177e4 1475
f5bbdacc 1476 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1477
8593fbc6
TG		 1478 buf = ops->datbuf;
1479 oob = ops->oobbuf;
1480
f8ac0414 1481 while (1) {
f5bbdacc
TG		 1482 bytes = min(mtd->writesize - col, readlen);
1483 aligned = (bytes == mtd->writesize);
61b03bd7 1484
f5bbdacc 1485 /* Is the current page in the buffer ? */
8593fbc6 1486 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1487 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1488
f5bbdacc
TG		 1489 if (likely(sndcmd)) {
1490 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1491 sndcmd = 0;
1da177e4 1492 }
1da177e4 1493
f5bbdacc 1494 /* Now read the page into the buffer */
956e944c 1495 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1496 ret = chip->ecc.read_page_raw(mtd, chip,
1497 bufpoi, page);
3d459559 1498 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1499 ret = chip->ecc.read_subpage(mtd, chip,
1500 col, bytes, bufpoi);
956e944c 1501 else
46a8cf2d
SN		 1502 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1503 page);
f5bbdacc 1504 if (ret < 0)
1da177e4 1505 break;
f5bbdacc
TG		 1506
1507 /* Transfer not aligned data */
1508 if (!aligned) {
c1194c79
AB		 1509 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1510 !(mtd->ecc_stats.failed - stats.failed))
3d459559 1511 chip->pagebuf = realpage;
4bf63fcb 1512 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1513 }
1514
8593fbc6
TG		 1515 buf += bytes;
1516
1517 if (unlikely(oob)) {
9aca334e 1518
b64d39d8
ML		 1519 int toread = min(oobreadlen, max_oobsize);
1520
1521 if (toread) {
1522 oob = nand_transfer_oob(chip,
1523 oob, ops, toread);
1524 oobreadlen -= toread;
1525 }
8593fbc6
TG		 1526 }
1527
f5bbdacc
TG		 1528 if (!(chip->options & NAND_NO_READRDY)) {
1529 /*
1530 * Apply delay or wait for ready/busy pin. Do
1531 * this before the AUTOINCR check, so no
1532 * problems arise if a chip which does auto
1533 * increment is marked as NOAUTOINCR by the
1534 * board driver.
1535 */
1536 if (!chip->dev_ready)
1537 udelay(chip->chip_delay);
1538 else
1539 nand_wait_ready(mtd);
1da177e4 1540 }
8593fbc6 1541 } else {
4bf63fcb 1542 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1543 buf += bytes;
1544 }
1da177e4 1545
f5bbdacc 1546 readlen -= bytes;
61b03bd7 1547
f5bbdacc 1548 if (!readlen)
61b03bd7 1549 break;
1da177e4
LT		 1550
1551 /* For subsequent reads align to page boundary. */
1552 col = 0;
1553 /* Increment page address */
1554 realpage++;
1555
ace4dfee 1556 page = realpage & chip->pagemask;
1da177e4
LT		 1557 /* Check, if we cross a chip boundary */
1558 if (!page) {
1559 chipnr++;
ace4dfee
TG		 1560 chip->select_chip(mtd, -1);
1561 chip->select_chip(mtd, chipnr);
1da177e4 1562 }
f5bbdacc 1563
61b03bd7
TG		 1564 /* Check, if the chip supports auto page increment
1565 * or if we have hit a block boundary.
e0c7d767 1566 */
f5bbdacc 1567 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1568 sndcmd = 1;
1da177e4
LT		 1569 }
1570
8593fbc6 1571 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1572 if (oob)
1573 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1574
f5bbdacc
TG		 1575 if (ret)
1576 return ret;
1577
9a1fcdfd
TG		 1578 if (mtd->ecc_stats.failed - stats.failed)
1579 return -EBADMSG;
1580
1581 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1582}
1583
1584/**
25985edc 1585 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
f5bbdacc
TG		 1586 * @mtd: MTD device structure
1587 * @from: offset to read from
1588 * @len: number of bytes to read
1589 * @retlen: pointer to variable to store the number of read bytes
1590 * @buf: the databuffer to put data
1591 *
1592 * Get hold of the chip and call nand_do_read
1593 */
1594static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1595 size_t *retlen, uint8_t *buf)
1596{
8593fbc6 1597 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1598 int ret;
1599
f5bbdacc
TG		 1600 /* Do not allow reads past end of device */
1601 if ((from + len) > mtd->size)
1602 return -EINVAL;
1603 if (!len)
1604 return 0;
1605
8593fbc6 1606 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1607
8593fbc6
TG		 1608 chip->ops.len = len;
1609 chip->ops.datbuf = buf;
1610 chip->ops.oobbuf = NULL;
1611
1612 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1613
7fd5aecc
RP		 1614 *retlen = chip->ops.retlen;
1615
f5bbdacc
TG		 1616 nand_release_device(mtd);
1617
1618 return ret;
1da177e4
LT		 1619}
1620
7bc3312b
TG		 1621/**
1622 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1623 * @mtd: mtd info structure
1624 * @chip: nand chip info structure
1625 * @page: page number to read
1626 * @sndcmd: flag whether to issue read command or not
1627 */
1628static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1629 int page, int sndcmd)
1630{
1631 if (sndcmd) {
1632 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1633 sndcmd = 0;
1634 }
1635 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1636 return sndcmd;
1637}
1638
1639/**
1640 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1641 * with syndromes
1642 * @mtd: mtd info structure
1643 * @chip: nand chip info structure
1644 * @page: page number to read
1645 * @sndcmd: flag whether to issue read command or not
1646 */
1647static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1648 int page, int sndcmd)
1649{
1650 uint8_t *buf = chip->oob_poi;
1651 int length = mtd->oobsize;
1652 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1653 int eccsize = chip->ecc.size;
1654 uint8_t *bufpoi = buf;
1655 int i, toread, sndrnd = 0, pos;
1656
1657 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1658 for (i = 0; i < chip->ecc.steps; i++) {
1659 if (sndrnd) {
1660 pos = eccsize + i * (eccsize + chunk);
1661 if (mtd->writesize > 512)
1662 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1663 else
1664 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1665 } else
1666 sndrnd = 1;
1667 toread = min_t(int, length, chunk);
1668 chip->read_buf(mtd, bufpoi, toread);
1669 bufpoi += toread;
1670 length -= toread;
1671 }
1672 if (length > 0)
1673 chip->read_buf(mtd, bufpoi, length);
1674
1675 return 1;
1676}
1677
1678/**
1679 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1680 * @mtd: mtd info structure
1681 * @chip: nand chip info structure
1682 * @page: page number to write
1683 */
1684static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1685 int page)
1686{
1687 int status = 0;
1688 const uint8_t *buf = chip->oob_poi;
1689 int length = mtd->oobsize;
1690
1691 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1692 chip->write_buf(mtd, buf, length);
1693 /* Send command to program the OOB data */
1694 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1695
1696 status = chip->waitfunc(mtd, chip);
1697
0d420f9d 1698 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1699}
1700
1701/**
1702 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1703 * with syndrome - only for large page flash !
1704 * @mtd: mtd info structure
1705 * @chip: nand chip info structure
1706 * @page: page number to write
1707 */
1708static int nand_write_oob_syndrome(struct mtd_info *mtd,
1709 struct nand_chip *chip, int page)
1710{
1711 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1712 int eccsize = chip->ecc.size, length = mtd->oobsize;
1713 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1714 const uint8_t *bufpoi = chip->oob_poi;
1715
1716 /*
1717 * data-ecc-data-ecc ... ecc-oob
1718 * or
1719 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1720 */
1721 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1722 pos = steps * (eccsize + chunk);
1723 steps = 0;
1724 } else
8b0036ee 1725 pos = eccsize;
7bc3312b
TG		 1726
1727 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1728 for (i = 0; i < steps; i++) {
1729 if (sndcmd) {
1730 if (mtd->writesize <= 512) {
1731 uint32_t fill = 0xFFFFFFFF;
1732
1733 len = eccsize;
1734 while (len > 0) {
1735 int num = min_t(int, len, 4);
1736 chip->write_buf(mtd, (uint8_t *)&fill,
1737 num);
1738 len -= num;
1739 }
1740 } else {
1741 pos = eccsize + i * (eccsize + chunk);
1742 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1743 }
1744 } else
1745 sndcmd = 1;
1746 len = min_t(int, length, chunk);
1747 chip->write_buf(mtd, bufpoi, len);
1748 bufpoi += len;
1749 length -= len;
1750 }
1751 if (length > 0)
1752 chip->write_buf(mtd, bufpoi, length);
1753
1754 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1755 status = chip->waitfunc(mtd, chip);
1756
1757 return status & NAND_STATUS_FAIL ? -EIO : 0;
1758}
1759
1da177e4 1760/**
8593fbc6 1761 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1762 * @mtd: MTD device structure
1763 * @from: offset to read from
8593fbc6 1764 * @ops: oob operations description structure
1da177e4
LT		 1765 *
1766 * NAND read out-of-band data from the spare area
1767 */
8593fbc6
TG		 1768static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1769 struct mtd_oob_ops *ops)
1da177e4 1770{
7bc3312b 1771 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1772 struct nand_chip *chip = mtd->priv;
7314e9e7 1773 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1774 int readlen = ops->ooblen;
1775 int len;
7bc3312b 1776 uint8_t *buf = ops->oobbuf;
61b03bd7 1777
20d8e248 1778 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1779 __func__, (unsigned long long)from, readlen);
1da177e4 1780
03736155 1781 if (ops->mode == MTD_OOB_AUTO)
7014568b 1782 len = chip->ecc.layout->oobavail;
03736155
AH		 1783 else
1784 len = mtd->oobsize;
1785
1786 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1787 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1788 "outside oob\n", __func__);
03736155
AH		 1789 return -EINVAL;
1790 }
1791
1792 /* Do not allow reads past end of device */
1793 if (unlikely(from >= mtd->size ||
1794 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1795 (from >> chip->page_shift)) * len)) {
20d8e248 1796 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1797 "of device\n", __func__);
03736155
AH		 1798 return -EINVAL;
1799 }
7014568b 1800
7314e9e7 1801 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1802 chip->select_chip(mtd, chipnr);
1da177e4 1803
7314e9e7
TG		 1804 /* Shift to get page */
1805 realpage = (int)(from >> chip->page_shift);
1806 page = realpage & chip->pagemask;
1da177e4 1807
f8ac0414 1808 while (1) {
7bc3312b 1809 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1810
1811 len = min(len, readlen);
1812 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1813
7314e9e7
TG		 1814 if (!(chip->options & NAND_NO_READRDY)) {
1815 /*
1816 * Apply delay or wait for ready/busy pin. Do this
1817 * before the AUTOINCR check, so no problems arise if a
1818 * chip which does auto increment is marked as
1819 * NOAUTOINCR by the board driver.
19870da7 1820 */
ace4dfee
TG		 1821 if (!chip->dev_ready)
1822 udelay(chip->chip_delay);
19870da7
TG		 1823 else
1824 nand_wait_ready(mtd);
7314e9e7 1825 }
19870da7 1826
7014568b 1827 readlen -= len;
0d420f9d
SZ		 1828 if (!readlen)
1829 break;
1830
7314e9e7
TG		 1831 /* Increment page address */
1832 realpage++;
1833
1834 page = realpage & chip->pagemask;
1835 /* Check, if we cross a chip boundary */
1836 if (!page) {
1837 chipnr++;
1838 chip->select_chip(mtd, -1);
1839 chip->select_chip(mtd, chipnr);
1da177e4 1840 }
7314e9e7
TG		 1841
1842 /* Check, if the chip supports auto page increment
1843 * or if we have hit a block boundary.
1844 */
1845 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1846 sndcmd = 1;
1da177e4
LT		 1847 }
1848
7014568b 1849 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1850 return 0;
1851}
1852
1853/**
8593fbc6 1854 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1855 * @mtd: MTD device structure
1da177e4 1856 * @from: offset to read from
8593fbc6 1857 * @ops: oob operation description structure
1da177e4 1858 *
8593fbc6 1859 * NAND read data and/or out-of-band data
1da177e4 1860 */
8593fbc6
TG		 1861static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1862 struct mtd_oob_ops *ops)
1da177e4 1863{
ace4dfee 1864 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1865 int ret = -ENOTSUPP;
1866
1867 ops->retlen = 0;
1da177e4
LT		 1868
1869 /* Do not allow reads past end of device */
7014568b 1870 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1871 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1872 "beyond end of device\n", __func__);
1da177e4
LT		 1873 return -EINVAL;
1874 }
1875
ace4dfee 1876 nand_get_device(chip, mtd, FL_READING);
1da177e4 1877
f8ac0414 1878 switch (ops->mode) {
8593fbc6
TG		 1879 case MTD_OOB_PLACE:
1880 case MTD_OOB_AUTO:
8593fbc6 1881 case MTD_OOB_RAW:
8593fbc6 1882 break;
1da177e4 1883
8593fbc6
TG		 1884 default:
1885 goto out;
1886 }
1da177e4 1887
8593fbc6
TG		 1888 if (!ops->datbuf)
1889 ret = nand_do_read_oob(mtd, from, ops);
1890 else
1891 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1892
7351d3a5 1893out:
8593fbc6
TG		 1894 nand_release_device(mtd);
1895 return ret;
1896}
61b03bd7 1897
1da177e4 1898
8593fbc6
TG		 1899/**
1900 * nand_write_page_raw - [Intern] raw page write function
1901 * @mtd: mtd info structure
1902 * @chip: nand chip info structure
1903 * @buf: data buffer
52ff49df
DB		 1904 *
1905 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1906 */
1907static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1908 const uint8_t *buf)
1909{
1910 chip->write_buf(mtd, buf, mtd->writesize);
1911 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1912}
1913
52ff49df
DB		 1914/**
1915 * nand_write_page_raw_syndrome - [Intern] raw page write function
1916 * @mtd: mtd info structure
1917 * @chip: nand chip info structure
1918 * @buf: data buffer
1919 *
1920 * We need a special oob layout and handling even when ECC isn't checked.
1921 */
7351d3a5
FF		 1922static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1923 struct nand_chip *chip,
1924 const uint8_t *buf)
52ff49df
DB		 1925{
1926 int eccsize = chip->ecc.size;
1927 int eccbytes = chip->ecc.bytes;
1928 uint8_t *oob = chip->oob_poi;
1929 int steps, size;
1930
1931 for (steps = chip->ecc.steps; steps > 0; steps--) {
1932 chip->write_buf(mtd, buf, eccsize);
1933 buf += eccsize;
1934
1935 if (chip->ecc.prepad) {
1936 chip->write_buf(mtd, oob, chip->ecc.prepad);
1937 oob += chip->ecc.prepad;
1938 }
1939
1940 chip->read_buf(mtd, oob, eccbytes);
1941 oob += eccbytes;
1942
1943 if (chip->ecc.postpad) {
1944 chip->write_buf(mtd, oob, chip->ecc.postpad);
1945 oob += chip->ecc.postpad;
1946 }
1947 }
1948
1949 size = mtd->oobsize - (oob - chip->oob_poi);
1950 if (size)
1951 chip->write_buf(mtd, oob, size);
1952}
9223a456 1953/**
d29ebdbe 1954 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1955 * @mtd: mtd info structure
1956 * @chip: nand chip info structure
1957 * @buf: data buffer
9223a456 1958 */
f75e5097
TG		 1959static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1960 const uint8_t *buf)
9223a456 1961{
f75e5097
TG		 1962 int i, eccsize = chip->ecc.size;
1963 int eccbytes = chip->ecc.bytes;
1964 int eccsteps = chip->ecc.steps;
4bf63fcb 1965 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1966 const uint8_t *p = buf;
8b099a39 1967 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1968
8593fbc6
TG		 1969 /* Software ecc calculation */
1970 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1971 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1972
8593fbc6
TG		 1973 for (i = 0; i < chip->ecc.total; i++)
1974 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1975
90424de8 1976 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1977}
9223a456 1978
f75e5097 1979/**
d29ebdbe 1980 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1981 * @mtd: mtd info structure
1982 * @chip: nand chip info structure
1983 * @buf: data buffer
1984 */
1985static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1986 const uint8_t *buf)
1987{
1988 int i, eccsize = chip->ecc.size;
1989 int eccbytes = chip->ecc.bytes;
1990 int eccsteps = chip->ecc.steps;
4bf63fcb 1991 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1992 const uint8_t *p = buf;
8b099a39 1993 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1994
f75e5097
TG		 1995 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1996 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1997 chip->write_buf(mtd, p, eccsize);
f75e5097 1998 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1999 }
2000
f75e5097
TG		 2001 for (i = 0; i < chip->ecc.total; i++)
2002 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2003
2004 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2005}
2006
61b03bd7 2007/**
d29ebdbe 2008 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 2009 * @mtd: mtd info structure
2010 * @chip: nand chip info structure
2011 * @buf: data buffer
1da177e4 2012 *
f75e5097
TG		 2013 * The hw generator calculates the error syndrome automatically. Therefor
2014 * we need a special oob layout and handling.
2015 */
2016static void nand_write_page_syndrome(struct mtd_info *mtd,
2017 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2018{
f75e5097
TG		 2019 int i, eccsize = chip->ecc.size;
2020 int eccbytes = chip->ecc.bytes;
2021 int eccsteps = chip->ecc.steps;
2022 const uint8_t *p = buf;
2023 uint8_t *oob = chip->oob_poi;
1da177e4 2024
f75e5097 2025 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2026
f75e5097
TG		 2027 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2028 chip->write_buf(mtd, p, eccsize);
61b03bd7 2029
f75e5097
TG		 2030 if (chip->ecc.prepad) {
2031 chip->write_buf(mtd, oob, chip->ecc.prepad);
2032 oob += chip->ecc.prepad;
2033 }
2034
2035 chip->ecc.calculate(mtd, p, oob);
2036 chip->write_buf(mtd, oob, eccbytes);
2037 oob += eccbytes;
2038
2039 if (chip->ecc.postpad) {
2040 chip->write_buf(mtd, oob, chip->ecc.postpad);
2041 oob += chip->ecc.postpad;
1da177e4 2042 }
1da177e4 2043 }
f75e5097
TG		 2044
2045 /* Calculate remaining oob bytes */
7e4178f9 2046 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2047 if (i)
2048 chip->write_buf(mtd, oob, i);
2049}
2050
2051/**
956e944c 2052 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 2053 * @mtd: MTD device structure
2054 * @chip: NAND chip descriptor
2055 * @buf: the data to write
2056 * @page: page number to write
2057 * @cached: cached programming
efbfe96c 2058 * @raw: use _raw version of write_page
f75e5097
TG		 2059 */
2060static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2061 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2062{
2063 int status;
2064
2065 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2066
956e944c
DW		 2067 if (unlikely(raw))
2068 chip->ecc.write_page_raw(mtd, chip, buf);
2069 else
2070 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2071
2072 /*
2073 * Cached progamming disabled for now, Not sure if its worth the
2074 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2075 */
2076 cached = 0;
2077
2078 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2079
2080 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2081 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2082 /*
2083 * See if operation failed and additional status checks are
2084 * available
2085 */
2086 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2087 status = chip->errstat(mtd, chip, FL_WRITING, status,
2088 page);
2089
2090 if (status & NAND_STATUS_FAIL)
2091 return -EIO;
2092 } else {
2093 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2094 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2095 }
2096
2097#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2098 /* Send command to read back the data */
2099 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2100
2101 if (chip->verify_buf(mtd, buf, mtd->writesize))
2102 return -EIO;
2103#endif
2104 return 0;
1da177e4
LT		 2105}
2106
8593fbc6
TG		 2107/**
2108 * nand_fill_oob - [Internal] Transfer client buffer to oob
2109 * @chip: nand chip structure
2110 * @oob: oob data buffer
b6d676db 2111 * @len: oob data write length
8593fbc6
TG		 2112 * @ops: oob ops structure
2113 */
782ce79a
ML		 2114static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2115 struct mtd_oob_ops *ops)
8593fbc6 2116{
f8ac0414 2117 switch (ops->mode) {
8593fbc6
TG		 2118
2119 case MTD_OOB_PLACE:
2120 case MTD_OOB_RAW:
2121 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2122 return oob + len;
2123
2124 case MTD_OOB_AUTO: {
2125 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2126 uint32_t boffs = 0, woffs = ops->ooboffs;
2127 size_t bytes = 0;
8593fbc6 2128
f8ac0414 2129 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 2130 /* Write request not from offset 0 ? */
2131 if (unlikely(woffs)) {
2132 if (woffs >= free->length) {
2133 woffs -= free->length;
2134 continue;
2135 }
2136 boffs = free->offset + woffs;
2137 bytes = min_t(size_t, len,
2138 (free->length - woffs));
2139 woffs = 0;
2140 } else {
2141 bytes = min_t(size_t, len, free->length);
2142 boffs = free->offset;
2143 }
8b0036ee 2144 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2145 oob += bytes;
2146 }
2147 return oob;
2148 }
2149 default:
2150 BUG();
2151 }
2152 return NULL;
2153}
2154
f8ac0414 2155#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2156
2157/**
8593fbc6 2158 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 2159 * @mtd: MTD device structure
2160 * @to: offset to write to
8593fbc6 2161 * @ops: oob operations description structure
1da177e4
LT		 2162 *
2163 * NAND write with ECC
2164 */
8593fbc6
TG		 2165static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2166 struct mtd_oob_ops *ops)
1da177e4 2167{
29072b96 2168 int chipnr, realpage, page, blockmask, column;
ace4dfee 2169 struct nand_chip *chip = mtd->priv;
8593fbc6 2170 uint32_t writelen = ops->len;
782ce79a
ML		 2171
2172 uint32_t oobwritelen = ops->ooblen;
2173 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2174 mtd->oobavail : mtd->oobsize;
2175
8593fbc6
TG		 2176 uint8_t *oob = ops->oobbuf;
2177 uint8_t *buf = ops->datbuf;
29072b96 2178 int ret, subpage;
1da177e4 2179
8593fbc6 2180 ops->retlen = 0;
29072b96
TG		 2181 if (!writelen)
2182 return 0;
1da177e4 2183
61b03bd7 2184 /* reject writes, which are not page aligned */
8593fbc6 2185 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2186 printk(KERN_NOTICE "%s: Attempt to write not "
2187 "page aligned data\n", __func__);
1da177e4
LT		 2188 return -EINVAL;
2189 }
2190
29072b96
TG		 2191 column = to & (mtd->writesize - 1);
2192 subpage = column || (writelen & (mtd->writesize - 1));
2193
2194 if (subpage && oob)
2195 return -EINVAL;
1da177e4 2196
6a930961
TG		 2197 chipnr = (int)(to >> chip->chip_shift);
2198 chip->select_chip(mtd, chipnr);
2199
1da177e4
LT		 2200 /* Check, if it is write protected */
2201 if (nand_check_wp(mtd))
8593fbc6 2202 return -EIO;
1da177e4 2203
f75e5097
TG		 2204 realpage = (int)(to >> chip->page_shift);
2205 page = realpage & chip->pagemask;
2206 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2207
2208 /* Invalidate the page cache, when we write to the cached page */
2209 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2210 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2211 chip->pagebuf = -1;
61b03bd7 2212
7dcdcbef
DW		 2213 /* If we're not given explicit OOB data, let it be 0xFF */
2214 if (likely(!oob))
2215 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 2216
782ce79a 2217 /* Don't allow multipage oob writes with offset */
cdcf12b2 2218 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2219 return -EINVAL;
2220
f8ac0414 2221 while (1) {
29072b96 2222 int bytes = mtd->writesize;
f75e5097 2223 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2224 uint8_t *wbuf = buf;
2225
2226 /* Partial page write ? */
2227 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2228 cached = 0;
2229 bytes = min_t(int, bytes - column, (int) writelen);
2230 chip->pagebuf = -1;
2231 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2232 memcpy(&chip->buffers->databuf[column], buf, bytes);
2233 wbuf = chip->buffers->databuf;
2234 }
1da177e4 2235
782ce79a
ML		 2236 if (unlikely(oob)) {
2237 size_t len = min(oobwritelen, oobmaxlen);
2238 oob = nand_fill_oob(chip, oob, len, ops);
2239 oobwritelen -= len;
2240 }
8593fbc6 2241
29072b96 2242 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2243 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2244 if (ret)
2245 break;
2246
2247 writelen -= bytes;
2248 if (!writelen)
2249 break;
2250
29072b96 2251 column = 0;
f75e5097
TG		 2252 buf += bytes;
2253 realpage++;
2254
2255 page = realpage & chip->pagemask;
2256 /* Check, if we cross a chip boundary */
2257 if (!page) {
2258 chipnr++;
2259 chip->select_chip(mtd, -1);
2260 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2261 }
2262 }
8593fbc6 2263
8593fbc6 2264 ops->retlen = ops->len - writelen;
7014568b
VW		 2265 if (unlikely(oob))
2266 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2267 return ret;
2268}
2269
2af7c653
SK		 2270/**
2271 * panic_nand_write - [MTD Interface] NAND write with ECC
2272 * @mtd: MTD device structure
2273 * @to: offset to write to
2274 * @len: number of bytes to write
2275 * @retlen: pointer to variable to store the number of written bytes
2276 * @buf: the data to write
2277 *
2278 * NAND write with ECC. Used when performing writes in interrupt context, this
2279 * may for example be called by mtdoops when writing an oops while in panic.
2280 */
2281static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2282 size_t *retlen, const uint8_t *buf)
2283{
2284 struct nand_chip *chip = mtd->priv;
2285 int ret;
2286
2287 /* Do not allow reads past end of device */
2288 if ((to + len) > mtd->size)
2289 return -EINVAL;
2290 if (!len)
2291 return 0;
2292
2293 /* Wait for the device to get ready. */
2294 panic_nand_wait(mtd, chip, 400);
2295
2296 /* Grab the device. */
2297 panic_nand_get_device(chip, mtd, FL_WRITING);
2298
2299 chip->ops.len = len;
2300 chip->ops.datbuf = (uint8_t *)buf;
2301 chip->ops.oobbuf = NULL;
2302
2303 ret = nand_do_write_ops(mtd, to, &chip->ops);
2304
2305 *retlen = chip->ops.retlen;
2306 return ret;
2307}
2308
f75e5097 2309/**
8593fbc6 2310 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2311 * @mtd: MTD device structure
f75e5097
TG		 2312 * @to: offset to write to
2313 * @len: number of bytes to write
8593fbc6
TG		 2314 * @retlen: pointer to variable to store the number of written bytes
2315 * @buf: the data to write
f75e5097 2316 *
8593fbc6 2317 * NAND write with ECC
f75e5097 2318 */
8593fbc6
TG		 2319static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2320 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2321{
2322 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2323 int ret;
2324
8593fbc6
TG		 2325 /* Do not allow reads past end of device */
2326 if ((to + len) > mtd->size)
f75e5097 2327 return -EINVAL;
8593fbc6
TG		 2328 if (!len)
2329 return 0;
f75e5097 2330
7bc3312b 2331 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2332
8593fbc6
TG		 2333 chip->ops.len = len;
2334 chip->ops.datbuf = (uint8_t *)buf;
2335 chip->ops.oobbuf = NULL;
f75e5097 2336
8593fbc6 2337 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2338
7fd5aecc
RP		 2339 *retlen = chip->ops.retlen;
2340
f75e5097 2341 nand_release_device(mtd);
8593fbc6 2342
8593fbc6 2343 return ret;
f75e5097 2344}
7314e9e7 2345
1da177e4 2346/**
8593fbc6 2347 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2348 * @mtd: MTD device structure
2349 * @to: offset to write to
8593fbc6 2350 * @ops: oob operation description structure
1da177e4
LT		 2351 *
2352 * NAND write out-of-band
2353 */
8593fbc6
TG		 2354static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2355 struct mtd_oob_ops *ops)
1da177e4 2356{
03736155 2357 int chipnr, page, status, len;
ace4dfee 2358 struct nand_chip *chip = mtd->priv;
1da177e4 2359
20d8e248 2360 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2361 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2362
03736155
AH		 2363 if (ops->mode == MTD_OOB_AUTO)
2364 len = chip->ecc.layout->oobavail;
2365 else
2366 len = mtd->oobsize;
2367
1da177e4 2368 /* Do not allow write past end of page */
03736155 2369 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2370 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2371 "past end of page\n", __func__);
1da177e4
LT		 2372 return -EINVAL;
2373 }
2374
03736155 2375 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2376 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2377 "write outside oob\n", __func__);
03736155
AH		 2378 return -EINVAL;
2379 }
2380
775adc3d 2381 /* Do not allow write past end of device */
03736155
AH		 2382 if (unlikely(to >= mtd->size ||
2383 ops->ooboffs + ops->ooblen >
2384 ((mtd->size >> chip->page_shift) -
2385 (to >> chip->page_shift)) * len)) {
20d8e248 2386 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2387 "end of device\n", __func__);
03736155
AH		 2388 return -EINVAL;
2389 }
2390
7314e9e7 2391 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2392 chip->select_chip(mtd, chipnr);
1da177e4 2393
7314e9e7
TG		 2394 /* Shift to get page */
2395 page = (int)(to >> chip->page_shift);
2396
2397 /*
2398 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2399 * of my DiskOnChip 2000 test units) will clear the whole data page too
2400 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2401 * it in the doc2000 driver in August 1999. dwmw2.
2402 */
ace4dfee 2403 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2404
2405 /* Check, if it is write protected */
2406 if (nand_check_wp(mtd))
8593fbc6 2407 return -EROFS;
61b03bd7 2408
1da177e4 2409 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2410 if (page == chip->pagebuf)
2411 chip->pagebuf = -1;
1da177e4 2412
7bc3312b 2413 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2414 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
7bc3312b
TG		 2415 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2416 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2417
7bc3312b
TG		 2418 if (status)
2419 return status;
1da177e4 2420
7014568b 2421 ops->oobretlen = ops->ooblen;
1da177e4 2422
7bc3312b 2423 return 0;
8593fbc6
TG		 2424}
2425
2426/**
2427 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2428 * @mtd: MTD device structure
844d3b42 2429 * @to: offset to write to
8593fbc6
TG		 2430 * @ops: oob operation description structure
2431 */
2432static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2433 struct mtd_oob_ops *ops)
2434{
8593fbc6
TG		 2435 struct nand_chip *chip = mtd->priv;
2436 int ret = -ENOTSUPP;
2437
2438 ops->retlen = 0;
2439
2440 /* Do not allow writes past end of device */
7014568b 2441 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2442 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2443 "end of device\n", __func__);
8593fbc6
TG		 2444 return -EINVAL;
2445 }
2446
7bc3312b 2447 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2448
f8ac0414 2449 switch (ops->mode) {
8593fbc6
TG		 2450 case MTD_OOB_PLACE:
2451 case MTD_OOB_AUTO:
8593fbc6 2452 case MTD_OOB_RAW:
8593fbc6
TG		 2453 break;
2454
2455 default:
2456 goto out;
2457 }
2458
2459 if (!ops->datbuf)
2460 ret = nand_do_write_oob(mtd, to, ops);
2461 else
2462 ret = nand_do_write_ops(mtd, to, ops);
2463
7351d3a5 2464out:
1da177e4 2465 nand_release_device(mtd);
1da177e4
LT		 2466 return ret;
2467}
2468
1da177e4
LT		 2469/**
2470 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2471 * @mtd: MTD device structure
2472 * @page: the page address of the block which will be erased
2473 *
2474 * Standard erase command for NAND chips
2475 */
e0c7d767 2476static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2477{
ace4dfee 2478 struct nand_chip *chip = mtd->priv;
1da177e4 2479 /* Send commands to erase a block */
ace4dfee
TG		 2480 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2481 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2482}
2483
2484/**
2485 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2486 * @mtd: MTD device structure
2487 * @page: the page address of the block which will be erased
2488 *
2489 * AND multi block erase command function
2490 * Erase 4 consecutive blocks
2491 */
e0c7d767 2492static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2493{
ace4dfee 2494 struct nand_chip *chip = mtd->priv;
1da177e4 2495 /* Send commands to erase a block */
ace4dfee
TG		 2496 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2497 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2498 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2499 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2500 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2501}
2502
2503/**
2504 * nand_erase - [MTD Interface] erase block(s)
2505 * @mtd: MTD device structure
2506 * @instr: erase instruction
2507 *
2508 * Erase one ore more blocks
2509 */
e0c7d767 2510static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2511{
e0c7d767 2512 return nand_erase_nand(mtd, instr, 0);
1da177e4 2513}
61b03bd7 2514
30f464b7 2515#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2516/**
ace4dfee 2517 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2518 * @mtd: MTD device structure
2519 * @instr: erase instruction
2520 * @allowbbt: allow erasing the bbt area
2521 *
2522 * Erase one ore more blocks
2523 */
ace4dfee
TG		 2524int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2525 int allowbbt)
1da177e4 2526{
69423d99 2527 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2528 struct nand_chip *chip = mtd->priv;
f8ac0414 2529 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2530 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2531 loff_t len;
1da177e4 2532
20d8e248 2533 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2534 __func__, (unsigned long long)instr->addr,
2535 (unsigned long long)instr->len);
1da177e4 2536
6fe5a6ac 2537 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2538 return -EINVAL;
1da177e4 2539
bb0eb217 2540 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2541
2542 /* Grab the lock and see if the device is available */
ace4dfee 2543 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2544
2545 /* Shift to get first page */
ace4dfee
TG		 2546 page = (int)(instr->addr >> chip->page_shift);
2547 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2548
2549 /* Calculate pages in each block */
ace4dfee 2550 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2551
2552 /* Select the NAND device */
ace4dfee 2553 chip->select_chip(mtd, chipnr);
1da177e4 2554
1da177e4
LT		 2555 /* Check, if it is write protected */
2556 if (nand_check_wp(mtd)) {
20d8e248 2557 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2558 __func__);
1da177e4
LT		 2559 instr->state = MTD_ERASE_FAILED;
2560 goto erase_exit;
2561 }
2562
ace4dfee
TG		 2563 /*
2564 * If BBT requires refresh, set the BBT page mask to see if the BBT
2565 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2566 * can not be matched. This is also done when the bbt is actually
2567 * erased to avoid recusrsive updates
2568 */
2569 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2570 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2571
1da177e4
LT		 2572 /* Loop through the pages */
2573 len = instr->len;
2574
2575 instr->state = MTD_ERASING;
2576
2577 while (len) {
ace4dfee
TG		 2578 /*
2579 * heck if we have a bad block, we do not erase bad blocks !
2580 */
2581 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2582 chip->page_shift, 0, allowbbt)) {
20d8e248 2583 printk(KERN_WARNING "%s: attempt to erase a bad block "
2584 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2585 instr->state = MTD_ERASE_FAILED;
2586 goto erase_exit;
2587 }
61b03bd7 2588
ace4dfee
TG		 2589 /*
2590 * Invalidate the page cache, if we erase the block which
2591 * contains the current cached page
2592 */
2593 if (page <= chip->pagebuf && chip->pagebuf <
2594 (page + pages_per_block))
2595 chip->pagebuf = -1;
1da177e4 2596
ace4dfee 2597 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2598
7bc3312b 2599 status = chip->waitfunc(mtd, chip);
1da177e4 2600
ace4dfee
TG		 2601 /*
2602 * See if operation failed and additional status checks are
2603 * available
2604 */
2605 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2606 status = chip->errstat(mtd, chip, FL_ERASING,
2607 status, page);
068e3c0a 2608
1da177e4 2609 /* See if block erase succeeded */
a4ab4c5d 2610 if (status & NAND_STATUS_FAIL) {
20d8e248 2611 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2612 "page 0x%08x\n", __func__, page);
1da177e4 2613 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2614 instr->fail_addr =
2615 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2616 goto erase_exit;
2617 }
30f464b7 2618
ace4dfee
TG		 2619 /*
2620 * If BBT requires refresh, set the BBT rewrite flag to the
2621 * page being erased
2622 */
2623 if (bbt_masked_page != 0xffffffff &&
2624 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2625 rewrite_bbt[chipnr] =
2626 ((loff_t)page << chip->page_shift);
61b03bd7 2627
1da177e4 2628 /* Increment page address and decrement length */
ace4dfee 2629 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2630 page += pages_per_block;
2631
2632 /* Check, if we cross a chip boundary */
ace4dfee 2633 if (len && !(page & chip->pagemask)) {
1da177e4 2634 chipnr++;
ace4dfee
TG		 2635 chip->select_chip(mtd, -1);
2636 chip->select_chip(mtd, chipnr);
30f464b7 2637
ace4dfee
TG		 2638 /*
2639 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2640 * page mask to see if this BBT should be rewritten
2641 */
2642 if (bbt_masked_page != 0xffffffff &&
2643 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2644 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2645 BBT_PAGE_MASK;
1da177e4
LT		 2646 }
2647 }
2648 instr->state = MTD_ERASE_DONE;
2649
7351d3a5 2650erase_exit:
1da177e4
LT		 2651
2652 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2653
2654 /* Deselect and wake up anyone waiting on the device */
2655 nand_release_device(mtd);
2656
49defc01
DW		 2657 /* Do call back function */
2658 if (!ret)
2659 mtd_erase_callback(instr);
2660
ace4dfee
TG		 2661 /*
2662 * If BBT requires refresh and erase was successful, rewrite any
2663 * selected bad block tables
2664 */
2665 if (bbt_masked_page == 0xffffffff || ret)
2666 return ret;
2667
2668 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2669 if (!rewrite_bbt[chipnr])
2670 continue;
2671 /* update the BBT for chip */
20d8e248 2672 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2673 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2674 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2675 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2676 }
2677
1da177e4
LT		 2678 /* Return more or less happy */
2679 return ret;
2680}
2681
2682/**
2683 * nand_sync - [MTD Interface] sync
2684 * @mtd: MTD device structure
2685 *
2686 * Sync is actually a wait for chip ready function
2687 */
e0c7d767 2688static void nand_sync(struct mtd_info *mtd)
1da177e4 2689{
ace4dfee 2690 struct nand_chip *chip = mtd->priv;
1da177e4 2691
20d8e248 2692 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2693
2694 /* Grab the lock and see if the device is available */
ace4dfee 2695 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2696 /* Release it and go back */
e0c7d767 2697 nand_release_device(mtd);
1da177e4
LT		 2698}
2699
1da177e4 2700/**
ace4dfee 2701 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2702 * @mtd: MTD device structure
844d3b42 2703 * @offs: offset relative to mtd start
1da177e4 2704 */
ace4dfee 2705static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2706{
2707 /* Check for invalid offset */
ace4dfee 2708 if (offs > mtd->size)
1da177e4 2709 return -EINVAL;
61b03bd7 2710
ace4dfee 2711 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2712}
2713
2714/**
ace4dfee 2715 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2716 * @mtd: MTD device structure
2717 * @ofs: offset relative to mtd start
2718 */
e0c7d767 2719static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2720{
ace4dfee 2721 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2722 int ret;
2723
f8ac0414
FF		 2724 ret = nand_block_isbad(mtd, ofs);
2725 if (ret) {
e0c7d767 2726 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2727 if (ret > 0)
2728 return 0;
e0c7d767
DW		 2729 return ret;
2730 }
1da177e4 2731
ace4dfee 2732 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2733}
2734
962034f4
VW		 2735/**
2736 * nand_suspend - [MTD Interface] Suspend the NAND flash
2737 * @mtd: MTD device structure
2738 */
2739static int nand_suspend(struct mtd_info *mtd)
2740{
ace4dfee 2741 struct nand_chip *chip = mtd->priv;
962034f4 2742
ace4dfee 2743 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2744}
2745
2746/**
2747 * nand_resume - [MTD Interface] Resume the NAND flash
2748 * @mtd: MTD device structure
2749 */
2750static void nand_resume(struct mtd_info *mtd)
2751{
ace4dfee 2752 struct nand_chip *chip = mtd->priv;
962034f4 2753
ace4dfee 2754 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2755 nand_release_device(mtd);
2756 else
20d8e248 2757 printk(KERN_ERR "%s called for a chip which is not "
2758 "in suspended state\n", __func__);
962034f4
VW		 2759}
2760
7aa65bfd
TG		 2761/*
2762 * Set default functions
2763 */
ace4dfee 2764static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2765{
1da177e4 2766 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2767 if (!chip->chip_delay)
2768 chip->chip_delay = 20;
1da177e4
LT		 2769
2770 /* check, if a user supplied command function given */
ace4dfee
TG		 2771 if (chip->cmdfunc == NULL)
2772 chip->cmdfunc = nand_command;
1da177e4
LT		 2773
2774 /* check, if a user supplied wait function given */
ace4dfee
TG		 2775 if (chip->waitfunc == NULL)
2776 chip->waitfunc = nand_wait;
2777
2778 if (!chip->select_chip)
2779 chip->select_chip = nand_select_chip;
2780 if (!chip->read_byte)
2781 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2782 if (!chip->read_word)
2783 chip->read_word = nand_read_word;
2784 if (!chip->block_bad)
2785 chip->block_bad = nand_block_bad;
2786 if (!chip->block_markbad)
2787 chip->block_markbad = nand_default_block_markbad;
2788 if (!chip->write_buf)
2789 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2790 if (!chip->read_buf)
2791 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2792 if (!chip->verify_buf)
2793 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2794 if (!chip->scan_bbt)
2795 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2796
2797 if (!chip->controller) {
2798 chip->controller = &chip->hwcontrol;
2799 spin_lock_init(&chip->controller->lock);
2800 init_waitqueue_head(&chip->controller->wq);
2801 }
2802
7aa65bfd
TG		 2803}
2804
d1e1f4e4
FF		 2805/*
2806 * sanitize ONFI strings so we can safely print them
2807 */
2808static void sanitize_string(uint8_t *s, size_t len)
2809{
2810 ssize_t i;
2811
2812 /* null terminate */
2813 s[len - 1] = 0;
2814
2815 /* remove non printable chars */
2816 for (i = 0; i < len - 1; i++) {
2817 if (s[i] < ' ' || s[i] > 127)
2818 s[i] = '?';
2819 }
2820
2821 /* remove trailing spaces */
2822 strim(s);
2823}
2824
2825static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2826{
2827 int i;
2828 while (len--) {
2829 crc ^= *p++ << 8;
2830 for (i = 0; i < 8; i++)
2831 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2832 }
2833
2834 return crc;
2835}
2836
6fb277ba
FF		 2837/*
2838 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2839 */
2840static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2841 int busw)
2842{
2843 struct nand_onfi_params *p = &chip->onfi_params;
2844 int i;
2845 int val;
2846
2847 /* try ONFI for unknow chip or LP */
2848 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2849 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2850 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2851 return 0;
2852
2853 printk(KERN_INFO "ONFI flash detected\n");
2854 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2855 for (i = 0; i < 3; i++) {
2856 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2857 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2858 le16_to_cpu(p->crc)) {
2859 printk(KERN_INFO "ONFI param page %d valid\n", i);
2860 break;
2861 }
2862 }
2863
2864 if (i == 3)
2865 return 0;
2866
2867 /* check version */
2868 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2869 if (val & (1 << 5))
2870 chip->onfi_version = 23;
2871 else if (val & (1 << 4))
6fb277ba
FF		 2872 chip->onfi_version = 22;
2873 else if (val & (1 << 3))
2874 chip->onfi_version = 21;
2875 else if (val & (1 << 2))
2876 chip->onfi_version = 20;
b7b1a29d 2877 else if (val & (1 << 1))
6fb277ba 2878 chip->onfi_version = 10;
b7b1a29d
BN		 2879 else
2880 chip->onfi_version = 0;
2881
2882 if (!chip->onfi_version) {
2883 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2884 __func__, val);
2885 return 0;
2886 }
6fb277ba
FF		 2887
2888 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2889 sanitize_string(p->model, sizeof(p->model));
2890 if (!mtd->name)
2891 mtd->name = p->model;
2892 mtd->writesize = le32_to_cpu(p->byte_per_page);
2893 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2894 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4ccb3b44 2895 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
6fb277ba
FF		 2896 busw = 0;
2897 if (le16_to_cpu(p->features) & 1)
2898 busw = NAND_BUSWIDTH_16;
2899
2900 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2901 chip->options |= (NAND_NO_READRDY |
2902 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2903
2904 return 1;
2905}
2906
7aa65bfd 2907/*
ace4dfee 2908 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2909 */
2910static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2911 struct nand_chip *chip,
7351d3a5
FF		 2912 int busw,
2913 int *maf_id, int *dev_id,
5e81e88a 2914 struct nand_flash_dev *type)
7aa65bfd 2915{
d1e1f4e4 2916 int i, maf_idx;
426c457a 2917 u8 id_data[8];
6fb277ba 2918 int ret;
1da177e4
LT		 2919
2920 /* Select the device */
ace4dfee 2921 chip->select_chip(mtd, 0);
1da177e4 2922
ef89a880
KB		 2923 /*
2924 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2925 * after power-up
2926 */
2927 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2928
1da177e4 2929 /* Send the command for reading device ID */
ace4dfee 2930 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2931
2932 /* Read manufacturer and device IDs */
ace4dfee 2933 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2934 *dev_id = chip->read_byte(mtd);
1da177e4 2935
ed8165c7
BD		 2936 /* Try again to make sure, as some systems the bus-hold or other
2937 * interface concerns can cause random data which looks like a
2938 * possibly credible NAND flash to appear. If the two results do
2939 * not match, ignore the device completely.
2940 */
2941
2942 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2943
d1e1f4e4 2944 for (i = 0; i < 2; i++)
426c457a 2945 id_data[i] = chip->read_byte(mtd);
ed8165c7 2946
d1e1f4e4 2947 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
ed8165c7
BD		 2948 printk(KERN_INFO "%s: second ID read did not match "
2949 "%02x,%02x against %02x,%02x\n", __func__,
d1e1f4e4 2950 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2951 return ERR_PTR(-ENODEV);
2952 }
2953
7aa65bfd 2954 if (!type)
5e81e88a
DW		 2955 type = nand_flash_ids;
2956
2957 for (; type->name != NULL; type++)
d1e1f4e4 2958 if (*dev_id == type->id)
f8ac0414 2959 break;
5e81e88a 2960
d1e1f4e4
FF		 2961 chip->onfi_version = 0;
2962 if (!type->name || !type->pagesize) {
6fb277ba
FF		 2963 /* Check is chip is ONFI compliant */
2964 ret = nand_flash_detect_onfi(mtd, chip, busw);
2965 if (ret)
2966 goto ident_done;
d1e1f4e4
FF		 2967 }
2968
2969 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2970
2971 /* Read entire ID string */
2972
2973 for (i = 0; i < 8; i++)
2974 id_data[i] = chip->read_byte(mtd);
2975
5e81e88a 2976 if (!type->name)
7aa65bfd
TG		 2977 return ERR_PTR(-ENODEV);
2978
ba0251fe
TG		 2979 if (!mtd->name)
2980 mtd->name = type->name;
2981
69423d99 2982 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2983
12a40a57
HS		 2984 if (!type->pagesize && chip->init_size) {
2985 /* set the pagesize, oobsize, erasesize by the driver*/
2986 busw = chip->init_size(mtd, chip, id_data);
2987 } else if (!type->pagesize) {
7aa65bfd 2988 int extid;
29072b96 2989 /* The 3rd id byte holds MLC / multichip data */
426c457a 2990 chip->cellinfo = id_data[2];
7aa65bfd 2991 /* The 4th id byte is the important one */
426c457a 2992 extid = id_data[3];
61b03bd7 2993
426c457a
KC		 2994 /*
2995 * Field definitions are in the following datasheets:
2996 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2997 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 2998 *
2999 * Check for wraparound + Samsung ID + nonzero 6th byte
3000 * to decide what to do.
3001 */
3002 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3003 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3004 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3005 id_data[5] != 0x00) {
3006 /* Calc pagesize */
3007 mtd->writesize = 2048 << (extid & 0x03);
3008 extid >>= 2;
3009 /* Calc oobsize */
34c5bf6c
BN		 3010 switch (extid & 0x03) {
3011 case 1:
3012 mtd->oobsize = 128;
3013 break;
3014 case 2:
3015 mtd->oobsize = 218;
3016 break;
3017 case 3:
3018 mtd->oobsize = 400;
3019 break;
3020 default:
3021 mtd->oobsize = 436;
3022 break;
3023 }
426c457a
KC		 3024 extid >>= 2;
3025 /* Calc blocksize */
3026 mtd->erasesize = (128 * 1024) <<
3027 (((extid >> 1) & 0x04) | (extid & 0x03));
3028 busw = 0;
3029 } else {
3030 /* Calc pagesize */
3031 mtd->writesize = 1024 << (extid & 0x03);
3032 extid >>= 2;
3033 /* Calc oobsize */
3034 mtd->oobsize = (8 << (extid & 0x01)) *
3035 (mtd->writesize >> 9);
3036 extid >>= 2;
3037 /* Calc blocksize. Blocksize is multiples of 64KiB */
3038 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3039 extid >>= 2;
3040 /* Get buswidth information */
3041 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3042 }
7aa65bfd
TG		 3043 } else {
3044 /*
ace4dfee 3045 * Old devices have chip data hardcoded in the device id table
7aa65bfd 3046 */
ba0251fe
TG		 3047 mtd->erasesize = type->erasesize;
3048 mtd->writesize = type->pagesize;
4cbb9b80 3049 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3050 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3051
3052 /*
3053 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3054 * some Spansion chips have erasesize that conflicts with size
3055 * listed in nand_ids table
3056 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3057 */
3058 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3059 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3060 id_data[7] == 0x00 && mtd->writesize == 512) {
3061 mtd->erasesize = 128 * 1024;
3062 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3063 }
7aa65bfd 3064 }
d1e1f4e4
FF		 3065 /* Get chip options, preserve non chip based options */
3066 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3067 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3068
3069 /* Check if chip is a not a samsung device. Do not clear the
3070 * options for chips which are not having an extended id.
3071 */
3072 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3073 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3074ident_done:
3075
3076 /*
3077 * Set chip as a default. Board drivers can override it, if necessary
3078 */
3079 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3080
7aa65bfd 3081 /* Try to identify manufacturer */
9a909867 3082 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3083 if (nand_manuf_ids[maf_idx].id == *maf_id)
3084 break;
3085 }
0ea4a755 3086
7aa65bfd
TG		 3087 /*
3088 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 3089 * chip correct !
7aa65bfd 3090 */
ace4dfee 3091 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 3092 printk(KERN_INFO "NAND device: Manufacturer ID:"
3093 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
d1e1f4e4 3094 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
7aa65bfd 3095 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 3096 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 3097 busw ? 16 : 8);
3098 return ERR_PTR(-EINVAL);
3099 }
61b03bd7 3100
7aa65bfd 3101 /* Calculate the address shift from the page size */
ace4dfee 3102 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 3103 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 3104 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3105
ace4dfee 3106 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3107 ffs(mtd->erasesize) - 1;
69423d99
AH		 3108 if (chip->chipsize & 0xffffffff)
3109 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3110 else {
3111 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3112 chip->chip_shift += 32 - 1;
3113 }
1da177e4 3114
7aa65bfd 3115 /* Set the bad block position */
065a1ed8 3116 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3117 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3118 else
3119 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3120
b60b08b0
KC		 3121 /*
3122 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3123 * on Samsung and Hynix MLC devices; stored in first two pages
3124 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3125 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3126 * only the first page.
b60b08b0
KC		 3127 */
3128 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3129 (*maf_id == NAND_MFR_SAMSUNG ||
3130 *maf_id == NAND_MFR_HYNIX))
30fe8115 3131 chip->options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3132 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3133 (*maf_id == NAND_MFR_SAMSUNG ||
3134 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3135 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3136 *maf_id == NAND_MFR_AMD)) ||
3137 (mtd->writesize == 2048 &&
3138 *maf_id == NAND_MFR_MICRON))
3139 chip->options |= NAND_BBT_SCAN2NDPAGE;
3140
58373ff0
BN		 3141 /*
3142 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3143 */
3144 if (!(busw & NAND_BUSWIDTH_16) &&
3145 *maf_id == NAND_MFR_STMICRO &&
3146 mtd->writesize == 2048) {
3147 chip->options |= NAND_BBT_SCANBYTE1AND6;
3148 chip->badblockpos = 0;
3149 }
b60b08b0 3150
7aa65bfd 3151 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3152 if (chip->options & NAND_4PAGE_ARRAY)
3153 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3154 else
ace4dfee 3155 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 3156
3157 /* Do not replace user supplied command function ! */
ace4dfee
TG		 3158 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3159 chip->cmdfunc = nand_command_lp;
7aa65bfd 3160
d1e1f4e4 3161 /* TODO onfi flash name */
7aa65bfd 3162 printk(KERN_INFO "NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3163 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3164 nand_manuf_ids[maf_idx].name,
0b524fb9 3165 chip->onfi_version ? chip->onfi_params.model : type->name);
7aa65bfd
TG		 3166
3167 return type;
3168}
3169
7aa65bfd 3170/**
3b85c321
DW		 3171 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3172 * @mtd: MTD device structure
3173 * @maxchips: Number of chips to scan for
5e81e88a 3174 * @table: Alternative NAND ID table
7aa65bfd 3175 *
3b85c321
DW		 3176 * This is the first phase of the normal nand_scan() function. It
3177 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 3178 *
3b85c321 3179 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3180 */
5e81e88a
DW		 3181int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3182 struct nand_flash_dev *table)
7aa65bfd 3183{
d1e1f4e4 3184 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3185 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3186 struct nand_flash_dev *type;
3187
7aa65bfd 3188 /* Get buswidth to select the correct functions */
ace4dfee 3189 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3190 /* Set the default functions */
ace4dfee 3191 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3192
3193 /* Read the flash type */
7351d3a5
FF		 3194 type = nand_get_flash_type(mtd, chip, busw,
3195 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3196
3197 if (IS_ERR(type)) {
b1c6e6db
BD		 3198 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3199 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 3200 chip->select_chip(mtd, -1);
7aa65bfd 3201 return PTR_ERR(type);
1da177e4
LT		 3202 }
3203
7aa65bfd 3204 /* Check for a chip array */
e0c7d767 3205 for (i = 1; i < maxchips; i++) {
ace4dfee 3206 chip->select_chip(mtd, i);
ef89a880
KB		 3207 /* See comment in nand_get_flash_type for reset */
3208 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3209 /* Send the command for reading device ID */
ace4dfee 3210 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3211 /* Read manufacturer and device IDs */
ace4dfee 3212 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3213 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3214 break;
3215 }
3216 if (i > 1)
3217 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 3218
1da177e4 3219 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3220 chip->numchips = i;
3221 mtd->size = i * chip->chipsize;
7aa65bfd 3222
3b85c321
DW		 3223 return 0;
3224}
7351d3a5 3225EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3226
3227
3228/**
3229 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3230 * @mtd: MTD device structure
3b85c321
DW		 3231 *
3232 * This is the second phase of the normal nand_scan() function. It
3233 * fills out all the uninitialized function pointers with the defaults
3234 * and scans for a bad block table if appropriate.
3235 */
3236int nand_scan_tail(struct mtd_info *mtd)
3237{
3238 int i;
3239 struct nand_chip *chip = mtd->priv;
3240
4bf63fcb
DW		 3241 if (!(chip->options & NAND_OWN_BUFFERS))
3242 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3243 if (!chip->buffers)
3244 return -ENOMEM;
3245
7dcdcbef 3246 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3247 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3248
7aa65bfd
TG		 3249 /*
3250 * If no default placement scheme is given, select an appropriate one
3251 */
193bd400 3252 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3253 switch (mtd->oobsize) {
1da177e4 3254 case 8:
5bd34c09 3255 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3256 break;
3257 case 16:
5bd34c09 3258 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3259 break;
3260 case 64:
5bd34c09 3261 chip->ecc.layout = &nand_oob_64;
1da177e4 3262 break;
81ec5364
TG		 3263 case 128:
3264 chip->ecc.layout = &nand_oob_128;
3265 break;
1da177e4 3266 default:
7aa65bfd
TG		 3267 printk(KERN_WARNING "No oob scheme defined for "
3268 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3269 BUG();
3270 }
3271 }
61b03bd7 3272
956e944c
DW		 3273 if (!chip->write_page)
3274 chip->write_page = nand_write_page;
3275
61b03bd7 3276 /*
7aa65bfd
TG		 3277 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3278 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3279 */
956e944c 3280
ace4dfee 3281 switch (chip->ecc.mode) {
6e0cb135
SN		 3282 case NAND_ECC_HW_OOB_FIRST:
3283 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3284 if (!chip->ecc.calculate || !chip->ecc.correct ||
3285 !chip->ecc.hwctl) {
3286 printk(KERN_WARNING "No ECC functions supplied; "
3287 "Hardware ECC not possible\n");
3288 BUG();
3289 }
3290 if (!chip->ecc.read_page)
3291 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3292
6dfc6d25 3293 case NAND_ECC_HW:
f5bbdacc
TG		 3294 /* Use standard hwecc read page function ? */
3295 if (!chip->ecc.read_page)
3296 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3297 if (!chip->ecc.write_page)
3298 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3299 if (!chip->ecc.read_page_raw)
3300 chip->ecc.read_page_raw = nand_read_page_raw;
3301 if (!chip->ecc.write_page_raw)
3302 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3303 if (!chip->ecc.read_oob)
3304 chip->ecc.read_oob = nand_read_oob_std;
3305 if (!chip->ecc.write_oob)
3306 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3307
6dfc6d25 3308 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3309 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3310 !chip->ecc.hwctl) &&
3311 (!chip->ecc.read_page ||
1c45f604 3312 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3313 !chip->ecc.write_page ||
1c45f604 3314 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3315 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3316 "Hardware ECC not possible\n");
3317 BUG();
3318 }
f75e5097 3319 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 3320 if (!chip->ecc.read_page)
3321 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3322 if (!chip->ecc.write_page)
3323 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3324 if (!chip->ecc.read_page_raw)
3325 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3326 if (!chip->ecc.write_page_raw)
3327 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3328 if (!chip->ecc.read_oob)
3329 chip->ecc.read_oob = nand_read_oob_syndrome;
3330 if (!chip->ecc.write_oob)
3331 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3332
ace4dfee 3333 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3334 break;
3335 printk(KERN_WARNING "%d byte HW ECC not possible on "
3336 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3337 chip->ecc.size, mtd->writesize);
3338 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3339
6dfc6d25 3340 case NAND_ECC_SOFT:
ace4dfee
TG		 3341 chip->ecc.calculate = nand_calculate_ecc;
3342 chip->ecc.correct = nand_correct_data;
f5bbdacc 3343 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3344 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3345 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3346 chip->ecc.read_page_raw = nand_read_page_raw;
3347 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3348 chip->ecc.read_oob = nand_read_oob_std;
3349 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3350 if (!chip->ecc.size)
3351 chip->ecc.size = 256;
ace4dfee 3352 chip->ecc.bytes = 3;
1da177e4 3353 break;
61b03bd7 3354
193bd400
ID		 3355 case NAND_ECC_SOFT_BCH:
3356 if (!mtd_nand_has_bch()) {
3357 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3358 BUG();
3359 }
3360 chip->ecc.calculate = nand_bch_calculate_ecc;
3361 chip->ecc.correct = nand_bch_correct_data;
3362 chip->ecc.read_page = nand_read_page_swecc;
3363 chip->ecc.read_subpage = nand_read_subpage;
3364 chip->ecc.write_page = nand_write_page_swecc;
3365 chip->ecc.read_page_raw = nand_read_page_raw;
3366 chip->ecc.write_page_raw = nand_write_page_raw;
3367 chip->ecc.read_oob = nand_read_oob_std;
3368 chip->ecc.write_oob = nand_write_oob_std;
3369 /*
3370 * Board driver should supply ecc.size and ecc.bytes values to
3371 * select how many bits are correctable; see nand_bch_init()
3372 * for details.
3373 * Otherwise, default to 4 bits for large page devices
3374 */
3375 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3376 chip->ecc.size = 512;
3377 chip->ecc.bytes = 7;
3378 }
3379 chip->ecc.priv = nand_bch_init(mtd,
3380 chip->ecc.size,
3381 chip->ecc.bytes,
3382 &chip->ecc.layout);
3383 if (!chip->ecc.priv) {
3384 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3385 BUG();
3386 }
3387 break;
3388
61b03bd7 3389 case NAND_ECC_NONE:
7aa65bfd
TG		 3390 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3391 "This is not recommended !!\n");
8593fbc6
TG		 3392 chip->ecc.read_page = nand_read_page_raw;
3393 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3394 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3395 chip->ecc.read_page_raw = nand_read_page_raw;
3396 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3397 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3398 chip->ecc.size = mtd->writesize;
3399 chip->ecc.bytes = 0;
1da177e4 3400 break;
956e944c 3401
1da177e4 3402 default:
7aa65bfd 3403 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3404 chip->ecc.mode);
61b03bd7 3405 BUG();
1da177e4 3406 }
61b03bd7 3407
5bd34c09
TG		 3408 /*
3409 * The number of bytes available for a client to place data into
3410 * the out of band area
3411 */
3412 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3413 for (i = 0; chip->ecc.layout->oobfree[i].length
3414 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3415 chip->ecc.layout->oobavail +=
3416 chip->ecc.layout->oobfree[i].length;
1f92267c 3417 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3418
7aa65bfd
TG		 3419 /*
3420 * Set the number of read / write steps for one page depending on ECC
3421 * mode
3422 */
ace4dfee 3423 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3424 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 3425 printk(KERN_WARNING "Invalid ecc parameters\n");
3426 BUG();
1da177e4 3427 }
f5bbdacc 3428 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3429
29072b96
TG		 3430 /*
3431 * Allow subpage writes up to ecc.steps. Not possible for MLC
3432 * FLASH.
3433 */
3434 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3435 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3436 switch (chip->ecc.steps) {
29072b96
TG		 3437 case 2:
3438 mtd->subpage_sft = 1;
3439 break;
3440 case 4:
3441 case 8:
81ec5364 3442 case 16:
29072b96
TG		 3443 mtd->subpage_sft = 2;
3444 break;
3445 }
3446 }
3447 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3448
04bbd0ea 3449 /* Initialize state */
ace4dfee 3450 chip->state = FL_READY;
1da177e4
LT		 3451
3452 /* De-select the device */
ace4dfee 3453 chip->select_chip(mtd, -1);
1da177e4
LT		 3454
3455 /* Invalidate the pagebuffer reference */
ace4dfee 3456 chip->pagebuf = -1;
1da177e4
LT		 3457
3458 /* Fill in remaining MTD driver data */
3459 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3460 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3461 MTD_CAP_NANDFLASH;
1da177e4
LT		 3462 mtd->erase = nand_erase;
3463 mtd->point = NULL;
3464 mtd->unpoint = NULL;
3465 mtd->read = nand_read;
3466 mtd->write = nand_write;
2af7c653 3467 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3468 mtd->read_oob = nand_read_oob;
3469 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3470 mtd->sync = nand_sync;
3471 mtd->lock = NULL;
3472 mtd->unlock = NULL;
962034f4
VW		 3473 mtd->suspend = nand_suspend;
3474 mtd->resume = nand_resume;
1da177e4
LT		 3475 mtd->block_isbad = nand_block_isbad;
3476 mtd->block_markbad = nand_block_markbad;
cbcab65a 3477 mtd->writebufsize = mtd->writesize;
1da177e4 3478
5bd34c09
TG		 3479 /* propagate ecc.layout to mtd_info */
3480 mtd->ecclayout = chip->ecc.layout;
1da177e4 3481
0040bf38 3482 /* Check, if we should skip the bad block table scan */
ace4dfee 3483 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3484 return 0;
1da177e4
LT		 3485
3486 /* Build bad block table */
ace4dfee 3487 return chip->scan_bbt(mtd);
1da177e4 3488}
7351d3a5 3489EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3490
a6e6abd5 3491/* is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5
FF		 3492 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3493 * to call us from in-kernel code if the core NAND support is modular. */
3b85c321
DW		 3494#ifdef MODULE
3495#define caller_is_module() (1)
3496#else
3497#define caller_is_module() \
a6e6abd5 3498 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3499#endif
3500
3501/**
3502 * nand_scan - [NAND Interface] Scan for the NAND device
3503 * @mtd: MTD device structure
3504 * @maxchips: Number of chips to scan for
3505 *
3506 * This fills out all the uninitialized function pointers
3507 * with the defaults.
3508 * The flash ID is read and the mtd/chip structures are
3509 * filled with the appropriate values.
3510 * The mtd->owner field must be set to the module of the caller
3511 *
3512 */
3513int nand_scan(struct mtd_info *mtd, int maxchips)
3514{
3515 int ret;
3516
3517 /* Many callers got this wrong, so check for it for a while... */
3518 if (!mtd->owner && caller_is_module()) {
20d8e248 3519 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3520 __func__);
3b85c321
DW		 3521 BUG();
3522 }
3523
5e81e88a 3524 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3525 if (!ret)
3526 ret = nand_scan_tail(mtd);
3527 return ret;
3528}
7351d3a5 3529EXPORT_SYMBOL(nand_scan);
3b85c321 3530
1da177e4 3531/**
61b03bd7 3532 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3533 * @mtd: MTD device structure
3534*/
e0c7d767 3535void nand_release(struct mtd_info *mtd)
1da177e4 3536{
ace4dfee 3537 struct nand_chip *chip = mtd->priv;
1da177e4 3538
193bd400
ID		 3539 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3540 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3541
1da177e4
LT		 3542#ifdef CONFIG_MTD_PARTITIONS
3543 /* Deregister partitions */
e0c7d767 3544 del_mtd_partitions(mtd);
1da177e4
LT		 3545#endif
3546 /* Deregister the device */
e0c7d767 3547 del_mtd_device(mtd);
1da177e4 3548
fa671646 3549 /* Free bad block table memory */
ace4dfee 3550 kfree(chip->bbt);
4bf63fcb
DW		 3551 if (!(chip->options & NAND_OWN_BUFFERS))
3552 kfree(chip->buffers);
58373ff0
BN		 3553
3554 /* Free bad block descriptor memory */
3555 if (chip->badblock_pattern && chip->badblock_pattern->options
3556 & NAND_BBT_DYNAMICSTRUCT)
3557 kfree(chip->badblock_pattern);
1da177e4 3558}
e0c7d767 3559EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3560
3561static int __init nand_base_init(void)
3562{
3563 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3564 return 0;
3565}
3566
3567static void __exit nand_base_exit(void)
3568{
3569 led_trigger_unregister_simple(nand_led_trigger);
3570}
3571
3572module_init(nand_base_init);
3573module_exit(nand_base_exit);
3574
e0c7d767 3575MODULE_LICENSE("GPL");
7351d3a5
FF		 3576MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3577MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3578MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)