Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
38b8d208 | 39 | #include <linux/nmi.h> |
1da177e4 LT |
40 | #include <linux/types.h> |
41 | #include <linux/mtd/mtd.h> | |
d4092d76 | 42 | #include <linux/mtd/rawnand.h> |
1da177e4 | 43 | #include <linux/mtd/nand_ecc.h> |
193bd400 | 44 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
45 | #include <linux/interrupt.h> |
46 | #include <linux/bitops.h> | |
7351d3a5 | 47 | #include <linux/io.h> |
1da177e4 | 48 | #include <linux/mtd/partitions.h> |
d48f62b9 | 49 | #include <linux/of.h> |
1da177e4 | 50 | |
41b207a7 BB |
51 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
52 | ||
53 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, | |
54 | struct mtd_oob_ops *ops); | |
1da177e4 LT |
55 | |
56 | /* Define default oob placement schemes for large and small page devices */ | |
41b207a7 BB |
57 | static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, |
58 | struct mtd_oob_region *oobregion) | |
59 | { | |
60 | struct nand_chip *chip = mtd_to_nand(mtd); | |
61 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 62 | |
41b207a7 BB |
63 | if (section > 1) |
64 | return -ERANGE; | |
1da177e4 | 65 | |
41b207a7 BB |
66 | if (!section) { |
67 | oobregion->offset = 0; | |
f7f8c175 MR |
68 | if (mtd->oobsize == 16) |
69 | oobregion->length = 4; | |
70 | else | |
71 | oobregion->length = 3; | |
41b207a7 | 72 | } else { |
f7f8c175 MR |
73 | if (mtd->oobsize == 8) |
74 | return -ERANGE; | |
75 | ||
41b207a7 BB |
76 | oobregion->offset = 6; |
77 | oobregion->length = ecc->total - 4; | |
78 | } | |
1da177e4 | 79 | |
41b207a7 BB |
80 | return 0; |
81 | } | |
82 | ||
83 | static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, | |
84 | struct mtd_oob_region *oobregion) | |
85 | { | |
86 | if (section > 1) | |
87 | return -ERANGE; | |
1da177e4 | 88 | |
41b207a7 BB |
89 | if (mtd->oobsize == 16) { |
90 | if (section) | |
91 | return -ERANGE; | |
92 | ||
93 | oobregion->length = 8; | |
94 | oobregion->offset = 8; | |
95 | } else { | |
96 | oobregion->length = 2; | |
97 | if (!section) | |
98 | oobregion->offset = 3; | |
99 | else | |
100 | oobregion->offset = 6; | |
101 | } | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { | |
107 | .ecc = nand_ooblayout_ecc_sp, | |
108 | .free = nand_ooblayout_free_sp, | |
81ec5364 | 109 | }; |
41b207a7 | 110 | EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); |
81ec5364 | 111 | |
41b207a7 BB |
112 | static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, |
113 | struct mtd_oob_region *oobregion) | |
114 | { | |
115 | struct nand_chip *chip = mtd_to_nand(mtd); | |
116 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 117 | |
882fd157 | 118 | if (section || !ecc->total) |
41b207a7 | 119 | return -ERANGE; |
8593fbc6 | 120 | |
41b207a7 BB |
121 | oobregion->length = ecc->total; |
122 | oobregion->offset = mtd->oobsize - oobregion->length; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, | |
128 | struct mtd_oob_region *oobregion) | |
129 | { | |
130 | struct nand_chip *chip = mtd_to_nand(mtd); | |
131 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
132 | ||
133 | if (section) | |
134 | return -ERANGE; | |
135 | ||
136 | oobregion->length = mtd->oobsize - ecc->total - 2; | |
137 | oobregion->offset = 2; | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { | |
143 | .ecc = nand_ooblayout_ecc_lp, | |
144 | .free = nand_ooblayout_free_lp, | |
145 | }; | |
146 | EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); | |
d470a97c | 147 | |
6a623e07 AC |
148 | /* |
149 | * Support the old "large page" layout used for 1-bit Hamming ECC where ECC | |
150 | * are placed at a fixed offset. | |
151 | */ | |
152 | static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, | |
153 | struct mtd_oob_region *oobregion) | |
154 | { | |
155 | struct nand_chip *chip = mtd_to_nand(mtd); | |
156 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
157 | ||
158 | if (section) | |
159 | return -ERANGE; | |
160 | ||
161 | switch (mtd->oobsize) { | |
162 | case 64: | |
163 | oobregion->offset = 40; | |
164 | break; | |
165 | case 128: | |
166 | oobregion->offset = 80; | |
167 | break; | |
168 | default: | |
169 | return -EINVAL; | |
170 | } | |
171 | ||
172 | oobregion->length = ecc->total; | |
173 | if (oobregion->offset + oobregion->length > mtd->oobsize) | |
174 | return -ERANGE; | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, | |
180 | struct mtd_oob_region *oobregion) | |
181 | { | |
182 | struct nand_chip *chip = mtd_to_nand(mtd); | |
183 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
184 | int ecc_offset = 0; | |
185 | ||
186 | if (section < 0 || section > 1) | |
187 | return -ERANGE; | |
188 | ||
189 | switch (mtd->oobsize) { | |
190 | case 64: | |
191 | ecc_offset = 40; | |
192 | break; | |
193 | case 128: | |
194 | ecc_offset = 80; | |
195 | break; | |
196 | default: | |
197 | return -EINVAL; | |
198 | } | |
199 | ||
200 | if (section == 0) { | |
201 | oobregion->offset = 2; | |
202 | oobregion->length = ecc_offset - 2; | |
203 | } else { | |
204 | oobregion->offset = ecc_offset + ecc->total; | |
205 | oobregion->length = mtd->oobsize - oobregion->offset; | |
206 | } | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
d4ed3b90 | 211 | static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { |
6a623e07 AC |
212 | .ecc = nand_ooblayout_ecc_lp_hamming, |
213 | .free = nand_ooblayout_free_lp_hamming, | |
214 | }; | |
215 | ||
6fe5a6ac VS |
216 | static int check_offs_len(struct mtd_info *mtd, |
217 | loff_t ofs, uint64_t len) | |
218 | { | |
862eba51 | 219 | struct nand_chip *chip = mtd_to_nand(mtd); |
6fe5a6ac VS |
220 | int ret = 0; |
221 | ||
222 | /* Start address must align on block boundary */ | |
daae74ca | 223 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 224 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
225 | ret = -EINVAL; |
226 | } | |
227 | ||
228 | /* Length must align on block boundary */ | |
daae74ca | 229 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 230 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
231 | ret = -EINVAL; |
232 | } | |
233 | ||
6fe5a6ac VS |
234 | return ret; |
235 | } | |
236 | ||
1da177e4 LT |
237 | /** |
238 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 239 | * @mtd: MTD device structure |
61b03bd7 | 240 | * |
b0bb6903 | 241 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 242 | */ |
e0c7d767 | 243 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 244 | { |
862eba51 | 245 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 246 | |
a36ed299 | 247 | /* Release the controller and the chip */ |
ace4dfee TG |
248 | spin_lock(&chip->controller->lock); |
249 | chip->controller->active = NULL; | |
250 | chip->state = FL_READY; | |
251 | wake_up(&chip->controller->wq); | |
252 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
253 | } |
254 | ||
255 | /** | |
256 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 257 | * @mtd: MTD device structure |
1da177e4 | 258 | * |
7854d3f7 | 259 | * Default read function for 8bit buswidth |
1da177e4 | 260 | */ |
58dd8f2b | 261 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 262 | { |
862eba51 | 263 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 264 | return readb(chip->IO_ADDR_R); |
1da177e4 LT |
265 | } |
266 | ||
1da177e4 | 267 | /** |
7854d3f7 | 268 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 269 | * @mtd: MTD device structure |
1da177e4 | 270 | * |
7854d3f7 BN |
271 | * Default read function for 16bit buswidth with endianness conversion. |
272 | * | |
1da177e4 | 273 | */ |
58dd8f2b | 274 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 275 | { |
862eba51 | 276 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 277 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 282 | * @mtd: MTD device structure |
1da177e4 | 283 | * |
7854d3f7 | 284 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
285 | */ |
286 | static u16 nand_read_word(struct mtd_info *mtd) | |
287 | { | |
862eba51 | 288 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 289 | return readw(chip->IO_ADDR_R); |
1da177e4 LT |
290 | } |
291 | ||
1da177e4 LT |
292 | /** |
293 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
294 | * @mtd: MTD device structure |
295 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
296 | * |
297 | * Default select function for 1 chip devices. | |
298 | */ | |
ace4dfee | 299 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 300 | { |
862eba51 | 301 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
302 | |
303 | switch (chipnr) { | |
1da177e4 | 304 | case -1: |
ace4dfee | 305 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
306 | break; |
307 | case 0: | |
1da177e4 LT |
308 | break; |
309 | ||
310 | default: | |
311 | BUG(); | |
312 | } | |
313 | } | |
314 | ||
05f78359 UKK |
315 | /** |
316 | * nand_write_byte - [DEFAULT] write single byte to chip | |
317 | * @mtd: MTD device structure | |
318 | * @byte: value to write | |
319 | * | |
320 | * Default function to write a byte to I/O[7:0] | |
321 | */ | |
322 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
323 | { | |
862eba51 | 324 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
325 | |
326 | chip->write_buf(mtd, &byte, 1); | |
327 | } | |
328 | ||
329 | /** | |
330 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
331 | * @mtd: MTD device structure | |
332 | * @byte: value to write | |
333 | * | |
334 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
335 | */ | |
336 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
337 | { | |
862eba51 | 338 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
339 | uint16_t word = byte; |
340 | ||
341 | /* | |
342 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
343 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
344 | * | |
345 | * When the host supports a 16-bit bus width, only data is | |
346 | * transferred at the 16-bit width. All address and command line | |
347 | * transfers shall use only the lower 8-bits of the data bus. During | |
348 | * command transfers, the host may place any value on the upper | |
349 | * 8-bits of the data bus. During address transfers, the host shall | |
350 | * set the upper 8-bits of the data bus to 00h. | |
351 | * | |
352 | * One user of the write_byte callback is nand_onfi_set_features. The | |
353 | * four parameters are specified to be written to I/O[7:0], but this is | |
354 | * neither an address nor a command transfer. Let's assume a 0 on the | |
355 | * upper I/O lines is OK. | |
356 | */ | |
357 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
358 | } | |
359 | ||
1da177e4 LT |
360 | /** |
361 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
362 | * @mtd: MTD device structure |
363 | * @buf: data buffer | |
364 | * @len: number of bytes to write | |
1da177e4 | 365 | * |
7854d3f7 | 366 | * Default write function for 8bit buswidth. |
1da177e4 | 367 | */ |
58dd8f2b | 368 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 369 | { |
862eba51 | 370 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 371 | |
76413839 | 372 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
373 | } |
374 | ||
375 | /** | |
61b03bd7 | 376 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
377 | * @mtd: MTD device structure |
378 | * @buf: buffer to store date | |
379 | * @len: number of bytes to read | |
1da177e4 | 380 | * |
7854d3f7 | 381 | * Default read function for 8bit buswidth. |
1da177e4 | 382 | */ |
58dd8f2b | 383 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 384 | { |
862eba51 | 385 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 386 | |
76413839 | 387 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
388 | } |
389 | ||
1da177e4 LT |
390 | /** |
391 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
392 | * @mtd: MTD device structure |
393 | * @buf: data buffer | |
394 | * @len: number of bytes to write | |
1da177e4 | 395 | * |
7854d3f7 | 396 | * Default write function for 16bit buswidth. |
1da177e4 | 397 | */ |
58dd8f2b | 398 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 399 | { |
862eba51 | 400 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 401 | u16 *p = (u16 *) buf; |
61b03bd7 | 402 | |
76413839 | 403 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
404 | } |
405 | ||
406 | /** | |
61b03bd7 | 407 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
408 | * @mtd: MTD device structure |
409 | * @buf: buffer to store date | |
410 | * @len: number of bytes to read | |
1da177e4 | 411 | * |
7854d3f7 | 412 | * Default read function for 16bit buswidth. |
1da177e4 | 413 | */ |
58dd8f2b | 414 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 415 | { |
862eba51 | 416 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 417 | u16 *p = (u16 *) buf; |
1da177e4 | 418 | |
76413839 | 419 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
420 | } |
421 | ||
1da177e4 LT |
422 | /** |
423 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
424 | * @mtd: MTD device structure |
425 | * @ofs: offset from device start | |
1da177e4 | 426 | * |
61b03bd7 | 427 | * Check, if the block is bad. |
1da177e4 | 428 | */ |
9f3e0429 | 429 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 430 | { |
c120e75e | 431 | int page, page_end, res; |
862eba51 | 432 | struct nand_chip *chip = mtd_to_nand(mtd); |
c120e75e | 433 | u8 bad; |
1da177e4 | 434 | |
5fb1549d | 435 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
436 | ofs += mtd->erasesize - mtd->writesize; |
437 | ||
1a12f46a | 438 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
c120e75e | 439 | page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1); |
1a12f46a | 440 | |
c120e75e MY |
441 | for (; page < page_end; page++) { |
442 | res = chip->ecc.read_oob(mtd, chip, page); | |
443 | if (res) | |
444 | return res; | |
445 | ||
446 | bad = chip->oob_poi[chip->badblockpos]; | |
cdbec050 BN |
447 | |
448 | if (likely(chip->badblockbits == 8)) | |
449 | res = bad != 0xFF; | |
e0b58d0a | 450 | else |
cdbec050 | 451 | res = hweight8(bad) < chip->badblockbits; |
c120e75e MY |
452 | if (res) |
453 | return res; | |
454 | } | |
e0b58d0a | 455 | |
c120e75e | 456 | return 0; |
1da177e4 LT |
457 | } |
458 | ||
459 | /** | |
5a0edb25 | 460 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
461 | * @mtd: MTD device structure |
462 | * @ofs: offset from device start | |
1da177e4 | 463 | * |
8b6e50c9 | 464 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
465 | * specific driver. It provides the details for writing a bad block marker to a |
466 | * block. | |
467 | */ | |
468 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
469 | { | |
862eba51 | 470 | struct nand_chip *chip = mtd_to_nand(mtd); |
5a0edb25 BN |
471 | struct mtd_oob_ops ops; |
472 | uint8_t buf[2] = { 0, 0 }; | |
473 | int ret = 0, res, i = 0; | |
474 | ||
0ec56dc4 | 475 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
476 | ops.oobbuf = buf; |
477 | ops.ooboffs = chip->badblockpos; | |
478 | if (chip->options & NAND_BUSWIDTH_16) { | |
479 | ops.ooboffs &= ~0x01; | |
480 | ops.len = ops.ooblen = 2; | |
481 | } else { | |
482 | ops.len = ops.ooblen = 1; | |
483 | } | |
484 | ops.mode = MTD_OPS_PLACE_OOB; | |
485 | ||
486 | /* Write to first/last page(s) if necessary */ | |
487 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
488 | ofs += mtd->erasesize - mtd->writesize; | |
489 | do { | |
490 | res = nand_do_write_oob(mtd, ofs, &ops); | |
491 | if (!ret) | |
492 | ret = res; | |
493 | ||
494 | i++; | |
495 | ofs += mtd->writesize; | |
496 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | /** | |
502 | * nand_block_markbad_lowlevel - mark a block bad | |
503 | * @mtd: MTD device structure | |
504 | * @ofs: offset from device start | |
505 | * | |
506 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
507 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
508 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
509 | * | |
b32843b7 | 510 | * We try operations in the following order: |
b6f6c294 | 511 | * |
e2414f4c | 512 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
513 | * (2) write bad block marker to OOB area of affected block (unless flag |
514 | * NAND_BBT_NO_OOB_BBM is present) | |
515 | * (3) update the BBT | |
b6f6c294 | 516 | * |
b32843b7 | 517 | * Note that we retain the first error encountered in (2) or (3), finish the |
e2414f4c | 518 | * procedures, and dump the error in the end. |
1da177e4 | 519 | */ |
5a0edb25 | 520 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 521 | { |
862eba51 | 522 | struct nand_chip *chip = mtd_to_nand(mtd); |
b32843b7 | 523 | int res, ret = 0; |
61b03bd7 | 524 | |
b32843b7 | 525 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
526 | struct erase_info einfo; |
527 | ||
528 | /* Attempt erase before marking OOB */ | |
529 | memset(&einfo, 0, sizeof(einfo)); | |
530 | einfo.mtd = mtd; | |
531 | einfo.addr = ofs; | |
daae74ca | 532 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 533 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 534 | |
b32843b7 | 535 | /* Write bad block marker to OOB */ |
6a8214aa | 536 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 537 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 538 | nand_release_device(mtd); |
f1a28c02 | 539 | } |
e2414f4c | 540 | |
b32843b7 BN |
541 | /* Mark block bad in BBT */ |
542 | if (chip->bbt) { | |
543 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
544 | if (!ret) |
545 | ret = res; | |
546 | } | |
547 | ||
f1a28c02 TG |
548 | if (!ret) |
549 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 550 | |
f1a28c02 | 551 | return ret; |
1da177e4 LT |
552 | } |
553 | ||
61b03bd7 | 554 | /** |
1da177e4 | 555 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 556 | * @mtd: MTD device structure |
1da177e4 | 557 | * |
8b6e50c9 BN |
558 | * Check, if the device is write protected. The function expects, that the |
559 | * device is already selected. | |
1da177e4 | 560 | */ |
e0c7d767 | 561 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 562 | { |
862eba51 | 563 | struct nand_chip *chip = mtd_to_nand(mtd); |
93edbad6 | 564 | |
8b6e50c9 | 565 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
566 | if (chip->options & NAND_BROKEN_XD) |
567 | return 0; | |
568 | ||
1da177e4 | 569 | /* Check the WP bit */ |
ace4dfee TG |
570 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
571 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
572 | } |
573 | ||
8471bb73 | 574 | /** |
c30e1f79 | 575 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
576 | * @mtd: MTD device structure |
577 | * @ofs: offset from device start | |
578 | * | |
c30e1f79 | 579 | * Check if the block is marked as reserved. |
8471bb73 EG |
580 | */ |
581 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
582 | { | |
862eba51 | 583 | struct nand_chip *chip = mtd_to_nand(mtd); |
8471bb73 EG |
584 | |
585 | if (!chip->bbt) | |
586 | return 0; | |
587 | /* Return info from the table */ | |
588 | return nand_isreserved_bbt(mtd, ofs); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /** |
592 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
593 | * @mtd: MTD device structure |
594 | * @ofs: offset from device start | |
8b6e50c9 | 595 | * @allowbbt: 1, if its allowed to access the bbt area |
1da177e4 LT |
596 | * |
597 | * Check, if the block is bad. Either by reading the bad block table or | |
598 | * calling of the scan function. | |
599 | */ | |
9f3e0429 | 600 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) |
1da177e4 | 601 | { |
862eba51 | 602 | struct nand_chip *chip = mtd_to_nand(mtd); |
61b03bd7 | 603 | |
ace4dfee | 604 | if (!chip->bbt) |
9f3e0429 | 605 | return chip->block_bad(mtd, ofs); |
61b03bd7 | 606 | |
1da177e4 | 607 | /* Return info from the table */ |
e0c7d767 | 608 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
609 | } |
610 | ||
2af7c653 SK |
611 | /** |
612 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
613 | * @mtd: MTD device structure |
614 | * @timeo: Timeout | |
2af7c653 SK |
615 | * |
616 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
617 | * context. | |
618 | */ | |
619 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
620 | { | |
862eba51 | 621 | struct nand_chip *chip = mtd_to_nand(mtd); |
2af7c653 SK |
622 | int i; |
623 | ||
624 | /* Wait for the device to get ready */ | |
625 | for (i = 0; i < timeo; i++) { | |
626 | if (chip->dev_ready(mtd)) | |
627 | break; | |
628 | touch_softlockup_watchdog(); | |
629 | mdelay(1); | |
630 | } | |
631 | } | |
632 | ||
b70af9be AS |
633 | /** |
634 | * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
635 | * @mtd: MTD device structure | |
636 | * | |
637 | * Wait for the ready pin after a command, and warn if a timeout occurs. | |
638 | */ | |
4b648b02 | 639 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 640 | { |
862eba51 | 641 | struct nand_chip *chip = mtd_to_nand(mtd); |
b70af9be | 642 | unsigned long timeo = 400; |
3b88775c | 643 | |
2af7c653 | 644 | if (in_interrupt() || oops_in_progress) |
b70af9be | 645 | return panic_nand_wait_ready(mtd, timeo); |
2af7c653 | 646 | |
7854d3f7 | 647 | /* Wait until command is processed or timeout occurs */ |
b70af9be | 648 | timeo = jiffies + msecs_to_jiffies(timeo); |
3b88775c | 649 | do { |
ace4dfee | 650 | if (chip->dev_ready(mtd)) |
4c7e054f | 651 | return; |
b70af9be | 652 | cond_resched(); |
61b03bd7 | 653 | } while (time_before(jiffies, timeo)); |
b70af9be | 654 | |
9ebfdf5b BN |
655 | if (!chip->dev_ready(mtd)) |
656 | pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); | |
3b88775c | 657 | } |
4b648b02 | 658 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 659 | |
60c70d66 RQ |
660 | /** |
661 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
662 | * @mtd: MTD device structure | |
663 | * @timeo: Timeout in ms | |
664 | * | |
665 | * Wait for status ready (i.e. command done) or timeout. | |
666 | */ | |
667 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
668 | { | |
862eba51 | 669 | register struct nand_chip *chip = mtd_to_nand(mtd); |
60c70d66 RQ |
670 | |
671 | timeo = jiffies + msecs_to_jiffies(timeo); | |
672 | do { | |
673 | if ((chip->read_byte(mtd) & NAND_STATUS_READY)) | |
674 | break; | |
675 | touch_softlockup_watchdog(); | |
676 | } while (time_before(jiffies, timeo)); | |
677 | }; | |
678 | ||
1da177e4 LT |
679 | /** |
680 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
681 | * @mtd: MTD device structure |
682 | * @command: the command to be sent | |
683 | * @column: the column address for this command, -1 if none | |
684 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 685 | * |
8b6e50c9 | 686 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 687 | * (512 Bytes per page). |
1da177e4 | 688 | */ |
7abd3ef9 TG |
689 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
690 | int column, int page_addr) | |
1da177e4 | 691 | { |
862eba51 | 692 | register struct nand_chip *chip = mtd_to_nand(mtd); |
7abd3ef9 | 693 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 694 | |
8b6e50c9 | 695 | /* Write out the command to the device */ |
1da177e4 LT |
696 | if (command == NAND_CMD_SEQIN) { |
697 | int readcmd; | |
698 | ||
28318776 | 699 | if (column >= mtd->writesize) { |
1da177e4 | 700 | /* OOB area */ |
28318776 | 701 | column -= mtd->writesize; |
1da177e4 LT |
702 | readcmd = NAND_CMD_READOOB; |
703 | } else if (column < 256) { | |
704 | /* First 256 bytes --> READ0 */ | |
705 | readcmd = NAND_CMD_READ0; | |
706 | } else { | |
707 | column -= 256; | |
708 | readcmd = NAND_CMD_READ1; | |
709 | } | |
ace4dfee | 710 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 711 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 712 | } |
ace4dfee | 713 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 714 | |
8b6e50c9 | 715 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
716 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
717 | /* Serially input address */ | |
718 | if (column != -1) { | |
719 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
720 | if (chip->options & NAND_BUSWIDTH_16 && |
721 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 722 | column >>= 1; |
ace4dfee | 723 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
724 | ctrl &= ~NAND_CTRL_CHANGE; |
725 | } | |
726 | if (page_addr != -1) { | |
ace4dfee | 727 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 728 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 729 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
14157f86 | 730 | if (chip->options & NAND_ROW_ADDR_3) |
ace4dfee | 731 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); |
1da177e4 | 732 | } |
ace4dfee | 733 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
734 | |
735 | /* | |
8b6e50c9 BN |
736 | * Program and erase have their own busy handlers status and sequential |
737 | * in needs no delay | |
e0c7d767 | 738 | */ |
1da177e4 | 739 | switch (command) { |
61b03bd7 | 740 | |
1da177e4 LT |
741 | case NAND_CMD_PAGEPROG: |
742 | case NAND_CMD_ERASE1: | |
743 | case NAND_CMD_ERASE2: | |
744 | case NAND_CMD_SEQIN: | |
745 | case NAND_CMD_STATUS: | |
3158fa0e | 746 | case NAND_CMD_READID: |
c5d664aa | 747 | case NAND_CMD_SET_FEATURES: |
1da177e4 LT |
748 | return; |
749 | ||
750 | case NAND_CMD_RESET: | |
ace4dfee | 751 | if (chip->dev_ready) |
1da177e4 | 752 | break; |
ace4dfee TG |
753 | udelay(chip->chip_delay); |
754 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 755 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
756 | chip->cmd_ctrl(mtd, |
757 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
758 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
759 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
760 | return; |
761 | ||
e0c7d767 | 762 | /* This applies to read commands */ |
2165c4a1 BB |
763 | case NAND_CMD_READ0: |
764 | /* | |
765 | * READ0 is sometimes used to exit GET STATUS mode. When this | |
766 | * is the case no address cycles are requested, and we can use | |
767 | * this information to detect that we should not wait for the | |
768 | * device to be ready. | |
769 | */ | |
770 | if (column == -1 && page_addr == -1) | |
771 | return; | |
772 | ||
1da177e4 | 773 | default: |
61b03bd7 | 774 | /* |
1da177e4 LT |
775 | * If we don't have access to the busy pin, we apply the given |
776 | * command delay | |
e0c7d767 | 777 | */ |
ace4dfee TG |
778 | if (!chip->dev_ready) { |
779 | udelay(chip->chip_delay); | |
1da177e4 | 780 | return; |
61b03bd7 | 781 | } |
1da177e4 | 782 | } |
8b6e50c9 BN |
783 | /* |
784 | * Apply this short delay always to ensure that we do wait tWB in | |
785 | * any case on any machine. | |
786 | */ | |
e0c7d767 | 787 | ndelay(100); |
3b88775c TG |
788 | |
789 | nand_wait_ready(mtd); | |
1da177e4 LT |
790 | } |
791 | ||
6ea40a3b BB |
792 | static void nand_ccs_delay(struct nand_chip *chip) |
793 | { | |
794 | /* | |
795 | * The controller already takes care of waiting for tCCS when the RNDIN | |
796 | * or RNDOUT command is sent, return directly. | |
797 | */ | |
798 | if (!(chip->options & NAND_WAIT_TCCS)) | |
799 | return; | |
800 | ||
801 | /* | |
802 | * Wait tCCS_min if it is correctly defined, otherwise wait 500ns | |
803 | * (which should be safe for all NANDs). | |
804 | */ | |
805 | if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min) | |
806 | ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000); | |
807 | else | |
808 | ndelay(500); | |
809 | } | |
810 | ||
1da177e4 LT |
811 | /** |
812 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
813 | * @mtd: MTD device structure |
814 | * @command: the command to be sent | |
815 | * @column: the column address for this command, -1 if none | |
816 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 817 | * |
7abd3ef9 | 818 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
819 | * devices. We don't have the separate regions as we have in the small page |
820 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 821 | */ |
7abd3ef9 TG |
822 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
823 | int column, int page_addr) | |
1da177e4 | 824 | { |
862eba51 | 825 | register struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
826 | |
827 | /* Emulate NAND_CMD_READOOB */ | |
828 | if (command == NAND_CMD_READOOB) { | |
28318776 | 829 | column += mtd->writesize; |
1da177e4 LT |
830 | command = NAND_CMD_READ0; |
831 | } | |
61b03bd7 | 832 | |
7abd3ef9 | 833 | /* Command latch cycle */ |
fb066ada | 834 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
835 | |
836 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 837 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
838 | |
839 | /* Serially input address */ | |
840 | if (column != -1) { | |
841 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
842 | if (chip->options & NAND_BUSWIDTH_16 && |
843 | !nand_opcode_8bits(command)) | |
1da177e4 | 844 | column >>= 1; |
ace4dfee | 845 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 846 | ctrl &= ~NAND_CTRL_CHANGE; |
fde85cfd | 847 | |
f5b88de2 | 848 | /* Only output a single addr cycle for 8bits opcodes. */ |
fde85cfd BB |
849 | if (!nand_opcode_8bits(command)) |
850 | chip->cmd_ctrl(mtd, column >> 8, ctrl); | |
61b03bd7 | 851 | } |
1da177e4 | 852 | if (page_addr != -1) { |
ace4dfee TG |
853 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
854 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 855 | NAND_NCE | NAND_ALE); |
14157f86 | 856 | if (chip->options & NAND_ROW_ADDR_3) |
ace4dfee | 857 | chip->cmd_ctrl(mtd, page_addr >> 16, |
7abd3ef9 | 858 | NAND_NCE | NAND_ALE); |
1da177e4 | 859 | } |
1da177e4 | 860 | } |
ace4dfee | 861 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
862 | |
863 | /* | |
8b6e50c9 | 864 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 865 | * in and status need no delay. |
30f464b7 | 866 | */ |
1da177e4 | 867 | switch (command) { |
61b03bd7 | 868 | |
1da177e4 LT |
869 | case NAND_CMD_CACHEDPROG: |
870 | case NAND_CMD_PAGEPROG: | |
871 | case NAND_CMD_ERASE1: | |
872 | case NAND_CMD_ERASE2: | |
873 | case NAND_CMD_SEQIN: | |
874 | case NAND_CMD_STATUS: | |
3158fa0e | 875 | case NAND_CMD_READID: |
c5d664aa | 876 | case NAND_CMD_SET_FEATURES: |
30f464b7 | 877 | return; |
1da177e4 | 878 | |
6ea40a3b BB |
879 | case NAND_CMD_RNDIN: |
880 | nand_ccs_delay(chip); | |
881 | return; | |
882 | ||
1da177e4 | 883 | case NAND_CMD_RESET: |
ace4dfee | 884 | if (chip->dev_ready) |
1da177e4 | 885 | break; |
ace4dfee | 886 | udelay(chip->chip_delay); |
12efdde3 TG |
887 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
888 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
889 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
890 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
891 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
892 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
893 | return; |
894 | ||
7bc3312b TG |
895 | case NAND_CMD_RNDOUT: |
896 | /* No ready / busy check necessary */ | |
897 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
898 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
899 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
900 | NAND_NCE | NAND_CTRL_CHANGE); | |
6ea40a3b BB |
901 | |
902 | nand_ccs_delay(chip); | |
7bc3312b TG |
903 | return; |
904 | ||
1da177e4 | 905 | case NAND_CMD_READ0: |
2165c4a1 BB |
906 | /* |
907 | * READ0 is sometimes used to exit GET STATUS mode. When this | |
908 | * is the case no address cycles are requested, and we can use | |
909 | * this information to detect that READSTART should not be | |
910 | * issued. | |
911 | */ | |
912 | if (column == -1 && page_addr == -1) | |
913 | return; | |
914 | ||
12efdde3 TG |
915 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
916 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
917 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
918 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 919 | |
e0c7d767 | 920 | /* This applies to read commands */ |
1da177e4 | 921 | default: |
61b03bd7 | 922 | /* |
1da177e4 | 923 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 924 | * command delay. |
e0c7d767 | 925 | */ |
ace4dfee TG |
926 | if (!chip->dev_ready) { |
927 | udelay(chip->chip_delay); | |
1da177e4 | 928 | return; |
61b03bd7 | 929 | } |
1da177e4 | 930 | } |
3b88775c | 931 | |
8b6e50c9 BN |
932 | /* |
933 | * Apply this short delay always to ensure that we do wait tWB in | |
934 | * any case on any machine. | |
935 | */ | |
e0c7d767 | 936 | ndelay(100); |
3b88775c TG |
937 | |
938 | nand_wait_ready(mtd); | |
1da177e4 LT |
939 | } |
940 | ||
2af7c653 SK |
941 | /** |
942 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
943 | * @chip: the nand chip descriptor |
944 | * @mtd: MTD device structure | |
945 | * @new_state: the state which is requested | |
2af7c653 SK |
946 | * |
947 | * Used when in panic, no locks are taken. | |
948 | */ | |
949 | static void panic_nand_get_device(struct nand_chip *chip, | |
950 | struct mtd_info *mtd, int new_state) | |
951 | { | |
7854d3f7 | 952 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
953 | chip->controller->active = chip; |
954 | chip->state = new_state; | |
955 | } | |
956 | ||
1da177e4 LT |
957 | /** |
958 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
959 | * @mtd: MTD device structure |
960 | * @new_state: the state which is requested | |
1da177e4 LT |
961 | * |
962 | * Get the device and lock it for exclusive access | |
963 | */ | |
2c0a2bed | 964 | static int |
6a8214aa | 965 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 966 | { |
862eba51 | 967 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
968 | spinlock_t *lock = &chip->controller->lock; |
969 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 970 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 971 | retry: |
0dfc6246 TG |
972 | spin_lock(lock); |
973 | ||
b8b3ee9a | 974 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
975 | if (!chip->controller->active) |
976 | chip->controller->active = chip; | |
a36ed299 | 977 | |
ace4dfee TG |
978 | if (chip->controller->active == chip && chip->state == FL_READY) { |
979 | chip->state = new_state; | |
0dfc6246 | 980 | spin_unlock(lock); |
962034f4 VW |
981 | return 0; |
982 | } | |
983 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
984 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
985 | chip->state = FL_PM_SUSPENDED; | |
986 | spin_unlock(lock); | |
987 | return 0; | |
6b0d9a84 | 988 | } |
0dfc6246 TG |
989 | } |
990 | set_current_state(TASK_UNINTERRUPTIBLE); | |
991 | add_wait_queue(wq, &wait); | |
992 | spin_unlock(lock); | |
993 | schedule(); | |
994 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
995 | goto retry; |
996 | } | |
997 | ||
2af7c653 | 998 | /** |
8b6e50c9 BN |
999 | * panic_nand_wait - [GENERIC] wait until the command is done |
1000 | * @mtd: MTD device structure | |
1001 | * @chip: NAND chip structure | |
1002 | * @timeo: timeout | |
2af7c653 SK |
1003 | * |
1004 | * Wait for command done. This is a helper function for nand_wait used when | |
1005 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 1006 | * an oops through mtdoops. |
2af7c653 SK |
1007 | */ |
1008 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
1009 | unsigned long timeo) | |
1010 | { | |
1011 | int i; | |
1012 | for (i = 0; i < timeo; i++) { | |
1013 | if (chip->dev_ready) { | |
1014 | if (chip->dev_ready(mtd)) | |
1015 | break; | |
1016 | } else { | |
1017 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
1018 | break; | |
1019 | } | |
1020 | mdelay(1); | |
f8ac0414 | 1021 | } |
2af7c653 SK |
1022 | } |
1023 | ||
1da177e4 | 1024 | /** |
8b6e50c9 BN |
1025 | * nand_wait - [DEFAULT] wait until the command is done |
1026 | * @mtd: MTD device structure | |
1027 | * @chip: NAND chip structure | |
1da177e4 | 1028 | * |
b70af9be | 1029 | * Wait for command done. This applies to erase and program only. |
844d3b42 | 1030 | */ |
7bc3312b | 1031 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
1032 | { |
1033 | ||
b70af9be AS |
1034 | int status; |
1035 | unsigned long timeo = 400; | |
1da177e4 | 1036 | |
8b6e50c9 BN |
1037 | /* |
1038 | * Apply this short delay always to ensure that we do wait tWB in any | |
1039 | * case on any machine. | |
1040 | */ | |
e0c7d767 | 1041 | ndelay(100); |
1da177e4 | 1042 | |
14c65786 | 1043 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 1044 | |
2af7c653 SK |
1045 | if (in_interrupt() || oops_in_progress) |
1046 | panic_nand_wait(mtd, chip, timeo); | |
1047 | else { | |
6d2559f8 | 1048 | timeo = jiffies + msecs_to_jiffies(timeo); |
b70af9be | 1049 | do { |
2af7c653 SK |
1050 | if (chip->dev_ready) { |
1051 | if (chip->dev_ready(mtd)) | |
1052 | break; | |
1053 | } else { | |
1054 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
1055 | break; | |
1056 | } | |
1057 | cond_resched(); | |
b70af9be | 1058 | } while (time_before(jiffies, timeo)); |
1da177e4 | 1059 | } |
8fe833c1 | 1060 | |
ace4dfee | 1061 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
1062 | /* This can happen if in case of timeout or buggy dev_ready */ |
1063 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
1064 | return status; |
1065 | } | |
1066 | ||
d8e725dd BB |
1067 | /** |
1068 | * nand_reset_data_interface - Reset data interface and timings | |
1069 | * @chip: The NAND chip | |
104e442a | 1070 | * @chipnr: Internal die id |
d8e725dd BB |
1071 | * |
1072 | * Reset the Data interface and timings to ONFI mode 0. | |
1073 | * | |
1074 | * Returns 0 for success or negative error code otherwise. | |
1075 | */ | |
104e442a | 1076 | static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) |
d8e725dd BB |
1077 | { |
1078 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1079 | const struct nand_data_interface *conf; | |
1080 | int ret; | |
1081 | ||
1082 | if (!chip->setup_data_interface) | |
1083 | return 0; | |
1084 | ||
1085 | /* | |
1086 | * The ONFI specification says: | |
1087 | * " | |
1088 | * To transition from NV-DDR or NV-DDR2 to the SDR data | |
1089 | * interface, the host shall use the Reset (FFh) command | |
1090 | * using SDR timing mode 0. A device in any timing mode is | |
1091 | * required to recognize Reset (FFh) command issued in SDR | |
1092 | * timing mode 0. | |
1093 | * " | |
1094 | * | |
1095 | * Configure the data interface in SDR mode and set the | |
1096 | * timings to timing mode 0. | |
1097 | */ | |
1098 | ||
1099 | conf = nand_get_default_data_interface(); | |
104e442a | 1100 | ret = chip->setup_data_interface(mtd, chipnr, conf); |
d8e725dd BB |
1101 | if (ret) |
1102 | pr_err("Failed to configure data interface to SDR timing mode 0\n"); | |
1103 | ||
1104 | return ret; | |
1105 | } | |
1106 | ||
1107 | /** | |
1108 | * nand_setup_data_interface - Setup the best data interface and timings | |
1109 | * @chip: The NAND chip | |
104e442a | 1110 | * @chipnr: Internal die id |
d8e725dd BB |
1111 | * |
1112 | * Find and configure the best data interface and NAND timings supported by | |
1113 | * the chip and the driver. | |
1114 | * First tries to retrieve supported timing modes from ONFI information, | |
1115 | * and if the NAND chip does not support ONFI, relies on the | |
1116 | * ->onfi_timing_mode_default specified in the nand_ids table. | |
1117 | * | |
1118 | * Returns 0 for success or negative error code otherwise. | |
1119 | */ | |
104e442a | 1120 | static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) |
d8e725dd BB |
1121 | { |
1122 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1123 | int ret; | |
1124 | ||
1125 | if (!chip->setup_data_interface || !chip->data_interface) | |
1126 | return 0; | |
1127 | ||
1128 | /* | |
1129 | * Ensure the timing mode has been changed on the chip side | |
1130 | * before changing timings on the controller side. | |
1131 | */ | |
a11bf5ed BB |
1132 | if (chip->onfi_version && |
1133 | (le16_to_cpu(chip->onfi_params.opt_cmd) & | |
1134 | ONFI_OPT_CMD_SET_GET_FEATURES)) { | |
d8e725dd BB |
1135 | u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { |
1136 | chip->onfi_timing_mode_default, | |
1137 | }; | |
1138 | ||
1139 | ret = chip->onfi_set_features(mtd, chip, | |
1140 | ONFI_FEATURE_ADDR_TIMING_MODE, | |
1141 | tmode_param); | |
1142 | if (ret) | |
1143 | goto err; | |
1144 | } | |
1145 | ||
104e442a | 1146 | ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); |
d8e725dd BB |
1147 | err: |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | /** | |
1152 | * nand_init_data_interface - find the best data interface and timings | |
1153 | * @chip: The NAND chip | |
1154 | * | |
1155 | * Find the best data interface and NAND timings supported by the chip | |
1156 | * and the driver. | |
1157 | * First tries to retrieve supported timing modes from ONFI information, | |
1158 | * and if the NAND chip does not support ONFI, relies on the | |
1159 | * ->onfi_timing_mode_default specified in the nand_ids table. After this | |
1160 | * function nand_chip->data_interface is initialized with the best timing mode | |
1161 | * available. | |
1162 | * | |
1163 | * Returns 0 for success or negative error code otherwise. | |
1164 | */ | |
1165 | static int nand_init_data_interface(struct nand_chip *chip) | |
1166 | { | |
1167 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1168 | int modes, mode, ret; | |
1169 | ||
1170 | if (!chip->setup_data_interface) | |
1171 | return 0; | |
1172 | ||
1173 | /* | |
1174 | * First try to identify the best timings from ONFI parameters and | |
1175 | * if the NAND does not support ONFI, fallback to the default ONFI | |
1176 | * timing mode. | |
1177 | */ | |
1178 | modes = onfi_get_async_timing_mode(chip); | |
1179 | if (modes == ONFI_TIMING_MODE_UNKNOWN) { | |
1180 | if (!chip->onfi_timing_mode_default) | |
1181 | return 0; | |
1182 | ||
1183 | modes = GENMASK(chip->onfi_timing_mode_default, 0); | |
1184 | } | |
1185 | ||
1186 | chip->data_interface = kzalloc(sizeof(*chip->data_interface), | |
1187 | GFP_KERNEL); | |
1188 | if (!chip->data_interface) | |
1189 | return -ENOMEM; | |
1190 | ||
1191 | for (mode = fls(modes) - 1; mode >= 0; mode--) { | |
1192 | ret = onfi_init_data_interface(chip, chip->data_interface, | |
1193 | NAND_SDR_IFACE, mode); | |
1194 | if (ret) | |
1195 | continue; | |
1196 | ||
104e442a BB |
1197 | /* Pass -1 to only */ |
1198 | ret = chip->setup_data_interface(mtd, | |
1199 | NAND_DATA_IFACE_CHECK_ONLY, | |
1200 | chip->data_interface); | |
d8e725dd BB |
1201 | if (!ret) { |
1202 | chip->onfi_timing_mode_default = mode; | |
1203 | break; | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | static void nand_release_data_interface(struct nand_chip *chip) | |
1211 | { | |
1212 | kfree(chip->data_interface); | |
1213 | } | |
1214 | ||
2f94abfe SH |
1215 | /** |
1216 | * nand_reset - Reset and initialize a NAND device | |
1217 | * @chip: The NAND chip | |
73f907fd | 1218 | * @chipnr: Internal die id |
2f94abfe SH |
1219 | * |
1220 | * Returns 0 for success or negative error code otherwise | |
1221 | */ | |
73f907fd | 1222 | int nand_reset(struct nand_chip *chip, int chipnr) |
2f94abfe SH |
1223 | { |
1224 | struct mtd_info *mtd = nand_to_mtd(chip); | |
d8e725dd BB |
1225 | int ret; |
1226 | ||
104e442a | 1227 | ret = nand_reset_data_interface(chip, chipnr); |
d8e725dd BB |
1228 | if (ret) |
1229 | return ret; | |
2f94abfe | 1230 | |
73f907fd BB |
1231 | /* |
1232 | * The CS line has to be released before we can apply the new NAND | |
1233 | * interface settings, hence this weird ->select_chip() dance. | |
1234 | */ | |
1235 | chip->select_chip(mtd, chipnr); | |
2f94abfe | 1236 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
73f907fd | 1237 | chip->select_chip(mtd, -1); |
2f94abfe | 1238 | |
73f907fd | 1239 | chip->select_chip(mtd, chipnr); |
104e442a | 1240 | ret = nand_setup_data_interface(chip, chipnr); |
73f907fd | 1241 | chip->select_chip(mtd, -1); |
d8e725dd BB |
1242 | if (ret) |
1243 | return ret; | |
1244 | ||
2f94abfe SH |
1245 | return 0; |
1246 | } | |
b9bb9842 | 1247 | EXPORT_SYMBOL_GPL(nand_reset); |
2f94abfe | 1248 | |
730a43fb BB |
1249 | /** |
1250 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
1251 | * @buf: buffer to test | |
1252 | * @len: buffer length | |
1253 | * @bitflips_threshold: maximum number of bitflips | |
1254 | * | |
1255 | * Check if a buffer contains only 0xff, which means the underlying region | |
1256 | * has been erased and is ready to be programmed. | |
1257 | * The bitflips_threshold specify the maximum number of bitflips before | |
1258 | * considering the region is not erased. | |
1259 | * Note: The logic of this function has been extracted from the memweight | |
1260 | * implementation, except that nand_check_erased_buf function exit before | |
1261 | * testing the whole buffer if the number of bitflips exceed the | |
1262 | * bitflips_threshold value. | |
1263 | * | |
1264 | * Returns a positive number of bitflips less than or equal to | |
1265 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1266 | * threshold. | |
1267 | */ | |
1268 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
1269 | { | |
1270 | const unsigned char *bitmap = buf; | |
1271 | int bitflips = 0; | |
1272 | int weight; | |
1273 | ||
1274 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
1275 | len--, bitmap++) { | |
1276 | weight = hweight8(*bitmap); | |
1277 | bitflips += BITS_PER_BYTE - weight; | |
1278 | if (unlikely(bitflips > bitflips_threshold)) | |
1279 | return -EBADMSG; | |
1280 | } | |
1281 | ||
1282 | for (; len >= sizeof(long); | |
1283 | len -= sizeof(long), bitmap += sizeof(long)) { | |
086567f1 PM |
1284 | unsigned long d = *((unsigned long *)bitmap); |
1285 | if (d == ~0UL) | |
1286 | continue; | |
1287 | weight = hweight_long(d); | |
730a43fb BB |
1288 | bitflips += BITS_PER_LONG - weight; |
1289 | if (unlikely(bitflips > bitflips_threshold)) | |
1290 | return -EBADMSG; | |
1291 | } | |
1292 | ||
1293 | for (; len > 0; len--, bitmap++) { | |
1294 | weight = hweight8(*bitmap); | |
1295 | bitflips += BITS_PER_BYTE - weight; | |
1296 | if (unlikely(bitflips > bitflips_threshold)) | |
1297 | return -EBADMSG; | |
1298 | } | |
1299 | ||
1300 | return bitflips; | |
1301 | } | |
1302 | ||
1303 | /** | |
1304 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
1305 | * 0xff data | |
1306 | * @data: data buffer to test | |
1307 | * @datalen: data length | |
1308 | * @ecc: ECC buffer | |
1309 | * @ecclen: ECC length | |
1310 | * @extraoob: extra OOB buffer | |
1311 | * @extraooblen: extra OOB length | |
1312 | * @bitflips_threshold: maximum number of bitflips | |
1313 | * | |
1314 | * Check if a data buffer and its associated ECC and OOB data contains only | |
1315 | * 0xff pattern, which means the underlying region has been erased and is | |
1316 | * ready to be programmed. | |
1317 | * The bitflips_threshold specify the maximum number of bitflips before | |
1318 | * considering the region as not erased. | |
1319 | * | |
1320 | * Note: | |
1321 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
1322 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
1323 | * report the number of errors per chunk, and the NAND core infrastructure | |
1324 | * expect you to return the maximum number of bitflips for the whole page. | |
1325 | * This is why you should always use this function on a single chunk and | |
1326 | * not on the whole page. After checking each chunk you should update your | |
1327 | * max_bitflips value accordingly. | |
1328 | * 2/ When checking for bitflips in erased pages you should not only check | |
1329 | * the payload data but also their associated ECC data, because a user might | |
1330 | * have programmed almost all bits to 1 but a few. In this case, we | |
1331 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
1332 | * this case. | |
1333 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
1334 | * data are protected by the ECC engine. | |
1335 | * It could also be used if you support subpages and want to attach some | |
1336 | * extra OOB data to an ECC chunk. | |
1337 | * | |
1338 | * Returns a positive number of bitflips less than or equal to | |
1339 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1340 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
1341 | */ | |
1342 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1343 | void *ecc, int ecclen, | |
1344 | void *extraoob, int extraooblen, | |
1345 | int bitflips_threshold) | |
1346 | { | |
1347 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
1348 | ||
1349 | data_bitflips = nand_check_erased_buf(data, datalen, | |
1350 | bitflips_threshold); | |
1351 | if (data_bitflips < 0) | |
1352 | return data_bitflips; | |
1353 | ||
1354 | bitflips_threshold -= data_bitflips; | |
1355 | ||
1356 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
1357 | if (ecc_bitflips < 0) | |
1358 | return ecc_bitflips; | |
1359 | ||
1360 | bitflips_threshold -= ecc_bitflips; | |
1361 | ||
1362 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
1363 | bitflips_threshold); | |
1364 | if (extraoob_bitflips < 0) | |
1365 | return extraoob_bitflips; | |
1366 | ||
1367 | if (data_bitflips) | |
1368 | memset(data, 0xff, datalen); | |
1369 | ||
1370 | if (ecc_bitflips) | |
1371 | memset(ecc, 0xff, ecclen); | |
1372 | ||
1373 | if (extraoob_bitflips) | |
1374 | memset(extraoob, 0xff, extraooblen); | |
1375 | ||
1376 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
1377 | } | |
1378 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
1379 | ||
8593fbc6 | 1380 | /** |
7854d3f7 | 1381 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1382 | * @mtd: mtd info structure |
1383 | * @chip: nand chip info structure | |
1384 | * @buf: buffer to store read data | |
1fbb938d | 1385 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1386 | * @page: page number to read |
52ff49df | 1387 | * |
7854d3f7 | 1388 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1389 | */ |
cc0f51ec TP |
1390 | int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1391 | uint8_t *buf, int oob_required, int page) | |
8593fbc6 TG |
1392 | { |
1393 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1394 | if (oob_required) |
1395 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1396 | return 0; |
1397 | } | |
cc0f51ec | 1398 | EXPORT_SYMBOL(nand_read_page_raw); |
8593fbc6 | 1399 | |
52ff49df | 1400 | /** |
7854d3f7 | 1401 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1402 | * @mtd: mtd info structure |
1403 | * @chip: nand chip info structure | |
1404 | * @buf: buffer to store read data | |
1fbb938d | 1405 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1406 | * @page: page number to read |
52ff49df DB |
1407 | * |
1408 | * We need a special oob layout and handling even when OOB isn't used. | |
1409 | */ | |
7351d3a5 | 1410 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1411 | struct nand_chip *chip, uint8_t *buf, |
1412 | int oob_required, int page) | |
52ff49df DB |
1413 | { |
1414 | int eccsize = chip->ecc.size; | |
1415 | int eccbytes = chip->ecc.bytes; | |
1416 | uint8_t *oob = chip->oob_poi; | |
1417 | int steps, size; | |
1418 | ||
1419 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1420 | chip->read_buf(mtd, buf, eccsize); | |
1421 | buf += eccsize; | |
1422 | ||
1423 | if (chip->ecc.prepad) { | |
1424 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1425 | oob += chip->ecc.prepad; | |
1426 | } | |
1427 | ||
1428 | chip->read_buf(mtd, oob, eccbytes); | |
1429 | oob += eccbytes; | |
1430 | ||
1431 | if (chip->ecc.postpad) { | |
1432 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1433 | oob += chip->ecc.postpad; | |
1434 | } | |
1435 | } | |
1436 | ||
1437 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1438 | if (size) | |
1439 | chip->read_buf(mtd, oob, size); | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | ||
1da177e4 | 1444 | /** |
7854d3f7 | 1445 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1446 | * @mtd: mtd info structure |
1447 | * @chip: nand chip info structure | |
1448 | * @buf: buffer to store read data | |
1fbb938d | 1449 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1450 | * @page: page number to read |
068e3c0a | 1451 | */ |
f5bbdacc | 1452 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1453 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1454 | { |
846031d3 | 1455 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
1456 | int eccbytes = chip->ecc.bytes; |
1457 | int eccsteps = chip->ecc.steps; | |
1458 | uint8_t *p = buf; | |
4bf63fcb DW |
1459 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1460 | uint8_t *ecc_code = chip->buffers->ecccode; | |
3f91e94f | 1461 | unsigned int max_bitflips = 0; |
f5bbdacc | 1462 | |
1fbb938d | 1463 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1464 | |
1465 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1466 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1467 | ||
846031d3 BB |
1468 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1469 | chip->ecc.total); | |
1470 | if (ret) | |
1471 | return ret; | |
f5bbdacc TG |
1472 | |
1473 | eccsteps = chip->ecc.steps; | |
1474 | p = buf; | |
1475 | ||
1476 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1477 | int stat; | |
1478 | ||
1479 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1480 | if (stat < 0) { |
f5bbdacc | 1481 | mtd->ecc_stats.failed++; |
3f91e94f | 1482 | } else { |
f5bbdacc | 1483 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1484 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1485 | } | |
f5bbdacc | 1486 | } |
3f91e94f | 1487 | return max_bitflips; |
22c60f5f | 1488 | } |
1da177e4 | 1489 | |
3d459559 | 1490 | /** |
837a6ba4 | 1491 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1492 | * @mtd: mtd info structure |
1493 | * @chip: nand chip info structure | |
1494 | * @data_offs: offset of requested data within the page | |
1495 | * @readlen: data length | |
1496 | * @bufpoi: buffer to store read data | |
e004debd | 1497 | * @page: page number to read |
3d459559 | 1498 | */ |
7351d3a5 | 1499 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1500 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1501 | int page) | |
3d459559 | 1502 | { |
846031d3 | 1503 | int start_step, end_step, num_steps, ret; |
3d459559 AK |
1504 | uint8_t *p; |
1505 | int data_col_addr, i, gaps = 0; | |
1506 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1507 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
846031d3 | 1508 | int index, section = 0; |
3f91e94f | 1509 | unsigned int max_bitflips = 0; |
846031d3 | 1510 | struct mtd_oob_region oobregion = { }; |
3d459559 | 1511 | |
7854d3f7 | 1512 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1513 | start_step = data_offs / chip->ecc.size; |
1514 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1515 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1516 | index = start_step * chip->ecc.bytes; |
3d459559 | 1517 | |
8b6e50c9 | 1518 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1519 | datafrag_len = num_steps * chip->ecc.size; |
1520 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1521 | ||
1522 | data_col_addr = start_step * chip->ecc.size; | |
1523 | /* If we read not a page aligned data */ | |
1524 | if (data_col_addr != 0) | |
1525 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1526 | ||
1527 | p = bufpoi + data_col_addr; | |
1528 | chip->read_buf(mtd, p, datafrag_len); | |
1529 | ||
8b6e50c9 | 1530 | /* Calculate ECC */ |
3d459559 AK |
1531 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1532 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1533 | ||
8b6e50c9 BN |
1534 | /* |
1535 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1536 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1537 | */ |
846031d3 BB |
1538 | ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); |
1539 | if (ret) | |
1540 | return ret; | |
1541 | ||
1542 | if (oobregion.length < eccfrag_len) | |
1543 | gaps = 1; | |
1544 | ||
3d459559 AK |
1545 | if (gaps) { |
1546 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1547 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1548 | } else { | |
8b6e50c9 | 1549 | /* |
7854d3f7 | 1550 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1551 | * about buswidth alignment in read_buf. |
1552 | */ | |
846031d3 | 1553 | aligned_pos = oobregion.offset & ~(busw - 1); |
3d459559 | 1554 | aligned_len = eccfrag_len; |
846031d3 | 1555 | if (oobregion.offset & (busw - 1)) |
3d459559 | 1556 | aligned_len++; |
846031d3 BB |
1557 | if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & |
1558 | (busw - 1)) | |
3d459559 AK |
1559 | aligned_len++; |
1560 | ||
7351d3a5 | 1561 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
846031d3 | 1562 | mtd->writesize + aligned_pos, -1); |
3d459559 AK |
1563 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1564 | } | |
1565 | ||
846031d3 BB |
1566 | ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode, |
1567 | chip->oob_poi, index, eccfrag_len); | |
1568 | if (ret) | |
1569 | return ret; | |
3d459559 AK |
1570 | |
1571 | p = bufpoi + data_col_addr; | |
1572 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1573 | int stat; | |
1574 | ||
7351d3a5 FF |
1575 | stat = chip->ecc.correct(mtd, p, |
1576 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
40cbe6ee BB |
1577 | if (stat == -EBADMSG && |
1578 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1579 | /* check for empty pages with bitflips */ | |
1580 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1581 | &chip->buffers->ecccode[i], | |
1582 | chip->ecc.bytes, | |
1583 | NULL, 0, | |
1584 | chip->ecc.strength); | |
1585 | } | |
1586 | ||
3f91e94f | 1587 | if (stat < 0) { |
3d459559 | 1588 | mtd->ecc_stats.failed++; |
3f91e94f | 1589 | } else { |
3d459559 | 1590 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1591 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1592 | } | |
3d459559 | 1593 | } |
3f91e94f | 1594 | return max_bitflips; |
3d459559 AK |
1595 | } |
1596 | ||
068e3c0a | 1597 | /** |
7854d3f7 | 1598 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1599 | * @mtd: mtd info structure |
1600 | * @chip: nand chip info structure | |
1601 | * @buf: buffer to store read data | |
1fbb938d | 1602 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1603 | * @page: page number to read |
068e3c0a | 1604 | * |
7854d3f7 | 1605 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1606 | */ |
f5bbdacc | 1607 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1608 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1609 | { |
846031d3 | 1610 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
1611 | int eccbytes = chip->ecc.bytes; |
1612 | int eccsteps = chip->ecc.steps; | |
1613 | uint8_t *p = buf; | |
4bf63fcb DW |
1614 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1615 | uint8_t *ecc_code = chip->buffers->ecccode; | |
3f91e94f | 1616 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1617 | |
1618 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1619 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1620 | chip->read_buf(mtd, p, eccsize); | |
1621 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1622 | } |
f75e5097 | 1623 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1624 | |
846031d3 BB |
1625 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1626 | chip->ecc.total); | |
1627 | if (ret) | |
1628 | return ret; | |
1da177e4 | 1629 | |
f5bbdacc TG |
1630 | eccsteps = chip->ecc.steps; |
1631 | p = buf; | |
61b03bd7 | 1632 | |
f5bbdacc TG |
1633 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1634 | int stat; | |
1da177e4 | 1635 | |
f5bbdacc | 1636 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
40cbe6ee BB |
1637 | if (stat == -EBADMSG && |
1638 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1639 | /* check for empty pages with bitflips */ | |
1640 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1641 | &ecc_code[i], eccbytes, | |
1642 | NULL, 0, | |
1643 | chip->ecc.strength); | |
1644 | } | |
1645 | ||
3f91e94f | 1646 | if (stat < 0) { |
f5bbdacc | 1647 | mtd->ecc_stats.failed++; |
3f91e94f | 1648 | } else { |
f5bbdacc | 1649 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1650 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1651 | } | |
f5bbdacc | 1652 | } |
3f91e94f | 1653 | return max_bitflips; |
f5bbdacc | 1654 | } |
1da177e4 | 1655 | |
6e0cb135 | 1656 | /** |
7854d3f7 | 1657 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1658 | * @mtd: mtd info structure |
1659 | * @chip: nand chip info structure | |
1660 | * @buf: buffer to store read data | |
1fbb938d | 1661 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1662 | * @page: page number to read |
6e0cb135 | 1663 | * |
8b6e50c9 BN |
1664 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1665 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1666 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1667 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1668 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1669 | */ |
1670 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1671 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 | 1672 | { |
846031d3 | 1673 | int i, eccsize = chip->ecc.size, ret; |
6e0cb135 SN |
1674 | int eccbytes = chip->ecc.bytes; |
1675 | int eccsteps = chip->ecc.steps; | |
1676 | uint8_t *p = buf; | |
1677 | uint8_t *ecc_code = chip->buffers->ecccode; | |
6e0cb135 | 1678 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
3f91e94f | 1679 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1680 | |
1681 | /* Read the OOB area first */ | |
1682 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1683 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1684 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1685 | ||
846031d3 BB |
1686 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1687 | chip->ecc.total); | |
1688 | if (ret) | |
1689 | return ret; | |
6e0cb135 SN |
1690 | |
1691 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1692 | int stat; | |
1693 | ||
1694 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1695 | chip->read_buf(mtd, p, eccsize); | |
1696 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1697 | ||
1698 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
40cbe6ee BB |
1699 | if (stat == -EBADMSG && |
1700 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1701 | /* check for empty pages with bitflips */ | |
1702 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1703 | &ecc_code[i], eccbytes, | |
1704 | NULL, 0, | |
1705 | chip->ecc.strength); | |
1706 | } | |
1707 | ||
3f91e94f | 1708 | if (stat < 0) { |
6e0cb135 | 1709 | mtd->ecc_stats.failed++; |
3f91e94f | 1710 | } else { |
6e0cb135 | 1711 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1712 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1713 | } | |
6e0cb135 | 1714 | } |
3f91e94f | 1715 | return max_bitflips; |
6e0cb135 SN |
1716 | } |
1717 | ||
f5bbdacc | 1718 | /** |
7854d3f7 | 1719 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1720 | * @mtd: mtd info structure |
1721 | * @chip: nand chip info structure | |
1722 | * @buf: buffer to store read data | |
1fbb938d | 1723 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1724 | * @page: page number to read |
f5bbdacc | 1725 | * |
8b6e50c9 BN |
1726 | * The hw generator calculates the error syndrome automatically. Therefore we |
1727 | * need a special oob layout and handling. | |
f5bbdacc TG |
1728 | */ |
1729 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1730 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1731 | { |
1732 | int i, eccsize = chip->ecc.size; | |
1733 | int eccbytes = chip->ecc.bytes; | |
1734 | int eccsteps = chip->ecc.steps; | |
40cbe6ee | 1735 | int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; |
f5bbdacc | 1736 | uint8_t *p = buf; |
f75e5097 | 1737 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1738 | unsigned int max_bitflips = 0; |
1da177e4 | 1739 | |
f5bbdacc TG |
1740 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1741 | int stat; | |
61b03bd7 | 1742 | |
f5bbdacc TG |
1743 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1744 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1745 | |
f5bbdacc TG |
1746 | if (chip->ecc.prepad) { |
1747 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1748 | oob += chip->ecc.prepad; | |
1749 | } | |
1da177e4 | 1750 | |
f5bbdacc TG |
1751 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1752 | chip->read_buf(mtd, oob, eccbytes); | |
1753 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1754 | |
f5bbdacc | 1755 | oob += eccbytes; |
1da177e4 | 1756 | |
f5bbdacc TG |
1757 | if (chip->ecc.postpad) { |
1758 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1759 | oob += chip->ecc.postpad; | |
61b03bd7 | 1760 | } |
40cbe6ee BB |
1761 | |
1762 | if (stat == -EBADMSG && | |
1763 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1764 | /* check for empty pages with bitflips */ | |
1765 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1766 | oob - eccpadbytes, | |
1767 | eccpadbytes, | |
1768 | NULL, 0, | |
1769 | chip->ecc.strength); | |
1770 | } | |
1771 | ||
1772 | if (stat < 0) { | |
1773 | mtd->ecc_stats.failed++; | |
1774 | } else { | |
1775 | mtd->ecc_stats.corrected += stat; | |
1776 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1777 | } | |
f5bbdacc | 1778 | } |
1da177e4 | 1779 | |
f5bbdacc | 1780 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1781 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1782 | if (i) |
1783 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1784 | |
3f91e94f | 1785 | return max_bitflips; |
f5bbdacc | 1786 | } |
1da177e4 | 1787 | |
f5bbdacc | 1788 | /** |
7854d3f7 | 1789 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
846031d3 | 1790 | * @mtd: mtd info structure |
8b6e50c9 BN |
1791 | * @oob: oob destination address |
1792 | * @ops: oob ops structure | |
1793 | * @len: size of oob to transfer | |
8593fbc6 | 1794 | */ |
846031d3 | 1795 | static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob, |
7014568b | 1796 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1797 | { |
846031d3 BB |
1798 | struct nand_chip *chip = mtd_to_nand(mtd); |
1799 | int ret; | |
1800 | ||
f8ac0414 | 1801 | switch (ops->mode) { |
8593fbc6 | 1802 | |
0612b9dd BN |
1803 | case MTD_OPS_PLACE_OOB: |
1804 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1805 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1806 | return oob + len; | |
1807 | ||
846031d3 BB |
1808 | case MTD_OPS_AUTO_OOB: |
1809 | ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, | |
1810 | ops->ooboffs, len); | |
1811 | BUG_ON(ret); | |
1812 | return oob + len; | |
1813 | ||
8593fbc6 TG |
1814 | default: |
1815 | BUG(); | |
1816 | } | |
1817 | return NULL; | |
1818 | } | |
1819 | ||
ba84fb59 BN |
1820 | /** |
1821 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1822 | * @mtd: MTD device structure | |
1823 | * @retry_mode: the retry mode to use | |
1824 | * | |
1825 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1826 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1827 | * a new threshold, the host should retry reading the page. | |
1828 | */ | |
1829 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1830 | { | |
862eba51 | 1831 | struct nand_chip *chip = mtd_to_nand(mtd); |
ba84fb59 BN |
1832 | |
1833 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1834 | ||
1835 | if (retry_mode >= chip->read_retries) | |
1836 | return -EINVAL; | |
1837 | ||
1838 | if (!chip->setup_read_retry) | |
1839 | return -EOPNOTSUPP; | |
1840 | ||
1841 | return chip->setup_read_retry(mtd, retry_mode); | |
1842 | } | |
1843 | ||
8593fbc6 | 1844 | /** |
7854d3f7 | 1845 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1846 | * @mtd: MTD device structure |
1847 | * @from: offset to read from | |
1848 | * @ops: oob ops structure | |
f5bbdacc TG |
1849 | * |
1850 | * Internal function. Called with chip held. | |
1851 | */ | |
8593fbc6 TG |
1852 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1853 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1854 | { |
e47f3db4 | 1855 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
862eba51 | 1856 | struct nand_chip *chip = mtd_to_nand(mtd); |
f5bbdacc | 1857 | int ret = 0; |
8593fbc6 | 1858 | uint32_t readlen = ops->len; |
7014568b | 1859 | uint32_t oobreadlen = ops->ooblen; |
29f1058a | 1860 | uint32_t max_oobsize = mtd_oobavail(mtd, ops); |
9aca334e | 1861 | |
8593fbc6 | 1862 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1863 | int use_bufpoi; |
edbc4540 | 1864 | unsigned int max_bitflips = 0; |
ba84fb59 | 1865 | int retry_mode = 0; |
b72f3dfb | 1866 | bool ecc_fail = false; |
1da177e4 | 1867 | |
f5bbdacc TG |
1868 | chipnr = (int)(from >> chip->chip_shift); |
1869 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1870 | |
f5bbdacc TG |
1871 | realpage = (int)(from >> chip->page_shift); |
1872 | page = realpage & chip->pagemask; | |
1da177e4 | 1873 | |
f5bbdacc | 1874 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1875 | |
8593fbc6 TG |
1876 | buf = ops->datbuf; |
1877 | oob = ops->oobbuf; | |
e47f3db4 | 1878 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1879 | |
f8ac0414 | 1880 | while (1) { |
b72f3dfb BN |
1881 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1882 | ||
f5bbdacc TG |
1883 | bytes = min(mtd->writesize - col, readlen); |
1884 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1885 | |
66507c7b KD |
1886 | if (!aligned) |
1887 | use_bufpoi = 1; | |
1888 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
1889 | use_bufpoi = !virt_addr_valid(buf) || |
1890 | !IS_ALIGNED((unsigned long)buf, | |
1891 | chip->buf_align); | |
66507c7b KD |
1892 | else |
1893 | use_bufpoi = 0; | |
1894 | ||
8b6e50c9 | 1895 | /* Is the current page in the buffer? */ |
8593fbc6 | 1896 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1897 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1898 | ||
1899 | if (use_bufpoi && aligned) | |
1900 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1901 | __func__, buf); | |
61b03bd7 | 1902 | |
ba84fb59 | 1903 | read_retry: |
3371d663 MG |
1904 | if (nand_standard_page_accessors(&chip->ecc)) |
1905 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1da177e4 | 1906 | |
edbc4540 MD |
1907 | /* |
1908 | * Now read the page into the buffer. Absent an error, | |
1909 | * the read methods return max bitflips per ecc step. | |
1910 | */ | |
0612b9dd | 1911 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1912 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1913 | oob_required, |
1914 | page); | |
a5ff4f10 JW |
1915 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1916 | !oob) | |
7351d3a5 | 1917 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1918 | col, bytes, bufpoi, |
1919 | page); | |
956e944c | 1920 | else |
46a8cf2d | 1921 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1922 | oob_required, page); |
6d77b9d0 | 1923 | if (ret < 0) { |
66507c7b | 1924 | if (use_bufpoi) |
6d77b9d0 BN |
1925 | /* Invalidate page cache */ |
1926 | chip->pagebuf = -1; | |
1da177e4 | 1927 | break; |
6d77b9d0 | 1928 | } |
f5bbdacc TG |
1929 | |
1930 | /* Transfer not aligned data */ | |
66507c7b | 1931 | if (use_bufpoi) { |
a5ff4f10 | 1932 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1933 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1934 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1935 | chip->pagebuf = realpage; |
edbc4540 MD |
1936 | chip->pagebuf_bitflips = ret; |
1937 | } else { | |
6d77b9d0 BN |
1938 | /* Invalidate page cache */ |
1939 | chip->pagebuf = -1; | |
edbc4540 | 1940 | } |
4bf63fcb | 1941 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1942 | } |
1943 | ||
8593fbc6 | 1944 | if (unlikely(oob)) { |
b64d39d8 ML |
1945 | int toread = min(oobreadlen, max_oobsize); |
1946 | ||
1947 | if (toread) { | |
846031d3 | 1948 | oob = nand_transfer_oob(mtd, |
b64d39d8 ML |
1949 | oob, ops, toread); |
1950 | oobreadlen -= toread; | |
1951 | } | |
8593fbc6 | 1952 | } |
5bc7c33c BN |
1953 | |
1954 | if (chip->options & NAND_NEED_READRDY) { | |
1955 | /* Apply delay or wait for ready/busy pin */ | |
1956 | if (!chip->dev_ready) | |
1957 | udelay(chip->chip_delay); | |
1958 | else | |
1959 | nand_wait_ready(mtd); | |
1960 | } | |
b72f3dfb | 1961 | |
ba84fb59 | 1962 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1963 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1964 | retry_mode++; |
1965 | ret = nand_setup_read_retry(mtd, | |
1966 | retry_mode); | |
1967 | if (ret < 0) | |
1968 | break; | |
1969 | ||
1970 | /* Reset failures; retry */ | |
1971 | mtd->ecc_stats.failed = ecc_failures; | |
1972 | goto read_retry; | |
1973 | } else { | |
1974 | /* No more retry modes; real failure */ | |
1975 | ecc_fail = true; | |
1976 | } | |
1977 | } | |
1978 | ||
1979 | buf += bytes; | |
07604686 | 1980 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
8593fbc6 | 1981 | } else { |
4bf63fcb | 1982 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1983 | buf += bytes; |
edbc4540 MD |
1984 | max_bitflips = max_t(unsigned int, max_bitflips, |
1985 | chip->pagebuf_bitflips); | |
8593fbc6 | 1986 | } |
1da177e4 | 1987 | |
f5bbdacc | 1988 | readlen -= bytes; |
61b03bd7 | 1989 | |
ba84fb59 BN |
1990 | /* Reset to retry mode 0 */ |
1991 | if (retry_mode) { | |
1992 | ret = nand_setup_read_retry(mtd, 0); | |
1993 | if (ret < 0) | |
1994 | break; | |
1995 | retry_mode = 0; | |
1996 | } | |
1997 | ||
f5bbdacc | 1998 | if (!readlen) |
61b03bd7 | 1999 | break; |
1da177e4 | 2000 | |
8b6e50c9 | 2001 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
2002 | col = 0; |
2003 | /* Increment page address */ | |
2004 | realpage++; | |
2005 | ||
ace4dfee | 2006 | page = realpage & chip->pagemask; |
1da177e4 LT |
2007 | /* Check, if we cross a chip boundary */ |
2008 | if (!page) { | |
2009 | chipnr++; | |
ace4dfee TG |
2010 | chip->select_chip(mtd, -1); |
2011 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 2012 | } |
1da177e4 | 2013 | } |
b0bb6903 | 2014 | chip->select_chip(mtd, -1); |
1da177e4 | 2015 | |
8593fbc6 | 2016 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
2017 | if (oob) |
2018 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 2019 | |
3f91e94f | 2020 | if (ret < 0) |
f5bbdacc TG |
2021 | return ret; |
2022 | ||
b72f3dfb | 2023 | if (ecc_fail) |
9a1fcdfd TG |
2024 | return -EBADMSG; |
2025 | ||
edbc4540 | 2026 | return max_bitflips; |
f5bbdacc TG |
2027 | } |
2028 | ||
7bc3312b | 2029 | /** |
7854d3f7 | 2030 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
2031 | * @mtd: mtd info structure |
2032 | * @chip: nand chip info structure | |
2033 | * @page: page number to read | |
7bc3312b | 2034 | */ |
9d02fc2a | 2035 | int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b | 2036 | { |
5c2ffb11 | 2037 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 2038 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 2039 | return 0; |
7bc3312b | 2040 | } |
9d02fc2a | 2041 | EXPORT_SYMBOL(nand_read_oob_std); |
7bc3312b TG |
2042 | |
2043 | /** | |
7854d3f7 | 2044 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 2045 | * with syndromes |
8b6e50c9 BN |
2046 | * @mtd: mtd info structure |
2047 | * @chip: nand chip info structure | |
2048 | * @page: page number to read | |
7bc3312b | 2049 | */ |
9d02fc2a BB |
2050 | int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
2051 | int page) | |
7bc3312b | 2052 | { |
7bc3312b TG |
2053 | int length = mtd->oobsize; |
2054 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
2055 | int eccsize = chip->ecc.size; | |
2ea69d21 | 2056 | uint8_t *bufpoi = chip->oob_poi; |
7bc3312b TG |
2057 | int i, toread, sndrnd = 0, pos; |
2058 | ||
2059 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
2060 | for (i = 0; i < chip->ecc.steps; i++) { | |
2061 | if (sndrnd) { | |
2062 | pos = eccsize + i * (eccsize + chunk); | |
2063 | if (mtd->writesize > 512) | |
2064 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
2065 | else | |
2066 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
2067 | } else | |
2068 | sndrnd = 1; | |
2069 | toread = min_t(int, length, chunk); | |
2070 | chip->read_buf(mtd, bufpoi, toread); | |
2071 | bufpoi += toread; | |
2072 | length -= toread; | |
2073 | } | |
2074 | if (length > 0) | |
2075 | chip->read_buf(mtd, bufpoi, length); | |
2076 | ||
5c2ffb11 | 2077 | return 0; |
7bc3312b | 2078 | } |
9d02fc2a | 2079 | EXPORT_SYMBOL(nand_read_oob_syndrome); |
7bc3312b TG |
2080 | |
2081 | /** | |
7854d3f7 | 2082 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
2083 | * @mtd: mtd info structure |
2084 | * @chip: nand chip info structure | |
2085 | * @page: page number to write | |
7bc3312b | 2086 | */ |
9d02fc2a | 2087 | int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b TG |
2088 | { |
2089 | int status = 0; | |
2090 | const uint8_t *buf = chip->oob_poi; | |
2091 | int length = mtd->oobsize; | |
2092 | ||
2093 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
2094 | chip->write_buf(mtd, buf, length); | |
2095 | /* Send command to program the OOB data */ | |
2096 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2097 | ||
2098 | status = chip->waitfunc(mtd, chip); | |
2099 | ||
0d420f9d | 2100 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b | 2101 | } |
9d02fc2a | 2102 | EXPORT_SYMBOL(nand_write_oob_std); |
7bc3312b TG |
2103 | |
2104 | /** | |
7854d3f7 | 2105 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
2106 | * with syndrome - only for large page flash |
2107 | * @mtd: mtd info structure | |
2108 | * @chip: nand chip info structure | |
2109 | * @page: page number to write | |
7bc3312b | 2110 | */ |
9d02fc2a BB |
2111 | int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
2112 | int page) | |
7bc3312b TG |
2113 | { |
2114 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
2115 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
2116 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
2117 | const uint8_t *bufpoi = chip->oob_poi; | |
2118 | ||
2119 | /* | |
2120 | * data-ecc-data-ecc ... ecc-oob | |
2121 | * or | |
2122 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
2123 | */ | |
2124 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
2125 | pos = steps * (eccsize + chunk); | |
2126 | steps = 0; | |
2127 | } else | |
8b0036ee | 2128 | pos = eccsize; |
7bc3312b TG |
2129 | |
2130 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
2131 | for (i = 0; i < steps; i++) { | |
2132 | if (sndcmd) { | |
2133 | if (mtd->writesize <= 512) { | |
2134 | uint32_t fill = 0xFFFFFFFF; | |
2135 | ||
2136 | len = eccsize; | |
2137 | while (len > 0) { | |
2138 | int num = min_t(int, len, 4); | |
2139 | chip->write_buf(mtd, (uint8_t *)&fill, | |
2140 | num); | |
2141 | len -= num; | |
2142 | } | |
2143 | } else { | |
2144 | pos = eccsize + i * (eccsize + chunk); | |
2145 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
2146 | } | |
2147 | } else | |
2148 | sndcmd = 1; | |
2149 | len = min_t(int, length, chunk); | |
2150 | chip->write_buf(mtd, bufpoi, len); | |
2151 | bufpoi += len; | |
2152 | length -= len; | |
2153 | } | |
2154 | if (length > 0) | |
2155 | chip->write_buf(mtd, bufpoi, length); | |
2156 | ||
2157 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2158 | status = chip->waitfunc(mtd, chip); | |
2159 | ||
2160 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
2161 | } | |
9d02fc2a | 2162 | EXPORT_SYMBOL(nand_write_oob_syndrome); |
7bc3312b | 2163 | |
1da177e4 | 2164 | /** |
7854d3f7 | 2165 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
2166 | * @mtd: MTD device structure |
2167 | * @from: offset to read from | |
2168 | * @ops: oob operations description structure | |
1da177e4 | 2169 | * |
8b6e50c9 | 2170 | * NAND read out-of-band data from the spare area. |
1da177e4 | 2171 | */ |
8593fbc6 TG |
2172 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
2173 | struct mtd_oob_ops *ops) | |
1da177e4 | 2174 | { |
c00a0991 | 2175 | int page, realpage, chipnr; |
862eba51 | 2176 | struct nand_chip *chip = mtd_to_nand(mtd); |
041e4575 | 2177 | struct mtd_ecc_stats stats; |
7014568b VW |
2178 | int readlen = ops->ooblen; |
2179 | int len; | |
7bc3312b | 2180 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 2181 | int ret = 0; |
61b03bd7 | 2182 | |
289c0522 | 2183 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 2184 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 2185 | |
041e4575 BN |
2186 | stats = mtd->ecc_stats; |
2187 | ||
29f1058a | 2188 | len = mtd_oobavail(mtd, ops); |
03736155 AH |
2189 | |
2190 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
2191 | pr_debug("%s: attempt to start read outside oob\n", |
2192 | __func__); | |
03736155 AH |
2193 | return -EINVAL; |
2194 | } | |
2195 | ||
2196 | /* Do not allow reads past end of device */ | |
2197 | if (unlikely(from >= mtd->size || | |
2198 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
2199 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
2200 | pr_debug("%s: attempt to read beyond end of device\n", |
2201 | __func__); | |
03736155 AH |
2202 | return -EINVAL; |
2203 | } | |
7014568b | 2204 | |
7314e9e7 | 2205 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 2206 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2207 | |
7314e9e7 TG |
2208 | /* Shift to get page */ |
2209 | realpage = (int)(from >> chip->page_shift); | |
2210 | page = realpage & chip->pagemask; | |
1da177e4 | 2211 | |
f8ac0414 | 2212 | while (1) { |
0612b9dd | 2213 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 2214 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 2215 | else |
1951f2f7 SL |
2216 | ret = chip->ecc.read_oob(mtd, chip, page); |
2217 | ||
2218 | if (ret < 0) | |
2219 | break; | |
7014568b VW |
2220 | |
2221 | len = min(len, readlen); | |
846031d3 | 2222 | buf = nand_transfer_oob(mtd, buf, ops, len); |
8593fbc6 | 2223 | |
5bc7c33c BN |
2224 | if (chip->options & NAND_NEED_READRDY) { |
2225 | /* Apply delay or wait for ready/busy pin */ | |
2226 | if (!chip->dev_ready) | |
2227 | udelay(chip->chip_delay); | |
2228 | else | |
2229 | nand_wait_ready(mtd); | |
2230 | } | |
2231 | ||
7014568b | 2232 | readlen -= len; |
0d420f9d SZ |
2233 | if (!readlen) |
2234 | break; | |
2235 | ||
7314e9e7 TG |
2236 | /* Increment page address */ |
2237 | realpage++; | |
2238 | ||
2239 | page = realpage & chip->pagemask; | |
2240 | /* Check, if we cross a chip boundary */ | |
2241 | if (!page) { | |
2242 | chipnr++; | |
2243 | chip->select_chip(mtd, -1); | |
2244 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2245 | } |
2246 | } | |
b0bb6903 | 2247 | chip->select_chip(mtd, -1); |
1da177e4 | 2248 | |
1951f2f7 SL |
2249 | ops->oobretlen = ops->ooblen - readlen; |
2250 | ||
2251 | if (ret < 0) | |
2252 | return ret; | |
041e4575 BN |
2253 | |
2254 | if (mtd->ecc_stats.failed - stats.failed) | |
2255 | return -EBADMSG; | |
2256 | ||
2257 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
2258 | } |
2259 | ||
2260 | /** | |
8593fbc6 | 2261 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
2262 | * @mtd: MTD device structure |
2263 | * @from: offset to read from | |
2264 | * @ops: oob operation description structure | |
1da177e4 | 2265 | * |
8b6e50c9 | 2266 | * NAND read data and/or out-of-band data. |
1da177e4 | 2267 | */ |
8593fbc6 TG |
2268 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
2269 | struct mtd_oob_ops *ops) | |
1da177e4 | 2270 | { |
fc6b4d12 | 2271 | int ret; |
8593fbc6 TG |
2272 | |
2273 | ops->retlen = 0; | |
1da177e4 LT |
2274 | |
2275 | /* Do not allow reads past end of device */ | |
7014568b | 2276 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
2277 | pr_debug("%s: attempt to read beyond end of device\n", |
2278 | __func__); | |
1da177e4 LT |
2279 | return -EINVAL; |
2280 | } | |
2281 | ||
fc6b4d12 AS |
2282 | if (ops->mode != MTD_OPS_PLACE_OOB && |
2283 | ops->mode != MTD_OPS_AUTO_OOB && | |
2284 | ops->mode != MTD_OPS_RAW) | |
2285 | return -ENOTSUPP; | |
1da177e4 | 2286 | |
fc6b4d12 | 2287 | nand_get_device(mtd, FL_READING); |
1da177e4 | 2288 | |
8593fbc6 TG |
2289 | if (!ops->datbuf) |
2290 | ret = nand_do_read_oob(mtd, from, ops); | |
2291 | else | |
2292 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2293 | |
8593fbc6 TG |
2294 | nand_release_device(mtd); |
2295 | return ret; | |
2296 | } | |
61b03bd7 | 2297 | |
1da177e4 | 2298 | |
8593fbc6 | 2299 | /** |
7854d3f7 | 2300 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2301 | * @mtd: mtd info structure |
2302 | * @chip: nand chip info structure | |
2303 | * @buf: data buffer | |
1fbb938d | 2304 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2305 | * @page: page number to write |
52ff49df | 2306 | * |
7854d3f7 | 2307 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2308 | */ |
cc0f51ec TP |
2309 | int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
2310 | const uint8_t *buf, int oob_required, int page) | |
8593fbc6 TG |
2311 | { |
2312 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2313 | if (oob_required) |
2314 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2315 | |
2316 | return 0; | |
1da177e4 | 2317 | } |
cc0f51ec | 2318 | EXPORT_SYMBOL(nand_write_page_raw); |
1da177e4 | 2319 | |
52ff49df | 2320 | /** |
7854d3f7 | 2321 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2322 | * @mtd: mtd info structure |
2323 | * @chip: nand chip info structure | |
2324 | * @buf: data buffer | |
1fbb938d | 2325 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2326 | * @page: page number to write |
52ff49df DB |
2327 | * |
2328 | * We need a special oob layout and handling even when ECC isn't checked. | |
2329 | */ | |
fdbad98d | 2330 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2331 | struct nand_chip *chip, |
45aaeff9 BB |
2332 | const uint8_t *buf, int oob_required, |
2333 | int page) | |
52ff49df DB |
2334 | { |
2335 | int eccsize = chip->ecc.size; | |
2336 | int eccbytes = chip->ecc.bytes; | |
2337 | uint8_t *oob = chip->oob_poi; | |
2338 | int steps, size; | |
2339 | ||
2340 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2341 | chip->write_buf(mtd, buf, eccsize); | |
2342 | buf += eccsize; | |
2343 | ||
2344 | if (chip->ecc.prepad) { | |
2345 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2346 | oob += chip->ecc.prepad; | |
2347 | } | |
2348 | ||
60c3bc1f | 2349 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2350 | oob += eccbytes; |
2351 | ||
2352 | if (chip->ecc.postpad) { | |
2353 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2354 | oob += chip->ecc.postpad; | |
2355 | } | |
2356 | } | |
2357 | ||
2358 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2359 | if (size) | |
2360 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2361 | |
2362 | return 0; | |
52ff49df | 2363 | } |
9223a456 | 2364 | /** |
7854d3f7 | 2365 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2366 | * @mtd: mtd info structure |
2367 | * @chip: nand chip info structure | |
2368 | * @buf: data buffer | |
1fbb938d | 2369 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2370 | * @page: page number to write |
9223a456 | 2371 | */ |
fdbad98d | 2372 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2373 | const uint8_t *buf, int oob_required, |
2374 | int page) | |
9223a456 | 2375 | { |
846031d3 | 2376 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
2377 | int eccbytes = chip->ecc.bytes; |
2378 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2379 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2380 | const uint8_t *p = buf; |
9223a456 | 2381 | |
7854d3f7 | 2382 | /* Software ECC calculation */ |
8593fbc6 TG |
2383 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2384 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2385 | |
846031d3 BB |
2386 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2387 | chip->ecc.total); | |
2388 | if (ret) | |
2389 | return ret; | |
9223a456 | 2390 | |
45aaeff9 | 2391 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
f75e5097 | 2392 | } |
9223a456 | 2393 | |
f75e5097 | 2394 | /** |
7854d3f7 | 2395 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2396 | * @mtd: mtd info structure |
2397 | * @chip: nand chip info structure | |
2398 | * @buf: data buffer | |
1fbb938d | 2399 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2400 | * @page: page number to write |
f75e5097 | 2401 | */ |
fdbad98d | 2402 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2403 | const uint8_t *buf, int oob_required, |
2404 | int page) | |
f75e5097 | 2405 | { |
846031d3 | 2406 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
2407 | int eccbytes = chip->ecc.bytes; |
2408 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2409 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2410 | const uint8_t *p = buf; |
9223a456 | 2411 | |
f75e5097 TG |
2412 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2413 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2414 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2415 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2416 | } |
2417 | ||
846031d3 BB |
2418 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2419 | chip->ecc.total); | |
2420 | if (ret) | |
2421 | return ret; | |
f75e5097 TG |
2422 | |
2423 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2424 | |
2425 | return 0; | |
9223a456 TG |
2426 | } |
2427 | ||
837a6ba4 GP |
2428 | |
2429 | /** | |
73c8aaf4 | 2430 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
2431 | * @mtd: mtd info structure |
2432 | * @chip: nand chip info structure | |
d6a95080 | 2433 | * @offset: column address of subpage within the page |
837a6ba4 | 2434 | * @data_len: data length |
d6a95080 | 2435 | * @buf: data buffer |
837a6ba4 | 2436 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2437 | * @page: page number to write |
837a6ba4 GP |
2438 | */ |
2439 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2440 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2441 | uint32_t data_len, const uint8_t *buf, |
45aaeff9 | 2442 | int oob_required, int page) |
837a6ba4 GP |
2443 | { |
2444 | uint8_t *oob_buf = chip->oob_poi; | |
2445 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2446 | int ecc_size = chip->ecc.size; | |
2447 | int ecc_bytes = chip->ecc.bytes; | |
2448 | int ecc_steps = chip->ecc.steps; | |
837a6ba4 GP |
2449 | uint32_t start_step = offset / ecc_size; |
2450 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2451 | int oob_bytes = mtd->oobsize / ecc_steps; | |
846031d3 | 2452 | int step, ret; |
837a6ba4 GP |
2453 | |
2454 | for (step = 0; step < ecc_steps; step++) { | |
2455 | /* configure controller for WRITE access */ | |
2456 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2457 | ||
2458 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2459 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2460 | |
2461 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2462 | if ((step < start_step) || (step > end_step)) | |
2463 | memset(ecc_calc, 0xff, ecc_bytes); | |
2464 | else | |
d6a95080 | 2465 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2466 | |
2467 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2468 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2469 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2470 | memset(oob_buf, 0xff, oob_bytes); | |
2471 | ||
d6a95080 | 2472 | buf += ecc_size; |
837a6ba4 GP |
2473 | ecc_calc += ecc_bytes; |
2474 | oob_buf += oob_bytes; | |
2475 | } | |
2476 | ||
2477 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2478 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2479 | ecc_calc = chip->buffers->ecccalc; | |
846031d3 BB |
2480 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2481 | chip->ecc.total); | |
2482 | if (ret) | |
2483 | return ret; | |
837a6ba4 GP |
2484 | |
2485 | /* write OOB buffer to NAND device */ | |
2486 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2487 | ||
2488 | return 0; | |
2489 | } | |
2490 | ||
2491 | ||
61b03bd7 | 2492 | /** |
7854d3f7 | 2493 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2494 | * @mtd: mtd info structure |
2495 | * @chip: nand chip info structure | |
2496 | * @buf: data buffer | |
1fbb938d | 2497 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2498 | * @page: page number to write |
1da177e4 | 2499 | * |
8b6e50c9 BN |
2500 | * The hw generator calculates the error syndrome automatically. Therefore we |
2501 | * need a special oob layout and handling. | |
f75e5097 | 2502 | */ |
fdbad98d | 2503 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d | 2504 | struct nand_chip *chip, |
45aaeff9 BB |
2505 | const uint8_t *buf, int oob_required, |
2506 | int page) | |
1da177e4 | 2507 | { |
f75e5097 TG |
2508 | int i, eccsize = chip->ecc.size; |
2509 | int eccbytes = chip->ecc.bytes; | |
2510 | int eccsteps = chip->ecc.steps; | |
2511 | const uint8_t *p = buf; | |
2512 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2513 | |
f75e5097 | 2514 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2515 | |
f75e5097 TG |
2516 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2517 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2518 | |
f75e5097 TG |
2519 | if (chip->ecc.prepad) { |
2520 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2521 | oob += chip->ecc.prepad; | |
2522 | } | |
2523 | ||
2524 | chip->ecc.calculate(mtd, p, oob); | |
2525 | chip->write_buf(mtd, oob, eccbytes); | |
2526 | oob += eccbytes; | |
2527 | ||
2528 | if (chip->ecc.postpad) { | |
2529 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2530 | oob += chip->ecc.postpad; | |
1da177e4 | 2531 | } |
1da177e4 | 2532 | } |
f75e5097 TG |
2533 | |
2534 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2535 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2536 | if (i) |
2537 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2538 | |
2539 | return 0; | |
f75e5097 TG |
2540 | } |
2541 | ||
2542 | /** | |
f107d7a4 | 2543 | * nand_write_page - write one page |
8b6e50c9 BN |
2544 | * @mtd: MTD device structure |
2545 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2546 | * @offset: address offset within the page |
2547 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2548 | * @buf: the data to write |
1fbb938d | 2549 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 | 2550 | * @page: page number to write |
8b6e50c9 | 2551 | * @raw: use _raw version of write_page |
f75e5097 TG |
2552 | */ |
2553 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 | 2554 | uint32_t offset, int data_len, const uint8_t *buf, |
0b4773fd | 2555 | int oob_required, int page, int raw) |
f75e5097 | 2556 | { |
837a6ba4 GP |
2557 | int status, subpage; |
2558 | ||
2559 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2560 | chip->ecc.write_subpage) | |
2561 | subpage = offset || (data_len < mtd->writesize); | |
2562 | else | |
2563 | subpage = 0; | |
f75e5097 | 2564 | |
3371d663 MG |
2565 | if (nand_standard_page_accessors(&chip->ecc)) |
2566 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
f75e5097 | 2567 | |
956e944c | 2568 | if (unlikely(raw)) |
837a6ba4 | 2569 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
45aaeff9 | 2570 | oob_required, page); |
837a6ba4 GP |
2571 | else if (subpage) |
2572 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
45aaeff9 | 2573 | buf, oob_required, page); |
956e944c | 2574 | else |
45aaeff9 BB |
2575 | status = chip->ecc.write_page(mtd, chip, buf, oob_required, |
2576 | page); | |
fdbad98d JW |
2577 | |
2578 | if (status < 0) | |
2579 | return status; | |
f75e5097 | 2580 | |
41145649 | 2581 | if (nand_standard_page_accessors(&chip->ecc)) { |
0b4773fd | 2582 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
f75e5097 | 2583 | |
7bc3312b | 2584 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2585 | if (status & NAND_STATUS_FAIL) |
2586 | return -EIO; | |
f75e5097 TG |
2587 | } |
2588 | ||
f75e5097 | 2589 | return 0; |
1da177e4 LT |
2590 | } |
2591 | ||
8593fbc6 | 2592 | /** |
7854d3f7 | 2593 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2594 | * @mtd: MTD device structure |
8b6e50c9 BN |
2595 | * @oob: oob data buffer |
2596 | * @len: oob data write length | |
2597 | * @ops: oob ops structure | |
8593fbc6 | 2598 | */ |
f722013e TAA |
2599 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2600 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2601 | { |
862eba51 | 2602 | struct nand_chip *chip = mtd_to_nand(mtd); |
846031d3 | 2603 | int ret; |
f722013e TAA |
2604 | |
2605 | /* | |
2606 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2607 | * data from a previous OOB read. | |
2608 | */ | |
2609 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2610 | ||
f8ac0414 | 2611 | switch (ops->mode) { |
8593fbc6 | 2612 | |
0612b9dd BN |
2613 | case MTD_OPS_PLACE_OOB: |
2614 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2615 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2616 | return oob + len; | |
2617 | ||
846031d3 BB |
2618 | case MTD_OPS_AUTO_OOB: |
2619 | ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, | |
2620 | ops->ooboffs, len); | |
2621 | BUG_ON(ret); | |
2622 | return oob + len; | |
2623 | ||
8593fbc6 TG |
2624 | default: |
2625 | BUG(); | |
2626 | } | |
2627 | return NULL; | |
2628 | } | |
2629 | ||
f8ac0414 | 2630 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2631 | |
2632 | /** | |
7854d3f7 | 2633 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2634 | * @mtd: MTD device structure |
2635 | * @to: offset to write to | |
2636 | * @ops: oob operations description structure | |
1da177e4 | 2637 | * |
8b6e50c9 | 2638 | * NAND write with ECC. |
1da177e4 | 2639 | */ |
8593fbc6 TG |
2640 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2641 | struct mtd_oob_ops *ops) | |
1da177e4 | 2642 | { |
73600b61 | 2643 | int chipnr, realpage, page, column; |
862eba51 | 2644 | struct nand_chip *chip = mtd_to_nand(mtd); |
8593fbc6 | 2645 | uint32_t writelen = ops->len; |
782ce79a ML |
2646 | |
2647 | uint32_t oobwritelen = ops->ooblen; | |
29f1058a | 2648 | uint32_t oobmaxlen = mtd_oobavail(mtd, ops); |
782ce79a | 2649 | |
8593fbc6 TG |
2650 | uint8_t *oob = ops->oobbuf; |
2651 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2652 | int ret; |
e47f3db4 | 2653 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2654 | |
8593fbc6 | 2655 | ops->retlen = 0; |
29072b96 TG |
2656 | if (!writelen) |
2657 | return 0; | |
1da177e4 | 2658 | |
8b6e50c9 | 2659 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2660 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2661 | pr_notice("%s: attempt to write non page aligned data\n", |
2662 | __func__); | |
1da177e4 LT |
2663 | return -EINVAL; |
2664 | } | |
2665 | ||
29072b96 | 2666 | column = to & (mtd->writesize - 1); |
1da177e4 | 2667 | |
6a930961 TG |
2668 | chipnr = (int)(to >> chip->chip_shift); |
2669 | chip->select_chip(mtd, chipnr); | |
2670 | ||
1da177e4 | 2671 | /* Check, if it is write protected */ |
b0bb6903 HS |
2672 | if (nand_check_wp(mtd)) { |
2673 | ret = -EIO; | |
2674 | goto err_out; | |
2675 | } | |
1da177e4 | 2676 | |
f75e5097 TG |
2677 | realpage = (int)(to >> chip->page_shift); |
2678 | page = realpage & chip->pagemask; | |
f75e5097 TG |
2679 | |
2680 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2681 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2682 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2683 | chip->pagebuf = -1; |
61b03bd7 | 2684 | |
782ce79a | 2685 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2686 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2687 | ret = -EINVAL; | |
2688 | goto err_out; | |
2689 | } | |
782ce79a | 2690 | |
f8ac0414 | 2691 | while (1) { |
29072b96 | 2692 | int bytes = mtd->writesize; |
29072b96 | 2693 | uint8_t *wbuf = buf; |
66507c7b | 2694 | int use_bufpoi; |
144f4c98 | 2695 | int part_pagewr = (column || writelen < mtd->writesize); |
66507c7b KD |
2696 | |
2697 | if (part_pagewr) | |
2698 | use_bufpoi = 1; | |
2699 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
2700 | use_bufpoi = !virt_addr_valid(buf) || |
2701 | !IS_ALIGNED((unsigned long)buf, | |
2702 | chip->buf_align); | |
66507c7b KD |
2703 | else |
2704 | use_bufpoi = 0; | |
29072b96 | 2705 | |
66507c7b KD |
2706 | /* Partial page write?, or need to use bounce buffer */ |
2707 | if (use_bufpoi) { | |
2708 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2709 | __func__, buf); | |
66507c7b KD |
2710 | if (part_pagewr) |
2711 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2712 | chip->pagebuf = -1; |
2713 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2714 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2715 | wbuf = chip->buffers->databuf; | |
2716 | } | |
1da177e4 | 2717 | |
782ce79a ML |
2718 | if (unlikely(oob)) { |
2719 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2720 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2721 | oobwritelen -= len; |
f722013e TAA |
2722 | } else { |
2723 | /* We still need to erase leftover OOB data */ | |
2724 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2725 | } |
f107d7a4 BB |
2726 | |
2727 | ret = nand_write_page(mtd, chip, column, bytes, wbuf, | |
0b4773fd | 2728 | oob_required, page, |
f107d7a4 | 2729 | (ops->mode == MTD_OPS_RAW)); |
f75e5097 TG |
2730 | if (ret) |
2731 | break; | |
2732 | ||
2733 | writelen -= bytes; | |
2734 | if (!writelen) | |
2735 | break; | |
2736 | ||
29072b96 | 2737 | column = 0; |
f75e5097 TG |
2738 | buf += bytes; |
2739 | realpage++; | |
2740 | ||
2741 | page = realpage & chip->pagemask; | |
2742 | /* Check, if we cross a chip boundary */ | |
2743 | if (!page) { | |
2744 | chipnr++; | |
2745 | chip->select_chip(mtd, -1); | |
2746 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2747 | } |
2748 | } | |
8593fbc6 | 2749 | |
8593fbc6 | 2750 | ops->retlen = ops->len - writelen; |
7014568b VW |
2751 | if (unlikely(oob)) |
2752 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2753 | |
2754 | err_out: | |
2755 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2756 | return ret; |
2757 | } | |
2758 | ||
2af7c653 SK |
2759 | /** |
2760 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2761 | * @mtd: MTD device structure |
2762 | * @to: offset to write to | |
2763 | * @len: number of bytes to write | |
2764 | * @retlen: pointer to variable to store the number of written bytes | |
2765 | * @buf: the data to write | |
2af7c653 SK |
2766 | * |
2767 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2768 | * may for example be called by mtdoops when writing an oops while in panic. | |
2769 | */ | |
2770 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2771 | size_t *retlen, const uint8_t *buf) | |
2772 | { | |
862eba51 | 2773 | struct nand_chip *chip = mtd_to_nand(mtd); |
30863e38 | 2774 | int chipnr = (int)(to >> chip->chip_shift); |
4a89ff88 | 2775 | struct mtd_oob_ops ops; |
2af7c653 SK |
2776 | int ret; |
2777 | ||
8b6e50c9 | 2778 | /* Grab the device */ |
2af7c653 SK |
2779 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2780 | ||
30863e38 BT |
2781 | chip->select_chip(mtd, chipnr); |
2782 | ||
2783 | /* Wait for the device to get ready */ | |
2784 | panic_nand_wait(mtd, chip, 400); | |
2785 | ||
0ec56dc4 | 2786 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2787 | ops.len = len; |
2788 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2789 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2790 | |
4a89ff88 | 2791 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2792 | |
4a89ff88 | 2793 | *retlen = ops.retlen; |
2af7c653 SK |
2794 | return ret; |
2795 | } | |
2796 | ||
1da177e4 | 2797 | /** |
8593fbc6 | 2798 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2799 | * @mtd: MTD device structure |
2800 | * @to: offset to write to | |
2801 | * @ops: oob operation description structure | |
1da177e4 | 2802 | * |
8b6e50c9 | 2803 | * NAND write out-of-band. |
1da177e4 | 2804 | */ |
8593fbc6 TG |
2805 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2806 | struct mtd_oob_ops *ops) | |
1da177e4 | 2807 | { |
03736155 | 2808 | int chipnr, page, status, len; |
862eba51 | 2809 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 2810 | |
289c0522 | 2811 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2812 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2813 | |
29f1058a | 2814 | len = mtd_oobavail(mtd, ops); |
03736155 | 2815 | |
1da177e4 | 2816 | /* Do not allow write past end of page */ |
03736155 | 2817 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2818 | pr_debug("%s: attempt to write past end of page\n", |
2819 | __func__); | |
1da177e4 LT |
2820 | return -EINVAL; |
2821 | } | |
2822 | ||
03736155 | 2823 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2824 | pr_debug("%s: attempt to start write outside oob\n", |
2825 | __func__); | |
03736155 AH |
2826 | return -EINVAL; |
2827 | } | |
2828 | ||
775adc3d | 2829 | /* Do not allow write past end of device */ |
03736155 AH |
2830 | if (unlikely(to >= mtd->size || |
2831 | ops->ooboffs + ops->ooblen > | |
2832 | ((mtd->size >> chip->page_shift) - | |
2833 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2834 | pr_debug("%s: attempt to write beyond end of device\n", |
2835 | __func__); | |
03736155 AH |
2836 | return -EINVAL; |
2837 | } | |
2838 | ||
7314e9e7 | 2839 | chipnr = (int)(to >> chip->chip_shift); |
7314e9e7 TG |
2840 | |
2841 | /* | |
2842 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2843 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2844 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2845 | * it in the doc2000 driver in August 1999. dwmw2. | |
2846 | */ | |
73f907fd BB |
2847 | nand_reset(chip, chipnr); |
2848 | ||
2849 | chip->select_chip(mtd, chipnr); | |
2850 | ||
2851 | /* Shift to get page */ | |
2852 | page = (int)(to >> chip->page_shift); | |
1da177e4 LT |
2853 | |
2854 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2855 | if (nand_check_wp(mtd)) { |
2856 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2857 | return -EROFS; |
b0bb6903 | 2858 | } |
61b03bd7 | 2859 | |
1da177e4 | 2860 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2861 | if (page == chip->pagebuf) |
2862 | chip->pagebuf = -1; | |
1da177e4 | 2863 | |
f722013e | 2864 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2865 | |
0612b9dd | 2866 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2867 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2868 | else | |
2869 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2870 | |
b0bb6903 HS |
2871 | chip->select_chip(mtd, -1); |
2872 | ||
7bc3312b TG |
2873 | if (status) |
2874 | return status; | |
1da177e4 | 2875 | |
7014568b | 2876 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2877 | |
7bc3312b | 2878 | return 0; |
8593fbc6 TG |
2879 | } |
2880 | ||
2881 | /** | |
2882 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2883 | * @mtd: MTD device structure |
2884 | * @to: offset to write to | |
2885 | * @ops: oob operation description structure | |
8593fbc6 TG |
2886 | */ |
2887 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2888 | struct mtd_oob_ops *ops) | |
2889 | { | |
8593fbc6 TG |
2890 | int ret = -ENOTSUPP; |
2891 | ||
2892 | ops->retlen = 0; | |
2893 | ||
2894 | /* Do not allow writes past end of device */ | |
7014568b | 2895 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2896 | pr_debug("%s: attempt to write beyond end of device\n", |
2897 | __func__); | |
8593fbc6 TG |
2898 | return -EINVAL; |
2899 | } | |
2900 | ||
6a8214aa | 2901 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2902 | |
f8ac0414 | 2903 | switch (ops->mode) { |
0612b9dd BN |
2904 | case MTD_OPS_PLACE_OOB: |
2905 | case MTD_OPS_AUTO_OOB: | |
2906 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2907 | break; |
2908 | ||
2909 | default: | |
2910 | goto out; | |
2911 | } | |
2912 | ||
2913 | if (!ops->datbuf) | |
2914 | ret = nand_do_write_oob(mtd, to, ops); | |
2915 | else | |
2916 | ret = nand_do_write_ops(mtd, to, ops); | |
2917 | ||
7351d3a5 | 2918 | out: |
1da177e4 | 2919 | nand_release_device(mtd); |
1da177e4 LT |
2920 | return ret; |
2921 | } | |
2922 | ||
1da177e4 | 2923 | /** |
49c50b97 | 2924 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2925 | * @mtd: MTD device structure |
2926 | * @page: the page address of the block which will be erased | |
1da177e4 | 2927 | * |
49c50b97 | 2928 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2929 | */ |
49c50b97 | 2930 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2931 | { |
862eba51 | 2932 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 2933 | /* Send commands to erase a block */ |
ace4dfee TG |
2934 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2935 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2936 | |
2937 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2938 | } |
2939 | ||
1da177e4 LT |
2940 | /** |
2941 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2942 | * @mtd: MTD device structure |
2943 | * @instr: erase instruction | |
1da177e4 | 2944 | * |
8b6e50c9 | 2945 | * Erase one ore more blocks. |
1da177e4 | 2946 | */ |
e0c7d767 | 2947 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2948 | { |
e0c7d767 | 2949 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2950 | } |
61b03bd7 | 2951 | |
1da177e4 | 2952 | /** |
7854d3f7 | 2953 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2954 | * @mtd: MTD device structure |
2955 | * @instr: erase instruction | |
2956 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2957 | * |
8b6e50c9 | 2958 | * Erase one ore more blocks. |
1da177e4 | 2959 | */ |
ace4dfee TG |
2960 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2961 | int allowbbt) | |
1da177e4 | 2962 | { |
69423d99 | 2963 | int page, status, pages_per_block, ret, chipnr; |
862eba51 | 2964 | struct nand_chip *chip = mtd_to_nand(mtd); |
69423d99 | 2965 | loff_t len; |
1da177e4 | 2966 | |
289c0522 BN |
2967 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2968 | __func__, (unsigned long long)instr->addr, | |
2969 | (unsigned long long)instr->len); | |
1da177e4 | 2970 | |
6fe5a6ac | 2971 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2972 | return -EINVAL; |
1da177e4 | 2973 | |
1da177e4 | 2974 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2975 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2976 | |
2977 | /* Shift to get first page */ | |
ace4dfee TG |
2978 | page = (int)(instr->addr >> chip->page_shift); |
2979 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2980 | |
2981 | /* Calculate pages in each block */ | |
ace4dfee | 2982 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2983 | |
2984 | /* Select the NAND device */ | |
ace4dfee | 2985 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2986 | |
1da177e4 LT |
2987 | /* Check, if it is write protected */ |
2988 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2989 | pr_debug("%s: device is write protected!\n", |
2990 | __func__); | |
1da177e4 LT |
2991 | instr->state = MTD_ERASE_FAILED; |
2992 | goto erase_exit; | |
2993 | } | |
2994 | ||
2995 | /* Loop through the pages */ | |
2996 | len = instr->len; | |
2997 | ||
2998 | instr->state = MTD_ERASING; | |
2999 | ||
3000 | while (len) { | |
12183a20 | 3001 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee | 3002 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
9f3e0429 | 3003 | chip->page_shift, allowbbt)) { |
d0370219 BN |
3004 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
3005 | __func__, page); | |
1da177e4 LT |
3006 | instr->state = MTD_ERASE_FAILED; |
3007 | goto erase_exit; | |
3008 | } | |
61b03bd7 | 3009 | |
ace4dfee TG |
3010 | /* |
3011 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 3012 | * contains the current cached page. |
ace4dfee TG |
3013 | */ |
3014 | if (page <= chip->pagebuf && chip->pagebuf < | |
3015 | (page + pages_per_block)) | |
3016 | chip->pagebuf = -1; | |
1da177e4 | 3017 | |
49c50b97 | 3018 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 LT |
3019 | |
3020 | /* See if block erase succeeded */ | |
a4ab4c5d | 3021 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
3022 | pr_debug("%s: failed erase, page 0x%08x\n", |
3023 | __func__, page); | |
1da177e4 | 3024 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
3025 | instr->fail_addr = |
3026 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
3027 | goto erase_exit; |
3028 | } | |
30f464b7 | 3029 | |
1da177e4 | 3030 | /* Increment page address and decrement length */ |
daae74ca | 3031 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
3032 | page += pages_per_block; |
3033 | ||
3034 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 3035 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 3036 | chipnr++; |
ace4dfee TG |
3037 | chip->select_chip(mtd, -1); |
3038 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
3039 | } |
3040 | } | |
3041 | instr->state = MTD_ERASE_DONE; | |
3042 | ||
7351d3a5 | 3043 | erase_exit: |
1da177e4 LT |
3044 | |
3045 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
3046 | |
3047 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 3048 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3049 | nand_release_device(mtd); |
3050 | ||
49defc01 DW |
3051 | /* Do call back function */ |
3052 | if (!ret) | |
3053 | mtd_erase_callback(instr); | |
3054 | ||
1da177e4 LT |
3055 | /* Return more or less happy */ |
3056 | return ret; | |
3057 | } | |
3058 | ||
3059 | /** | |
3060 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 3061 | * @mtd: MTD device structure |
1da177e4 | 3062 | * |
8b6e50c9 | 3063 | * Sync is actually a wait for chip ready function. |
1da177e4 | 3064 | */ |
e0c7d767 | 3065 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 3066 | { |
289c0522 | 3067 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
3068 | |
3069 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 3070 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 3071 | /* Release it and go back */ |
e0c7d767 | 3072 | nand_release_device(mtd); |
1da177e4 LT |
3073 | } |
3074 | ||
1da177e4 | 3075 | /** |
ace4dfee | 3076 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
3077 | * @mtd: MTD device structure |
3078 | * @offs: offset relative to mtd start | |
1da177e4 | 3079 | */ |
ace4dfee | 3080 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 3081 | { |
9f3e0429 AT |
3082 | struct nand_chip *chip = mtd_to_nand(mtd); |
3083 | int chipnr = (int)(offs >> chip->chip_shift); | |
3084 | int ret; | |
3085 | ||
3086 | /* Select the NAND device */ | |
3087 | nand_get_device(mtd, FL_READING); | |
3088 | chip->select_chip(mtd, chipnr); | |
3089 | ||
3090 | ret = nand_block_checkbad(mtd, offs, 0); | |
3091 | ||
3092 | chip->select_chip(mtd, -1); | |
3093 | nand_release_device(mtd); | |
3094 | ||
3095 | return ret; | |
1da177e4 LT |
3096 | } |
3097 | ||
3098 | /** | |
ace4dfee | 3099 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
3100 | * @mtd: MTD device structure |
3101 | * @ofs: offset relative to mtd start | |
1da177e4 | 3102 | */ |
e0c7d767 | 3103 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 3104 | { |
1da177e4 LT |
3105 | int ret; |
3106 | ||
f8ac0414 FF |
3107 | ret = nand_block_isbad(mtd, ofs); |
3108 | if (ret) { | |
8b6e50c9 | 3109 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
3110 | if (ret > 0) |
3111 | return 0; | |
e0c7d767 DW |
3112 | return ret; |
3113 | } | |
1da177e4 | 3114 | |
5a0edb25 | 3115 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
3116 | } |
3117 | ||
5671842f ZB |
3118 | /** |
3119 | * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd | |
3120 | * @mtd: MTD device structure | |
3121 | * @ofs: offset relative to mtd start | |
3122 | * @len: length of mtd | |
3123 | */ | |
3124 | static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len) | |
3125 | { | |
3126 | struct nand_chip *chip = mtd_to_nand(mtd); | |
3127 | u32 part_start_block; | |
3128 | u32 part_end_block; | |
3129 | u32 part_start_die; | |
3130 | u32 part_end_die; | |
3131 | ||
3132 | /* | |
3133 | * max_bb_per_die and blocks_per_die used to determine | |
3134 | * the maximum bad block count. | |
3135 | */ | |
3136 | if (!chip->max_bb_per_die || !chip->blocks_per_die) | |
3137 | return -ENOTSUPP; | |
3138 | ||
3139 | /* Get the start and end of the partition in erase blocks. */ | |
3140 | part_start_block = mtd_div_by_eb(ofs, mtd); | |
3141 | part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1; | |
3142 | ||
3143 | /* Get the start and end LUNs of the partition. */ | |
3144 | part_start_die = part_start_block / chip->blocks_per_die; | |
3145 | part_end_die = part_end_block / chip->blocks_per_die; | |
3146 | ||
3147 | /* | |
3148 | * Look up the bad blocks per unit and multiply by the number of units | |
3149 | * that the partition spans. | |
3150 | */ | |
3151 | return chip->max_bb_per_die * (part_end_die - part_start_die + 1); | |
3152 | } | |
3153 | ||
7db03ecc HS |
3154 | /** |
3155 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
3156 | * @mtd: MTD device structure | |
3157 | * @chip: nand chip info structure | |
3158 | * @addr: feature address. | |
3159 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3160 | */ | |
3161 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3162 | int addr, uint8_t *subfeature_param) | |
3163 | { | |
3164 | int status; | |
05f78359 | 3165 | int i; |
7db03ecc | 3166 | |
d914c932 DM |
3167 | if (!chip->onfi_version || |
3168 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3169 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3170 | return -EINVAL; |
3171 | ||
3172 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
3173 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3174 | chip->write_byte(mtd, subfeature_param[i]); | |
3175 | ||
7db03ecc HS |
3176 | status = chip->waitfunc(mtd, chip); |
3177 | if (status & NAND_STATUS_FAIL) | |
3178 | return -EIO; | |
3179 | return 0; | |
3180 | } | |
3181 | ||
3182 | /** | |
3183 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
3184 | * @mtd: MTD device structure | |
3185 | * @chip: nand chip info structure | |
3186 | * @addr: feature address. | |
3187 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3188 | */ | |
3189 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3190 | int addr, uint8_t *subfeature_param) | |
3191 | { | |
05f78359 UKK |
3192 | int i; |
3193 | ||
d914c932 DM |
3194 | if (!chip->onfi_version || |
3195 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3196 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3197 | return -EINVAL; |
3198 | ||
7db03ecc | 3199 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); |
05f78359 UKK |
3200 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3201 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
3202 | return 0; |
3203 | } | |
3204 | ||
4a78cc64 BB |
3205 | /** |
3206 | * nand_onfi_get_set_features_notsupp - set/get features stub returning | |
3207 | * -ENOTSUPP | |
3208 | * @mtd: MTD device structure | |
3209 | * @chip: nand chip info structure | |
3210 | * @addr: feature address. | |
3211 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3212 | * | |
3213 | * Should be used by NAND controller drivers that do not support the SET/GET | |
3214 | * FEATURES operations. | |
3215 | */ | |
3216 | int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, | |
3217 | struct nand_chip *chip, int addr, | |
3218 | u8 *subfeature_param) | |
3219 | { | |
3220 | return -ENOTSUPP; | |
3221 | } | |
3222 | EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp); | |
3223 | ||
962034f4 VW |
3224 | /** |
3225 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 3226 | * @mtd: MTD device structure |
962034f4 VW |
3227 | */ |
3228 | static int nand_suspend(struct mtd_info *mtd) | |
3229 | { | |
6a8214aa | 3230 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
3231 | } |
3232 | ||
3233 | /** | |
3234 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 3235 | * @mtd: MTD device structure |
962034f4 VW |
3236 | */ |
3237 | static void nand_resume(struct mtd_info *mtd) | |
3238 | { | |
862eba51 | 3239 | struct nand_chip *chip = mtd_to_nand(mtd); |
962034f4 | 3240 | |
ace4dfee | 3241 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
3242 | nand_release_device(mtd); |
3243 | else | |
d0370219 BN |
3244 | pr_err("%s called for a chip which is not in suspended state\n", |
3245 | __func__); | |
962034f4 VW |
3246 | } |
3247 | ||
72ea4036 SB |
3248 | /** |
3249 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
3250 | * prevent further operations | |
3251 | * @mtd: MTD device structure | |
3252 | */ | |
3253 | static void nand_shutdown(struct mtd_info *mtd) | |
3254 | { | |
9ca641b0 | 3255 | nand_get_device(mtd, FL_PM_SUSPENDED); |
72ea4036 SB |
3256 | } |
3257 | ||
8b6e50c9 | 3258 | /* Set default functions */ |
29a198a1 | 3259 | static void nand_set_defaults(struct nand_chip *chip) |
7aa65bfd | 3260 | { |
29a198a1 BB |
3261 | unsigned int busw = chip->options & NAND_BUSWIDTH_16; |
3262 | ||
1da177e4 | 3263 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
3264 | if (!chip->chip_delay) |
3265 | chip->chip_delay = 20; | |
1da177e4 LT |
3266 | |
3267 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
3268 | if (chip->cmdfunc == NULL) |
3269 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
3270 | |
3271 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
3272 | if (chip->waitfunc == NULL) |
3273 | chip->waitfunc = nand_wait; | |
3274 | ||
3275 | if (!chip->select_chip) | |
3276 | chip->select_chip = nand_select_chip; | |
68e80780 | 3277 | |
4204cccd HS |
3278 | /* set for ONFI nand */ |
3279 | if (!chip->onfi_set_features) | |
3280 | chip->onfi_set_features = nand_onfi_set_features; | |
3281 | if (!chip->onfi_get_features) | |
3282 | chip->onfi_get_features = nand_onfi_get_features; | |
3283 | ||
68e80780 BN |
3284 | /* If called twice, pointers that depend on busw may need to be reset */ |
3285 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
3286 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
3287 | if (!chip->read_word) | |
3288 | chip->read_word = nand_read_word; | |
3289 | if (!chip->block_bad) | |
3290 | chip->block_bad = nand_block_bad; | |
3291 | if (!chip->block_markbad) | |
3292 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 3293 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 3294 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
3295 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
3296 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 3297 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 3298 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
3299 | if (!chip->scan_bbt) |
3300 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
3301 | |
3302 | if (!chip->controller) { | |
3303 | chip->controller = &chip->hwcontrol; | |
d45bc58d | 3304 | nand_hw_control_init(chip->controller); |
f75e5097 TG |
3305 | } |
3306 | ||
477544c6 MY |
3307 | if (!chip->buf_align) |
3308 | chip->buf_align = 1; | |
7aa65bfd TG |
3309 | } |
3310 | ||
8b6e50c9 | 3311 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3312 | static void sanitize_string(uint8_t *s, size_t len) |
3313 | { | |
3314 | ssize_t i; | |
3315 | ||
8b6e50c9 | 3316 | /* Null terminate */ |
d1e1f4e4 FF |
3317 | s[len - 1] = 0; |
3318 | ||
8b6e50c9 | 3319 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3320 | for (i = 0; i < len - 1; i++) { |
3321 | if (s[i] < ' ' || s[i] > 127) | |
3322 | s[i] = '?'; | |
3323 | } | |
3324 | ||
8b6e50c9 | 3325 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3326 | strim(s); |
3327 | } | |
3328 | ||
3329 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3330 | { | |
3331 | int i; | |
3332 | while (len--) { | |
3333 | crc ^= *p++ << 8; | |
3334 | for (i = 0; i < 8; i++) | |
3335 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3336 | } | |
3337 | ||
3338 | return crc; | |
3339 | } | |
3340 | ||
6dcbe0cd | 3341 | /* Parse the Extended Parameter Page. */ |
cbe435a1 BB |
3342 | static int nand_flash_detect_ext_param_page(struct nand_chip *chip, |
3343 | struct nand_onfi_params *p) | |
6dcbe0cd | 3344 | { |
cbe435a1 | 3345 | struct mtd_info *mtd = nand_to_mtd(chip); |
6dcbe0cd HS |
3346 | struct onfi_ext_param_page *ep; |
3347 | struct onfi_ext_section *s; | |
3348 | struct onfi_ext_ecc_info *ecc; | |
3349 | uint8_t *cursor; | |
3350 | int ret = -EINVAL; | |
3351 | int len; | |
3352 | int i; | |
3353 | ||
3354 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3355 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3356 | if (!ep) |
3357 | return -ENOMEM; | |
6dcbe0cd HS |
3358 | |
3359 | /* Send our own NAND_CMD_PARAM. */ | |
3360 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3361 | ||
3362 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3363 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3364 | sizeof(*p) * p->num_of_param_pages , -1); | |
3365 | ||
3366 | /* Read out the Extended Parameter Page. */ | |
3367 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3368 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3369 | != le16_to_cpu(ep->crc))) { | |
3370 | pr_debug("fail in the CRC.\n"); | |
3371 | goto ext_out; | |
3372 | } | |
3373 | ||
3374 | /* | |
3375 | * Check the signature. | |
3376 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3377 | */ | |
3378 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3379 | pr_debug("The signature is invalid.\n"); | |
3380 | goto ext_out; | |
3381 | } | |
3382 | ||
3383 | /* find the ECC section. */ | |
3384 | cursor = (uint8_t *)(ep + 1); | |
3385 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3386 | s = ep->sections + i; | |
3387 | if (s->type == ONFI_SECTION_TYPE_2) | |
3388 | break; | |
3389 | cursor += s->length * 16; | |
3390 | } | |
3391 | if (i == ONFI_EXT_SECTION_MAX) { | |
3392 | pr_debug("We can not find the ECC section.\n"); | |
3393 | goto ext_out; | |
3394 | } | |
3395 | ||
3396 | /* get the info we want. */ | |
3397 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3398 | ||
4ae7d228 BN |
3399 | if (!ecc->codeword_size) { |
3400 | pr_debug("Invalid codeword size\n"); | |
3401 | goto ext_out; | |
6dcbe0cd HS |
3402 | } |
3403 | ||
4ae7d228 BN |
3404 | chip->ecc_strength_ds = ecc->ecc_bits; |
3405 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3406 | ret = 0; |
6dcbe0cd HS |
3407 | |
3408 | ext_out: | |
3409 | kfree(ep); | |
3410 | return ret; | |
3411 | } | |
3412 | ||
6fb277ba | 3413 | /* |
8b6e50c9 | 3414 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba | 3415 | */ |
29a198a1 | 3416 | static int nand_flash_detect_onfi(struct nand_chip *chip) |
6fb277ba | 3417 | { |
cbe435a1 | 3418 | struct mtd_info *mtd = nand_to_mtd(chip); |
6fb277ba | 3419 | struct nand_onfi_params *p = &chip->onfi_params; |
bd9c6e99 | 3420 | int i, j; |
6fb277ba FF |
3421 | int val; |
3422 | ||
7854d3f7 | 3423 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3424 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3425 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3426 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3427 | return 0; | |
3428 | ||
6fb277ba FF |
3429 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3430 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3431 | for (j = 0; j < sizeof(*p); j++) |
3432 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3433 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3434 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3435 | break; |
3436 | } | |
3437 | } | |
3438 | ||
c7f23a70 BN |
3439 | if (i == 3) { |
3440 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3441 | return 0; |
c7f23a70 | 3442 | } |
6fb277ba | 3443 | |
8b6e50c9 | 3444 | /* Check version */ |
6fb277ba | 3445 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3446 | if (val & (1 << 5)) |
3447 | chip->onfi_version = 23; | |
3448 | else if (val & (1 << 4)) | |
6fb277ba FF |
3449 | chip->onfi_version = 22; |
3450 | else if (val & (1 << 3)) | |
3451 | chip->onfi_version = 21; | |
3452 | else if (val & (1 << 2)) | |
3453 | chip->onfi_version = 20; | |
b7b1a29d | 3454 | else if (val & (1 << 1)) |
6fb277ba | 3455 | chip->onfi_version = 10; |
b7b1a29d BN |
3456 | |
3457 | if (!chip->onfi_version) { | |
20171642 | 3458 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3459 | return 0; |
3460 | } | |
6fb277ba FF |
3461 | |
3462 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3463 | sanitize_string(p->model, sizeof(p->model)); | |
3464 | if (!mtd->name) | |
3465 | mtd->name = p->model; | |
4355b70c | 3466 | |
6fb277ba | 3467 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3468 | |
3469 | /* | |
3470 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3471 | * (don't ask me who thought of this...). MTD assumes that these | |
3472 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3473 | */ | |
3474 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3475 | mtd->erasesize *= mtd->writesize; | |
3476 | ||
6fb277ba | 3477 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3478 | |
3479 | /* See erasesize comment */ | |
3480 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3481 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3482 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 | 3483 | |
34da5f5f ZB |
3484 | chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun); |
3485 | chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun); | |
3486 | ||
e2985fc1 | 3487 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) |
29a198a1 | 3488 | chip->options |= NAND_BUSWIDTH_16; |
6fb277ba | 3489 | |
10c86bab HS |
3490 | if (p->ecc_bits != 0xff) { |
3491 | chip->ecc_strength_ds = p->ecc_bits; | |
3492 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3493 | } else if (chip->onfi_version >= 21 && |
3494 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3495 | ||
3496 | /* | |
3497 | * The nand_flash_detect_ext_param_page() uses the | |
3498 | * Change Read Column command which maybe not supported | |
3499 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3500 | * now. We do not replace user supplied command function. | |
3501 | */ | |
3502 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3503 | chip->cmdfunc = nand_command_lp; | |
3504 | ||
3505 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
cbe435a1 | 3506 | if (nand_flash_detect_ext_param_page(chip, p)) |
c7f23a70 BN |
3507 | pr_warn("Failed to detect ONFI extended param page\n"); |
3508 | } else { | |
3509 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3510 | } |
3511 | ||
6fb277ba FF |
3512 | return 1; |
3513 | } | |
3514 | ||
91361818 HS |
3515 | /* |
3516 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3517 | */ | |
29a198a1 | 3518 | static int nand_flash_detect_jedec(struct nand_chip *chip) |
91361818 | 3519 | { |
cbe435a1 | 3520 | struct mtd_info *mtd = nand_to_mtd(chip); |
91361818 HS |
3521 | struct nand_jedec_params *p = &chip->jedec_params; |
3522 | struct jedec_ecc_info *ecc; | |
3523 | int val; | |
3524 | int i, j; | |
3525 | ||
3526 | /* Try JEDEC for unknown chip or LP */ | |
3527 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3528 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3529 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3530 | chip->read_byte(mtd) != 'C') | |
3531 | return 0; | |
3532 | ||
3533 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3534 | for (i = 0; i < 3; i++) { | |
3535 | for (j = 0; j < sizeof(*p); j++) | |
3536 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3537 | ||
3538 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3539 | le16_to_cpu(p->crc)) | |
3540 | break; | |
3541 | } | |
3542 | ||
3543 | if (i == 3) { | |
3544 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3545 | return 0; | |
3546 | } | |
3547 | ||
3548 | /* Check version */ | |
3549 | val = le16_to_cpu(p->revision); | |
3550 | if (val & (1 << 2)) | |
3551 | chip->jedec_version = 10; | |
3552 | else if (val & (1 << 1)) | |
3553 | chip->jedec_version = 1; /* vendor specific version */ | |
3554 | ||
3555 | if (!chip->jedec_version) { | |
3556 | pr_info("unsupported JEDEC version: %d\n", val); | |
3557 | return 0; | |
3558 | } | |
3559 | ||
3560 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3561 | sanitize_string(p->model, sizeof(p->model)); | |
3562 | if (!mtd->name) | |
3563 | mtd->name = p->model; | |
3564 | ||
3565 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3566 | ||
3567 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3568 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3569 | mtd->erasesize *= mtd->writesize; | |
3570 | ||
3571 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3572 | ||
3573 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3574 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3575 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3576 | chip->bits_per_cell = p->bits_per_cell; | |
3577 | ||
3578 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
29a198a1 | 3579 | chip->options |= NAND_BUSWIDTH_16; |
91361818 HS |
3580 | |
3581 | /* ECC info */ | |
3582 | ecc = &p->ecc_info[0]; | |
3583 | ||
3584 | if (ecc->codeword_size >= 9) { | |
3585 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3586 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3587 | } else { | |
3588 | pr_warn("Invalid codeword size\n"); | |
3589 | } | |
3590 | ||
3591 | return 1; | |
3592 | } | |
3593 | ||
e3b88bd6 BN |
3594 | /* |
3595 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3596 | * @id_data: the ID string | |
3597 | * @arrlen: the length of the @id_data array | |
3598 | * @period: the period of repitition | |
3599 | * | |
3600 | * Check if an ID string is repeated within a given sequence of bytes at | |
3601 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3602 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3603 | * if the repetition has a period of @period; otherwise, returns zero. |
3604 | */ | |
3605 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3606 | { | |
3607 | int i, j; | |
3608 | for (i = 0; i < period; i++) | |
3609 | for (j = i + period; j < arrlen; j += period) | |
3610 | if (id_data[i] != id_data[j]) | |
3611 | return 0; | |
3612 | return 1; | |
3613 | } | |
3614 | ||
3615 | /* | |
3616 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3617 | * @id_data: the ID string | |
3618 | * @arrlen: the length of the @id_data array | |
3619 | ||
3620 | * Returns the length of the ID string, according to known wraparound/trailing | |
3621 | * zero patterns. If no pattern exists, returns the length of the array. | |
3622 | */ | |
3623 | static int nand_id_len(u8 *id_data, int arrlen) | |
3624 | { | |
3625 | int last_nonzero, period; | |
3626 | ||
3627 | /* Find last non-zero byte */ | |
3628 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3629 | if (id_data[last_nonzero]) | |
3630 | break; | |
3631 | ||
3632 | /* All zeros */ | |
3633 | if (last_nonzero < 0) | |
3634 | return 0; | |
3635 | ||
3636 | /* Calculate wraparound period */ | |
3637 | for (period = 1; period < arrlen; period++) | |
3638 | if (nand_id_has_period(id_data, arrlen, period)) | |
3639 | break; | |
3640 | ||
3641 | /* There's a repeated pattern */ | |
3642 | if (period < arrlen) | |
3643 | return period; | |
3644 | ||
3645 | /* There are trailing zeros */ | |
3646 | if (last_nonzero < arrlen - 1) | |
3647 | return last_nonzero + 1; | |
3648 | ||
3649 | /* No pattern detected */ | |
3650 | return arrlen; | |
3651 | } | |
3652 | ||
7db906b7 HS |
3653 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3654 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3655 | { | |
3656 | int bits; | |
3657 | ||
3658 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3659 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3660 | return bits + 1; | |
3661 | } | |
3662 | ||
fc09bbc0 BN |
3663 | /* |
3664 | * Many new NAND share similar device ID codes, which represent the size of the | |
3665 | * chip. The rest of the parameters must be decoded according to generic or | |
3666 | * manufacturer-specific "extended ID" decoding patterns. | |
3667 | */ | |
abbe26d1 | 3668 | void nand_decode_ext_id(struct nand_chip *chip) |
fc09bbc0 | 3669 | { |
cbe435a1 | 3670 | struct mtd_info *mtd = nand_to_mtd(chip); |
9b2d61f8 | 3671 | int extid; |
7f501f0a | 3672 | u8 *id_data = chip->id.data; |
fc09bbc0 | 3673 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3674 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3675 | /* The 4th id byte is the important one */ |
3676 | extid = id_data[3]; | |
3677 | ||
01389b6b BB |
3678 | /* Calc pagesize */ |
3679 | mtd->writesize = 1024 << (extid & 0x03); | |
3680 | extid >>= 2; | |
3681 | /* Calc oobsize */ | |
3682 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); | |
3683 | extid >>= 2; | |
3684 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3685 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3686 | extid >>= 2; | |
3687 | /* Get buswidth information */ | |
3688 | if (extid & 0x1) | |
3689 | chip->options |= NAND_BUSWIDTH_16; | |
fc09bbc0 | 3690 | } |
abbe26d1 | 3691 | EXPORT_SYMBOL_GPL(nand_decode_ext_id); |
fc09bbc0 | 3692 | |
f23a481c BN |
3693 | /* |
3694 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3695 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3696 | * the chip. | |
3697 | */ | |
29a198a1 | 3698 | static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) |
f23a481c | 3699 | { |
cbe435a1 | 3700 | struct mtd_info *mtd = nand_to_mtd(chip); |
f23a481c BN |
3701 | |
3702 | mtd->erasesize = type->erasesize; | |
3703 | mtd->writesize = type->pagesize; | |
3704 | mtd->oobsize = mtd->writesize / 32; | |
f23a481c | 3705 | |
1c195e90 HS |
3706 | /* All legacy ID NAND are small-page, SLC */ |
3707 | chip->bits_per_cell = 1; | |
f23a481c BN |
3708 | } |
3709 | ||
7e74c2d7 BN |
3710 | /* |
3711 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3712 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3713 | * page size, cell-type information). | |
3714 | */ | |
7f501f0a | 3715 | static void nand_decode_bbm_options(struct nand_chip *chip) |
7e74c2d7 | 3716 | { |
cbe435a1 | 3717 | struct mtd_info *mtd = nand_to_mtd(chip); |
7e74c2d7 BN |
3718 | |
3719 | /* Set the bad block position */ | |
3720 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3721 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3722 | else | |
3723 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
7e74c2d7 BN |
3724 | } |
3725 | ||
ec6e87e3 HS |
3726 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3727 | { | |
3728 | return type->id_len; | |
3729 | } | |
3730 | ||
cbe435a1 | 3731 | static bool find_full_id_nand(struct nand_chip *chip, |
29a198a1 | 3732 | struct nand_flash_dev *type) |
ec6e87e3 | 3733 | { |
cbe435a1 | 3734 | struct mtd_info *mtd = nand_to_mtd(chip); |
7f501f0a | 3735 | u8 *id_data = chip->id.data; |
cbe435a1 | 3736 | |
ec6e87e3 HS |
3737 | if (!strncmp(type->id, id_data, type->id_len)) { |
3738 | mtd->writesize = type->pagesize; | |
3739 | mtd->erasesize = type->erasesize; | |
3740 | mtd->oobsize = type->oobsize; | |
3741 | ||
7db906b7 | 3742 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3743 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3744 | chip->options |= type->options; | |
57219342 HS |
3745 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3746 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3747 | chip->onfi_timing_mode_default = |
3748 | type->onfi_timing_mode_default; | |
ec6e87e3 | 3749 | |
092b6a1d CZ |
3750 | if (!mtd->name) |
3751 | mtd->name = type->name; | |
3752 | ||
ec6e87e3 HS |
3753 | return true; |
3754 | } | |
3755 | return false; | |
3756 | } | |
3757 | ||
abbe26d1 BB |
3758 | /* |
3759 | * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC | |
3760 | * compliant and does not have a full-id or legacy-id entry in the nand_ids | |
3761 | * table. | |
3762 | */ | |
3763 | static void nand_manufacturer_detect(struct nand_chip *chip) | |
3764 | { | |
3765 | /* | |
3766 | * Try manufacturer detection if available and use | |
3767 | * nand_decode_ext_id() otherwise. | |
3768 | */ | |
3769 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
69fc0129 LW |
3770 | chip->manufacturer.desc->ops->detect) { |
3771 | /* The 3rd id byte holds MLC / multichip data */ | |
3772 | chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); | |
abbe26d1 | 3773 | chip->manufacturer.desc->ops->detect(chip); |
69fc0129 | 3774 | } else { |
abbe26d1 | 3775 | nand_decode_ext_id(chip); |
69fc0129 | 3776 | } |
abbe26d1 BB |
3777 | } |
3778 | ||
3779 | /* | |
3780 | * Manufacturer initialization. This function is called for all NANDs including | |
3781 | * ONFI and JEDEC compliant ones. | |
3782 | * Manufacturer drivers should put all their specific initialization code in | |
3783 | * their ->init() hook. | |
3784 | */ | |
3785 | static int nand_manufacturer_init(struct nand_chip *chip) | |
3786 | { | |
3787 | if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || | |
3788 | !chip->manufacturer.desc->ops->init) | |
3789 | return 0; | |
3790 | ||
3791 | return chip->manufacturer.desc->ops->init(chip); | |
3792 | } | |
3793 | ||
3794 | /* | |
3795 | * Manufacturer cleanup. This function is called for all NANDs including | |
3796 | * ONFI and JEDEC compliant ones. | |
3797 | * Manufacturer drivers should put all their specific cleanup code in their | |
3798 | * ->cleanup() hook. | |
3799 | */ | |
3800 | static void nand_manufacturer_cleanup(struct nand_chip *chip) | |
3801 | { | |
3802 | /* Release manufacturer private data */ | |
3803 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
3804 | chip->manufacturer.desc->ops->cleanup) | |
3805 | chip->manufacturer.desc->ops->cleanup(chip); | |
3806 | } | |
3807 | ||
7aa65bfd | 3808 | /* |
8b6e50c9 | 3809 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd | 3810 | */ |
7bb42799 | 3811 | static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) |
7aa65bfd | 3812 | { |
bcc678c2 | 3813 | const struct nand_manufacturer *manufacturer; |
cbe435a1 | 3814 | struct mtd_info *mtd = nand_to_mtd(chip); |
bb77082f | 3815 | int busw; |
f84674b8 | 3816 | int i; |
7f501f0a BB |
3817 | u8 *id_data = chip->id.data; |
3818 | u8 maf_id, dev_id; | |
1da177e4 | 3819 | |
ef89a880 KB |
3820 | /* |
3821 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3822 | * after power-up. |
ef89a880 | 3823 | */ |
73f907fd BB |
3824 | nand_reset(chip, 0); |
3825 | ||
3826 | /* Select the device */ | |
3827 | chip->select_chip(mtd, 0); | |
ef89a880 | 3828 | |
1da177e4 | 3829 | /* Send the command for reading device ID */ |
ace4dfee | 3830 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3831 | |
3832 | /* Read manufacturer and device IDs */ | |
7f501f0a BB |
3833 | maf_id = chip->read_byte(mtd); |
3834 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 3835 | |
8b6e50c9 BN |
3836 | /* |
3837 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3838 | * interface concerns can cause random data which looks like a |
3839 | * possibly credible NAND flash to appear. If the two results do | |
3840 | * not match, ignore the device completely. | |
3841 | */ | |
3842 | ||
3843 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3844 | ||
4aef9b78 | 3845 | /* Read entire ID string */ |
5158bd55 | 3846 | for (i = 0; i < ARRAY_SIZE(chip->id.data); i++) |
426c457a | 3847 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3848 | |
7f501f0a | 3849 | if (id_data[0] != maf_id || id_data[1] != dev_id) { |
20171642 | 3850 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
7f501f0a | 3851 | maf_id, dev_id, id_data[0], id_data[1]); |
4722c0e9 | 3852 | return -ENODEV; |
ed8165c7 BD |
3853 | } |
3854 | ||
5158bd55 | 3855 | chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); |
7f501f0a | 3856 | |
abbe26d1 BB |
3857 | /* Try to identify manufacturer */ |
3858 | manufacturer = nand_get_manufacturer(maf_id); | |
3859 | chip->manufacturer.desc = manufacturer; | |
3860 | ||
7aa65bfd | 3861 | if (!type) |
5e81e88a DW |
3862 | type = nand_flash_ids; |
3863 | ||
29a198a1 BB |
3864 | /* |
3865 | * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic | |
3866 | * override it. | |
3867 | * This is required to make sure initial NAND bus width set by the | |
3868 | * NAND controller driver is coherent with the real NAND bus width | |
3869 | * (extracted by auto-detection code). | |
3870 | */ | |
3871 | busw = chip->options & NAND_BUSWIDTH_16; | |
3872 | ||
3873 | /* | |
3874 | * The flag is only set (never cleared), reset it to its default value | |
3875 | * before starting auto-detection. | |
3876 | */ | |
3877 | chip->options &= ~NAND_BUSWIDTH_16; | |
3878 | ||
ec6e87e3 HS |
3879 | for (; type->name != NULL; type++) { |
3880 | if (is_full_id_nand(type)) { | |
29a198a1 | 3881 | if (find_full_id_nand(chip, type)) |
ec6e87e3 | 3882 | goto ident_done; |
7f501f0a | 3883 | } else if (dev_id == type->dev_id) { |
db5b09f6 | 3884 | break; |
ec6e87e3 HS |
3885 | } |
3886 | } | |
5e81e88a | 3887 | |
d1e1f4e4 FF |
3888 | chip->onfi_version = 0; |
3889 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3890 | /* Check if the chip is ONFI compliant */ |
29a198a1 | 3891 | if (nand_flash_detect_onfi(chip)) |
6fb277ba | 3892 | goto ident_done; |
91361818 HS |
3893 | |
3894 | /* Check if the chip is JEDEC compliant */ | |
29a198a1 | 3895 | if (nand_flash_detect_jedec(chip)) |
91361818 | 3896 | goto ident_done; |
d1e1f4e4 FF |
3897 | } |
3898 | ||
5e81e88a | 3899 | if (!type->name) |
4722c0e9 | 3900 | return -ENODEV; |
7aa65bfd | 3901 | |
ba0251fe TG |
3902 | if (!mtd->name) |
3903 | mtd->name = type->name; | |
3904 | ||
69423d99 | 3905 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3906 | |
abbe26d1 BB |
3907 | if (!type->pagesize) |
3908 | nand_manufacturer_detect(chip); | |
3909 | else | |
29a198a1 | 3910 | nand_decode_id(chip, type); |
abbe26d1 | 3911 | |
bf7a01bf BN |
3912 | /* Get chip options */ |
3913 | chip->options |= type->options; | |
d1e1f4e4 | 3914 | |
d1e1f4e4 FF |
3915 | ident_done: |
3916 | ||
64b37b2a | 3917 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
29a198a1 BB |
3918 | WARN_ON(busw & NAND_BUSWIDTH_16); |
3919 | nand_set_defaults(chip); | |
64b37b2a MC |
3920 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
3921 | /* | |
3922 | * Check, if buswidth is correct. Hardware drivers should set | |
3923 | * chip correct! | |
3924 | */ | |
20171642 | 3925 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 3926 | maf_id, dev_id); |
bcc678c2 BB |
3927 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
3928 | mtd->name); | |
29a198a1 BB |
3929 | pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, |
3930 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); | |
4722c0e9 | 3931 | return -EINVAL; |
7aa65bfd | 3932 | } |
61b03bd7 | 3933 | |
7f501f0a | 3934 | nand_decode_bbm_options(chip); |
7e74c2d7 | 3935 | |
7aa65bfd | 3936 | /* Calculate the address shift from the page size */ |
ace4dfee | 3937 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3938 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3939 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3940 | |
ace4dfee | 3941 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3942 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3943 | if (chip->chipsize & 0xffffffff) |
3944 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3945 | else { |
3946 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3947 | chip->chip_shift += 32 - 1; | |
3948 | } | |
1da177e4 | 3949 | |
14157f86 MY |
3950 | if (chip->chip_shift - chip->page_shift > 16) |
3951 | chip->options |= NAND_ROW_ADDR_3; | |
3952 | ||
26d9be11 | 3953 | chip->badblockbits = 8; |
49c50b97 | 3954 | chip->erase = single_erase; |
7aa65bfd | 3955 | |
8b6e50c9 | 3956 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3957 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3958 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3959 | |
20171642 | 3960 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 3961 | maf_id, dev_id); |
ffdac6cd HS |
3962 | |
3963 | if (chip->onfi_version) | |
bcc678c2 BB |
3964 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
3965 | chip->onfi_params.model); | |
ffdac6cd | 3966 | else if (chip->jedec_version) |
bcc678c2 BB |
3967 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
3968 | chip->jedec_params.model); | |
ffdac6cd | 3969 | else |
bcc678c2 BB |
3970 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
3971 | type->name); | |
ffdac6cd | 3972 | |
3755a991 | 3973 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 3974 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 3975 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
4722c0e9 | 3976 | return 0; |
7aa65bfd TG |
3977 | } |
3978 | ||
d48f62b9 BB |
3979 | static const char * const nand_ecc_modes[] = { |
3980 | [NAND_ECC_NONE] = "none", | |
3981 | [NAND_ECC_SOFT] = "soft", | |
3982 | [NAND_ECC_HW] = "hw", | |
3983 | [NAND_ECC_HW_SYNDROME] = "hw_syndrome", | |
3984 | [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first", | |
785818fa | 3985 | [NAND_ECC_ON_DIE] = "on-die", |
d48f62b9 BB |
3986 | }; |
3987 | ||
3988 | static int of_get_nand_ecc_mode(struct device_node *np) | |
3989 | { | |
3990 | const char *pm; | |
3991 | int err, i; | |
3992 | ||
3993 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
3994 | if (err < 0) | |
3995 | return err; | |
3996 | ||
3997 | for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++) | |
3998 | if (!strcasecmp(pm, nand_ecc_modes[i])) | |
3999 | return i; | |
4000 | ||
ae211bcf RM |
4001 | /* |
4002 | * For backward compatibility we support few obsoleted values that don't | |
4003 | * have their mappings into nand_ecc_modes_t anymore (they were merged | |
4004 | * with other enums). | |
4005 | */ | |
4006 | if (!strcasecmp(pm, "soft_bch")) | |
4007 | return NAND_ECC_SOFT; | |
4008 | ||
d48f62b9 BB |
4009 | return -ENODEV; |
4010 | } | |
4011 | ||
ba4f46b2 RM |
4012 | static const char * const nand_ecc_algos[] = { |
4013 | [NAND_ECC_HAMMING] = "hamming", | |
4014 | [NAND_ECC_BCH] = "bch", | |
4015 | }; | |
4016 | ||
d48f62b9 BB |
4017 | static int of_get_nand_ecc_algo(struct device_node *np) |
4018 | { | |
4019 | const char *pm; | |
ba4f46b2 | 4020 | int err, i; |
d48f62b9 | 4021 | |
ba4f46b2 RM |
4022 | err = of_property_read_string(np, "nand-ecc-algo", &pm); |
4023 | if (!err) { | |
4024 | for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++) | |
4025 | if (!strcasecmp(pm, nand_ecc_algos[i])) | |
4026 | return i; | |
4027 | return -ENODEV; | |
4028 | } | |
d48f62b9 BB |
4029 | |
4030 | /* | |
4031 | * For backward compatibility we also read "nand-ecc-mode" checking | |
4032 | * for some obsoleted values that were specifying ECC algorithm. | |
4033 | */ | |
4034 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
4035 | if (err < 0) | |
4036 | return err; | |
4037 | ||
4038 | if (!strcasecmp(pm, "soft")) | |
4039 | return NAND_ECC_HAMMING; | |
4040 | else if (!strcasecmp(pm, "soft_bch")) | |
4041 | return NAND_ECC_BCH; | |
4042 | ||
4043 | return -ENODEV; | |
4044 | } | |
4045 | ||
4046 | static int of_get_nand_ecc_step_size(struct device_node *np) | |
4047 | { | |
4048 | int ret; | |
4049 | u32 val; | |
4050 | ||
4051 | ret = of_property_read_u32(np, "nand-ecc-step-size", &val); | |
4052 | return ret ? ret : val; | |
4053 | } | |
4054 | ||
4055 | static int of_get_nand_ecc_strength(struct device_node *np) | |
4056 | { | |
4057 | int ret; | |
4058 | u32 val; | |
4059 | ||
4060 | ret = of_property_read_u32(np, "nand-ecc-strength", &val); | |
4061 | return ret ? ret : val; | |
4062 | } | |
4063 | ||
4064 | static int of_get_nand_bus_width(struct device_node *np) | |
4065 | { | |
4066 | u32 val; | |
4067 | ||
4068 | if (of_property_read_u32(np, "nand-bus-width", &val)) | |
4069 | return 8; | |
4070 | ||
4071 | switch (val) { | |
4072 | case 8: | |
4073 | case 16: | |
4074 | return val; | |
4075 | default: | |
4076 | return -EIO; | |
4077 | } | |
4078 | } | |
4079 | ||
4080 | static bool of_get_nand_on_flash_bbt(struct device_node *np) | |
4081 | { | |
4082 | return of_property_read_bool(np, "nand-on-flash-bbt"); | |
4083 | } | |
4084 | ||
7194a29a | 4085 | static int nand_dt_init(struct nand_chip *chip) |
5844feea | 4086 | { |
7194a29a | 4087 | struct device_node *dn = nand_get_flash_node(chip); |
79082457 | 4088 | int ecc_mode, ecc_algo, ecc_strength, ecc_step; |
5844feea | 4089 | |
7194a29a BB |
4090 | if (!dn) |
4091 | return 0; | |
4092 | ||
5844feea BN |
4093 | if (of_get_nand_bus_width(dn) == 16) |
4094 | chip->options |= NAND_BUSWIDTH_16; | |
4095 | ||
4096 | if (of_get_nand_on_flash_bbt(dn)) | |
4097 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
4098 | ||
4099 | ecc_mode = of_get_nand_ecc_mode(dn); | |
79082457 | 4100 | ecc_algo = of_get_nand_ecc_algo(dn); |
5844feea BN |
4101 | ecc_strength = of_get_nand_ecc_strength(dn); |
4102 | ecc_step = of_get_nand_ecc_step_size(dn); | |
4103 | ||
5844feea BN |
4104 | if (ecc_mode >= 0) |
4105 | chip->ecc.mode = ecc_mode; | |
4106 | ||
79082457 RM |
4107 | if (ecc_algo >= 0) |
4108 | chip->ecc.algo = ecc_algo; | |
4109 | ||
5844feea BN |
4110 | if (ecc_strength >= 0) |
4111 | chip->ecc.strength = ecc_strength; | |
4112 | ||
4113 | if (ecc_step > 0) | |
4114 | chip->ecc.size = ecc_step; | |
4115 | ||
ba78ee00 BB |
4116 | if (of_property_read_bool(dn, "nand-ecc-maximize")) |
4117 | chip->ecc.options |= NAND_ECC_MAXIMIZE; | |
4118 | ||
5844feea BN |
4119 | return 0; |
4120 | } | |
4121 | ||
7aa65bfd | 4122 | /** |
3b85c321 | 4123 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
4124 | * @mtd: MTD device structure |
4125 | * @maxchips: number of chips to scan for | |
4126 | * @table: alternative NAND ID table | |
7aa65bfd | 4127 | * |
8b6e50c9 BN |
4128 | * This is the first phase of the normal nand_scan() function. It reads the |
4129 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd TG |
4130 | * |
4131 | */ | |
5e81e88a DW |
4132 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
4133 | struct nand_flash_dev *table) | |
7aa65bfd | 4134 | { |
bb77082f | 4135 | int i, nand_maf_id, nand_dev_id; |
862eba51 | 4136 | struct nand_chip *chip = mtd_to_nand(mtd); |
5844feea BN |
4137 | int ret; |
4138 | ||
7194a29a BB |
4139 | ret = nand_dt_init(chip); |
4140 | if (ret) | |
4141 | return ret; | |
7aa65bfd | 4142 | |
f7a8e38f BN |
4143 | if (!mtd->name && mtd->dev.parent) |
4144 | mtd->name = dev_name(mtd->dev.parent); | |
4145 | ||
76fe334f AS |
4146 | if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) { |
4147 | /* | |
4148 | * Default functions assigned for chip_select() and | |
4149 | * cmdfunc() both expect cmd_ctrl() to be populated, | |
4150 | * so we need to check that that's the case | |
4151 | */ | |
4152 | pr_err("chip.cmd_ctrl() callback is not provided"); | |
4153 | return -EINVAL; | |
4154 | } | |
7aa65bfd | 4155 | /* Set the default functions */ |
29a198a1 | 4156 | nand_set_defaults(chip); |
7aa65bfd TG |
4157 | |
4158 | /* Read the flash type */ | |
7bb42799 | 4159 | ret = nand_detect(chip, table); |
4722c0e9 | 4160 | if (ret) { |
b1c6e6db | 4161 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 4162 | pr_warn("No NAND device found\n"); |
ace4dfee | 4163 | chip->select_chip(mtd, -1); |
4722c0e9 | 4164 | return ret; |
1da177e4 LT |
4165 | } |
4166 | ||
7f501f0a BB |
4167 | nand_maf_id = chip->id.data[0]; |
4168 | nand_dev_id = chip->id.data[1]; | |
4169 | ||
07300164 HS |
4170 | chip->select_chip(mtd, -1); |
4171 | ||
7aa65bfd | 4172 | /* Check for a chip array */ |
e0c7d767 | 4173 | for (i = 1; i < maxchips; i++) { |
ef89a880 | 4174 | /* See comment in nand_get_flash_type for reset */ |
73f907fd BB |
4175 | nand_reset(chip, i); |
4176 | ||
4177 | chip->select_chip(mtd, i); | |
1da177e4 | 4178 | /* Send the command for reading device ID */ |
ace4dfee | 4179 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 4180 | /* Read manufacturer and device IDs */ |
ace4dfee | 4181 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
4182 | nand_dev_id != chip->read_byte(mtd)) { |
4183 | chip->select_chip(mtd, -1); | |
1da177e4 | 4184 | break; |
07300164 HS |
4185 | } |
4186 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4187 | } |
4188 | if (i > 1) | |
20171642 | 4189 | pr_info("%d chips detected\n", i); |
61b03bd7 | 4190 | |
1da177e4 | 4191 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
4192 | chip->numchips = i; |
4193 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 4194 | |
3b85c321 DW |
4195 | return 0; |
4196 | } | |
7351d3a5 | 4197 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 4198 | |
06f384c9 RM |
4199 | static int nand_set_ecc_soft_ops(struct mtd_info *mtd) |
4200 | { | |
4201 | struct nand_chip *chip = mtd_to_nand(mtd); | |
4202 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4203 | ||
e4225ae8 | 4204 | if (WARN_ON(ecc->mode != NAND_ECC_SOFT)) |
06f384c9 RM |
4205 | return -EINVAL; |
4206 | ||
4207 | switch (ecc->algo) { | |
4208 | case NAND_ECC_HAMMING: | |
4209 | ecc->calculate = nand_calculate_ecc; | |
4210 | ecc->correct = nand_correct_data; | |
4211 | ecc->read_page = nand_read_page_swecc; | |
4212 | ecc->read_subpage = nand_read_subpage; | |
4213 | ecc->write_page = nand_write_page_swecc; | |
4214 | ecc->read_page_raw = nand_read_page_raw; | |
4215 | ecc->write_page_raw = nand_write_page_raw; | |
4216 | ecc->read_oob = nand_read_oob_std; | |
4217 | ecc->write_oob = nand_write_oob_std; | |
4218 | if (!ecc->size) | |
4219 | ecc->size = 256; | |
4220 | ecc->bytes = 3; | |
4221 | ecc->strength = 1; | |
4222 | return 0; | |
4223 | case NAND_ECC_BCH: | |
4224 | if (!mtd_nand_has_bch()) { | |
4225 | WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
4226 | return -EINVAL; | |
4227 | } | |
4228 | ecc->calculate = nand_bch_calculate_ecc; | |
4229 | ecc->correct = nand_bch_correct_data; | |
4230 | ecc->read_page = nand_read_page_swecc; | |
4231 | ecc->read_subpage = nand_read_subpage; | |
4232 | ecc->write_page = nand_write_page_swecc; | |
4233 | ecc->read_page_raw = nand_read_page_raw; | |
4234 | ecc->write_page_raw = nand_write_page_raw; | |
4235 | ecc->read_oob = nand_read_oob_std; | |
4236 | ecc->write_oob = nand_write_oob_std; | |
8bbba481 | 4237 | |
06f384c9 RM |
4238 | /* |
4239 | * Board driver should supply ecc.size and ecc.strength | |
4240 | * values to select how many bits are correctable. | |
4241 | * Otherwise, default to 4 bits for large page devices. | |
4242 | */ | |
4243 | if (!ecc->size && (mtd->oobsize >= 64)) { | |
4244 | ecc->size = 512; | |
4245 | ecc->strength = 4; | |
4246 | } | |
4247 | ||
4248 | /* | |
4249 | * if no ecc placement scheme was provided pickup the default | |
4250 | * large page one. | |
4251 | */ | |
4252 | if (!mtd->ooblayout) { | |
4253 | /* handle large page devices only */ | |
4254 | if (mtd->oobsize < 64) { | |
4255 | WARN(1, "OOB layout is required when using software BCH on small pages\n"); | |
4256 | return -EINVAL; | |
4257 | } | |
4258 | ||
4259 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); | |
8bbba481 BB |
4260 | |
4261 | } | |
4262 | ||
4263 | /* | |
4264 | * We can only maximize ECC config when the default layout is | |
4265 | * used, otherwise we don't know how many bytes can really be | |
4266 | * used. | |
4267 | */ | |
4268 | if (mtd->ooblayout == &nand_ooblayout_lp_ops && | |
4269 | ecc->options & NAND_ECC_MAXIMIZE) { | |
4270 | int steps, bytes; | |
4271 | ||
4272 | /* Always prefer 1k blocks over 512bytes ones */ | |
4273 | ecc->size = 1024; | |
4274 | steps = mtd->writesize / ecc->size; | |
4275 | ||
4276 | /* Reserve 2 bytes for the BBM */ | |
4277 | bytes = (mtd->oobsize - 2) / steps; | |
4278 | ecc->strength = bytes * 8 / fls(8 * ecc->size); | |
06f384c9 RM |
4279 | } |
4280 | ||
4281 | /* See nand_bch_init() for details. */ | |
4282 | ecc->bytes = 0; | |
4283 | ecc->priv = nand_bch_init(mtd); | |
4284 | if (!ecc->priv) { | |
4285 | WARN(1, "BCH ECC initialization failed!\n"); | |
4286 | return -EINVAL; | |
4287 | } | |
4288 | return 0; | |
4289 | default: | |
4290 | WARN(1, "Unsupported ECC algorithm!\n"); | |
4291 | return -EINVAL; | |
4292 | } | |
4293 | } | |
4294 | ||
2c8f8afa MY |
4295 | /** |
4296 | * nand_check_ecc_caps - check the sanity of preset ECC settings | |
4297 | * @chip: nand chip info structure | |
4298 | * @caps: ECC caps info structure | |
4299 | * @oobavail: OOB size that the ECC engine can use | |
4300 | * | |
4301 | * When ECC step size and strength are already set, check if they are supported | |
4302 | * by the controller and the calculated ECC bytes fit within the chip's OOB. | |
4303 | * On success, the calculated ECC bytes is set. | |
4304 | */ | |
4305 | int nand_check_ecc_caps(struct nand_chip *chip, | |
4306 | const struct nand_ecc_caps *caps, int oobavail) | |
4307 | { | |
4308 | struct mtd_info *mtd = nand_to_mtd(chip); | |
4309 | const struct nand_ecc_step_info *stepinfo; | |
4310 | int preset_step = chip->ecc.size; | |
4311 | int preset_strength = chip->ecc.strength; | |
4312 | int nsteps, ecc_bytes; | |
4313 | int i, j; | |
4314 | ||
4315 | if (WARN_ON(oobavail < 0)) | |
4316 | return -EINVAL; | |
4317 | ||
4318 | if (!preset_step || !preset_strength) | |
4319 | return -ENODATA; | |
4320 | ||
4321 | nsteps = mtd->writesize / preset_step; | |
4322 | ||
4323 | for (i = 0; i < caps->nstepinfos; i++) { | |
4324 | stepinfo = &caps->stepinfos[i]; | |
4325 | ||
4326 | if (stepinfo->stepsize != preset_step) | |
4327 | continue; | |
4328 | ||
4329 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
4330 | if (stepinfo->strengths[j] != preset_strength) | |
4331 | continue; | |
4332 | ||
4333 | ecc_bytes = caps->calc_ecc_bytes(preset_step, | |
4334 | preset_strength); | |
4335 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
4336 | return ecc_bytes; | |
4337 | ||
4338 | if (ecc_bytes * nsteps > oobavail) { | |
4339 | pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", | |
4340 | preset_step, preset_strength); | |
4341 | return -ENOSPC; | |
4342 | } | |
4343 | ||
4344 | chip->ecc.bytes = ecc_bytes; | |
4345 | ||
4346 | return 0; | |
4347 | } | |
4348 | } | |
4349 | ||
4350 | pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", | |
4351 | preset_step, preset_strength); | |
4352 | ||
4353 | return -ENOTSUPP; | |
4354 | } | |
4355 | EXPORT_SYMBOL_GPL(nand_check_ecc_caps); | |
4356 | ||
4357 | /** | |
4358 | * nand_match_ecc_req - meet the chip's requirement with least ECC bytes | |
4359 | * @chip: nand chip info structure | |
4360 | * @caps: ECC engine caps info structure | |
4361 | * @oobavail: OOB size that the ECC engine can use | |
4362 | * | |
4363 | * If a chip's ECC requirement is provided, try to meet it with the least | |
4364 | * number of ECC bytes (i.e. with the largest number of OOB-free bytes). | |
4365 | * On success, the chosen ECC settings are set. | |
4366 | */ | |
4367 | int nand_match_ecc_req(struct nand_chip *chip, | |
4368 | const struct nand_ecc_caps *caps, int oobavail) | |
4369 | { | |
4370 | struct mtd_info *mtd = nand_to_mtd(chip); | |
4371 | const struct nand_ecc_step_info *stepinfo; | |
4372 | int req_step = chip->ecc_step_ds; | |
4373 | int req_strength = chip->ecc_strength_ds; | |
4374 | int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; | |
4375 | int best_step, best_strength, best_ecc_bytes; | |
4376 | int best_ecc_bytes_total = INT_MAX; | |
4377 | int i, j; | |
4378 | ||
4379 | if (WARN_ON(oobavail < 0)) | |
4380 | return -EINVAL; | |
4381 | ||
4382 | /* No information provided by the NAND chip */ | |
4383 | if (!req_step || !req_strength) | |
4384 | return -ENOTSUPP; | |
4385 | ||
4386 | /* number of correctable bits the chip requires in a page */ | |
4387 | req_corr = mtd->writesize / req_step * req_strength; | |
4388 | ||
4389 | for (i = 0; i < caps->nstepinfos; i++) { | |
4390 | stepinfo = &caps->stepinfos[i]; | |
4391 | step_size = stepinfo->stepsize; | |
4392 | ||
4393 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
4394 | strength = stepinfo->strengths[j]; | |
4395 | ||
4396 | /* | |
4397 | * If both step size and strength are smaller than the | |
4398 | * chip's requirement, it is not easy to compare the | |
4399 | * resulted reliability. | |
4400 | */ | |
4401 | if (step_size < req_step && strength < req_strength) | |
4402 | continue; | |
4403 | ||
4404 | if (mtd->writesize % step_size) | |
4405 | continue; | |
4406 | ||
4407 | nsteps = mtd->writesize / step_size; | |
4408 | ||
4409 | ecc_bytes = caps->calc_ecc_bytes(step_size, strength); | |
4410 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
4411 | continue; | |
4412 | ecc_bytes_total = ecc_bytes * nsteps; | |
4413 | ||
4414 | if (ecc_bytes_total > oobavail || | |
4415 | strength * nsteps < req_corr) | |
4416 | continue; | |
4417 | ||
4418 | /* | |
4419 | * We assume the best is to meet the chip's requrement | |
4420 | * with the least number of ECC bytes. | |
4421 | */ | |
4422 | if (ecc_bytes_total < best_ecc_bytes_total) { | |
4423 | best_ecc_bytes_total = ecc_bytes_total; | |
4424 | best_step = step_size; | |
4425 | best_strength = strength; | |
4426 | best_ecc_bytes = ecc_bytes; | |
4427 | } | |
4428 | } | |
4429 | } | |
4430 | ||
4431 | if (best_ecc_bytes_total == INT_MAX) | |
4432 | return -ENOTSUPP; | |
4433 | ||
4434 | chip->ecc.size = best_step; | |
4435 | chip->ecc.strength = best_strength; | |
4436 | chip->ecc.bytes = best_ecc_bytes; | |
4437 | ||
4438 | return 0; | |
4439 | } | |
4440 | EXPORT_SYMBOL_GPL(nand_match_ecc_req); | |
4441 | ||
4442 | /** | |
4443 | * nand_maximize_ecc - choose the max ECC strength available | |
4444 | * @chip: nand chip info structure | |
4445 | * @caps: ECC engine caps info structure | |
4446 | * @oobavail: OOB size that the ECC engine can use | |
4447 | * | |
4448 | * Choose the max ECC strength that is supported on the controller, and can fit | |
4449 | * within the chip's OOB. On success, the chosen ECC settings are set. | |
4450 | */ | |
4451 | int nand_maximize_ecc(struct nand_chip *chip, | |
4452 | const struct nand_ecc_caps *caps, int oobavail) | |
4453 | { | |
4454 | struct mtd_info *mtd = nand_to_mtd(chip); | |
4455 | const struct nand_ecc_step_info *stepinfo; | |
4456 | int step_size, strength, nsteps, ecc_bytes, corr; | |
4457 | int best_corr = 0; | |
4458 | int best_step = 0; | |
4459 | int best_strength, best_ecc_bytes; | |
4460 | int i, j; | |
4461 | ||
4462 | if (WARN_ON(oobavail < 0)) | |
4463 | return -EINVAL; | |
4464 | ||
4465 | for (i = 0; i < caps->nstepinfos; i++) { | |
4466 | stepinfo = &caps->stepinfos[i]; | |
4467 | step_size = stepinfo->stepsize; | |
4468 | ||
4469 | /* If chip->ecc.size is already set, respect it */ | |
4470 | if (chip->ecc.size && step_size != chip->ecc.size) | |
4471 | continue; | |
4472 | ||
4473 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
4474 | strength = stepinfo->strengths[j]; | |
4475 | ||
4476 | if (mtd->writesize % step_size) | |
4477 | continue; | |
4478 | ||
4479 | nsteps = mtd->writesize / step_size; | |
4480 | ||
4481 | ecc_bytes = caps->calc_ecc_bytes(step_size, strength); | |
4482 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
4483 | continue; | |
4484 | ||
4485 | if (ecc_bytes * nsteps > oobavail) | |
4486 | continue; | |
4487 | ||
4488 | corr = strength * nsteps; | |
4489 | ||
4490 | /* | |
4491 | * If the number of correctable bits is the same, | |
4492 | * bigger step_size has more reliability. | |
4493 | */ | |
4494 | if (corr > best_corr || | |
4495 | (corr == best_corr && step_size > best_step)) { | |
4496 | best_corr = corr; | |
4497 | best_step = step_size; | |
4498 | best_strength = strength; | |
4499 | best_ecc_bytes = ecc_bytes; | |
4500 | } | |
4501 | } | |
4502 | } | |
4503 | ||
4504 | if (!best_corr) | |
4505 | return -ENOTSUPP; | |
4506 | ||
4507 | chip->ecc.size = best_step; | |
4508 | chip->ecc.strength = best_strength; | |
4509 | chip->ecc.bytes = best_ecc_bytes; | |
4510 | ||
4511 | return 0; | |
4512 | } | |
4513 | EXPORT_SYMBOL_GPL(nand_maximize_ecc); | |
4514 | ||
67a9ad9b EG |
4515 | /* |
4516 | * Check if the chip configuration meet the datasheet requirements. | |
4517 | ||
4518 | * If our configuration corrects A bits per B bytes and the minimum | |
4519 | * required correction level is X bits per Y bytes, then we must ensure | |
4520 | * both of the following are true: | |
4521 | * | |
4522 | * (1) A / B >= X / Y | |
4523 | * (2) A >= X | |
4524 | * | |
4525 | * Requirement (1) ensures we can correct for the required bitflip density. | |
4526 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
4527 | * in the same sector. | |
4528 | */ | |
4529 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
4530 | { | |
862eba51 | 4531 | struct nand_chip *chip = mtd_to_nand(mtd); |
67a9ad9b EG |
4532 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
4533 | int corr, ds_corr; | |
4534 | ||
4535 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
4536 | /* Not enough information */ | |
4537 | return true; | |
4538 | ||
4539 | /* | |
4540 | * We get the number of corrected bits per page to compare | |
4541 | * the correction density. | |
4542 | */ | |
4543 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
4544 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
4545 | ||
4546 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
4547 | } | |
3b85c321 | 4548 | |
3371d663 MG |
4549 | static bool invalid_ecc_page_accessors(struct nand_chip *chip) |
4550 | { | |
4551 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4552 | ||
4553 | if (nand_standard_page_accessors(ecc)) | |
4554 | return false; | |
4555 | ||
4556 | /* | |
4557 | * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND | |
4558 | * controller driver implements all the page accessors because | |
4559 | * default helpers are not suitable when the core does not | |
4560 | * send the READ0/PAGEPROG commands. | |
4561 | */ | |
4562 | return (!ecc->read_page || !ecc->write_page || | |
4563 | !ecc->read_page_raw || !ecc->write_page_raw || | |
4564 | (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) || | |
4565 | (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage && | |
4566 | ecc->hwctl && ecc->calculate)); | |
4567 | } | |
4568 | ||
3b85c321 DW |
4569 | /** |
4570 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 4571 | * @mtd: MTD device structure |
3b85c321 | 4572 | * |
8b6e50c9 BN |
4573 | * This is the second phase of the normal nand_scan() function. It fills out |
4574 | * all the uninitialized function pointers with the defaults and scans for a | |
4575 | * bad block table if appropriate. | |
3b85c321 DW |
4576 | */ |
4577 | int nand_scan_tail(struct mtd_info *mtd) | |
4578 | { | |
862eba51 | 4579 | struct nand_chip *chip = mtd_to_nand(mtd); |
97de79e0 | 4580 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
3deb9979 | 4581 | struct nand_buffers *nbuf = NULL; |
f84674b8 | 4582 | int ret, i; |
3b85c321 | 4583 | |
e2414f4c | 4584 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
11eaf6df | 4585 | if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && |
78771049 | 4586 | !(chip->bbt_options & NAND_BBT_USE_FLASH))) { |
f84674b8 | 4587 | return -EINVAL; |
78771049 | 4588 | } |
e2414f4c | 4589 | |
3371d663 MG |
4590 | if (invalid_ecc_page_accessors(chip)) { |
4591 | pr_err("Invalid ECC page accessors setup\n"); | |
f84674b8 | 4592 | return -EINVAL; |
3371d663 MG |
4593 | } |
4594 | ||
f02ea4e6 | 4595 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3deb9979 | 4596 | nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL); |
f84674b8 BB |
4597 | if (!nbuf) |
4598 | return -ENOMEM; | |
3deb9979 MY |
4599 | |
4600 | nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL); | |
4601 | if (!nbuf->ecccalc) { | |
4602 | ret = -ENOMEM; | |
f84674b8 | 4603 | goto err_free_nbuf; |
3deb9979 MY |
4604 | } |
4605 | ||
4606 | nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL); | |
4607 | if (!nbuf->ecccode) { | |
4608 | ret = -ENOMEM; | |
f84674b8 | 4609 | goto err_free_nbuf; |
3deb9979 MY |
4610 | } |
4611 | ||
4612 | nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize, | |
4613 | GFP_KERNEL); | |
4614 | if (!nbuf->databuf) { | |
4615 | ret = -ENOMEM; | |
f84674b8 | 4616 | goto err_free_nbuf; |
3deb9979 | 4617 | } |
f02ea4e6 HS |
4618 | |
4619 | chip->buffers = nbuf; | |
f84674b8 BB |
4620 | } else if (!chip->buffers) { |
4621 | return -ENOMEM; | |
f02ea4e6 | 4622 | } |
4bf63fcb | 4623 | |
f84674b8 BB |
4624 | /* |
4625 | * FIXME: some NAND manufacturer drivers expect the first die to be | |
4626 | * selected when manufacturer->init() is called. They should be fixed | |
4627 | * to explictly select the relevant die when interacting with the NAND | |
4628 | * chip. | |
4629 | */ | |
4630 | chip->select_chip(mtd, 0); | |
4631 | ret = nand_manufacturer_init(chip); | |
4632 | chip->select_chip(mtd, -1); | |
4633 | if (ret) | |
4634 | goto err_free_nbuf; | |
4635 | ||
7dcdcbef | 4636 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 4637 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 4638 | |
7aa65bfd | 4639 | /* |
8b6e50c9 | 4640 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 4641 | */ |
06f384c9 | 4642 | if (!mtd->ooblayout && |
e4225ae8 | 4643 | !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) { |
61b03bd7 | 4644 | switch (mtd->oobsize) { |
1da177e4 | 4645 | case 8: |
1da177e4 | 4646 | case 16: |
41b207a7 | 4647 | mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); |
1da177e4 LT |
4648 | break; |
4649 | case 64: | |
81ec5364 | 4650 | case 128: |
6a623e07 | 4651 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops); |
81ec5364 | 4652 | break; |
1da177e4 | 4653 | default: |
882fd157 MR |
4654 | /* |
4655 | * Expose the whole OOB area to users if ECC_NONE | |
4656 | * is passed. We could do that for all kind of | |
4657 | * ->oobsize, but we must keep the old large/small | |
4658 | * page with ECC layout when ->oobsize <= 128 for | |
4659 | * compatibility reasons. | |
4660 | */ | |
4661 | if (ecc->mode == NAND_ECC_NONE) { | |
4662 | mtd_set_ooblayout(mtd, | |
4663 | &nand_ooblayout_lp_ops); | |
4664 | break; | |
4665 | } | |
4666 | ||
11eaf6df EG |
4667 | WARN(1, "No oob scheme defined for oobsize %d\n", |
4668 | mtd->oobsize); | |
4669 | ret = -EINVAL; | |
f84674b8 | 4670 | goto err_nand_manuf_cleanup; |
1da177e4 LT |
4671 | } |
4672 | } | |
61b03bd7 | 4673 | |
61b03bd7 | 4674 | /* |
8b6e50c9 | 4675 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 4676 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 4677 | */ |
956e944c | 4678 | |
97de79e0 | 4679 | switch (ecc->mode) { |
6e0cb135 SN |
4680 | case NAND_ECC_HW_OOB_FIRST: |
4681 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 4682 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
11eaf6df EG |
4683 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
4684 | ret = -EINVAL; | |
f84674b8 | 4685 | goto err_nand_manuf_cleanup; |
6e0cb135 | 4686 | } |
97de79e0 HS |
4687 | if (!ecc->read_page) |
4688 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 4689 | |
6dfc6d25 | 4690 | case NAND_ECC_HW: |
8b6e50c9 | 4691 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
4692 | if (!ecc->read_page) |
4693 | ecc->read_page = nand_read_page_hwecc; | |
4694 | if (!ecc->write_page) | |
4695 | ecc->write_page = nand_write_page_hwecc; | |
4696 | if (!ecc->read_page_raw) | |
4697 | ecc->read_page_raw = nand_read_page_raw; | |
4698 | if (!ecc->write_page_raw) | |
4699 | ecc->write_page_raw = nand_write_page_raw; | |
4700 | if (!ecc->read_oob) | |
4701 | ecc->read_oob = nand_read_oob_std; | |
4702 | if (!ecc->write_oob) | |
4703 | ecc->write_oob = nand_write_oob_std; | |
4704 | if (!ecc->read_subpage) | |
4705 | ecc->read_subpage = nand_read_subpage; | |
44991b3d | 4706 | if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) |
97de79e0 | 4707 | ecc->write_subpage = nand_write_subpage_hwecc; |
f5bbdacc | 4708 | |
6dfc6d25 | 4709 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
4710 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
4711 | (!ecc->read_page || | |
4712 | ecc->read_page == nand_read_page_hwecc || | |
4713 | !ecc->write_page || | |
4714 | ecc->write_page == nand_write_page_hwecc)) { | |
11eaf6df EG |
4715 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
4716 | ret = -EINVAL; | |
f84674b8 | 4717 | goto err_nand_manuf_cleanup; |
6dfc6d25 | 4718 | } |
8b6e50c9 | 4719 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
4720 | if (!ecc->read_page) |
4721 | ecc->read_page = nand_read_page_syndrome; | |
4722 | if (!ecc->write_page) | |
4723 | ecc->write_page = nand_write_page_syndrome; | |
4724 | if (!ecc->read_page_raw) | |
4725 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
4726 | if (!ecc->write_page_raw) | |
4727 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
4728 | if (!ecc->read_oob) | |
4729 | ecc->read_oob = nand_read_oob_syndrome; | |
4730 | if (!ecc->write_oob) | |
4731 | ecc->write_oob = nand_write_oob_syndrome; | |
4732 | ||
4733 | if (mtd->writesize >= ecc->size) { | |
4734 | if (!ecc->strength) { | |
11eaf6df EG |
4735 | WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); |
4736 | ret = -EINVAL; | |
f84674b8 | 4737 | goto err_nand_manuf_cleanup; |
e2788c98 | 4738 | } |
6dfc6d25 | 4739 | break; |
e2788c98 | 4740 | } |
2ac63d90 RM |
4741 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4742 | ecc->size, mtd->writesize); | |
97de79e0 | 4743 | ecc->mode = NAND_ECC_SOFT; |
e9d4faed | 4744 | ecc->algo = NAND_ECC_HAMMING; |
61b03bd7 | 4745 | |
6dfc6d25 | 4746 | case NAND_ECC_SOFT: |
06f384c9 RM |
4747 | ret = nand_set_ecc_soft_ops(mtd); |
4748 | if (ret) { | |
11eaf6df | 4749 | ret = -EINVAL; |
f84674b8 | 4750 | goto err_nand_manuf_cleanup; |
193bd400 ID |
4751 | } |
4752 | break; | |
4753 | ||
785818fa TP |
4754 | case NAND_ECC_ON_DIE: |
4755 | if (!ecc->read_page || !ecc->write_page) { | |
4756 | WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); | |
4757 | ret = -EINVAL; | |
f84674b8 | 4758 | goto err_nand_manuf_cleanup; |
785818fa TP |
4759 | } |
4760 | if (!ecc->read_oob) | |
4761 | ecc->read_oob = nand_read_oob_std; | |
4762 | if (!ecc->write_oob) | |
4763 | ecc->write_oob = nand_write_oob_std; | |
4764 | break; | |
4765 | ||
61b03bd7 | 4766 | case NAND_ECC_NONE: |
2ac63d90 | 4767 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4768 | ecc->read_page = nand_read_page_raw; |
4769 | ecc->write_page = nand_write_page_raw; | |
4770 | ecc->read_oob = nand_read_oob_std; | |
4771 | ecc->read_page_raw = nand_read_page_raw; | |
4772 | ecc->write_page_raw = nand_write_page_raw; | |
4773 | ecc->write_oob = nand_write_oob_std; | |
4774 | ecc->size = mtd->writesize; | |
4775 | ecc->bytes = 0; | |
4776 | ecc->strength = 0; | |
1da177e4 | 4777 | break; |
956e944c | 4778 | |
1da177e4 | 4779 | default: |
11eaf6df EG |
4780 | WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode); |
4781 | ret = -EINVAL; | |
f84674b8 | 4782 | goto err_nand_manuf_cleanup; |
1da177e4 | 4783 | } |
61b03bd7 | 4784 | |
9ce244b3 | 4785 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4786 | if (!ecc->read_oob_raw) |
4787 | ecc->read_oob_raw = ecc->read_oob; | |
4788 | if (!ecc->write_oob_raw) | |
4789 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4790 | |
846031d3 | 4791 | /* propagate ecc info to mtd_info */ |
846031d3 BB |
4792 | mtd->ecc_strength = ecc->strength; |
4793 | mtd->ecc_step_size = ecc->size; | |
67a9ad9b | 4794 | |
7aa65bfd TG |
4795 | /* |
4796 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4797 | * mode. |
7aa65bfd | 4798 | */ |
97de79e0 HS |
4799 | ecc->steps = mtd->writesize / ecc->size; |
4800 | if (ecc->steps * ecc->size != mtd->writesize) { | |
11eaf6df EG |
4801 | WARN(1, "Invalid ECC parameters\n"); |
4802 | ret = -EINVAL; | |
f84674b8 | 4803 | goto err_nand_manuf_cleanup; |
1da177e4 | 4804 | } |
97de79e0 | 4805 | ecc->total = ecc->steps * ecc->bytes; |
79e0348c MY |
4806 | if (ecc->total > mtd->oobsize) { |
4807 | WARN(1, "Total number of ECC bytes exceeded oobsize\n"); | |
4808 | ret = -EINVAL; | |
f84674b8 | 4809 | goto err_nand_manuf_cleanup; |
79e0348c | 4810 | } |
61b03bd7 | 4811 | |
846031d3 BB |
4812 | /* |
4813 | * The number of bytes available for a client to place data into | |
4814 | * the out of band area. | |
4815 | */ | |
4816 | ret = mtd_ooblayout_count_freebytes(mtd); | |
4817 | if (ret < 0) | |
4818 | ret = 0; | |
4819 | ||
4820 | mtd->oobavail = ret; | |
4821 | ||
4822 | /* ECC sanity check: warn if it's too weak */ | |
4823 | if (!nand_ecc_strength_good(mtd)) | |
4824 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
4825 | mtd->name); | |
4826 | ||
8b6e50c9 | 4827 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4828 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4829 | switch (ecc->steps) { |
29072b96 TG |
4830 | case 2: |
4831 | mtd->subpage_sft = 1; | |
4832 | break; | |
4833 | case 4: | |
4834 | case 8: | |
81ec5364 | 4835 | case 16: |
29072b96 TG |
4836 | mtd->subpage_sft = 2; |
4837 | break; | |
4838 | } | |
4839 | } | |
4840 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4841 | ||
04bbd0ea | 4842 | /* Initialize state */ |
ace4dfee | 4843 | chip->state = FL_READY; |
1da177e4 | 4844 | |
1da177e4 | 4845 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4846 | chip->pagebuf = -1; |
1da177e4 | 4847 | |
a5ff4f10 | 4848 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4849 | switch (ecc->mode) { |
4850 | case NAND_ECC_SOFT: | |
4007e2d1 RL |
4851 | if (chip->page_shift > 9) |
4852 | chip->options |= NAND_SUBPAGE_READ; | |
4853 | break; | |
4854 | ||
4855 | default: | |
4856 | break; | |
4857 | } | |
a5ff4f10 | 4858 | |
1da177e4 | 4859 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4860 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4861 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4862 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4863 | mtd->_erase = nand_erase; |
4864 | mtd->_point = NULL; | |
4865 | mtd->_unpoint = NULL; | |
3c3c10bb AB |
4866 | mtd->_panic_write = panic_nand_write; |
4867 | mtd->_read_oob = nand_read_oob; | |
4868 | mtd->_write_oob = nand_write_oob; | |
4869 | mtd->_sync = nand_sync; | |
4870 | mtd->_lock = NULL; | |
4871 | mtd->_unlock = NULL; | |
4872 | mtd->_suspend = nand_suspend; | |
4873 | mtd->_resume = nand_resume; | |
72ea4036 | 4874 | mtd->_reboot = nand_shutdown; |
8471bb73 | 4875 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4876 | mtd->_block_isbad = nand_block_isbad; |
4877 | mtd->_block_markbad = nand_block_markbad; | |
5671842f | 4878 | mtd->_max_bad_blocks = nand_max_bad_blocks; |
cbcab65a | 4879 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4880 | |
ea3b2ea2 SL |
4881 | /* |
4882 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4883 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4884 | * properly set. | |
4885 | */ | |
4886 | if (!mtd->bitflip_threshold) | |
240181fd | 4887 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 4888 | |
f84674b8 BB |
4889 | /* Initialize the ->data_interface field. */ |
4890 | ret = nand_init_data_interface(chip); | |
4891 | if (ret) | |
4892 | goto err_nand_manuf_cleanup; | |
4893 | ||
4894 | /* Enter fastest possible mode on all dies. */ | |
4895 | for (i = 0; i < chip->numchips; i++) { | |
4896 | chip->select_chip(mtd, i); | |
4897 | ret = nand_setup_data_interface(chip, i); | |
4898 | chip->select_chip(mtd, -1); | |
4899 | ||
4900 | if (ret) | |
4901 | goto err_nand_data_iface_cleanup; | |
4902 | } | |
4903 | ||
0040bf38 | 4904 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4905 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4906 | return 0; |
1da177e4 LT |
4907 | |
4908 | /* Build bad block table */ | |
44d4182e BN |
4909 | ret = chip->scan_bbt(mtd); |
4910 | if (ret) | |
f84674b8 BB |
4911 | goto err_nand_data_iface_cleanup; |
4912 | ||
44d4182e BN |
4913 | return 0; |
4914 | ||
f84674b8 BB |
4915 | err_nand_data_iface_cleanup: |
4916 | nand_release_data_interface(chip); | |
4917 | ||
4918 | err_nand_manuf_cleanup: | |
4919 | nand_manufacturer_cleanup(chip); | |
4920 | ||
4921 | err_free_nbuf: | |
3deb9979 MY |
4922 | if (nbuf) { |
4923 | kfree(nbuf->databuf); | |
4924 | kfree(nbuf->ecccode); | |
4925 | kfree(nbuf->ecccalc); | |
4926 | kfree(nbuf); | |
4927 | } | |
78771049 | 4928 | |
11eaf6df | 4929 | return ret; |
1da177e4 | 4930 | } |
7351d3a5 | 4931 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4932 | |
8b6e50c9 BN |
4933 | /* |
4934 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4935 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4936 | * to call us from in-kernel code if the core NAND support is modular. |
4937 | */ | |
3b85c321 DW |
4938 | #ifdef MODULE |
4939 | #define caller_is_module() (1) | |
4940 | #else | |
4941 | #define caller_is_module() \ | |
a6e6abd5 | 4942 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4943 | #endif |
4944 | ||
4945 | /** | |
4946 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4947 | * @mtd: MTD device structure |
4948 | * @maxchips: number of chips to scan for | |
3b85c321 | 4949 | * |
8b6e50c9 BN |
4950 | * This fills out all the uninitialized function pointers with the defaults. |
4951 | * The flash ID is read and the mtd/chip structures are filled with the | |
20c07a5b | 4952 | * appropriate values. |
3b85c321 DW |
4953 | */ |
4954 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4955 | { | |
4956 | int ret; | |
4957 | ||
5e81e88a | 4958 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4959 | if (!ret) |
4960 | ret = nand_scan_tail(mtd); | |
4961 | return ret; | |
4962 | } | |
7351d3a5 | 4963 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4964 | |
1da177e4 | 4965 | /** |
d44154f9 RW |
4966 | * nand_cleanup - [NAND Interface] Free resources held by the NAND device |
4967 | * @chip: NAND chip object | |
8b6e50c9 | 4968 | */ |
d44154f9 | 4969 | void nand_cleanup(struct nand_chip *chip) |
1da177e4 | 4970 | { |
e4225ae8 | 4971 | if (chip->ecc.mode == NAND_ECC_SOFT && |
06f384c9 | 4972 | chip->ecc.algo == NAND_ECC_BCH) |
193bd400 ID |
4973 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); |
4974 | ||
d8e725dd BB |
4975 | nand_release_data_interface(chip); |
4976 | ||
fa671646 | 4977 | /* Free bad block table memory */ |
ace4dfee | 4978 | kfree(chip->bbt); |
3deb9979 MY |
4979 | if (!(chip->options & NAND_OWN_BUFFERS) && chip->buffers) { |
4980 | kfree(chip->buffers->databuf); | |
4981 | kfree(chip->buffers->ecccode); | |
4982 | kfree(chip->buffers->ecccalc); | |
4bf63fcb | 4983 | kfree(chip->buffers); |
3deb9979 | 4984 | } |
58373ff0 BN |
4985 | |
4986 | /* Free bad block descriptor memory */ | |
4987 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4988 | & NAND_BBT_DYNAMICSTRUCT) | |
4989 | kfree(chip->badblock_pattern); | |
abbe26d1 BB |
4990 | |
4991 | /* Free manufacturer priv data. */ | |
4992 | nand_manufacturer_cleanup(chip); | |
1da177e4 | 4993 | } |
d44154f9 RW |
4994 | EXPORT_SYMBOL_GPL(nand_cleanup); |
4995 | ||
4996 | /** | |
4997 | * nand_release - [NAND Interface] Unregister the MTD device and free resources | |
4998 | * held by the NAND device | |
4999 | * @mtd: MTD device structure | |
5000 | */ | |
5001 | void nand_release(struct mtd_info *mtd) | |
5002 | { | |
5003 | mtd_device_unregister(mtd); | |
5004 | nand_cleanup(mtd_to_nand(mtd)); | |
5005 | } | |
e0c7d767 | 5006 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 | 5007 | |
e0c7d767 | 5008 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
5009 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
5010 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 5011 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |