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mtd: mtd_oobtest: printk -> pr_{info,err,crit}
[linux-2.6-block.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
6fe5a6ac
VS		 126 return ret;
127}
128
1da177e4
LT		 129/**
130 * nand_release_device - [GENERIC] release chip
8b6e50c9 131 * @mtd: MTD device structure
61b03bd7 132 *
8b6e50c9 133 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 134 */
e0c7d767 135static void nand_release_device(struct mtd_info *mtd)
1da177e4 136{
ace4dfee 137 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 138
139 /* De-select the NAND device */
ace4dfee 140 chip->select_chip(mtd, -1);
0dfc6246 141
a36ed299 142 /* Release the controller and the chip */
ace4dfee
TG		 143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
1da177e4
LT		 148}
149
150/**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 152 * @mtd: MTD device structure
1da177e4 153 *
7854d3f7 154 * Default read function for 8bit buswidth
1da177e4 155 */
58dd8f2b 156static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 157{
ace4dfee
TG		 158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
1da177e4
LT		 160}
161
1da177e4
LT		 162/**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 165 * @mtd: MTD device structure
1da177e4 166 *
7854d3f7
BN		 167 * Default read function for 16bit buswidth with endianness conversion.
168 *
1da177e4 169 */
58dd8f2b 170static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 171{
ace4dfee
TG		 172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 174}
175
1da177e4
LT		 176/**
177 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 178 * @mtd: MTD device structure
1da177e4 179 *
7854d3f7 180 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 181 */
182static u16 nand_read_word(struct mtd_info *mtd)
183{
ace4dfee
TG		 184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
1da177e4
LT		 186}
187
1da177e4
LT		 188/**
189 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 192 *
193 * Default select function for 1 chip devices.
194 */
ace4dfee 195static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 196{
ace4dfee
TG		 197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
1da177e4 200 case -1:
ace4dfee 201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 202 break;
203 case 0:
1da177e4
LT		 204 break;
205
206 default:
207 BUG();
208 }
209}
210
211/**
212 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
1da177e4 216 *
7854d3f7 217 * Default write function for 8bit buswidth.
1da177e4 218 */
58dd8f2b 219static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 220{
221 int i;
ace4dfee 222 struct nand_chip *chip = mtd->priv;
1da177e4 223
e0c7d767 224 for (i = 0; i < len; i++)
ace4dfee 225 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 226}
227
228/**
61b03bd7 229 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
1da177e4 233 *
7854d3f7 234 * Default read function for 8bit buswidth.
1da177e4 235 */
58dd8f2b 236static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 237{
238 int i;
ace4dfee 239 struct nand_chip *chip = mtd->priv;
1da177e4 240
e0c7d767 241 for (i = 0; i < len; i++)
ace4dfee 242 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 243}
244
1da177e4
LT		 245/**
246 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 247 * @mtd: MTD device structure
248 * @buf: data buffer
249 * @len: number of bytes to write
1da177e4 250 *
7854d3f7 251 * Default write function for 16bit buswidth.
1da177e4 252 */
58dd8f2b 253static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 254{
255 int i;
ace4dfee 256 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 257 u16 *p = (u16 *) buf;
258 len >>= 1;
61b03bd7 259
e0c7d767 260 for (i = 0; i < len; i++)
ace4dfee 261 writew(p[i], chip->IO_ADDR_W);
61b03bd7 262
1da177e4
LT		 263}
264
265/**
61b03bd7 266 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
1da177e4 270 *
7854d3f7 271 * Default read function for 16bit buswidth.
1da177e4 272 */
58dd8f2b 273static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 274{
275 int i;
ace4dfee 276 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 277 u16 *p = (u16 *) buf;
278 len >>= 1;
279
e0c7d767 280 for (i = 0; i < len; i++)
ace4dfee 281 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 282}
283
1da177e4
LT		 284/**
285 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 286 * @mtd: MTD device structure
287 * @ofs: offset from device start
288 * @getchip: 0, if the chip is already selected
1da177e4 289 *
61b03bd7 290 * Check, if the block is bad.
1da177e4
LT		 291 */
292static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
293{
cdbec050 294 int page, chipnr, res = 0, i = 0;
ace4dfee 295 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 296 u16 bad;
297
5fb1549d 298 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 299 ofs += mtd->erasesize - mtd->writesize;
300
1a12f46a
TK		 301 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
302
1da177e4 303 if (getchip) {
ace4dfee 304 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 305
ace4dfee 306 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 307
308 /* Select the NAND device */
ace4dfee 309 chip->select_chip(mtd, chipnr);
1a12f46a 310 }
1da177e4 311
cdbec050
BN		 312 do {
313 if (chip->options & NAND_BUSWIDTH_16) {
314 chip->cmdfunc(mtd, NAND_CMD_READOOB,
315 chip->badblockpos & 0xFE, page);
316 bad = cpu_to_le16(chip->read_word(mtd));
317 if (chip->badblockpos & 0x1)
318 bad >>= 8;
319 else
320 bad &= 0xFF;
321 } else {
322 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
323 page);
324 bad = chip->read_byte(mtd);
325 }
326
327 if (likely(chip->badblockbits == 8))
328 res = bad != 0xFF;
e0b58d0a 329 else
cdbec050
BN		 330 res = hweight8(bad) < chip->badblockbits;
331 ofs += mtd->writesize;
332 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
333 i++;
334 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 335
ace4dfee 336 if (getchip)
1da177e4 337 nand_release_device(mtd);
61b03bd7 338
1da177e4
LT		 339 return res;
340}
341
342/**
343 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 344 * @mtd: MTD device structure
345 * @ofs: offset from device start
1da177e4 346 *
8b6e50c9 347 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 348 * specific driver. We try operations in the following order, according to our
349 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
350 * (1) erase the affected block, to allow OOB marker to be written cleanly
351 * (2) update in-memory BBT
352 * (3) write bad block marker to OOB area of affected block
353 * (4) update flash-based BBT
354 * Note that we retain the first error encountered in (3) or (4), finish the
355 * procedures, and dump the error in the end.
1da177e4
LT		 356*/
357static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
358{
ace4dfee 359 struct nand_chip *chip = mtd->priv;
58dd8f2b 360 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 361 int block, res, ret = 0, i = 0;
362 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 363
e2414f4c 364 if (write_oob) {
00918429
BN		 365 struct erase_info einfo;
366
367 /* Attempt erase before marking OOB */
368 memset(&einfo, 0, sizeof(einfo));
369 einfo.mtd = mtd;
370 einfo.addr = ofs;
371 einfo.len = 1 << chip->phys_erase_shift;
372 nand_erase_nand(mtd, &einfo, 0);
373 }
374
1da177e4 375 /* Get block number */
4226b510 376 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 377 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 378 if (chip->bbt)
379 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 380
e2414f4c
BN		 381 /* Write bad block marker to OOB */
382 if (write_oob) {
4a89ff88 383 struct mtd_oob_ops ops;
df698621 384 loff_t wr_ofs = ofs;
4a89ff88 385
c0b8ba7b 386 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 387
4a89ff88
BN		 388 ops.datbuf = NULL;
389 ops.oobbuf = buf;
85443319
BN		 390 ops.ooboffs = chip->badblockpos;
391 if (chip->options & NAND_BUSWIDTH_16) {
392 ops.ooboffs &= ~0x01;
393 ops.len = ops.ooblen = 2;
394 } else {
395 ops.len = ops.ooblen = 1;
396 }
23b1a99b 397 ops.mode = MTD_OPS_PLACE_OOB;
df698621 398
e2414f4c 399 /* Write to first/last page(s) if necessary */
df698621
BN		 400 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
401 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 402 do {
e2414f4c
BN		 403 res = nand_do_write_oob(mtd, wr_ofs, &ops);
404 if (!ret)
405 ret = res;
02ed70bb 406
02ed70bb 407 i++;
df698621 408 wr_ofs += mtd->writesize;
e2414f4c 409 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 410
c0b8ba7b 411 nand_release_device(mtd);
f1a28c02 412 }
e2414f4c
BN		 413
414 /* Update flash-based bad block table */
415 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
416 res = nand_update_bbt(mtd, ofs);
417 if (!ret)
418 ret = res;
419 }
420
f1a28c02
TG		 421 if (!ret)
422 mtd->ecc_stats.badblocks++;
c0b8ba7b 423
f1a28c02 424 return ret;
1da177e4
LT		 425}
426
61b03bd7 427/**
1da177e4 428 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 429 * @mtd: MTD device structure
1da177e4 430 *
8b6e50c9
BN		 431 * Check, if the device is write protected. The function expects, that the
432 * device is already selected.
1da177e4 433 */
e0c7d767 434static int nand_check_wp(struct mtd_info *mtd)
1da177e4 435{
ace4dfee 436 struct nand_chip *chip = mtd->priv;
93edbad6 437
8b6e50c9 438 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 439 if (chip->options & NAND_BROKEN_XD)
440 return 0;
441
1da177e4 442 /* Check the WP bit */
ace4dfee
TG		 443 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
444 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 445}
446
447/**
448 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 449 * @mtd: MTD device structure
450 * @ofs: offset from device start
451 * @getchip: 0, if the chip is already selected
452 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 453 *
454 * Check, if the block is bad. Either by reading the bad block table or
455 * calling of the scan function.
456 */
2c0a2bed
TG		 457static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
458 int allowbbt)
1da177e4 459{
ace4dfee 460 struct nand_chip *chip = mtd->priv;
61b03bd7 461
ace4dfee
TG		 462 if (!chip->bbt)
463 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 464
1da177e4 465 /* Return info from the table */
e0c7d767 466 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 467}
468
2af7c653
SK		 469/**
470 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 471 * @mtd: MTD device structure
472 * @timeo: Timeout
2af7c653
SK		 473 *
474 * Helper function for nand_wait_ready used when needing to wait in interrupt
475 * context.
476 */
477static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
478{
479 struct nand_chip *chip = mtd->priv;
480 int i;
481
482 /* Wait for the device to get ready */
483 for (i = 0; i < timeo; i++) {
484 if (chip->dev_ready(mtd))
485 break;
486 touch_softlockup_watchdog();
487 mdelay(1);
488 }
489}
490
7854d3f7 491/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 492void nand_wait_ready(struct mtd_info *mtd)
3b88775c 493{
ace4dfee 494 struct nand_chip *chip = mtd->priv;
e0c7d767 495 unsigned long timeo = jiffies + 2;
3b88775c 496
2af7c653
SK		 497 /* 400ms timeout */
498 if (in_interrupt() || oops_in_progress)
499 return panic_nand_wait_ready(mtd, 400);
500
8fe833c1 501 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 502 /* Wait until command is processed or timeout occurs */
3b88775c 503 do {
ace4dfee 504 if (chip->dev_ready(mtd))
8fe833c1 505 break;
8446f1d3 506 touch_softlockup_watchdog();
61b03bd7 507 } while (time_before(jiffies, timeo));
8fe833c1 508 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 509}
4b648b02 510EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 511
1da177e4
LT		 512/**
513 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 514 * @mtd: MTD device structure
515 * @command: the command to be sent
516 * @column: the column address for this command, -1 if none
517 * @page_addr: the page address for this command, -1 if none
1da177e4 518 *
8b6e50c9
BN		 519 * Send command to NAND device. This function is used for small page devices
520 * (256/512 Bytes per page).
1da177e4 521 */
7abd3ef9
TG		 522static void nand_command(struct mtd_info *mtd, unsigned int command,
523 int column, int page_addr)
1da177e4 524{
ace4dfee 525 register struct nand_chip *chip = mtd->priv;
7abd3ef9 526 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 527
8b6e50c9 528 /* Write out the command to the device */
1da177e4
LT		 529 if (command == NAND_CMD_SEQIN) {
530 int readcmd;
531
28318776 532 if (column >= mtd->writesize) {
1da177e4 533 /* OOB area */
28318776 534 column -= mtd->writesize;
1da177e4
LT		 535 readcmd = NAND_CMD_READOOB;
536 } else if (column < 256) {
537 /* First 256 bytes --> READ0 */
538 readcmd = NAND_CMD_READ0;
539 } else {
540 column -= 256;
541 readcmd = NAND_CMD_READ1;
542 }
ace4dfee 543 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 544 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 545 }
ace4dfee 546 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 547
8b6e50c9 548 /* Address cycle, when necessary */
7abd3ef9
TG		 549 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
550 /* Serially input address */
551 if (column != -1) {
552 /* Adjust columns for 16 bit buswidth */
ace4dfee 553 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 554 column >>= 1;
ace4dfee 555 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 556 ctrl &= ~NAND_CTRL_CHANGE;
557 }
558 if (page_addr != -1) {
ace4dfee 559 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 560 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 561 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 562 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 563 if (chip->chipsize > (32 << 20))
564 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 565 }
ace4dfee 566 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 567
568 /*
8b6e50c9
BN		 569 * Program and erase have their own busy handlers status and sequential
570 * in needs no delay
e0c7d767 571 */
1da177e4 572 switch (command) {
61b03bd7 573
1da177e4
LT		 574 case NAND_CMD_PAGEPROG:
575 case NAND_CMD_ERASE1:
576 case NAND_CMD_ERASE2:
577 case NAND_CMD_SEQIN:
578 case NAND_CMD_STATUS:
579 return;
580
581 case NAND_CMD_RESET:
ace4dfee 582 if (chip->dev_ready)
1da177e4 583 break;
ace4dfee
TG		 584 udelay(chip->chip_delay);
585 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 586 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 587 chip->cmd_ctrl(mtd,
588 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 589 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
590 ;
1da177e4
LT		 591 return;
592
e0c7d767 593 /* This applies to read commands */
1da177e4 594 default:
61b03bd7 595 /*
1da177e4
LT		 596 * If we don't have access to the busy pin, we apply the given
597 * command delay
e0c7d767 598 */
ace4dfee
TG		 599 if (!chip->dev_ready) {
600 udelay(chip->chip_delay);
1da177e4 601 return;
61b03bd7 602 }
1da177e4 603 }
8b6e50c9
BN		 604 /*
605 * Apply this short delay always to ensure that we do wait tWB in
606 * any case on any machine.
607 */
e0c7d767 608 ndelay(100);
3b88775c
TG		 609
610 nand_wait_ready(mtd);
1da177e4
LT		 611}
612
613/**
614 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 615 * @mtd: MTD device structure
616 * @command: the command to be sent
617 * @column: the column address for this command, -1 if none
618 * @page_addr: the page address for this command, -1 if none
1da177e4 619 *
7abd3ef9 620 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 621 * devices. We don't have the separate regions as we have in the small page
622 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 623 */
7abd3ef9
TG		 624static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
625 int column, int page_addr)
1da177e4 626{
ace4dfee 627 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 628
629 /* Emulate NAND_CMD_READOOB */
630 if (command == NAND_CMD_READOOB) {
28318776 631 column += mtd->writesize;
1da177e4
LT		 632 command = NAND_CMD_READ0;
633 }
61b03bd7 634
7abd3ef9 635 /* Command latch cycle */
ace4dfee 636 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 637 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 638
639 if (column != -1 || page_addr != -1) {
7abd3ef9 640 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 641
642 /* Serially input address */
643 if (column != -1) {
644 /* Adjust columns for 16 bit buswidth */
ace4dfee 645 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 646 column >>= 1;
ace4dfee 647 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 648 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 649 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 650 }
1da177e4 651 if (page_addr != -1) {
ace4dfee
TG		 652 chip->cmd_ctrl(mtd, page_addr, ctrl);
653 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 654 NAND_NCE | NAND_ALE);
1da177e4 655 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 656 if (chip->chipsize > (128 << 20))
657 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 658 NAND_NCE | NAND_ALE);
1da177e4 659 }
1da177e4 660 }
ace4dfee 661 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 662
663 /*
8b6e50c9
BN		 664 * Program and erase have their own busy handlers status, sequential
665 * in, and deplete1 need no delay.
30f464b7 666 */
1da177e4 667 switch (command) {
61b03bd7 668
1da177e4
LT		 669 case NAND_CMD_CACHEDPROG:
670 case NAND_CMD_PAGEPROG:
671 case NAND_CMD_ERASE1:
672 case NAND_CMD_ERASE2:
673 case NAND_CMD_SEQIN:
7bc3312b 674 case NAND_CMD_RNDIN:
1da177e4 675 case NAND_CMD_STATUS:
30f464b7 676 case NAND_CMD_DEPLETE1:
1da177e4
LT		 677 return;
678
30f464b7
DM		 679 case NAND_CMD_STATUS_ERROR:
680 case NAND_CMD_STATUS_ERROR0:
681 case NAND_CMD_STATUS_ERROR1:
682 case NAND_CMD_STATUS_ERROR2:
683 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 684 /* Read error status commands require only a short delay */
ace4dfee 685 udelay(chip->chip_delay);
30f464b7 686 return;
1da177e4
LT		 687
688 case NAND_CMD_RESET:
ace4dfee 689 if (chip->dev_ready)
1da177e4 690 break;
ace4dfee 691 udelay(chip->chip_delay);
12efdde3
TG		 692 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
693 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
694 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
695 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 696 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
697 ;
1da177e4
LT		 698 return;
699
7bc3312b
TG		 700 case NAND_CMD_RNDOUT:
701 /* No ready / busy check necessary */
702 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
703 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
704 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
705 NAND_NCE | NAND_CTRL_CHANGE);
706 return;
707
1da177e4 708 case NAND_CMD_READ0:
12efdde3
TG		 709 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
710 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
711 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
712 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 713
e0c7d767 714 /* This applies to read commands */
1da177e4 715 default:
61b03bd7 716 /*
1da177e4 717 * If we don't have access to the busy pin, we apply the given
8b6e50c9 718 * command delay.
e0c7d767 719 */
ace4dfee
TG		 720 if (!chip->dev_ready) {
721 udelay(chip->chip_delay);
1da177e4 722 return;
61b03bd7 723 }
1da177e4 724 }
3b88775c 725
8b6e50c9
BN		 726 /*
727 * Apply this short delay always to ensure that we do wait tWB in
728 * any case on any machine.
729 */
e0c7d767 730 ndelay(100);
3b88775c
TG		 731
732 nand_wait_ready(mtd);
1da177e4
LT		 733}
734
2af7c653
SK		 735/**
736 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 737 * @chip: the nand chip descriptor
738 * @mtd: MTD device structure
739 * @new_state: the state which is requested
2af7c653
SK		 740 *
741 * Used when in panic, no locks are taken.
742 */
743static void panic_nand_get_device(struct nand_chip *chip,
744 struct mtd_info *mtd, int new_state)
745{
7854d3f7 746 /* Hardware controller shared among independent devices */
2af7c653
SK		 747 chip->controller->active = chip;
748 chip->state = new_state;
749}
750
1da177e4
LT		 751/**
752 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 753 * @chip: the nand chip descriptor
754 * @mtd: MTD device structure
755 * @new_state: the state which is requested
1da177e4
LT		 756 *
757 * Get the device and lock it for exclusive access
758 */
2c0a2bed 759static int
ace4dfee 760nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 761{
ace4dfee
TG		 762 spinlock_t *lock = &chip->controller->lock;
763 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 764 DECLARE_WAITQUEUE(wait, current);
7351d3a5 765retry:
0dfc6246
TG		 766 spin_lock(lock);
767
b8b3ee9a 768 /* Hardware controller shared among independent devices */
ace4dfee
TG		 769 if (!chip->controller->active)
770 chip->controller->active = chip;
a36ed299 771
ace4dfee
TG		 772 if (chip->controller->active == chip && chip->state == FL_READY) {
773 chip->state = new_state;
0dfc6246 774 spin_unlock(lock);
962034f4
VW		 775 return 0;
776 }
777 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 778 if (chip->controller->active->state == FL_PM_SUSPENDED) {
779 chip->state = FL_PM_SUSPENDED;
780 spin_unlock(lock);
781 return 0;
6b0d9a84 782 }
0dfc6246
TG		 783 }
784 set_current_state(TASK_UNINTERRUPTIBLE);
785 add_wait_queue(wq, &wait);
786 spin_unlock(lock);
787 schedule();
788 remove_wait_queue(wq, &wait);
1da177e4
LT		 789 goto retry;
790}
791
2af7c653 792/**
8b6e50c9
BN		 793 * panic_nand_wait - [GENERIC] wait until the command is done
794 * @mtd: MTD device structure
795 * @chip: NAND chip structure
796 * @timeo: timeout
2af7c653
SK		 797 *
798 * Wait for command done. This is a helper function for nand_wait used when
799 * we are in interrupt context. May happen when in panic and trying to write
b595076a 800 * an oops through mtdoops.
2af7c653
SK		 801 */
802static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
803 unsigned long timeo)
804{
805 int i;
806 for (i = 0; i < timeo; i++) {
807 if (chip->dev_ready) {
808 if (chip->dev_ready(mtd))
809 break;
810 } else {
811 if (chip->read_byte(mtd) & NAND_STATUS_READY)
812 break;
813 }
814 mdelay(1);
f8ac0414 815 }
2af7c653
SK		 816}
817
1da177e4 818/**
8b6e50c9
BN		 819 * nand_wait - [DEFAULT] wait until the command is done
820 * @mtd: MTD device structure
821 * @chip: NAND chip structure
1da177e4 822 *
8b6e50c9
BN		 823 * Wait for command done. This applies to erase and program only. Erase can
824 * take up to 400ms and program up to 20ms according to general NAND and
825 * SmartMedia specs.
844d3b42 826 */
7bc3312b 827static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 828{
829
e0c7d767 830 unsigned long timeo = jiffies;
7bc3312b 831 int status, state = chip->state;
61b03bd7 832
1da177e4 833 if (state == FL_ERASING)
e0c7d767 834 timeo += (HZ * 400) / 1000;
1da177e4 835 else
e0c7d767 836 timeo += (HZ * 20) / 1000;
1da177e4 837
8fe833c1
RP		 838 led_trigger_event(nand_led_trigger, LED_FULL);
839
8b6e50c9
BN		 840 /*
841 * Apply this short delay always to ensure that we do wait tWB in any
842 * case on any machine.
843 */
e0c7d767 844 ndelay(100);
1da177e4 845
ace4dfee
TG		 846 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
847 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 848 else
ace4dfee 849 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 850
2af7c653
SK		 851 if (in_interrupt() || oops_in_progress)
852 panic_nand_wait(mtd, chip, timeo);
853 else {
854 while (time_before(jiffies, timeo)) {
855 if (chip->dev_ready) {
856 if (chip->dev_ready(mtd))
857 break;
858 } else {
859 if (chip->read_byte(mtd) & NAND_STATUS_READY)
860 break;
861 }
862 cond_resched();
1da177e4 863 }
1da177e4 864 }
8fe833c1
RP		 865 led_trigger_event(nand_led_trigger, LED_OFF);
866
ace4dfee 867 status = (int)chip->read_byte(mtd);
1da177e4
LT		 868 return status;
869}
870
7d70f334 871/**
b6d676db 872 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 873 * @mtd: mtd info
874 * @ofs: offset to start unlock from
875 * @len: length to unlock
8b6e50c9
BN		 876 * @invert: when = 0, unlock the range of blocks within the lower and
877 * upper boundary address
878 * when = 1, unlock the range of blocks outside the boundaries
879 * of the lower and upper boundary address
7d70f334 880 *
8b6e50c9 881 * Returs unlock status.
7d70f334
VS		 882 */
883static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
884 uint64_t len, int invert)
885{
886 int ret = 0;
887 int status, page;
888 struct nand_chip *chip = mtd->priv;
889
890 /* Submit address of first page to unlock */
891 page = ofs >> chip->page_shift;
892 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
893
894 /* Submit address of last page to unlock */
895 page = (ofs + len) >> chip->page_shift;
896 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
897 (page | invert) & chip->pagemask);
898
899 /* Call wait ready function */
900 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 901 /* See if device thinks it succeeded */
902 if (status & 0x01) {
289c0522 903 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 904 __func__, status);
905 ret = -EIO;
906 }
907
908 return ret;
909}
910
911/**
b6d676db 912 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 913 * @mtd: mtd info
914 * @ofs: offset to start unlock from
915 * @len: length to unlock
7d70f334 916 *
8b6e50c9 917 * Returns unlock status.
7d70f334
VS		 918 */
919int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
920{
921 int ret = 0;
922 int chipnr;
923 struct nand_chip *chip = mtd->priv;
924
289c0522 925 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 926 __func__, (unsigned long long)ofs, len);
927
928 if (check_offs_len(mtd, ofs, len))
929 ret = -EINVAL;
930
931 /* Align to last block address if size addresses end of the device */
932 if (ofs + len == mtd->size)
933 len -= mtd->erasesize;
934
935 nand_get_device(chip, mtd, FL_UNLOCKING);
936
937 /* Shift to get chip number */
938 chipnr = ofs >> chip->chip_shift;
939
940 chip->select_chip(mtd, chipnr);
941
942 /* Check, if it is write protected */
943 if (nand_check_wp(mtd)) {
289c0522 944 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 945 __func__);
946 ret = -EIO;
947 goto out;
948 }
949
950 ret = __nand_unlock(mtd, ofs, len, 0);
951
952out:
7d70f334
VS		 953 nand_release_device(mtd);
954
955 return ret;
956}
7351d3a5 957EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 958
959/**
b6d676db 960 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 961 * @mtd: mtd info
962 * @ofs: offset to start unlock from
963 * @len: length to unlock
7d70f334 964 *
8b6e50c9
BN		 965 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
966 * have this feature, but it allows only to lock all blocks, not for specified
967 * range for block. Implementing 'lock' feature by making use of 'unlock', for
968 * now.
7d70f334 969 *
8b6e50c9 970 * Returns lock status.
7d70f334
VS		 971 */
972int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
973{
974 int ret = 0;
975 int chipnr, status, page;
976 struct nand_chip *chip = mtd->priv;
977
289c0522 978 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 979 __func__, (unsigned long long)ofs, len);
980
981 if (check_offs_len(mtd, ofs, len))
982 ret = -EINVAL;
983
984 nand_get_device(chip, mtd, FL_LOCKING);
985
986 /* Shift to get chip number */
987 chipnr = ofs >> chip->chip_shift;
988
989 chip->select_chip(mtd, chipnr);
990
991 /* Check, if it is write protected */
992 if (nand_check_wp(mtd)) {
289c0522 993 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 994 __func__);
995 status = MTD_ERASE_FAILED;
996 ret = -EIO;
997 goto out;
998 }
999
1000 /* Submit address of first page to lock */
1001 page = ofs >> chip->page_shift;
1002 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1003
1004 /* Call wait ready function */
1005 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1006 /* See if device thinks it succeeded */
1007 if (status & 0x01) {
289c0522 1008 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1009 __func__, status);
1010 ret = -EIO;
1011 goto out;
1012 }
1013
1014 ret = __nand_unlock(mtd, ofs, len, 0x1);
1015
1016out:
7d70f334
VS		 1017 nand_release_device(mtd);
1018
1019 return ret;
1020}
7351d3a5 1021EXPORT_SYMBOL(nand_lock);
7d70f334 1022
8593fbc6 1023/**
7854d3f7 1024 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1025 * @mtd: mtd info structure
1026 * @chip: nand chip info structure
1027 * @buf: buffer to store read data
1fbb938d 1028 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1029 * @page: page number to read
52ff49df 1030 *
7854d3f7 1031 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1032 */
1033static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1034 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1035{
1036 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1037 if (oob_required)
1038 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1039 return 0;
1040}
1041
52ff49df 1042/**
7854d3f7 1043 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1044 * @mtd: mtd info structure
1045 * @chip: nand chip info structure
1046 * @buf: buffer to store read data
1fbb938d 1047 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1048 * @page: page number to read
52ff49df
DB		 1049 *
1050 * We need a special oob layout and handling even when OOB isn't used.
1051 */
7351d3a5 1052static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1053 struct nand_chip *chip, uint8_t *buf,
1054 int oob_required, int page)
52ff49df
DB		 1055{
1056 int eccsize = chip->ecc.size;
1057 int eccbytes = chip->ecc.bytes;
1058 uint8_t *oob = chip->oob_poi;
1059 int steps, size;
1060
1061 for (steps = chip->ecc.steps; steps > 0; steps--) {
1062 chip->read_buf(mtd, buf, eccsize);
1063 buf += eccsize;
1064
1065 if (chip->ecc.prepad) {
1066 chip->read_buf(mtd, oob, chip->ecc.prepad);
1067 oob += chip->ecc.prepad;
1068 }
1069
1070 chip->read_buf(mtd, oob, eccbytes);
1071 oob += eccbytes;
1072
1073 if (chip->ecc.postpad) {
1074 chip->read_buf(mtd, oob, chip->ecc.postpad);
1075 oob += chip->ecc.postpad;
1076 }
1077 }
1078
1079 size = mtd->oobsize - (oob - chip->oob_poi);
1080 if (size)
1081 chip->read_buf(mtd, oob, size);
1082
1083 return 0;
1084}
1085
1da177e4 1086/**
7854d3f7 1087 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1088 * @mtd: mtd info structure
1089 * @chip: nand chip info structure
1090 * @buf: buffer to store read data
1fbb938d 1091 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1092 * @page: page number to read
068e3c0a 1093 */
f5bbdacc 1094static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1095 uint8_t *buf, int oob_required, int page)
1da177e4 1096{
f5bbdacc
TG		 1097 int i, eccsize = chip->ecc.size;
1098 int eccbytes = chip->ecc.bytes;
1099 int eccsteps = chip->ecc.steps;
1100 uint8_t *p = buf;
4bf63fcb
DW		 1101 uint8_t *ecc_calc = chip->buffers->ecccalc;
1102 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1103 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1104 unsigned int max_bitflips = 0;
f5bbdacc 1105
1fbb938d 1106 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1107
1108 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1109 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1110
1111 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1112 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1113
1114 eccsteps = chip->ecc.steps;
1115 p = buf;
1116
1117 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1118 int stat;
1119
1120 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1121 if (stat < 0) {
f5bbdacc 1122 mtd->ecc_stats.failed++;
3f91e94f 1123 } else {
f5bbdacc 1124 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1125 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1126 }
f5bbdacc 1127 }
3f91e94f 1128 return max_bitflips;
22c60f5f 1129}
1da177e4 1130
3d459559 1131/**
7854d3f7 1132 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1133 * @mtd: mtd info structure
1134 * @chip: nand chip info structure
1135 * @data_offs: offset of requested data within the page
1136 * @readlen: data length
1137 * @bufpoi: buffer to store read data
3d459559 1138 */
7351d3a5
FF		 1139static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1140 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1141{
1142 int start_step, end_step, num_steps;
1143 uint32_t *eccpos = chip->ecc.layout->eccpos;
1144 uint8_t *p;
1145 int data_col_addr, i, gaps = 0;
1146 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1147 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1148 int index = 0;
3f91e94f 1149 unsigned int max_bitflips = 0;
3d459559 1150
7854d3f7 1151 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1152 start_step = data_offs / chip->ecc.size;
1153 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1154 num_steps = end_step - start_step + 1;
1155
8b6e50c9 1156 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1157 datafrag_len = num_steps * chip->ecc.size;
1158 eccfrag_len = num_steps * chip->ecc.bytes;
1159
1160 data_col_addr = start_step * chip->ecc.size;
1161 /* If we read not a page aligned data */
1162 if (data_col_addr != 0)
1163 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1164
1165 p = bufpoi + data_col_addr;
1166 chip->read_buf(mtd, p, datafrag_len);
1167
8b6e50c9 1168 /* Calculate ECC */
3d459559
AK		 1169 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1170 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1171
8b6e50c9
BN		 1172 /*
1173 * The performance is faster if we position offsets according to
7854d3f7 1174 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1175 */
3d459559
AK		 1176 for (i = 0; i < eccfrag_len - 1; i++) {
1177 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1178 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1179 gaps = 1;
1180 break;
1181 }
1182 }
1183 if (gaps) {
1184 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1185 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1186 } else {
8b6e50c9 1187 /*
7854d3f7 1188 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1189 * about buswidth alignment in read_buf.
1190 */
7351d3a5
FF		 1191 index = start_step * chip->ecc.bytes;
1192
1193 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1194 aligned_len = eccfrag_len;
7351d3a5 1195 if (eccpos[index] & (busw - 1))
3d459559 1196 aligned_len++;
7351d3a5 1197 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1198 aligned_len++;
1199
7351d3a5
FF		 1200 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1201 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1202 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1203 }
1204
1205 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1206 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1207
1208 p = bufpoi + data_col_addr;
1209 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1210 int stat;
1211
7351d3a5
FF		 1212 stat = chip->ecc.correct(mtd, p,
1213 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1214 if (stat < 0) {
3d459559 1215 mtd->ecc_stats.failed++;
3f91e94f 1216 } else {
3d459559 1217 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1218 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1219 }
3d459559 1220 }
3f91e94f 1221 return max_bitflips;
3d459559
AK		 1222}
1223
068e3c0a 1224/**
7854d3f7 1225 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1226 * @mtd: mtd info structure
1227 * @chip: nand chip info structure
1228 * @buf: buffer to store read data
1fbb938d 1229 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1230 * @page: page number to read
068e3c0a 1231 *
7854d3f7 1232 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1233 */
f5bbdacc 1234static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1235 uint8_t *buf, int oob_required, int page)
1da177e4 1236{
f5bbdacc
TG		 1237 int i, eccsize = chip->ecc.size;
1238 int eccbytes = chip->ecc.bytes;
1239 int eccsteps = chip->ecc.steps;
1240 uint8_t *p = buf;
4bf63fcb
DW		 1241 uint8_t *ecc_calc = chip->buffers->ecccalc;
1242 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1243 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1244 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1245
1246 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1247 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1248 chip->read_buf(mtd, p, eccsize);
1249 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1250 }
f75e5097 1251 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1252
f5bbdacc 1253 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1254 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1255
f5bbdacc
TG		 1256 eccsteps = chip->ecc.steps;
1257 p = buf;
61b03bd7 1258
f5bbdacc
TG		 1259 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1260 int stat;
1da177e4 1261
f5bbdacc 1262 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1263 if (stat < 0) {
f5bbdacc 1264 mtd->ecc_stats.failed++;
3f91e94f 1265 } else {
f5bbdacc 1266 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1267 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1268 }
f5bbdacc 1269 }
3f91e94f 1270 return max_bitflips;
f5bbdacc 1271}
1da177e4 1272
6e0cb135 1273/**
7854d3f7 1274 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1275 * @mtd: mtd info structure
1276 * @chip: nand chip info structure
1277 * @buf: buffer to store read data
1fbb938d 1278 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1279 * @page: page number to read
6e0cb135 1280 *
8b6e50c9
BN		 1281 * Hardware ECC for large page chips, require OOB to be read first. For this
1282 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1283 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1284 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1285 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1286 */
1287static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1288 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1289{
1290 int i, eccsize = chip->ecc.size;
1291 int eccbytes = chip->ecc.bytes;
1292 int eccsteps = chip->ecc.steps;
1293 uint8_t *p = buf;
1294 uint8_t *ecc_code = chip->buffers->ecccode;
1295 uint32_t *eccpos = chip->ecc.layout->eccpos;
1296 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1297 unsigned int max_bitflips = 0;
6e0cb135
SN		 1298
1299 /* Read the OOB area first */
1300 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1301 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1302 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1303
1304 for (i = 0; i < chip->ecc.total; i++)
1305 ecc_code[i] = chip->oob_poi[eccpos[i]];
1306
1307 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1308 int stat;
1309
1310 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1311 chip->read_buf(mtd, p, eccsize);
1312 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1313
1314 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1315 if (stat < 0) {
6e0cb135 1316 mtd->ecc_stats.failed++;
3f91e94f 1317 } else {
6e0cb135 1318 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1319 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1320 }
6e0cb135 1321 }
3f91e94f 1322 return max_bitflips;
6e0cb135
SN		 1323}
1324
f5bbdacc 1325/**
7854d3f7 1326 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1327 * @mtd: mtd info structure
1328 * @chip: nand chip info structure
1329 * @buf: buffer to store read data
1fbb938d 1330 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1331 * @page: page number to read
f5bbdacc 1332 *
8b6e50c9
BN		 1333 * The hw generator calculates the error syndrome automatically. Therefore we
1334 * need a special oob layout and handling.
f5bbdacc
TG		 1335 */
1336static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1337 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1338{
1339 int i, eccsize = chip->ecc.size;
1340 int eccbytes = chip->ecc.bytes;
1341 int eccsteps = chip->ecc.steps;
1342 uint8_t *p = buf;
f75e5097 1343 uint8_t *oob = chip->oob_poi;
3f91e94f 1344 unsigned int max_bitflips = 0;
1da177e4 1345
f5bbdacc
TG		 1346 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1347 int stat;
61b03bd7 1348
f5bbdacc
TG		 1349 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1350 chip->read_buf(mtd, p, eccsize);
1da177e4 1351
f5bbdacc
TG		 1352 if (chip->ecc.prepad) {
1353 chip->read_buf(mtd, oob, chip->ecc.prepad);
1354 oob += chip->ecc.prepad;
1355 }
1da177e4 1356
f5bbdacc
TG		 1357 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1358 chip->read_buf(mtd, oob, eccbytes);
1359 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1360
3f91e94f 1361 if (stat < 0) {
f5bbdacc 1362 mtd->ecc_stats.failed++;
3f91e94f 1363 } else {
f5bbdacc 1364 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1365 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1366 }
61b03bd7 1367
f5bbdacc 1368 oob += eccbytes;
1da177e4 1369
f5bbdacc
TG		 1370 if (chip->ecc.postpad) {
1371 chip->read_buf(mtd, oob, chip->ecc.postpad);
1372 oob += chip->ecc.postpad;
61b03bd7 1373 }
f5bbdacc 1374 }
1da177e4 1375
f5bbdacc 1376 /* Calculate remaining oob bytes */
7e4178f9 1377 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1378 if (i)
1379 chip->read_buf(mtd, oob, i);
61b03bd7 1380
3f91e94f 1381 return max_bitflips;
f5bbdacc 1382}
1da177e4 1383
f5bbdacc 1384/**
7854d3f7 1385 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1386 * @chip: nand chip structure
1387 * @oob: oob destination address
1388 * @ops: oob ops structure
1389 * @len: size of oob to transfer
8593fbc6
TG		 1390 */
1391static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1392 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1393{
f8ac0414 1394 switch (ops->mode) {
8593fbc6 1395
0612b9dd
BN		 1396 case MTD_OPS_PLACE_OOB:
1397 case MTD_OPS_RAW:
8593fbc6
TG		 1398 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1399 return oob + len;
1400
0612b9dd 1401 case MTD_OPS_AUTO_OOB: {
8593fbc6 1402 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1403 uint32_t boffs = 0, roffs = ops->ooboffs;
1404 size_t bytes = 0;
8593fbc6 1405
f8ac0414 1406 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1407 /* Read request not from offset 0? */
7bc3312b
TG		 1408 if (unlikely(roffs)) {
1409 if (roffs >= free->length) {
1410 roffs -= free->length;
1411 continue;
1412 }
1413 boffs = free->offset + roffs;
1414 bytes = min_t(size_t, len,
1415 (free->length - roffs));
1416 roffs = 0;
1417 } else {
1418 bytes = min_t(size_t, len, free->length);
1419 boffs = free->offset;
1420 }
1421 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1422 oob += bytes;
1423 }
1424 return oob;
1425 }
1426 default:
1427 BUG();
1428 }
1429 return NULL;
1430}
1431
1432/**
7854d3f7 1433 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1434 * @mtd: MTD device structure
1435 * @from: offset to read from
1436 * @ops: oob ops structure
f5bbdacc
TG		 1437 *
1438 * Internal function. Called with chip held.
1439 */
8593fbc6
TG		 1440static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1441 struct mtd_oob_ops *ops)
f5bbdacc 1442{
e47f3db4 1443 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1444 struct nand_chip *chip = mtd->priv;
1445 struct mtd_ecc_stats stats;
f5bbdacc 1446 int ret = 0;
8593fbc6 1447 uint32_t readlen = ops->len;
7014568b 1448 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1449 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1450 mtd->oobavail : mtd->oobsize;
1451
8593fbc6 1452 uint8_t *bufpoi, *oob, *buf;
edbc4540 1453 unsigned int max_bitflips = 0;
1da177e4 1454
f5bbdacc 1455 stats = mtd->ecc_stats;
1da177e4 1456
f5bbdacc
TG		 1457 chipnr = (int)(from >> chip->chip_shift);
1458 chip->select_chip(mtd, chipnr);
61b03bd7 1459
f5bbdacc
TG		 1460 realpage = (int)(from >> chip->page_shift);
1461 page = realpage & chip->pagemask;
1da177e4 1462
f5bbdacc 1463 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1464
8593fbc6
TG		 1465 buf = ops->datbuf;
1466 oob = ops->oobbuf;
e47f3db4 1467 oob_required = oob ? 1 : 0;
8593fbc6 1468
f8ac0414 1469 while (1) {
f5bbdacc
TG		 1470 bytes = min(mtd->writesize - col, readlen);
1471 aligned = (bytes == mtd->writesize);
61b03bd7 1472
8b6e50c9 1473 /* Is the current page in the buffer? */
8593fbc6 1474 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1475 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1476
c00a0991 1477 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1478
edbc4540
MD		 1479 /*
1480 * Now read the page into the buffer. Absent an error,
1481 * the read methods return max bitflips per ecc step.
1482 */
0612b9dd 1483 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1484 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1485 oob_required,
1486 page);
a5ff4f10
JW		 1487 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1488 !oob)
7351d3a5
FF		 1489 ret = chip->ecc.read_subpage(mtd, chip,
1490 col, bytes, bufpoi);
956e944c 1491 else
46a8cf2d 1492 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1493 oob_required, page);
6d77b9d0
BN		 1494 if (ret < 0) {
1495 if (!aligned)
1496 /* Invalidate page cache */
1497 chip->pagebuf = -1;
1da177e4 1498 break;
6d77b9d0 1499 }
f5bbdacc 1500
edbc4540
MD		 1501 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1502
f5bbdacc
TG		 1503 /* Transfer not aligned data */
1504 if (!aligned) {
a5ff4f10 1505 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1506 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1507 (ops->mode != MTD_OPS_RAW)) {
3d459559 1508 chip->pagebuf = realpage;
edbc4540
MD		 1509 chip->pagebuf_bitflips = ret;
1510 } else {
6d77b9d0
BN		 1511 /* Invalidate page cache */
1512 chip->pagebuf = -1;
edbc4540 1513 }
4bf63fcb 1514 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1515 }
1516
8593fbc6
TG		 1517 buf += bytes;
1518
1519 if (unlikely(oob)) {
b64d39d8
ML		 1520 int toread = min(oobreadlen, max_oobsize);
1521
1522 if (toread) {
1523 oob = nand_transfer_oob(chip,
1524 oob, ops, toread);
1525 oobreadlen -= toread;
1526 }
8593fbc6 1527 }
8593fbc6 1528 } else {
4bf63fcb 1529 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1530 buf += bytes;
edbc4540
MD		 1531 max_bitflips = max_t(unsigned int, max_bitflips,
1532 chip->pagebuf_bitflips);
8593fbc6 1533 }
1da177e4 1534
f5bbdacc 1535 readlen -= bytes;
61b03bd7 1536
f5bbdacc 1537 if (!readlen)
61b03bd7 1538 break;
1da177e4 1539
8b6e50c9 1540 /* For subsequent reads align to page boundary */
1da177e4
LT		 1541 col = 0;
1542 /* Increment page address */
1543 realpage++;
1544
ace4dfee 1545 page = realpage & chip->pagemask;
1da177e4
LT		 1546 /* Check, if we cross a chip boundary */
1547 if (!page) {
1548 chipnr++;
ace4dfee
TG		 1549 chip->select_chip(mtd, -1);
1550 chip->select_chip(mtd, chipnr);
1da177e4 1551 }
1da177e4
LT		 1552 }
1553
8593fbc6 1554 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1555 if (oob)
1556 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1557
3f91e94f 1558 if (ret < 0)
f5bbdacc
TG		 1559 return ret;
1560
9a1fcdfd
TG		 1561 if (mtd->ecc_stats.failed - stats.failed)
1562 return -EBADMSG;
1563
edbc4540 1564 return max_bitflips;
f5bbdacc
TG		 1565}
1566
1567/**
25985edc 1568 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1569 * @mtd: MTD device structure
1570 * @from: offset to read from
1571 * @len: number of bytes to read
1572 * @retlen: pointer to variable to store the number of read bytes
1573 * @buf: the databuffer to put data
f5bbdacc 1574 *
8b6e50c9 1575 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1576 */
1577static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1578 size_t *retlen, uint8_t *buf)
1579{
8593fbc6 1580 struct nand_chip *chip = mtd->priv;
4a89ff88 1581 struct mtd_oob_ops ops;
f5bbdacc
TG		 1582 int ret;
1583
8593fbc6 1584 nand_get_device(chip, mtd, FL_READING);
4a89ff88
BN		 1585 ops.len = len;
1586 ops.datbuf = buf;
1587 ops.oobbuf = NULL;
11041ae6 1588 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 1589 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1590 *retlen = ops.retlen;
f5bbdacc 1591 nand_release_device(mtd);
f5bbdacc 1592 return ret;
1da177e4
LT		 1593}
1594
7bc3312b 1595/**
7854d3f7 1596 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1597 * @mtd: mtd info structure
1598 * @chip: nand chip info structure
1599 * @page: page number to read
7bc3312b
TG		 1600 */
1601static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1602 int page)
7bc3312b 1603{
5c2ffb11 1604 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1605 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1606 return 0;
7bc3312b
TG		 1607}
1608
1609/**
7854d3f7 1610 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1611 * with syndromes
8b6e50c9
BN		 1612 * @mtd: mtd info structure
1613 * @chip: nand chip info structure
1614 * @page: page number to read
7bc3312b
TG		 1615 */
1616static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1617 int page)
7bc3312b
TG		 1618{
1619 uint8_t *buf = chip->oob_poi;
1620 int length = mtd->oobsize;
1621 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1622 int eccsize = chip->ecc.size;
1623 uint8_t *bufpoi = buf;
1624 int i, toread, sndrnd = 0, pos;
1625
1626 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1627 for (i = 0; i < chip->ecc.steps; i++) {
1628 if (sndrnd) {
1629 pos = eccsize + i * (eccsize + chunk);
1630 if (mtd->writesize > 512)
1631 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1632 else
1633 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1634 } else
1635 sndrnd = 1;
1636 toread = min_t(int, length, chunk);
1637 chip->read_buf(mtd, bufpoi, toread);
1638 bufpoi += toread;
1639 length -= toread;
1640 }
1641 if (length > 0)
1642 chip->read_buf(mtd, bufpoi, length);
1643
5c2ffb11 1644 return 0;
7bc3312b
TG		 1645}
1646
1647/**
7854d3f7 1648 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1649 * @mtd: mtd info structure
1650 * @chip: nand chip info structure
1651 * @page: page number to write
7bc3312b
TG		 1652 */
1653static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1654 int page)
1655{
1656 int status = 0;
1657 const uint8_t *buf = chip->oob_poi;
1658 int length = mtd->oobsize;
1659
1660 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1661 chip->write_buf(mtd, buf, length);
1662 /* Send command to program the OOB data */
1663 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1664
1665 status = chip->waitfunc(mtd, chip);
1666
0d420f9d 1667 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1668}
1669
1670/**
7854d3f7 1671 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1672 * with syndrome - only for large page flash
1673 * @mtd: mtd info structure
1674 * @chip: nand chip info structure
1675 * @page: page number to write
7bc3312b
TG		 1676 */
1677static int nand_write_oob_syndrome(struct mtd_info *mtd,
1678 struct nand_chip *chip, int page)
1679{
1680 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1681 int eccsize = chip->ecc.size, length = mtd->oobsize;
1682 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1683 const uint8_t *bufpoi = chip->oob_poi;
1684
1685 /*
1686 * data-ecc-data-ecc ... ecc-oob
1687 * or
1688 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1689 */
1690 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1691 pos = steps * (eccsize + chunk);
1692 steps = 0;
1693 } else
8b0036ee 1694 pos = eccsize;
7bc3312b
TG		 1695
1696 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1697 for (i = 0; i < steps; i++) {
1698 if (sndcmd) {
1699 if (mtd->writesize <= 512) {
1700 uint32_t fill = 0xFFFFFFFF;
1701
1702 len = eccsize;
1703 while (len > 0) {
1704 int num = min_t(int, len, 4);
1705 chip->write_buf(mtd, (uint8_t *)&fill,
1706 num);
1707 len -= num;
1708 }
1709 } else {
1710 pos = eccsize + i * (eccsize + chunk);
1711 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1712 }
1713 } else
1714 sndcmd = 1;
1715 len = min_t(int, length, chunk);
1716 chip->write_buf(mtd, bufpoi, len);
1717 bufpoi += len;
1718 length -= len;
1719 }
1720 if (length > 0)
1721 chip->write_buf(mtd, bufpoi, length);
1722
1723 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1724 status = chip->waitfunc(mtd, chip);
1725
1726 return status & NAND_STATUS_FAIL ? -EIO : 0;
1727}
1728
1da177e4 1729/**
7854d3f7 1730 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1731 * @mtd: MTD device structure
1732 * @from: offset to read from
1733 * @ops: oob operations description structure
1da177e4 1734 *
8b6e50c9 1735 * NAND read out-of-band data from the spare area.
1da177e4 1736 */
8593fbc6
TG		 1737static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1738 struct mtd_oob_ops *ops)
1da177e4 1739{
c00a0991 1740 int page, realpage, chipnr;
ace4dfee 1741 struct nand_chip *chip = mtd->priv;
041e4575 1742 struct mtd_ecc_stats stats;
7014568b
VW		 1743 int readlen = ops->ooblen;
1744 int len;
7bc3312b 1745 uint8_t *buf = ops->oobbuf;
1951f2f7 1746 int ret = 0;
61b03bd7 1747
289c0522 1748 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1749 __func__, (unsigned long long)from, readlen);
1da177e4 1750
041e4575
BN		 1751 stats = mtd->ecc_stats;
1752
0612b9dd 1753 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1754 len = chip->ecc.layout->oobavail;
03736155
AH		 1755 else
1756 len = mtd->oobsize;
1757
1758 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1759 pr_debug("%s: attempt to start read outside oob\n",
1760 __func__);
03736155
AH		 1761 return -EINVAL;
1762 }
1763
1764 /* Do not allow reads past end of device */
1765 if (unlikely(from >= mtd->size ||
1766 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1767 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1768 pr_debug("%s: attempt to read beyond end of device\n",
1769 __func__);
03736155
AH		 1770 return -EINVAL;
1771 }
7014568b 1772
7314e9e7 1773 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1774 chip->select_chip(mtd, chipnr);
1da177e4 1775
7314e9e7
TG		 1776 /* Shift to get page */
1777 realpage = (int)(from >> chip->page_shift);
1778 page = realpage & chip->pagemask;
1da177e4 1779
f8ac0414 1780 while (1) {
0612b9dd 1781 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1782 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1783 else
1951f2f7
SL		 1784 ret = chip->ecc.read_oob(mtd, chip, page);
1785
1786 if (ret < 0)
1787 break;
7014568b
VW		 1788
1789 len = min(len, readlen);
1790 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1791
7014568b 1792 readlen -= len;
0d420f9d
SZ		 1793 if (!readlen)
1794 break;
1795
7314e9e7
TG		 1796 /* Increment page address */
1797 realpage++;
1798
1799 page = realpage & chip->pagemask;
1800 /* Check, if we cross a chip boundary */
1801 if (!page) {
1802 chipnr++;
1803 chip->select_chip(mtd, -1);
1804 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1805 }
1806 }
1807
1951f2f7
SL		 1808 ops->oobretlen = ops->ooblen - readlen;
1809
1810 if (ret < 0)
1811 return ret;
041e4575
BN		 1812
1813 if (mtd->ecc_stats.failed - stats.failed)
1814 return -EBADMSG;
1815
1816 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1817}
1818
1819/**
8593fbc6 1820 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1821 * @mtd: MTD device structure
1822 * @from: offset to read from
1823 * @ops: oob operation description structure
1da177e4 1824 *
8b6e50c9 1825 * NAND read data and/or out-of-band data.
1da177e4 1826 */
8593fbc6
TG		 1827static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1828 struct mtd_oob_ops *ops)
1da177e4 1829{
ace4dfee 1830 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1831 int ret = -ENOTSUPP;
1832
1833 ops->retlen = 0;
1da177e4
LT		 1834
1835 /* Do not allow reads past end of device */
7014568b 1836 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1837 pr_debug("%s: attempt to read beyond end of device\n",
1838 __func__);
1da177e4
LT		 1839 return -EINVAL;
1840 }
1841
ace4dfee 1842 nand_get_device(chip, mtd, FL_READING);
1da177e4 1843
f8ac0414 1844 switch (ops->mode) {
0612b9dd
BN		 1845 case MTD_OPS_PLACE_OOB:
1846 case MTD_OPS_AUTO_OOB:
1847 case MTD_OPS_RAW:
8593fbc6 1848 break;
1da177e4 1849
8593fbc6
TG		 1850 default:
1851 goto out;
1852 }
1da177e4 1853
8593fbc6
TG		 1854 if (!ops->datbuf)
1855 ret = nand_do_read_oob(mtd, from, ops);
1856 else
1857 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1858
7351d3a5 1859out:
8593fbc6
TG		 1860 nand_release_device(mtd);
1861 return ret;
1862}
61b03bd7 1863
1da177e4 1864
8593fbc6 1865/**
7854d3f7 1866 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1867 * @mtd: mtd info structure
1868 * @chip: nand chip info structure
1869 * @buf: data buffer
1fbb938d 1870 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1871 *
7854d3f7 1872 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1873 */
fdbad98d 1874static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1875 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1876{
1877 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1878 if (oob_required)
1879 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1880
1881 return 0;
1da177e4
LT		 1882}
1883
52ff49df 1884/**
7854d3f7 1885 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1886 * @mtd: mtd info structure
1887 * @chip: nand chip info structure
1888 * @buf: data buffer
1fbb938d 1889 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1890 *
1891 * We need a special oob layout and handling even when ECC isn't checked.
1892 */
fdbad98d 1893static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1894 struct nand_chip *chip,
1fbb938d 1895 const uint8_t *buf, int oob_required)
52ff49df
DB		 1896{
1897 int eccsize = chip->ecc.size;
1898 int eccbytes = chip->ecc.bytes;
1899 uint8_t *oob = chip->oob_poi;
1900 int steps, size;
1901
1902 for (steps = chip->ecc.steps; steps > 0; steps--) {
1903 chip->write_buf(mtd, buf, eccsize);
1904 buf += eccsize;
1905
1906 if (chip->ecc.prepad) {
1907 chip->write_buf(mtd, oob, chip->ecc.prepad);
1908 oob += chip->ecc.prepad;
1909 }
1910
1911 chip->read_buf(mtd, oob, eccbytes);
1912 oob += eccbytes;
1913
1914 if (chip->ecc.postpad) {
1915 chip->write_buf(mtd, oob, chip->ecc.postpad);
1916 oob += chip->ecc.postpad;
1917 }
1918 }
1919
1920 size = mtd->oobsize - (oob - chip->oob_poi);
1921 if (size)
1922 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 1923
1924 return 0;
52ff49df 1925}
9223a456 1926/**
7854d3f7 1927 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1928 * @mtd: mtd info structure
1929 * @chip: nand chip info structure
1930 * @buf: data buffer
1fbb938d 1931 * @oob_required: must write chip->oob_poi to OOB
9223a456 1932 */
fdbad98d 1933static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1934 const uint8_t *buf, int oob_required)
9223a456 1935{
f75e5097
TG		 1936 int i, eccsize = chip->ecc.size;
1937 int eccbytes = chip->ecc.bytes;
1938 int eccsteps = chip->ecc.steps;
4bf63fcb 1939 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1940 const uint8_t *p = buf;
8b099a39 1941 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1942
7854d3f7 1943 /* Software ECC calculation */
8593fbc6
TG		 1944 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1945 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1946
8593fbc6
TG		 1947 for (i = 0; i < chip->ecc.total; i++)
1948 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1949
fdbad98d 1950 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1951}
9223a456 1952
f75e5097 1953/**
7854d3f7 1954 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1955 * @mtd: mtd info structure
1956 * @chip: nand chip info structure
1957 * @buf: data buffer
1fbb938d 1958 * @oob_required: must write chip->oob_poi to OOB
f75e5097 1959 */
fdbad98d 1960static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1961 const uint8_t *buf, int oob_required)
f75e5097
TG		 1962{
1963 int i, eccsize = chip->ecc.size;
1964 int eccbytes = chip->ecc.bytes;
1965 int eccsteps = chip->ecc.steps;
4bf63fcb 1966 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1967 const uint8_t *p = buf;
8b099a39 1968 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1969
f75e5097
TG		 1970 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1971 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1972 chip->write_buf(mtd, p, eccsize);
f75e5097 1973 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1974 }
1975
f75e5097
TG		 1976 for (i = 0; i < chip->ecc.total; i++)
1977 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1978
1979 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1980
1981 return 0;
9223a456
TG		 1982}
1983
61b03bd7 1984/**
7854d3f7 1985 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 1986 * @mtd: mtd info structure
1987 * @chip: nand chip info structure
1988 * @buf: data buffer
1fbb938d 1989 * @oob_required: must write chip->oob_poi to OOB
1da177e4 1990 *
8b6e50c9
BN		 1991 * The hw generator calculates the error syndrome automatically. Therefore we
1992 * need a special oob layout and handling.
f75e5097 1993 */
fdbad98d 1994static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1995 struct nand_chip *chip,
1996 const uint8_t *buf, int oob_required)
1da177e4 1997{
f75e5097
TG		 1998 int i, eccsize = chip->ecc.size;
1999 int eccbytes = chip->ecc.bytes;
2000 int eccsteps = chip->ecc.steps;
2001 const uint8_t *p = buf;
2002 uint8_t *oob = chip->oob_poi;
1da177e4 2003
f75e5097 2004 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2005
f75e5097
TG		 2006 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2007 chip->write_buf(mtd, p, eccsize);
61b03bd7 2008
f75e5097
TG		 2009 if (chip->ecc.prepad) {
2010 chip->write_buf(mtd, oob, chip->ecc.prepad);
2011 oob += chip->ecc.prepad;
2012 }
2013
2014 chip->ecc.calculate(mtd, p, oob);
2015 chip->write_buf(mtd, oob, eccbytes);
2016 oob += eccbytes;
2017
2018 if (chip->ecc.postpad) {
2019 chip->write_buf(mtd, oob, chip->ecc.postpad);
2020 oob += chip->ecc.postpad;
1da177e4 2021 }
1da177e4 2022 }
f75e5097
TG		 2023
2024 /* Calculate remaining oob bytes */
7e4178f9 2025 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2026 if (i)
2027 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2028
2029 return 0;
f75e5097
TG		 2030}
2031
2032/**
956e944c 2033 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2034 * @mtd: MTD device structure
2035 * @chip: NAND chip descriptor
2036 * @buf: the data to write
1fbb938d 2037 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2038 * @page: page number to write
2039 * @cached: cached programming
2040 * @raw: use _raw version of write_page
f75e5097
TG		 2041 */
2042static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d
BN		 2043 const uint8_t *buf, int oob_required, int page,
2044 int cached, int raw)
f75e5097
TG		 2045{
2046 int status;
2047
2048 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2049
956e944c 2050 if (unlikely(raw))
fdbad98d 2051 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
956e944c 2052 else
fdbad98d
JW		 2053 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2054
2055 if (status < 0)
2056 return status;
f75e5097
TG		 2057
2058 /*
7854d3f7 2059 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2060 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2061 */
2062 cached = 0;
2063
2064 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2065
2066 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2067 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2068 /*
2069 * See if operation failed and additional status checks are
8b6e50c9 2070 * available.
f75e5097
TG		 2071 */
2072 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2073 status = chip->errstat(mtd, chip, FL_WRITING, status,
2074 page);
2075
2076 if (status & NAND_STATUS_FAIL)
2077 return -EIO;
2078 } else {
2079 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2080 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2081 }
2082
f75e5097 2083 return 0;
1da177e4
LT		 2084}
2085
8593fbc6 2086/**
7854d3f7 2087 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2088 * @mtd: MTD device structure
8b6e50c9
BN		 2089 * @oob: oob data buffer
2090 * @len: oob data write length
2091 * @ops: oob ops structure
8593fbc6 2092 */
f722013e
TAA		 2093static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2094 struct mtd_oob_ops *ops)
8593fbc6 2095{
f722013e
TAA		 2096 struct nand_chip *chip = mtd->priv;
2097
2098 /*
2099 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2100 * data from a previous OOB read.
2101 */
2102 memset(chip->oob_poi, 0xff, mtd->oobsize);
2103
f8ac0414 2104 switch (ops->mode) {
8593fbc6 2105
0612b9dd
BN		 2106 case MTD_OPS_PLACE_OOB:
2107 case MTD_OPS_RAW:
8593fbc6
TG		 2108 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2109 return oob + len;
2110
0612b9dd 2111 case MTD_OPS_AUTO_OOB: {
8593fbc6 2112 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2113 uint32_t boffs = 0, woffs = ops->ooboffs;
2114 size_t bytes = 0;
8593fbc6 2115
f8ac0414 2116 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2117 /* Write request not from offset 0? */
7bc3312b
TG		 2118 if (unlikely(woffs)) {
2119 if (woffs >= free->length) {
2120 woffs -= free->length;
2121 continue;
2122 }
2123 boffs = free->offset + woffs;
2124 bytes = min_t(size_t, len,
2125 (free->length - woffs));
2126 woffs = 0;
2127 } else {
2128 bytes = min_t(size_t, len, free->length);
2129 boffs = free->offset;
2130 }
8b0036ee 2131 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2132 oob += bytes;
2133 }
2134 return oob;
2135 }
2136 default:
2137 BUG();
2138 }
2139 return NULL;
2140}
2141
f8ac0414 2142#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2143
2144/**
7854d3f7 2145 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2146 * @mtd: MTD device structure
2147 * @to: offset to write to
2148 * @ops: oob operations description structure
1da177e4 2149 *
8b6e50c9 2150 * NAND write with ECC.
1da177e4 2151 */
8593fbc6
TG		 2152static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2153 struct mtd_oob_ops *ops)
1da177e4 2154{
29072b96 2155 int chipnr, realpage, page, blockmask, column;
ace4dfee 2156 struct nand_chip *chip = mtd->priv;
8593fbc6 2157 uint32_t writelen = ops->len;
782ce79a
ML		 2158
2159 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2160 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2161 mtd->oobavail : mtd->oobsize;
2162
8593fbc6
TG		 2163 uint8_t *oob = ops->oobbuf;
2164 uint8_t *buf = ops->datbuf;
29072b96 2165 int ret, subpage;
e47f3db4 2166 int oob_required = oob ? 1 : 0;
1da177e4 2167
8593fbc6 2168 ops->retlen = 0;
29072b96
TG		 2169 if (!writelen)
2170 return 0;
1da177e4 2171
8b6e50c9 2172 /* Reject writes, which are not page aligned */
8593fbc6 2173 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2174 pr_notice("%s: attempt to write non page aligned data\n",
2175 __func__);
1da177e4
LT		 2176 return -EINVAL;
2177 }
2178
29072b96
TG		 2179 column = to & (mtd->writesize - 1);
2180 subpage = column || (writelen & (mtd->writesize - 1));
2181
2182 if (subpage && oob)
2183 return -EINVAL;
1da177e4 2184
6a930961
TG		 2185 chipnr = (int)(to >> chip->chip_shift);
2186 chip->select_chip(mtd, chipnr);
2187
1da177e4
LT		 2188 /* Check, if it is write protected */
2189 if (nand_check_wp(mtd))
8593fbc6 2190 return -EIO;
1da177e4 2191
f75e5097
TG		 2192 realpage = (int)(to >> chip->page_shift);
2193 page = realpage & chip->pagemask;
2194 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2195
2196 /* Invalidate the page cache, when we write to the cached page */
2197 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2198 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2199 chip->pagebuf = -1;
61b03bd7 2200
782ce79a 2201 /* Don't allow multipage oob writes with offset */
cdcf12b2 2202 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2203 return -EINVAL;
2204
f8ac0414 2205 while (1) {
29072b96 2206 int bytes = mtd->writesize;
f75e5097 2207 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2208 uint8_t *wbuf = buf;
2209
8b6e50c9 2210 /* Partial page write? */
29072b96
TG		 2211 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2212 cached = 0;
2213 bytes = min_t(int, bytes - column, (int) writelen);
2214 chip->pagebuf = -1;
2215 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2216 memcpy(&chip->buffers->databuf[column], buf, bytes);
2217 wbuf = chip->buffers->databuf;
2218 }
1da177e4 2219
782ce79a
ML		 2220 if (unlikely(oob)) {
2221 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2222 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2223 oobwritelen -= len;
f722013e
TAA		 2224 } else {
2225 /* We still need to erase leftover OOB data */
2226 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2227 }
8593fbc6 2228
e47f3db4
BN		 2229 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2230 cached, (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2231 if (ret)
2232 break;
2233
2234 writelen -= bytes;
2235 if (!writelen)
2236 break;
2237
29072b96 2238 column = 0;
f75e5097
TG		 2239 buf += bytes;
2240 realpage++;
2241
2242 page = realpage & chip->pagemask;
2243 /* Check, if we cross a chip boundary */
2244 if (!page) {
2245 chipnr++;
2246 chip->select_chip(mtd, -1);
2247 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2248 }
2249 }
8593fbc6 2250
8593fbc6 2251 ops->retlen = ops->len - writelen;
7014568b
VW		 2252 if (unlikely(oob))
2253 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2254 return ret;
2255}
2256
2af7c653
SK		 2257/**
2258 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2259 * @mtd: MTD device structure
2260 * @to: offset to write to
2261 * @len: number of bytes to write
2262 * @retlen: pointer to variable to store the number of written bytes
2263 * @buf: the data to write
2af7c653
SK		 2264 *
2265 * NAND write with ECC. Used when performing writes in interrupt context, this
2266 * may for example be called by mtdoops when writing an oops while in panic.
2267 */
2268static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2269 size_t *retlen, const uint8_t *buf)
2270{
2271 struct nand_chip *chip = mtd->priv;
4a89ff88 2272 struct mtd_oob_ops ops;
2af7c653
SK		 2273 int ret;
2274
8b6e50c9 2275 /* Wait for the device to get ready */
2af7c653
SK		 2276 panic_nand_wait(mtd, chip, 400);
2277
8b6e50c9 2278 /* Grab the device */
2af7c653
SK		 2279 panic_nand_get_device(chip, mtd, FL_WRITING);
2280
4a89ff88
BN		 2281 ops.len = len;
2282 ops.datbuf = (uint8_t *)buf;
2283 ops.oobbuf = NULL;
11041ae6 2284 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 2285
4a89ff88 2286 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2287
4a89ff88 2288 *retlen = ops.retlen;
2af7c653
SK		 2289 return ret;
2290}
2291
f75e5097 2292/**
8593fbc6 2293 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2294 * @mtd: MTD device structure
2295 * @to: offset to write to
2296 * @len: number of bytes to write
2297 * @retlen: pointer to variable to store the number of written bytes
2298 * @buf: the data to write
f75e5097 2299 *
8b6e50c9 2300 * NAND write with ECC.
f75e5097 2301 */
8593fbc6
TG		 2302static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2303 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2304{
2305 struct nand_chip *chip = mtd->priv;
4a89ff88 2306 struct mtd_oob_ops ops;
f75e5097
TG		 2307 int ret;
2308
7bc3312b 2309 nand_get_device(chip, mtd, FL_WRITING);
4a89ff88
BN		 2310 ops.len = len;
2311 ops.datbuf = (uint8_t *)buf;
2312 ops.oobbuf = NULL;
11041ae6 2313 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 2314 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2315 *retlen = ops.retlen;
f75e5097 2316 nand_release_device(mtd);
8593fbc6 2317 return ret;
f75e5097 2318}
7314e9e7 2319
1da177e4 2320/**
8593fbc6 2321 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2322 * @mtd: MTD device structure
2323 * @to: offset to write to
2324 * @ops: oob operation description structure
1da177e4 2325 *
8b6e50c9 2326 * NAND write out-of-band.
1da177e4 2327 */
8593fbc6
TG		 2328static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2329 struct mtd_oob_ops *ops)
1da177e4 2330{
03736155 2331 int chipnr, page, status, len;
ace4dfee 2332 struct nand_chip *chip = mtd->priv;
1da177e4 2333
289c0522 2334 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2335 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2336
0612b9dd 2337 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2338 len = chip->ecc.layout->oobavail;
2339 else
2340 len = mtd->oobsize;
2341
1da177e4 2342 /* Do not allow write past end of page */
03736155 2343 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2344 pr_debug("%s: attempt to write past end of page\n",
2345 __func__);
1da177e4
LT		 2346 return -EINVAL;
2347 }
2348
03736155 2349 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2350 pr_debug("%s: attempt to start write outside oob\n",
2351 __func__);
03736155
AH		 2352 return -EINVAL;
2353 }
2354
775adc3d 2355 /* Do not allow write past end of device */
03736155
AH		 2356 if (unlikely(to >= mtd->size ||
2357 ops->ooboffs + ops->ooblen >
2358 ((mtd->size >> chip->page_shift) -
2359 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2360 pr_debug("%s: attempt to write beyond end of device\n",
2361 __func__);
03736155
AH		 2362 return -EINVAL;
2363 }
2364
7314e9e7 2365 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2366 chip->select_chip(mtd, chipnr);
1da177e4 2367
7314e9e7
TG		 2368 /* Shift to get page */
2369 page = (int)(to >> chip->page_shift);
2370
2371 /*
2372 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2373 * of my DiskOnChip 2000 test units) will clear the whole data page too
2374 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2375 * it in the doc2000 driver in August 1999. dwmw2.
2376 */
ace4dfee 2377 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2378
2379 /* Check, if it is write protected */
2380 if (nand_check_wp(mtd))
8593fbc6 2381 return -EROFS;
61b03bd7 2382
1da177e4 2383 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2384 if (page == chip->pagebuf)
2385 chip->pagebuf = -1;
1da177e4 2386
f722013e 2387 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2388
0612b9dd 2389 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2390 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2391 else
2392 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2393
7bc3312b
TG		 2394 if (status)
2395 return status;
1da177e4 2396
7014568b 2397 ops->oobretlen = ops->ooblen;
1da177e4 2398
7bc3312b 2399 return 0;
8593fbc6
TG		 2400}
2401
2402/**
2403 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2404 * @mtd: MTD device structure
2405 * @to: offset to write to
2406 * @ops: oob operation description structure
8593fbc6
TG		 2407 */
2408static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2409 struct mtd_oob_ops *ops)
2410{
8593fbc6
TG		 2411 struct nand_chip *chip = mtd->priv;
2412 int ret = -ENOTSUPP;
2413
2414 ops->retlen = 0;
2415
2416 /* Do not allow writes past end of device */
7014568b 2417 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2418 pr_debug("%s: attempt to write beyond end of device\n",
2419 __func__);
8593fbc6
TG		 2420 return -EINVAL;
2421 }
2422
7bc3312b 2423 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2424
f8ac0414 2425 switch (ops->mode) {
0612b9dd
BN		 2426 case MTD_OPS_PLACE_OOB:
2427 case MTD_OPS_AUTO_OOB:
2428 case MTD_OPS_RAW:
8593fbc6
TG		 2429 break;
2430
2431 default:
2432 goto out;
2433 }
2434
2435 if (!ops->datbuf)
2436 ret = nand_do_write_oob(mtd, to, ops);
2437 else
2438 ret = nand_do_write_ops(mtd, to, ops);
2439
7351d3a5 2440out:
1da177e4 2441 nand_release_device(mtd);
1da177e4
LT		 2442 return ret;
2443}
2444
1da177e4 2445/**
7854d3f7 2446 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2447 * @mtd: MTD device structure
2448 * @page: the page address of the block which will be erased
1da177e4 2449 *
8b6e50c9 2450 * Standard erase command for NAND chips.
1da177e4 2451 */
e0c7d767 2452static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2453{
ace4dfee 2454 struct nand_chip *chip = mtd->priv;
1da177e4 2455 /* Send commands to erase a block */
ace4dfee
TG		 2456 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2457 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2458}
2459
2460/**
7854d3f7 2461 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2462 * @mtd: MTD device structure
2463 * @page: the page address of the block which will be erased
1da177e4 2464 *
8b6e50c9 2465 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2466 */
e0c7d767 2467static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2468{
ace4dfee 2469 struct nand_chip *chip = mtd->priv;
1da177e4 2470 /* Send commands to erase a block */
ace4dfee
TG		 2471 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2472 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2473 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2474 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2475 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2476}
2477
2478/**
2479 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2480 * @mtd: MTD device structure
2481 * @instr: erase instruction
1da177e4 2482 *
8b6e50c9 2483 * Erase one ore more blocks.
1da177e4 2484 */
e0c7d767 2485static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2486{
e0c7d767 2487 return nand_erase_nand(mtd, instr, 0);
1da177e4 2488}
61b03bd7 2489
30f464b7 2490#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2491/**
7854d3f7 2492 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2493 * @mtd: MTD device structure
2494 * @instr: erase instruction
2495 * @allowbbt: allow erasing the bbt area
1da177e4 2496 *
8b6e50c9 2497 * Erase one ore more blocks.
1da177e4 2498 */
ace4dfee
TG		 2499int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2500 int allowbbt)
1da177e4 2501{
69423d99 2502 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2503 struct nand_chip *chip = mtd->priv;
f8ac0414 2504 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2505 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2506 loff_t len;
1da177e4 2507
289c0522
BN		 2508 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2509 __func__, (unsigned long long)instr->addr,
2510 (unsigned long long)instr->len);
1da177e4 2511
6fe5a6ac 2512 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2513 return -EINVAL;
1da177e4 2514
1da177e4 2515 /* Grab the lock and see if the device is available */
ace4dfee 2516 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2517
2518 /* Shift to get first page */
ace4dfee
TG		 2519 page = (int)(instr->addr >> chip->page_shift);
2520 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2521
2522 /* Calculate pages in each block */
ace4dfee 2523 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2524
2525 /* Select the NAND device */
ace4dfee 2526 chip->select_chip(mtd, chipnr);
1da177e4 2527
1da177e4
LT		 2528 /* Check, if it is write protected */
2529 if (nand_check_wp(mtd)) {
289c0522
BN		 2530 pr_debug("%s: device is write protected!\n",
2531 __func__);
1da177e4
LT		 2532 instr->state = MTD_ERASE_FAILED;
2533 goto erase_exit;
2534 }
2535
ace4dfee
TG		 2536 /*
2537 * If BBT requires refresh, set the BBT page mask to see if the BBT
2538 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2539 * can not be matched. This is also done when the bbt is actually
7854d3f7 2540 * erased to avoid recursive updates.
ace4dfee
TG		 2541 */
2542 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2543 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2544
1da177e4
LT		 2545 /* Loop through the pages */
2546 len = instr->len;
2547
2548 instr->state = MTD_ERASING;
2549
2550 while (len) {
12183a20 2551 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2552 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2553 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2554 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2555 __func__, page);
1da177e4
LT		 2556 instr->state = MTD_ERASE_FAILED;
2557 goto erase_exit;
2558 }
61b03bd7 2559
ace4dfee
TG		 2560 /*
2561 * Invalidate the page cache, if we erase the block which
8b6e50c9 2562 * contains the current cached page.
ace4dfee
TG		 2563 */
2564 if (page <= chip->pagebuf && chip->pagebuf <
2565 (page + pages_per_block))
2566 chip->pagebuf = -1;
1da177e4 2567
ace4dfee 2568 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2569
7bc3312b 2570 status = chip->waitfunc(mtd, chip);
1da177e4 2571
ace4dfee
TG		 2572 /*
2573 * See if operation failed and additional status checks are
2574 * available
2575 */
2576 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2577 status = chip->errstat(mtd, chip, FL_ERASING,
2578 status, page);
068e3c0a 2579
1da177e4 2580 /* See if block erase succeeded */
a4ab4c5d 2581 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2582 pr_debug("%s: failed erase, page 0x%08x\n",
2583 __func__, page);
1da177e4 2584 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2585 instr->fail_addr =
2586 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2587 goto erase_exit;
2588 }
30f464b7 2589
ace4dfee
TG		 2590 /*
2591 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2592 * page being erased.
ace4dfee
TG		 2593 */
2594 if (bbt_masked_page != 0xffffffff &&
2595 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2596 rewrite_bbt[chipnr] =
2597 ((loff_t)page << chip->page_shift);
61b03bd7 2598
1da177e4 2599 /* Increment page address and decrement length */
ace4dfee 2600 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2601 page += pages_per_block;
2602
2603 /* Check, if we cross a chip boundary */
ace4dfee 2604 if (len && !(page & chip->pagemask)) {
1da177e4 2605 chipnr++;
ace4dfee
TG		 2606 chip->select_chip(mtd, -1);
2607 chip->select_chip(mtd, chipnr);
30f464b7 2608
ace4dfee
TG		 2609 /*
2610 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2611 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2612 */
2613 if (bbt_masked_page != 0xffffffff &&
2614 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2615 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2616 BBT_PAGE_MASK;
1da177e4
LT		 2617 }
2618 }
2619 instr->state = MTD_ERASE_DONE;
2620
7351d3a5 2621erase_exit:
1da177e4
LT		 2622
2623 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2624
2625 /* Deselect and wake up anyone waiting on the device */
2626 nand_release_device(mtd);
2627
49defc01
DW		 2628 /* Do call back function */
2629 if (!ret)
2630 mtd_erase_callback(instr);
2631
ace4dfee
TG		 2632 /*
2633 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2634 * selected bad block tables.
ace4dfee
TG		 2635 */
2636 if (bbt_masked_page == 0xffffffff || ret)
2637 return ret;
2638
2639 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2640 if (!rewrite_bbt[chipnr])
2641 continue;
8b6e50c9 2642 /* Update the BBT for chip */
289c0522
BN		 2643 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2644 __func__, chipnr, rewrite_bbt[chipnr],
2645 chip->bbt_td->pages[chipnr]);
ace4dfee 2646 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2647 }
2648
1da177e4
LT		 2649 /* Return more or less happy */
2650 return ret;
2651}
2652
2653/**
2654 * nand_sync - [MTD Interface] sync
8b6e50c9 2655 * @mtd: MTD device structure
1da177e4 2656 *
8b6e50c9 2657 * Sync is actually a wait for chip ready function.
1da177e4 2658 */
e0c7d767 2659static void nand_sync(struct mtd_info *mtd)
1da177e4 2660{
ace4dfee 2661 struct nand_chip *chip = mtd->priv;
1da177e4 2662
289c0522 2663 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2664
2665 /* Grab the lock and see if the device is available */
ace4dfee 2666 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2667 /* Release it and go back */
e0c7d767 2668 nand_release_device(mtd);
1da177e4
LT		 2669}
2670
1da177e4 2671/**
ace4dfee 2672 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2673 * @mtd: MTD device structure
2674 * @offs: offset relative to mtd start
1da177e4 2675 */
ace4dfee 2676static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2677{
ace4dfee 2678 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2679}
2680
2681/**
ace4dfee 2682 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2683 * @mtd: MTD device structure
2684 * @ofs: offset relative to mtd start
1da177e4 2685 */
e0c7d767 2686static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2687{
ace4dfee 2688 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2689 int ret;
2690
f8ac0414
FF		 2691 ret = nand_block_isbad(mtd, ofs);
2692 if (ret) {
8b6e50c9 2693 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2694 if (ret > 0)
2695 return 0;
e0c7d767
DW		 2696 return ret;
2697 }
1da177e4 2698
ace4dfee 2699 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2700}
2701
7db03ecc
HS		 2702/**
2703 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2704 * @mtd: MTD device structure
2705 * @chip: nand chip info structure
2706 * @addr: feature address.
2707 * @subfeature_param: the subfeature parameters, a four bytes array.
2708 */
2709static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2710 int addr, uint8_t *subfeature_param)
2711{
2712 int status;
2713
2714 if (!chip->onfi_version)
2715 return -EINVAL;
2716
2717 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2718 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2719 status = chip->waitfunc(mtd, chip);
2720 if (status & NAND_STATUS_FAIL)
2721 return -EIO;
2722 return 0;
2723}
2724
2725/**
2726 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2727 * @mtd: MTD device structure
2728 * @chip: nand chip info structure
2729 * @addr: feature address.
2730 * @subfeature_param: the subfeature parameters, a four bytes array.
2731 */
2732static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2733 int addr, uint8_t *subfeature_param)
2734{
2735 if (!chip->onfi_version)
2736 return -EINVAL;
2737
2738 /* clear the sub feature parameters */
2739 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2740
2741 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2742 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2743 return 0;
2744}
2745
962034f4
VW		 2746/**
2747 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2748 * @mtd: MTD device structure
962034f4
VW		 2749 */
2750static int nand_suspend(struct mtd_info *mtd)
2751{
ace4dfee 2752 struct nand_chip *chip = mtd->priv;
962034f4 2753
ace4dfee 2754 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2755}
2756
2757/**
2758 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2759 * @mtd: MTD device structure
962034f4
VW		 2760 */
2761static void nand_resume(struct mtd_info *mtd)
2762{
ace4dfee 2763 struct nand_chip *chip = mtd->priv;
962034f4 2764
ace4dfee 2765 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2766 nand_release_device(mtd);
2767 else
d0370219
BN		 2768 pr_err("%s called for a chip which is not in suspended state\n",
2769 __func__);
962034f4
VW		 2770}
2771
8b6e50c9 2772/* Set default functions */
ace4dfee 2773static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2774{
1da177e4 2775 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2776 if (!chip->chip_delay)
2777 chip->chip_delay = 20;
1da177e4
LT		 2778
2779 /* check, if a user supplied command function given */
ace4dfee
TG		 2780 if (chip->cmdfunc == NULL)
2781 chip->cmdfunc = nand_command;
1da177e4
LT		 2782
2783 /* check, if a user supplied wait function given */
ace4dfee
TG		 2784 if (chip->waitfunc == NULL)
2785 chip->waitfunc = nand_wait;
2786
2787 if (!chip->select_chip)
2788 chip->select_chip = nand_select_chip;
2789 if (!chip->read_byte)
2790 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2791 if (!chip->read_word)
2792 chip->read_word = nand_read_word;
2793 if (!chip->block_bad)
2794 chip->block_bad = nand_block_bad;
2795 if (!chip->block_markbad)
2796 chip->block_markbad = nand_default_block_markbad;
2797 if (!chip->write_buf)
2798 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2799 if (!chip->read_buf)
2800 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 2801 if (!chip->scan_bbt)
2802 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2803
2804 if (!chip->controller) {
2805 chip->controller = &chip->hwcontrol;
2806 spin_lock_init(&chip->controller->lock);
2807 init_waitqueue_head(&chip->controller->wq);
2808 }
2809
7aa65bfd
TG		 2810}
2811
8b6e50c9 2812/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2813static void sanitize_string(uint8_t *s, size_t len)
2814{
2815 ssize_t i;
2816
8b6e50c9 2817 /* Null terminate */
d1e1f4e4
FF		 2818 s[len - 1] = 0;
2819
8b6e50c9 2820 /* Remove non printable chars */
d1e1f4e4
FF		 2821 for (i = 0; i < len - 1; i++) {
2822 if (s[i] < ' ' || s[i] > 127)
2823 s[i] = '?';
2824 }
2825
8b6e50c9 2826 /* Remove trailing spaces */
d1e1f4e4
FF		 2827 strim(s);
2828}
2829
2830static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2831{
2832 int i;
2833 while (len--) {
2834 crc ^= *p++ << 8;
2835 for (i = 0; i < 8; i++)
2836 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2837 }
2838
2839 return crc;
2840}
2841
6fb277ba 2842/*
8b6e50c9 2843 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2844 */
2845static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2846 int *busw)
6fb277ba
FF		 2847{
2848 struct nand_onfi_params *p = &chip->onfi_params;
2849 int i;
2850 int val;
2851
7854d3f7 2852 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2853 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2854 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2855 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2856 return 0;
2857
6fb277ba
FF		 2858 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2859 for (i = 0; i < 3; i++) {
2860 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2861 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2862 le16_to_cpu(p->crc)) {
9a4d4d69 2863 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2864 break;
2865 }
2866 }
2867
2868 if (i == 3)
2869 return 0;
2870
8b6e50c9 2871 /* Check version */
6fb277ba 2872 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2873 if (val & (1 << 5))
2874 chip->onfi_version = 23;
2875 else if (val & (1 << 4))
6fb277ba
FF		 2876 chip->onfi_version = 22;
2877 else if (val & (1 << 3))
2878 chip->onfi_version = 21;
2879 else if (val & (1 << 2))
2880 chip->onfi_version = 20;
b7b1a29d 2881 else if (val & (1 << 1))
6fb277ba 2882 chip->onfi_version = 10;
b7b1a29d
BN		 2883 else
2884 chip->onfi_version = 0;
2885
2886 if (!chip->onfi_version) {
d0370219 2887 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2888 return 0;
2889 }
6fb277ba
FF		 2890
2891 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2892 sanitize_string(p->model, sizeof(p->model));
2893 if (!mtd->name)
2894 mtd->name = p->model;
2895 mtd->writesize = le32_to_cpu(p->byte_per_page);
2896 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2897 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2898 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2899 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2900 *busw = 0;
6fb277ba 2901 if (le16_to_cpu(p->features) & 1)
08c248fb 2902 *busw = NAND_BUSWIDTH_16;
6fb277ba 2903
d42b5de3 2904 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2905 return 1;
2906}
2907
e3b88bd6
BN		 2908/*
2909 * nand_id_has_period - Check if an ID string has a given wraparound period
2910 * @id_data: the ID string
2911 * @arrlen: the length of the @id_data array
2912 * @period: the period of repitition
2913 *
2914 * Check if an ID string is repeated within a given sequence of bytes at
2915 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2916 * period of 2). This is a helper function for nand_id_len(). Returns non-zero
2917 * if the repetition has a period of @period; otherwise, returns zero.
2918 */
2919static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2920{
2921 int i, j;
2922 for (i = 0; i < period; i++)
2923 for (j = i + period; j < arrlen; j += period)
2924 if (id_data[i] != id_data[j])
2925 return 0;
2926 return 1;
2927}
2928
2929/*
2930 * nand_id_len - Get the length of an ID string returned by CMD_READID
2931 * @id_data: the ID string
2932 * @arrlen: the length of the @id_data array
2933
2934 * Returns the length of the ID string, according to known wraparound/trailing
2935 * zero patterns. If no pattern exists, returns the length of the array.
2936 */
2937static int nand_id_len(u8 *id_data, int arrlen)
2938{
2939 int last_nonzero, period;
2940
2941 /* Find last non-zero byte */
2942 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2943 if (id_data[last_nonzero])
2944 break;
2945
2946 /* All zeros */
2947 if (last_nonzero < 0)
2948 return 0;
2949
2950 /* Calculate wraparound period */
2951 for (period = 1; period < arrlen; period++)
2952 if (nand_id_has_period(id_data, arrlen, period))
2953 break;
2954
2955 /* There's a repeated pattern */
2956 if (period < arrlen)
2957 return period;
2958
2959 /* There are trailing zeros */
2960 if (last_nonzero < arrlen - 1)
2961 return last_nonzero + 1;
2962
2963 /* No pattern detected */
2964 return arrlen;
2965}
2966
fc09bbc0
BN		 2967/*
2968 * Many new NAND share similar device ID codes, which represent the size of the
2969 * chip. The rest of the parameters must be decoded according to generic or
2970 * manufacturer-specific "extended ID" decoding patterns.
2971 */
2972static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2973 u8 id_data[8], int *busw)
2974{
e3b88bd6 2975 int extid, id_len;
fc09bbc0
BN		 2976 /* The 3rd id byte holds MLC / multichip data */
2977 chip->cellinfo = id_data[2];
2978 /* The 4th id byte is the important one */
2979 extid = id_data[3];
2980
e3b88bd6
BN		 2981 id_len = nand_id_len(id_data, 8);
2982
fc09bbc0
BN		 2983 /*
2984 * Field definitions are in the following datasheets:
2985 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 2986 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 2987 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 2988 *
af451af4
BN		 2989 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2990 * ID to decide what to do.
fc09bbc0 2991 */
af451af4 2992 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
6924d99f 2993 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
af451af4 2994 id_data[5] != 0x00) {
fc09bbc0
BN		 2995 /* Calc pagesize */
2996 mtd->writesize = 2048 << (extid & 0x03);
2997 extid >>= 2;
2998 /* Calc oobsize */
e2d3a35e 2999 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3000 case 1:
3001 mtd->oobsize = 128;
3002 break;
3003 case 2:
3004 mtd->oobsize = 218;
3005 break;
3006 case 3:
3007 mtd->oobsize = 400;
3008 break;
e2d3a35e 3009 case 4:
fc09bbc0
BN		 3010 mtd->oobsize = 436;
3011 break;
e2d3a35e
BN		 3012 case 5:
3013 mtd->oobsize = 512;
3014 break;
3015 case 6:
3016 default: /* Other cases are "reserved" (unknown) */
3017 mtd->oobsize = 640;
3018 break;
fc09bbc0
BN		 3019 }
3020 extid >>= 2;
3021 /* Calc blocksize */
3022 mtd->erasesize = (128 * 1024) <<
3023 (((extid >> 1) & 0x04) | (extid & 0x03));
3024 *busw = 0;
73ca392f
BN		 3025 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3026 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3027 unsigned int tmp;
3028
3029 /* Calc pagesize */
3030 mtd->writesize = 2048 << (extid & 0x03);
3031 extid >>= 2;
3032 /* Calc oobsize */
3033 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3034 case 0:
3035 mtd->oobsize = 128;
3036 break;
3037 case 1:
3038 mtd->oobsize = 224;
3039 break;
3040 case 2:
3041 mtd->oobsize = 448;
3042 break;
3043 case 3:
3044 mtd->oobsize = 64;
3045 break;
3046 case 4:
3047 mtd->oobsize = 32;
3048 break;
3049 case 5:
3050 mtd->oobsize = 16;
3051 break;
3052 default:
3053 mtd->oobsize = 640;
3054 break;
3055 }
3056 extid >>= 2;
3057 /* Calc blocksize */
3058 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3059 if (tmp < 0x03)
3060 mtd->erasesize = (128 * 1024) << tmp;
3061 else if (tmp == 0x03)
3062 mtd->erasesize = 768 * 1024;
3063 else
3064 mtd->erasesize = (64 * 1024) << tmp;
3065 *busw = 0;
fc09bbc0
BN		 3066 } else {
3067 /* Calc pagesize */
3068 mtd->writesize = 1024 << (extid & 0x03);
3069 extid >>= 2;
3070 /* Calc oobsize */
3071 mtd->oobsize = (8 << (extid & 0x01)) *
3072 (mtd->writesize >> 9);
3073 extid >>= 2;
3074 /* Calc blocksize. Blocksize is multiples of 64KiB */
3075 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3076 extid >>= 2;
3077 /* Get buswidth information */
3078 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3079 }
3080}
3081
f23a481c
BN		 3082/*
3083 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3084 * decodes a matching ID table entry and assigns the MTD size parameters for
3085 * the chip.
3086 */
3087static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3088 struct nand_flash_dev *type, u8 id_data[8],
3089 int *busw)
3090{
3091 int maf_id = id_data[0];
3092
3093 mtd->erasesize = type->erasesize;
3094 mtd->writesize = type->pagesize;
3095 mtd->oobsize = mtd->writesize / 32;
3096 *busw = type->options & NAND_BUSWIDTH_16;
3097
3098 /*
3099 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3100 * some Spansion chips have erasesize that conflicts with size
3101 * listed in nand_ids table.
3102 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3103 */
3104 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3105 && id_data[6] == 0x00 && id_data[7] == 0x00
3106 && mtd->writesize == 512) {
3107 mtd->erasesize = 128 * 1024;
3108 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3109 }
3110}
3111
7e74c2d7
BN		 3112/*
3113 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3114 * heuristic patterns using various detected parameters (e.g., manufacturer,
3115 * page size, cell-type information).
3116 */
3117static void nand_decode_bbm_options(struct mtd_info *mtd,
3118 struct nand_chip *chip, u8 id_data[8])
3119{
3120 int maf_id = id_data[0];
3121
3122 /* Set the bad block position */
3123 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3124 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3125 else
3126 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3127
3128 /*
3129 * Bad block marker is stored in the last page of each block on Samsung
3130 * and Hynix MLC devices; stored in first two pages of each block on
3131 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3132 * AMD/Spansion, and Macronix. All others scan only the first page.
3133 */
3134 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3135 (maf_id == NAND_MFR_SAMSUNG ||
3136 maf_id == NAND_MFR_HYNIX))
3137 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3138 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139 (maf_id == NAND_MFR_SAMSUNG ||
3140 maf_id == NAND_MFR_HYNIX ||
3141 maf_id == NAND_MFR_TOSHIBA ||
3142 maf_id == NAND_MFR_AMD ||
3143 maf_id == NAND_MFR_MACRONIX)) ||
3144 (mtd->writesize == 2048 &&
3145 maf_id == NAND_MFR_MICRON))
3146 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3147}
3148
7aa65bfd 3149/*
8b6e50c9 3150 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3151 */
3152static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3153 struct nand_chip *chip,
7351d3a5
FF		 3154 int busw,
3155 int *maf_id, int *dev_id,
5e81e88a 3156 struct nand_flash_dev *type)
7aa65bfd 3157{
d1e1f4e4 3158 int i, maf_idx;
426c457a 3159 u8 id_data[8];
1da177e4
LT		 3160
3161 /* Select the device */
ace4dfee 3162 chip->select_chip(mtd, 0);
1da177e4 3163
ef89a880
KB		 3164 /*
3165 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3166 * after power-up.
ef89a880
KB		 3167 */
3168 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3169
1da177e4 3170 /* Send the command for reading device ID */
ace4dfee 3171 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3172
3173 /* Read manufacturer and device IDs */
ace4dfee 3174 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3175 *dev_id = chip->read_byte(mtd);
1da177e4 3176
8b6e50c9
BN		 3177 /*
3178 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3179 * interface concerns can cause random data which looks like a
3180 * possibly credible NAND flash to appear. If the two results do
3181 * not match, ignore the device completely.
3182 */
3183
3184 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3185
4aef9b78
BN		 3186 /* Read entire ID string */
3187 for (i = 0; i < 8; i++)
426c457a 3188 id_data[i] = chip->read_byte(mtd);
ed8165c7 3189
d1e1f4e4 3190 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 3191 pr_info("%s: second ID read did not match "
d0370219
BN		 3192 "%02x,%02x against %02x,%02x\n", __func__,
3193 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3194 return ERR_PTR(-ENODEV);
3195 }
3196
7aa65bfd 3197 if (!type)
5e81e88a
DW		 3198 type = nand_flash_ids;
3199
3200 for (; type->name != NULL; type++)
d1e1f4e4 3201 if (*dev_id == type->id)
f8ac0414 3202 break;
5e81e88a 3203
d1e1f4e4
FF		 3204 chip->onfi_version = 0;
3205 if (!type->name || !type->pagesize) {
6fb277ba 3206 /* Check is chip is ONFI compliant */
47450b35 3207 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3208 goto ident_done;
d1e1f4e4
FF		 3209 }
3210
5e81e88a 3211 if (!type->name)
7aa65bfd
TG		 3212 return ERR_PTR(-ENODEV);
3213
ba0251fe
TG		 3214 if (!mtd->name)
3215 mtd->name = type->name;
3216
69423d99 3217 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3218
12a40a57 3219 if (!type->pagesize && chip->init_size) {
8b6e50c9 3220 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3221 busw = chip->init_size(mtd, chip, id_data);
3222 } else if (!type->pagesize) {
fc09bbc0
BN		 3223 /* Decode parameters from extended ID */
3224 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3225 } else {
f23a481c 3226 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3227 }
bf7a01bf
BN		 3228 /* Get chip options */
3229 chip->options |= type->options;
d1e1f4e4 3230
8b6e50c9
BN		 3231 /*
3232 * Check if chip is not a Samsung device. Do not clear the
3233 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3234 */
3235 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3236 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3237ident_done:
3238
7aa65bfd 3239 /* Try to identify manufacturer */
9a909867 3240 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3241 if (nand_manuf_ids[maf_idx].id == *maf_id)
3242 break;
3243 }
0ea4a755 3244
7aa65bfd
TG		 3245 /*
3246 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3247 * chip correct!
7aa65bfd 3248 */
ace4dfee 3249 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3250 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3251 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3252 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3253 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3254 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3255 busw ? 16 : 8);
7aa65bfd
TG		 3256 return ERR_PTR(-EINVAL);
3257 }
61b03bd7 3258
7e74c2d7
BN		 3259 nand_decode_bbm_options(mtd, chip, id_data);
3260
7aa65bfd 3261 /* Calculate the address shift from the page size */
ace4dfee 3262 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3263 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3264 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3265
ace4dfee 3266 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3267 ffs(mtd->erasesize) - 1;
69423d99
AH		 3268 if (chip->chipsize & 0xffffffff)
3269 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3270 else {
3271 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3272 chip->chip_shift += 32 - 1;
3273 }
1da177e4 3274
26d9be11
AB		 3275 chip->badblockbits = 8;
3276
7aa65bfd 3277 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3278 if (chip->options & NAND_4PAGE_ARRAY)
3279 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3280 else
ace4dfee 3281 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3282
8b6e50c9 3283 /* Do not replace user supplied command function! */
ace4dfee
TG		 3284 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3285 chip->cmdfunc = nand_command_lp;
7aa65bfd 3286
886bd33d
HS		 3287 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3288 " page size: %d, OOB size: %d\n",
3289 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3290 chip->onfi_version ? chip->onfi_params.model : type->name,
3291 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3292
3293 return type;
3294}
3295
7aa65bfd 3296/**
3b85c321 3297 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3298 * @mtd: MTD device structure
3299 * @maxchips: number of chips to scan for
3300 * @table: alternative NAND ID table
7aa65bfd 3301 *
8b6e50c9
BN		 3302 * This is the first phase of the normal nand_scan() function. It reads the
3303 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3304 *
3b85c321 3305 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3306 */
5e81e88a
DW		 3307int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3308 struct nand_flash_dev *table)
7aa65bfd 3309{
d1e1f4e4 3310 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3311 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3312 struct nand_flash_dev *type;
3313
7aa65bfd 3314 /* Get buswidth to select the correct functions */
ace4dfee 3315 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3316 /* Set the default functions */
ace4dfee 3317 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3318
3319 /* Read the flash type */
7351d3a5
FF		 3320 type = nand_get_flash_type(mtd, chip, busw,
3321 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3322
3323 if (IS_ERR(type)) {
b1c6e6db 3324 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3325 pr_warn("No NAND device found\n");
ace4dfee 3326 chip->select_chip(mtd, -1);
7aa65bfd 3327 return PTR_ERR(type);
1da177e4
LT		 3328 }
3329
7aa65bfd 3330 /* Check for a chip array */
e0c7d767 3331 for (i = 1; i < maxchips; i++) {
ace4dfee 3332 chip->select_chip(mtd, i);
ef89a880
KB		 3333 /* See comment in nand_get_flash_type for reset */
3334 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3335 /* Send the command for reading device ID */
ace4dfee 3336 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3337 /* Read manufacturer and device IDs */
ace4dfee 3338 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3339 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3340 break;
3341 }
3342 if (i > 1)
9a4d4d69 3343 pr_info("%d NAND chips detected\n", i);
61b03bd7 3344
1da177e4 3345 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3346 chip->numchips = i;
3347 mtd->size = i * chip->chipsize;
7aa65bfd 3348
3b85c321
DW		 3349 return 0;
3350}
7351d3a5 3351EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3352
3353
3354/**
3355 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3356 * @mtd: MTD device structure
3b85c321 3357 *
8b6e50c9
BN		 3358 * This is the second phase of the normal nand_scan() function. It fills out
3359 * all the uninitialized function pointers with the defaults and scans for a
3360 * bad block table if appropriate.
3b85c321
DW		 3361 */
3362int nand_scan_tail(struct mtd_info *mtd)
3363{
3364 int i;
3365 struct nand_chip *chip = mtd->priv;
3366
e2414f4c
BN		 3367 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3368 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3369 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3370
4bf63fcb
DW		 3371 if (!(chip->options & NAND_OWN_BUFFERS))
3372 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3373 if (!chip->buffers)
3374 return -ENOMEM;
3375
7dcdcbef 3376 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3377 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3378
7aa65bfd 3379 /*
8b6e50c9 3380 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3381 */
193bd400 3382 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3383 switch (mtd->oobsize) {
1da177e4 3384 case 8:
5bd34c09 3385 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3386 break;
3387 case 16:
5bd34c09 3388 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3389 break;
3390 case 64:
5bd34c09 3391 chip->ecc.layout = &nand_oob_64;
1da177e4 3392 break;
81ec5364
TG		 3393 case 128:
3394 chip->ecc.layout = &nand_oob_128;
3395 break;
1da177e4 3396 default:
d0370219
BN		 3397 pr_warn("No oob scheme defined for oobsize %d\n",
3398 mtd->oobsize);
1da177e4
LT		 3399 BUG();
3400 }
3401 }
61b03bd7 3402
956e944c
DW		 3403 if (!chip->write_page)
3404 chip->write_page = nand_write_page;
3405
7db03ecc
HS		 3406 /* set for ONFI nand */
3407 if (!chip->onfi_set_features)
3408 chip->onfi_set_features = nand_onfi_set_features;
3409 if (!chip->onfi_get_features)
3410 chip->onfi_get_features = nand_onfi_get_features;
3411
61b03bd7 3412 /*
8b6e50c9 3413 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3414 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3415 */
956e944c 3416
ace4dfee 3417 switch (chip->ecc.mode) {
6e0cb135
SN		 3418 case NAND_ECC_HW_OOB_FIRST:
3419 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3420 if (!chip->ecc.calculate || !chip->ecc.correct ||
3421 !chip->ecc.hwctl) {
9a4d4d69 3422 pr_warn("No ECC functions supplied; "
d0370219 3423 "hardware ECC not possible\n");
6e0cb135
SN		 3424 BUG();
3425 }
3426 if (!chip->ecc.read_page)
3427 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3428
6dfc6d25 3429 case NAND_ECC_HW:
8b6e50c9 3430 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3431 if (!chip->ecc.read_page)
3432 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3433 if (!chip->ecc.write_page)
3434 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3435 if (!chip->ecc.read_page_raw)
3436 chip->ecc.read_page_raw = nand_read_page_raw;
3437 if (!chip->ecc.write_page_raw)
3438 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3439 if (!chip->ecc.read_oob)
3440 chip->ecc.read_oob = nand_read_oob_std;
3441 if (!chip->ecc.write_oob)
3442 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3443
6dfc6d25 3444 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3445 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3446 !chip->ecc.hwctl) &&
3447 (!chip->ecc.read_page ||
1c45f604 3448 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3449 !chip->ecc.write_page ||
1c45f604 3450 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3451 pr_warn("No ECC functions supplied; "
d0370219 3452 "hardware ECC not possible\n");
6dfc6d25
TG		 3453 BUG();
3454 }
8b6e50c9 3455 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3456 if (!chip->ecc.read_page)
3457 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3458 if (!chip->ecc.write_page)
3459 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3460 if (!chip->ecc.read_page_raw)
3461 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3462 if (!chip->ecc.write_page_raw)
3463 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3464 if (!chip->ecc.read_oob)
3465 chip->ecc.read_oob = nand_read_oob_syndrome;
3466 if (!chip->ecc.write_oob)
3467 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3468
e2788c98
MD		 3469 if (mtd->writesize >= chip->ecc.size) {
3470 if (!chip->ecc.strength) {
3471 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3472 BUG();
3473 }
6dfc6d25 3474 break;
e2788c98 3475 }
9a4d4d69 3476 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3477 "%d byte page size, fallback to SW ECC\n",
3478 chip->ecc.size, mtd->writesize);
ace4dfee 3479 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3480
6dfc6d25 3481 case NAND_ECC_SOFT:
ace4dfee
TG		 3482 chip->ecc.calculate = nand_calculate_ecc;
3483 chip->ecc.correct = nand_correct_data;
f5bbdacc 3484 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3485 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3486 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3487 chip->ecc.read_page_raw = nand_read_page_raw;
3488 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3489 chip->ecc.read_oob = nand_read_oob_std;
3490 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3491 if (!chip->ecc.size)
3492 chip->ecc.size = 256;
ace4dfee 3493 chip->ecc.bytes = 3;
6a918bad 3494 chip->ecc.strength = 1;
1da177e4 3495 break;
61b03bd7 3496
193bd400
ID		 3497 case NAND_ECC_SOFT_BCH:
3498 if (!mtd_nand_has_bch()) {
9a4d4d69 3499 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3500 BUG();
3501 }
3502 chip->ecc.calculate = nand_bch_calculate_ecc;
3503 chip->ecc.correct = nand_bch_correct_data;
3504 chip->ecc.read_page = nand_read_page_swecc;
3505 chip->ecc.read_subpage = nand_read_subpage;
3506 chip->ecc.write_page = nand_write_page_swecc;
3507 chip->ecc.read_page_raw = nand_read_page_raw;
3508 chip->ecc.write_page_raw = nand_write_page_raw;
3509 chip->ecc.read_oob = nand_read_oob_std;
3510 chip->ecc.write_oob = nand_write_oob_std;
3511 /*
3512 * Board driver should supply ecc.size and ecc.bytes values to
3513 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3514 * for details. Otherwise, default to 4 bits for large page
3515 * devices.
193bd400
ID		 3516 */
3517 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3518 chip->ecc.size = 512;
3519 chip->ecc.bytes = 7;
3520 }
3521 chip->ecc.priv = nand_bch_init(mtd,
3522 chip->ecc.size,
3523 chip->ecc.bytes,
3524 &chip->ecc.layout);
3525 if (!chip->ecc.priv) {
9a4d4d69 3526 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3527 BUG();
3528 }
6a918bad 3529 chip->ecc.strength =
e2788c98 3530 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3531 break;
3532
61b03bd7 3533 case NAND_ECC_NONE:
9a4d4d69 3534 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3535 "This is not recommended!\n");
8593fbc6
TG		 3536 chip->ecc.read_page = nand_read_page_raw;
3537 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3538 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3539 chip->ecc.read_page_raw = nand_read_page_raw;
3540 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3541 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3542 chip->ecc.size = mtd->writesize;
3543 chip->ecc.bytes = 0;
6a918bad 3544 chip->ecc.strength = 0;
1da177e4 3545 break;
956e944c 3546
1da177e4 3547 default:
d0370219 3548 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3549 BUG();
1da177e4 3550 }
61b03bd7 3551
9ce244b3 3552 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3553 if (!chip->ecc.read_oob_raw)
3554 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3555 if (!chip->ecc.write_oob_raw)
3556 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3557
5bd34c09
TG		 3558 /*
3559 * The number of bytes available for a client to place data into
8b6e50c9 3560 * the out of band area.
5bd34c09
TG		 3561 */
3562 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3563 for (i = 0; chip->ecc.layout->oobfree[i].length
3564 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3565 chip->ecc.layout->oobavail +=
3566 chip->ecc.layout->oobfree[i].length;
1f92267c 3567 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3568
7aa65bfd
TG		 3569 /*
3570 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3571 * mode.
7aa65bfd 3572 */
ace4dfee 3573 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3574 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3575 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3576 BUG();
1da177e4 3577 }
f5bbdacc 3578 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3579
8b6e50c9 3580 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3581 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3582 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3583 switch (chip->ecc.steps) {
29072b96
TG		 3584 case 2:
3585 mtd->subpage_sft = 1;
3586 break;
3587 case 4:
3588 case 8:
81ec5364 3589 case 16:
29072b96
TG		 3590 mtd->subpage_sft = 2;
3591 break;
3592 }
3593 }
3594 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3595
04bbd0ea 3596 /* Initialize state */
ace4dfee 3597 chip->state = FL_READY;
1da177e4
LT		 3598
3599 /* De-select the device */
ace4dfee 3600 chip->select_chip(mtd, -1);
1da177e4
LT		 3601
3602 /* Invalidate the pagebuffer reference */
ace4dfee 3603 chip->pagebuf = -1;
1da177e4 3604
a5ff4f10
JW		 3605 /* Large page NAND with SOFT_ECC should support subpage reads */
3606 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3607 chip->options |= NAND_SUBPAGE_READ;
3608
1da177e4
LT		 3609 /* Fill in remaining MTD driver data */
3610 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3611 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3612 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3613 mtd->_erase = nand_erase;
3614 mtd->_point = NULL;
3615 mtd->_unpoint = NULL;
3616 mtd->_read = nand_read;
3617 mtd->_write = nand_write;
3618 mtd->_panic_write = panic_nand_write;
3619 mtd->_read_oob = nand_read_oob;
3620 mtd->_write_oob = nand_write_oob;
3621 mtd->_sync = nand_sync;
3622 mtd->_lock = NULL;
3623 mtd->_unlock = NULL;
3624 mtd->_suspend = nand_suspend;
3625 mtd->_resume = nand_resume;
3626 mtd->_block_isbad = nand_block_isbad;
3627 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3628 mtd->writebufsize = mtd->writesize;
1da177e4 3629
6a918bad 3630 /* propagate ecc info to mtd_info */
5bd34c09 3631 mtd->ecclayout = chip->ecc.layout;
86c2072b 3632 mtd->ecc_strength = chip->ecc.strength;
ea3b2ea2
SL		 3633 /*
3634 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3635 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3636 * properly set.
3637 */
3638 if (!mtd->bitflip_threshold)
3639 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3640
0040bf38 3641 /* Check, if we should skip the bad block table scan */
ace4dfee 3642 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3643 return 0;
1da177e4
LT		 3644
3645 /* Build bad block table */
ace4dfee 3646 return chip->scan_bbt(mtd);
1da177e4 3647}
7351d3a5 3648EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3649
8b6e50c9
BN		 3650/*
3651 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3652 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3653 * to call us from in-kernel code if the core NAND support is modular.
3654 */
3b85c321
DW		 3655#ifdef MODULE
3656#define caller_is_module() (1)
3657#else
3658#define caller_is_module() \
a6e6abd5 3659 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3660#endif
3661
3662/**
3663 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3664 * @mtd: MTD device structure
3665 * @maxchips: number of chips to scan for
3b85c321 3666 *
8b6e50c9
BN		 3667 * This fills out all the uninitialized function pointers with the defaults.
3668 * The flash ID is read and the mtd/chip structures are filled with the
3669 * appropriate values. The mtd->owner field must be set to the module of the
3670 * caller.
3b85c321
DW		 3671 */
3672int nand_scan(struct mtd_info *mtd, int maxchips)
3673{
3674 int ret;
3675
3676 /* Many callers got this wrong, so check for it for a while... */
3677 if (!mtd->owner && caller_is_module()) {
d0370219 3678 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3679 BUG();
3680 }
3681
5e81e88a 3682 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3683 if (!ret)
3684 ret = nand_scan_tail(mtd);
3685 return ret;
3686}
7351d3a5 3687EXPORT_SYMBOL(nand_scan);
3b85c321 3688
1da177e4 3689/**
61b03bd7 3690 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3691 * @mtd: MTD device structure
3692 */
e0c7d767 3693void nand_release(struct mtd_info *mtd)
1da177e4 3694{
ace4dfee 3695 struct nand_chip *chip = mtd->priv;
1da177e4 3696
193bd400
ID		 3697 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3698 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3699
5ffcaf3d 3700 mtd_device_unregister(mtd);
1da177e4 3701
fa671646 3702 /* Free bad block table memory */
ace4dfee 3703 kfree(chip->bbt);
4bf63fcb
DW		 3704 if (!(chip->options & NAND_OWN_BUFFERS))
3705 kfree(chip->buffers);
58373ff0
BN		 3706
3707 /* Free bad block descriptor memory */
3708 if (chip->badblock_pattern && chip->badblock_pattern->options
3709 & NAND_BBT_DYNAMICSTRUCT)
3710 kfree(chip->badblock_pattern);
1da177e4 3711}
e0c7d767 3712EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3713
3714static int __init nand_base_init(void)
3715{
3716 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3717 return 0;
3718}
3719
3720static void __exit nand_base_exit(void)
3721{
3722 led_trigger_unregister_simple(nand_led_trigger);
3723}
3724
3725module_init(nand_base_init);
3726module_exit(nand_base_exit);
3727
e0c7d767 3728MODULE_LICENSE("GPL");
7351d3a5
FF		 3729MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3730MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3731MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux 6.x block layer and io_uring tree(s)