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kbuild, mtd, net: a few comment typo fixes and rewording
[linux-2.6-block.git] / drivers / mtd / nand / mxc_nand.c
CommitLineData
34f6e157
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
63f1474c
SH		 33#include <linux/irq.h>
34#include <linux/completion.h>
34f6e157
SH		 35
36#include <asm/mach/flash.h>
37#include <mach/mxc_nand.h>
9467114e 38#include <mach/hardware.h>
34f6e157
SH		 39
40#define DRIVER_NAME "mxc_nand"
41
9467114e 42#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
a47bfd2e 43#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
71ec5155
SH		 44#define nfc_is_v3_2() cpu_is_mx51()
45#define nfc_is_v3() nfc_is_v3_2()
9467114e 46
34f6e157 47/* Addresses for NFC registers */
1bc99180
SH		 48#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56#define NFC_V1_V2_WRPROT (host->regs + 0x12)
57#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59#define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20)
60#define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22)
61#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
62#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
63#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
64
6e85dfdc 65#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
1bc99180
SH		 66#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
67#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
68#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
69#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
70#define NFC_V1_V2_CONFIG1_RST (1 << 6)
71#define NFC_V1_V2_CONFIG1_CE (1 << 7)
b8db2f51
SH		 72#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
73#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
74#define NFC_V2_CONFIG1_FP_INT (1 << 11)
1bc99180
SH		 75
76#define NFC_V1_V2_CONFIG2_INT (1 << 15)
77
78/*
79 * Operation modes for the NFC. Valid for v1, v2 and v3
80 * type controllers.
81 */
82#define NFC_CMD (1 << 0)
83#define NFC_ADDR (1 << 1)
84#define NFC_INPUT (1 << 2)
85#define NFC_OUTPUT (1 << 3)
86#define NFC_ID (1 << 4)
87#define NFC_STATUS (1 << 5)
34f6e157 88
71ec5155
SH		 89#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
90#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
91
92#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
93#define NFC_V3_CONFIG1_SP_EN (1 << 0)
94#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
95
96#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
97
98#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
99
100#define NFC_V3_WRPROT (host->regs_ip + 0x0)
101#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
102#define NFC_V3_WRPROT_LOCK (1 << 1)
103#define NFC_V3_WRPROT_UNLOCK (1 << 2)
104#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
105
106#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
107
108#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
109#define NFC_V3_CONFIG2_PS_512 (0 << 0)
110#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
111#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
112#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
113#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
114#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
115#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
116#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
117#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
118#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
119#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
120#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
121#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
122
123#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
124#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
125#define NFC_V3_CONFIG3_FW8 (1 << 3)
126#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
127#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
128#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
129#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
130
131#define NFC_V3_IPC (host->regs_ip + 0x2C)
132#define NFC_V3_IPC_CREQ (1 << 0)
133#define NFC_V3_IPC_INT (1 << 31)
134
135#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
34f6e157
SH		 136
137struct mxc_nand_host {
138 struct mtd_info mtd;
139 struct nand_chip nand;
140 struct mtd_partition *parts;
141 struct device *dev;
142
c6de7e1b
SH		 143 void *spare0;
144 void *main_area0;
c6de7e1b
SH		 145
146 void __iomem *base;
34f6e157 147 void __iomem *regs;
71ec5155
SH		 148 void __iomem *regs_axi;
149 void __iomem *regs_ip;
34f6e157 150 int status_request;
34f6e157
SH		 151 struct clk *clk;
152 int clk_act;
153 int irq;
94f77e50 154 int eccsize;
34f6e157 155
63f1474c 156 struct completion op_completion;
34f6e157 157
f8f9608d
SH		 158 uint8_t *data_buf;
159 unsigned int buf_start;
160 int spare_len;
5f97304e
SH		 161
162 void (*preset)(struct mtd_info *);
163 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
164 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
165 void (*send_page)(struct mtd_info *, unsigned int);
166 void (*send_read_id)(struct mxc_nand_host *);
167 uint16_t (*get_dev_status)(struct mxc_nand_host *);
7aaf28ac 168 int (*check_int)(struct mxc_nand_host *);
63f1474c 169 void (*irq_control)(struct mxc_nand_host *, int);
34f6e157
SH		 170};
171
34f6e157 172/* OOB placement block for use with hardware ecc generation */
9467114e 173static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
34f6e157
SH		 174 .eccbytes = 5,
175 .eccpos = {6, 7, 8, 9, 10},
8c1fd89a 176 .oobfree = {{0, 5}, {12, 4}, }
bd3fd62e
VB		 177};
178
9467114e 179static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
bd3fd62e
VB		 180 .eccbytes = 20,
181 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
182 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
183 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
34f6e157
SH		 184};
185
9467114e
SH		 186/* OOB description for 512 byte pages with 16 byte OOB */
187static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
188 .eccbytes = 1 * 9,
189 .eccpos = {
190 7, 8, 9, 10, 11, 12, 13, 14, 15
191 },
192 .oobfree = {
193 {.offset = 0, .length = 5}
194 }
195};
196
197/* OOB description for 2048 byte pages with 64 byte OOB */
198static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
199 .eccbytes = 4 * 9,
200 .eccpos = {
201 7, 8, 9, 10, 11, 12, 13, 14, 15,
202 23, 24, 25, 26, 27, 28, 29, 30, 31,
203 39, 40, 41, 42, 43, 44, 45, 46, 47,
204 55, 56, 57, 58, 59, 60, 61, 62, 63
205 },
206 .oobfree = {
207 {.offset = 2, .length = 4},
208 {.offset = 16, .length = 7},
209 {.offset = 32, .length = 7},
210 {.offset = 48, .length = 7}
211 }
212};
213
34f6e157
SH		 214#ifdef CONFIG_MTD_PARTITIONS
215static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
216#endif
217
218static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
219{
220 struct mxc_nand_host *host = dev_id;
221
63f1474c
SH		 222 if (!host->check_int(host))
223 return IRQ_NONE;
34f6e157 224
63f1474c
SH		 225 host->irq_control(host, 0);
226
227 complete(&host->op_completion);
34f6e157
SH		 228
229 return IRQ_HANDLED;
230}
231
71ec5155
SH		 232static int check_int_v3(struct mxc_nand_host *host)
233{
234 uint32_t tmp;
235
236 tmp = readl(NFC_V3_IPC);
237 if (!(tmp & NFC_V3_IPC_INT))
238 return 0;
239
240 tmp &= ~NFC_V3_IPC_INT;
241 writel(tmp, NFC_V3_IPC);
242
243 return 1;
244}
245
7aaf28ac
SH		 246static int check_int_v1_v2(struct mxc_nand_host *host)
247{
248 uint32_t tmp;
249
1bc99180
SH		 250 tmp = readw(NFC_V1_V2_CONFIG2);
251 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
7aaf28ac
SH		 252 return 0;
253
63f1474c
SH		 254 if (!cpu_is_mx21())
255 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
7aaf28ac
SH		 256
257 return 1;
258}
259
63f1474c
SH		 260/*
261 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
262 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
263 * driver can enable/disable the irq line rather than simply masking the
264 * interrupts.
265 */
266static void irq_control_mx21(struct mxc_nand_host *host, int activate)
267{
268 if (activate)
269 enable_irq(host->irq);
270 else
271 disable_irq_nosync(host->irq);
272}
273
274static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
275{
276 uint16_t tmp;
277
278 tmp = readw(NFC_V1_V2_CONFIG1);
279
280 if (activate)
281 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
282 else
283 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
284
285 writew(tmp, NFC_V1_V2_CONFIG1);
286}
287
288static void irq_control_v3(struct mxc_nand_host *host, int activate)
289{
290 uint32_t tmp;
291
292 tmp = readl(NFC_V3_CONFIG2);
293
294 if (activate)
295 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
296 else
297 tmp |= NFC_V3_CONFIG2_INT_MSK;
298
299 writel(tmp, NFC_V3_CONFIG2);
300}
301
34f6e157
SH		 302/* This function polls the NANDFC to wait for the basic operation to
303 * complete by checking the INT bit of config2 register.
304 */
c110eaf4 305static void wait_op_done(struct mxc_nand_host *host, int useirq)
34f6e157 306{
a47bfd2e 307 int max_retries = 8000;
34f6e157
SH		 308
309 if (useirq) {
7aaf28ac 310 if (!host->check_int(host)) {
63f1474c
SH		 311 INIT_COMPLETION(host->op_completion);
312 host->irq_control(host, 1);
313 wait_for_completion(&host->op_completion);
34f6e157
SH		 314 }
315 } else {
316 while (max_retries-- > 0) {
7aaf28ac 317 if (host->check_int(host))
34f6e157 318 break;
7aaf28ac 319
34f6e157
SH		 320 udelay(1);
321 }
43950a60 322 if (max_retries < 0)
62465491
SH		 323 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
324 __func__);
34f6e157
SH		 325 }
326}
327
71ec5155
SH		 328static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
329{
330 /* fill command */
331 writel(cmd, NFC_V3_FLASH_CMD);
332
333 /* send out command */
334 writel(NFC_CMD, NFC_V3_LAUNCH);
335
336 /* Wait for operation to complete */
337 wait_op_done(host, useirq);
338}
339
34f6e157
SH		 340/* This function issues the specified command to the NAND device and
341 * waits for completion. */
5f97304e 342static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
34f6e157
SH		 343{
344 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
345
1bc99180
SH		 346 writew(cmd, NFC_V1_V2_FLASH_CMD);
347 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
34f6e157 348
a47bfd2e
IC		 349 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
350 int max_retries = 100;
351 /* Reset completion is indicated by NFC_CONFIG2 */
352 /* being set to 0 */
353 while (max_retries-- > 0) {
1bc99180 354 if (readw(NFC_V1_V2_CONFIG2) == 0) {
a47bfd2e
IC		 355 break;
356 }
357 udelay(1);
358 }
359 if (max_retries < 0)
360 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
361 __func__);
362 } else {
363 /* Wait for operation to complete */
364 wait_op_done(host, useirq);
365 }
34f6e157
SH		 366}
367
71ec5155
SH		 368static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
369{
370 /* fill address */
371 writel(addr, NFC_V3_FLASH_ADDR0);
372
373 /* send out address */
374 writel(NFC_ADDR, NFC_V3_LAUNCH);
375
376 wait_op_done(host, 0);
377}
378
34f6e157
SH		 379/* This function sends an address (or partial address) to the
380 * NAND device. The address is used to select the source/destination for
381 * a NAND command. */
5f97304e 382static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
34f6e157
SH		 383{
384 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
385
1bc99180
SH		 386 writew(addr, NFC_V1_V2_FLASH_ADDR);
387 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
34f6e157
SH		 388
389 /* Wait for operation to complete */
c110eaf4 390 wait_op_done(host, islast);
34f6e157
SH		 391}
392
71ec5155
SH		 393static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
394{
395 struct nand_chip *nand_chip = mtd->priv;
396 struct mxc_nand_host *host = nand_chip->priv;
397 uint32_t tmp;
398
399 tmp = readl(NFC_V3_CONFIG1);
400 tmp &= ~(7 << 4);
401 writel(tmp, NFC_V3_CONFIG1);
402
403 /* transfer data from NFC ram to nand */
404 writel(ops, NFC_V3_LAUNCH);
405
406 wait_op_done(host, false);
407}
408
5f97304e 409static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
34f6e157 410{
2d69c7fa
SH		 411 struct nand_chip *nand_chip = mtd->priv;
412 struct mxc_nand_host *host = nand_chip->priv;
c5d23f1b 413 int bufs, i;
34f6e157 414
9467114e 415 if (nfc_is_v1() && mtd->writesize > 512)
c5d23f1b
SH		 416 bufs = 4;
417 else
418 bufs = 1;
34f6e157 419
c5d23f1b 420 for (i = 0; i < bufs; i++) {
34f6e157 421
c5d23f1b 422 /* NANDFC buffer 0 is used for page read/write */
1bc99180 423 writew(i, NFC_V1_V2_BUF_ADDR);
34f6e157 424
1bc99180 425 writew(ops, NFC_V1_V2_CONFIG2);
34f6e157 426
c5d23f1b 427 /* Wait for operation to complete */
c110eaf4 428 wait_op_done(host, true);
34f6e157 429 }
34f6e157
SH		 430}
431
71ec5155
SH		 432static void send_read_id_v3(struct mxc_nand_host *host)
433{
434 /* Read ID into main buffer */
435 writel(NFC_ID, NFC_V3_LAUNCH);
436
437 wait_op_done(host, true);
438
439 memcpy(host->data_buf, host->main_area0, 16);
440}
441
34f6e157 442/* Request the NANDFC to perform a read of the NAND device ID. */
5f97304e 443static void send_read_id_v1_v2(struct mxc_nand_host *host)
34f6e157
SH		 444{
445 struct nand_chip *this = &host->nand;
34f6e157
SH		 446
447 /* NANDFC buffer 0 is used for device ID output */
1bc99180 448 writew(0x0, NFC_V1_V2_BUF_ADDR);
34f6e157 449
1bc99180 450 writew(NFC_ID, NFC_V1_V2_CONFIG2);
34f6e157
SH		 451
452 /* Wait for operation to complete */
c110eaf4 453 wait_op_done(host, true);
34f6e157 454
f7b66e5e
JO		 455 memcpy(host->data_buf, host->main_area0, 16);
456
34f6e157 457 if (this->options & NAND_BUSWIDTH_16) {
34f6e157 458 /* compress the ID info */
f7b66e5e
JO		 459 host->data_buf[1] = host->data_buf[2];
460 host->data_buf[2] = host->data_buf[4];
461 host->data_buf[3] = host->data_buf[6];
462 host->data_buf[4] = host->data_buf[8];
463 host->data_buf[5] = host->data_buf[10];
34f6e157
SH		 464 }
465}
466
71ec5155
SH		 467static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
468{
469 writew(NFC_STATUS, NFC_V3_LAUNCH);
470 wait_op_done(host, true);
471
472 return readl(NFC_V3_CONFIG1) >> 16;
473}
474
34f6e157
SH		 475/* This function requests the NANDFC to perform a read of the
476 * NAND device status and returns the current status. */
5f97304e 477static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
34f6e157 478{
c29c607a 479 void __iomem *main_buf = host->main_area0;
34f6e157 480 uint32_t store;
f06368f7 481 uint16_t ret;
34f6e157 482
c29c607a 483 writew(0x0, NFC_V1_V2_BUF_ADDR);
34f6e157 484
c29c607a
SH		 485 /*
486 * The device status is stored in main_area0. To
487 * prevent corruption of the buffer save the value
488 * and restore it afterwards.
489 */
34f6e157 490 store = readl(main_buf);
34f6e157 491
1bc99180 492 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
c110eaf4 493 wait_op_done(host, true);
34f6e157 494
34f6e157 495 ret = readw(main_buf);
c29c607a 496
34f6e157
SH		 497 writel(store, main_buf);
498
499 return ret;
500}
501
502/* This functions is used by upper layer to checks if device is ready */
503static int mxc_nand_dev_ready(struct mtd_info *mtd)
504{
505 /*
506 * NFC handles R/B internally. Therefore, this function
507 * always returns status as ready.
508 */
509 return 1;
510}
511
512static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
513{
514 /*
515 * If HW ECC is enabled, we turn it on during init. There is
516 * no need to enable again here.
517 */
518}
519
94f77e50 520static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
34f6e157
SH		 521 u_char *read_ecc, u_char *calc_ecc)
522{
523 struct nand_chip *nand_chip = mtd->priv;
524 struct mxc_nand_host *host = nand_chip->priv;
525
526 /*
527 * 1-Bit errors are automatically corrected in HW. No need for
528 * additional correction. 2-Bit errors cannot be corrected by
529 * HW ECC, so we need to return failure
530 */
1bc99180 531 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
34f6e157
SH		 532
533 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
534 DEBUG(MTD_DEBUG_LEVEL0,
535 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
536 return -1;
537 }
538
539 return 0;
540}
541
94f77e50
SH		 542static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
543 u_char *read_ecc, u_char *calc_ecc)
544{
545 struct nand_chip *nand_chip = mtd->priv;
546 struct mxc_nand_host *host = nand_chip->priv;
547 u32 ecc_stat, err;
548 int no_subpages = 1;
549 int ret = 0;
550 u8 ecc_bit_mask, err_limit;
551
552 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
553 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
554
555 no_subpages = mtd->writesize >> 9;
556
71ec5155
SH		 557 if (nfc_is_v21())
558 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
559 else
560 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
94f77e50
SH		 561
562 do {
563 err = ecc_stat & ecc_bit_mask;
564 if (err > err_limit) {
565 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
566 return -1;
567 } else {
568 ret += err;
569 }
570 ecc_stat >>= 4;
571 } while (--no_subpages);
572
573 mtd->ecc_stats.corrected += ret;
574 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
575
576 return ret;
577}
578
34f6e157
SH		 579static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
580 u_char *ecc_code)
581{
582 return 0;
583}
584
585static u_char mxc_nand_read_byte(struct mtd_info *mtd)
586{
587 struct nand_chip *nand_chip = mtd->priv;
588 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 589 uint8_t ret;
34f6e157
SH		 590
591 /* Check for status request */
592 if (host->status_request)
5f97304e 593 return host->get_dev_status(host) & 0xFF;
34f6e157 594
f8f9608d
SH		 595 ret = *(uint8_t *)(host->data_buf + host->buf_start);
596 host->buf_start++;
34f6e157
SH		 597
598 return ret;
599}
600
601static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
602{
603 struct nand_chip *nand_chip = mtd->priv;
604 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d 605 uint16_t ret;
34f6e157 606
f8f9608d
SH		 607 ret = *(uint16_t *)(host->data_buf + host->buf_start);
608 host->buf_start += 2;
34f6e157
SH		 609
610 return ret;
611}
612
613/* Write data of length len to buffer buf. The data to be
614 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
615 * Operation by the NFC, the data is written to NAND Flash */
616static void mxc_nand_write_buf(struct mtd_info *mtd,
617 const u_char *buf, int len)
618{
619 struct nand_chip *nand_chip = mtd->priv;
620 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 621 u16 col = host->buf_start;
622 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 623
f8f9608d 624 n = min(n, len);
34f6e157 625
f8f9608d 626 memcpy(host->data_buf + col, buf, n);
34f6e157 627
f8f9608d 628 host->buf_start += n;
34f6e157
SH		 629}
630
631/* Read the data buffer from the NAND Flash. To read the data from NAND
632 * Flash first the data output cycle is initiated by the NFC, which copies
633 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
634 */
635static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
636{
637 struct nand_chip *nand_chip = mtd->priv;
638 struct mxc_nand_host *host = nand_chip->priv;
f8f9608d
SH		 639 u16 col = host->buf_start;
640 int n = mtd->oobsize + mtd->writesize - col;
34f6e157 641
f8f9608d 642 n = min(n, len);
34f6e157 643
f8f9608d 644 memcpy(buf, host->data_buf + col, len);
34f6e157 645
f8f9608d 646 host->buf_start += len;
34f6e157
SH		 647}
648
649/* Used by the upper layer to verify the data in NAND Flash
650 * with the data in the buf. */
651static int mxc_nand_verify_buf(struct mtd_info *mtd,
652 const u_char *buf, int len)
653{
654 return -EFAULT;
655}
656
657/* This function is used by upper layer for select and
658 * deselect of the NAND chip */
659static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
660{
661 struct nand_chip *nand_chip = mtd->priv;
662 struct mxc_nand_host *host = nand_chip->priv;
663
34f6e157
SH		 664 switch (chip) {
665 case -1:
666 /* Disable the NFC clock */
667 if (host->clk_act) {
668 clk_disable(host->clk);
669 host->clk_act = 0;
670 }
671 break;
672 case 0:
673 /* Enable the NFC clock */
674 if (!host->clk_act) {
675 clk_enable(host->clk);
676 host->clk_act = 1;
677 }
678 break;
679
680 default:
681 break;
682 }
683}
684
f8f9608d
SH		 685/*
686 * Function to transfer data to/from spare area.
687 */
688static void copy_spare(struct mtd_info *mtd, bool bfrom)
34f6e157 689{
f8f9608d
SH		 690 struct nand_chip *this = mtd->priv;
691 struct mxc_nand_host *host = this->priv;
692 u16 i, j;
693 u16 n = mtd->writesize >> 9;
694 u8 *d = host->data_buf + mtd->writesize;
c6de7e1b 695 u8 *s = host->spare0;
f8f9608d
SH		 696 u16 t = host->spare_len;
697
698 j = (mtd->oobsize / n >> 1) << 1;
699
700 if (bfrom) {
701 for (i = 0; i < n - 1; i++)
702 memcpy(d + i * j, s + i * t, j);
703
704 /* the last section */
705 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
706 } else {
707 for (i = 0; i < n - 1; i++)
708 memcpy(&s[i * t], &d[i * j], j);
34f6e157 709
f8f9608d
SH		 710 /* the last section */
711 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
34f6e157 712 }
f8f9608d 713}
34f6e157 714
a3e65b64
SH		 715static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
716{
717 struct nand_chip *nand_chip = mtd->priv;
718 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 719
720 /* Write out column address, if necessary */
721 if (column != -1) {
722 /*
723 * MXC NANDFC can only perform full page+spare or
724 * spare-only read/write. When the upper layers
177b241d
GE		 725 * perform a read/write buf operation, the saved column
726 * address is used to index into the full page.
34f6e157 727 */
5f97304e 728 host->send_addr(host, 0, page_addr == -1);
2d69c7fa 729 if (mtd->writesize > 512)
34f6e157 730 /* another col addr cycle for 2k page */
5f97304e 731 host->send_addr(host, 0, false);
34f6e157
SH		 732 }
733
734 /* Write out page address, if necessary */
735 if (page_addr != -1) {
736 /* paddr_0 - p_addr_7 */
5f97304e 737 host->send_addr(host, (page_addr & 0xff), false);
34f6e157 738
2d69c7fa 739 if (mtd->writesize > 512) {
bd3fd62e
VB		 740 if (mtd->size >= 0x10000000) {
741 /* paddr_8 - paddr_15 */
5f97304e
SH		 742 host->send_addr(host, (page_addr >> 8) & 0xff, false);
743 host->send_addr(host, (page_addr >> 16) & 0xff, true);
bd3fd62e
VB		 744 } else
745 /* paddr_8 - paddr_15 */
5f97304e 746 host->send_addr(host, (page_addr >> 8) & 0xff, true);
34f6e157
SH		 747 } else {
748 /* One more address cycle for higher density devices */
749 if (mtd->size >= 0x4000000) {
750 /* paddr_8 - paddr_15 */
5f97304e
SH		 751 host->send_addr(host, (page_addr >> 8) & 0xff, false);
752 host->send_addr(host, (page_addr >> 16) & 0xff, true);
34f6e157
SH		 753 } else
754 /* paddr_8 - paddr_15 */
5f97304e 755 host->send_addr(host, (page_addr >> 8) & 0xff, true);
34f6e157
SH		 756 }
757 }
a3e65b64
SH		 758}
759
6e85dfdc
SH		 760/*
761 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
762 * on how much oob the nand chip has. For 8bit ecc we need at least
763 * 26 bytes of oob data per 512 byte block.
764 */
765static int get_eccsize(struct mtd_info *mtd)
766{
767 int oobbytes_per_512 = 0;
768
769 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
770
771 if (oobbytes_per_512 < 26)
772 return 4;
773 else
774 return 8;
775}
776
5f97304e 777static void preset_v1_v2(struct mtd_info *mtd)
d4840180
IC		 778{
779 struct nand_chip *nand_chip = mtd->priv;
780 struct mxc_nand_host *host = nand_chip->priv;
b8db2f51
SH		 781 uint16_t config1 = 0;
782
783 if (nand_chip->ecc.mode == NAND_ECC_HW)
784 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
785
786 if (nfc_is_v21())
787 config1 |= NFC_V2_CONFIG1_FP_INT;
788
789 if (!cpu_is_mx21())
790 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
6e85dfdc
SH		 791
792 if (nfc_is_v21() && mtd->writesize) {
b8db2f51
SH		 793 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
794
6e85dfdc
SH		 795 host->eccsize = get_eccsize(mtd);
796 if (host->eccsize == 4)
b8db2f51
SH		 797 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
798
799 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
d4840180 800 } else {
6e85dfdc 801 host->eccsize = 1;
d4840180 802 }
6e85dfdc 803
b8db2f51 804 writew(config1, NFC_V1_V2_CONFIG1);
d4840180
IC		 805 /* preset operation */
806
807 /* Unlock the internal RAM Buffer */
1bc99180 808 writew(0x2, NFC_V1_V2_CONFIG);
d4840180
IC		 809
810 /* Blocks to be unlocked */
811 if (nfc_is_v21()) {
1bc99180
SH		 812 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR);
813 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR);
d4840180 814 } else if (nfc_is_v1()) {
1bc99180
SH		 815 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
816 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
d4840180
IC		 817 } else
818 BUG();
819
820 /* Unlock Block Command for given address range */
1bc99180 821 writew(0x4, NFC_V1_V2_WRPROT);
d4840180
IC		 822}
823
71ec5155
SH		 824static void preset_v3(struct mtd_info *mtd)
825{
826 struct nand_chip *chip = mtd->priv;
827 struct mxc_nand_host *host = chip->priv;
828 uint32_t config2, config3;
829 int i, addr_phases;
830
831 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
832 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
833
834 /* Unlock the internal RAM Buffer */
835 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
836 NFC_V3_WRPROT);
837
838 /* Blocks to be unlocked */
839 for (i = 0; i < NAND_MAX_CHIPS; i++)
840 writel(0x0 | (0xffff << 16),
841 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
842
843 writel(0, NFC_V3_IPC);
844
845 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
846 NFC_V3_CONFIG2_2CMD_PHASES |
847 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
848 NFC_V3_CONFIG2_ST_CMD(0x70) |
63f1474c 849 NFC_V3_CONFIG2_INT_MSK |
71ec5155
SH		 850 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
851
852 if (chip->ecc.mode == NAND_ECC_HW)
853 config2 |= NFC_V3_CONFIG2_ECC_EN;
854
855 addr_phases = fls(chip->pagemask) >> 3;
856
857 if (mtd->writesize == 2048) {
858 config2 |= NFC_V3_CONFIG2_PS_2048;
859 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
860 } else if (mtd->writesize == 4096) {
861 config2 |= NFC_V3_CONFIG2_PS_4096;
862 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
863 } else {
864 config2 |= NFC_V3_CONFIG2_PS_512;
865 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
866 }
867
868 if (mtd->writesize) {
869 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
870 host->eccsize = get_eccsize(mtd);
871 if (host->eccsize == 8)
872 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
873 }
874
875 writel(config2, NFC_V3_CONFIG2);
876
877 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
878 NFC_V3_CONFIG3_NO_SDMA |
879 NFC_V3_CONFIG3_RBB_MODE |
880 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
881 NFC_V3_CONFIG3_ADD_OP(0);
882
883 if (!(chip->options & NAND_BUSWIDTH_16))
884 config3 |= NFC_V3_CONFIG3_FW8;
885
886 writel(config3, NFC_V3_CONFIG3);
887
888 writel(0, NFC_V3_DELAY_LINE);
d4840180
IC		 889}
890
34f6e157
SH		 891/* Used by the upper layer to write command to NAND Flash for
892 * different operations to be carried out on NAND Flash */
893static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
894 int column, int page_addr)
895{
896 struct nand_chip *nand_chip = mtd->priv;
897 struct mxc_nand_host *host = nand_chip->priv;
34f6e157
SH		 898
899 DEBUG(MTD_DEBUG_LEVEL3,
900 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
901 command, column, page_addr);
902
903 /* Reset command state information */
904 host->status_request = false;
34f6e157 905
34f6e157 906 /* Command pre-processing step */
34f6e157 907 switch (command) {
d4840180 908 case NAND_CMD_RESET:
5f97304e
SH		 909 host->preset(mtd);
910 host->send_cmd(host, command, false);
d4840180 911 break;
34f6e157 912
34f6e157 913 case NAND_CMD_STATUS:
f8f9608d 914 host->buf_start = 0;
34f6e157 915 host->status_request = true;
34f6e157 916
5f97304e 917 host->send_cmd(host, command, true);
89121a6b 918 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 919 break;
920
34f6e157 921 case NAND_CMD_READ0:
34f6e157 922 case NAND_CMD_READOOB:
89121a6b
SH		 923 if (command == NAND_CMD_READ0)
924 host->buf_start = column;
925 else
926 host->buf_start = column + mtd->writesize;
f8f9608d 927
5ea32021 928 command = NAND_CMD_READ0; /* only READ0 is valid */
89121a6b 929
5f97304e 930 host->send_cmd(host, command, false);
89121a6b
SH		 931 mxc_do_addr_cycle(mtd, column, page_addr);
932
2d69c7fa 933 if (mtd->writesize > 512)
5f97304e 934 host->send_cmd(host, NAND_CMD_READSTART, true);
c5d23f1b 935
5f97304e 936 host->send_page(mtd, NFC_OUTPUT);
89121a6b 937
c6de7e1b 938 memcpy(host->data_buf, host->main_area0, mtd->writesize);
89121a6b 939 copy_spare(mtd, true);
34f6e157
SH		 940 break;
941
34f6e157 942 case NAND_CMD_SEQIN:
5ea32021
SH		 943 if (column >= mtd->writesize)
944 /* call ourself to read a page */
945 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
34f6e157 946
5ea32021 947 host->buf_start = column;
89121a6b 948
5f97304e 949 host->send_cmd(host, command, false);
89121a6b 950 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 951 break;
952
953 case NAND_CMD_PAGEPROG:
c6de7e1b 954 memcpy(host->main_area0, host->data_buf, mtd->writesize);
f8f9608d 955 copy_spare(mtd, false);
5f97304e
SH		 956 host->send_page(mtd, NFC_INPUT);
957 host->send_cmd(host, command, true);
89121a6b 958 mxc_do_addr_cycle(mtd, column, page_addr);
34f6e157
SH		 959 break;
960
34f6e157 961 case NAND_CMD_READID:
5f97304e 962 host->send_cmd(host, command, true);
89121a6b 963 mxc_do_addr_cycle(mtd, column, page_addr);
5f97304e 964 host->send_read_id(host);
9467114e 965 host->buf_start = column;
34f6e157
SH		 966 break;
967
89121a6b 968 case NAND_CMD_ERASE1:
34f6e157 969 case NAND_CMD_ERASE2:
5f97304e 970 host->send_cmd(host, command, false);
89121a6b
SH		 971 mxc_do_addr_cycle(mtd, column, page_addr);
972
34f6e157
SH		 973 break;
974 }
975}
976
f1372055
SH		 977/*
978 * The generic flash bbt decriptors overlap with our ecc
979 * hardware, so define some i.MX specific ones.
980 */
981static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
982static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
983
984static struct nand_bbt_descr bbt_main_descr = {
985 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
986 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
987 .offs = 0,
988 .len = 4,
989 .veroffs = 4,
990 .maxblocks = 4,
991 .pattern = bbt_pattern,
992};
993
994static struct nand_bbt_descr bbt_mirror_descr = {
995 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
996 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
997 .offs = 0,
998 .len = 4,
999 .veroffs = 4,
1000 .maxblocks = 4,
1001 .pattern = mirror_pattern,
1002};
1003
34f6e157
SH		 1004static int __init mxcnd_probe(struct platform_device *pdev)
1005{
1006 struct nand_chip *this;
1007 struct mtd_info *mtd;
1008 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1009 struct mxc_nand_host *host;
1010 struct resource *res;
2ebf0622 1011 int err = 0, __maybe_unused nr_parts = 0;
9467114e 1012 struct nand_ecclayout *oob_smallpage, *oob_largepage;
34f6e157
SH		 1013
1014 /* Allocate memory for MTD device structure and private data */
f8f9608d
SH		 1015 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1016 NAND_MAX_OOBSIZE, GFP_KERNEL);
34f6e157
SH		 1017 if (!host)
1018 return -ENOMEM;
1019
f8f9608d 1020 host->data_buf = (uint8_t *)(host + 1);
f8f9608d 1021
34f6e157
SH		 1022 host->dev = &pdev->dev;
1023 /* structures must be linked */
1024 this = &host->nand;
1025 mtd = &host->mtd;
1026 mtd->priv = this;
1027 mtd->owner = THIS_MODULE;
87f39f04 1028 mtd->dev.parent = &pdev->dev;
1fbff0a6 1029 mtd->name = DRIVER_NAME;
34f6e157
SH		 1030
1031 /* 50 us command delay time */
1032 this->chip_delay = 5;
1033
1034 this->priv = host;
1035 this->dev_ready = mxc_nand_dev_ready;
1036 this->cmdfunc = mxc_nand_command;
1037 this->select_chip = mxc_nand_select_chip;
1038 this->read_byte = mxc_nand_read_byte;
1039 this->read_word = mxc_nand_read_word;
1040 this->write_buf = mxc_nand_write_buf;
1041 this->read_buf = mxc_nand_read_buf;
1042 this->verify_buf = mxc_nand_verify_buf;
1043
e65fb009 1044 host->clk = clk_get(&pdev->dev, "nfc");
8541c118
VB		 1045 if (IS_ERR(host->clk)) {
1046 err = PTR_ERR(host->clk);
34f6e157 1047 goto eclk;
8541c118 1048 }
34f6e157
SH		 1049
1050 clk_enable(host->clk);
1051 host->clk_act = 1;
1052
1053 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1054 if (!res) {
1055 err = -ENODEV;
1056 goto eres;
1057 }
1058
c6de7e1b
SH		 1059 host->base = ioremap(res->start, resource_size(res));
1060 if (!host->base) {
8541c118 1061 err = -ENOMEM;
34f6e157
SH		 1062 goto eres;
1063 }
1064
c6de7e1b 1065 host->main_area0 = host->base;
9467114e 1066
5f97304e
SH		 1067 if (nfc_is_v1() || nfc_is_v21()) {
1068 host->preset = preset_v1_v2;
1069 host->send_cmd = send_cmd_v1_v2;
1070 host->send_addr = send_addr_v1_v2;
1071 host->send_page = send_page_v1_v2;
1072 host->send_read_id = send_read_id_v1_v2;
1073 host->get_dev_status = get_dev_status_v1_v2;
7aaf28ac 1074 host->check_int = check_int_v1_v2;
63f1474c
SH		 1075 if (cpu_is_mx21())
1076 host->irq_control = irq_control_mx21;
1077 else
1078 host->irq_control = irq_control_v1_v2;
5f97304e 1079 }
9467114e
SH		 1080
1081 if (nfc_is_v21()) {
938cf997 1082 host->regs = host->base + 0x1e00;
9467114e
SH		 1083 host->spare0 = host->base + 0x1000;
1084 host->spare_len = 64;
1085 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1086 oob_largepage = &nandv2_hw_eccoob_largepage;
d4840180 1087 this->ecc.bytes = 9;
9467114e 1088 } else if (nfc_is_v1()) {
938cf997 1089 host->regs = host->base + 0xe00;
9467114e
SH		 1090 host->spare0 = host->base + 0x800;
1091 host->spare_len = 16;
1092 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1093 oob_largepage = &nandv1_hw_eccoob_largepage;
9467114e 1094 this->ecc.bytes = 3;
71ec5155
SH		 1095 host->eccsize = 1;
1096 } else if (nfc_is_v3_2()) {
1097 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1098 if (!res) {
1099 err = -ENODEV;
1100 goto eirq;
1101 }
1102 host->regs_ip = ioremap(res->start, resource_size(res));
1103 if (!host->regs_ip) {
1104 err = -ENOMEM;
1105 goto eirq;
1106 }
1107 host->regs_axi = host->base + 0x1e00;
1108 host->spare0 = host->base + 0x1000;
1109 host->spare_len = 64;
1110 host->preset = preset_v3;
1111 host->send_cmd = send_cmd_v3;
1112 host->send_addr = send_addr_v3;
1113 host->send_page = send_page_v3;
1114 host->send_read_id = send_read_id_v3;
1115 host->check_int = check_int_v3;
1116 host->get_dev_status = get_dev_status_v3;
63f1474c 1117 host->irq_control = irq_control_v3;
71ec5155
SH		 1118 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1119 oob_largepage = &nandv2_hw_eccoob_largepage;
9467114e
SH		 1120 } else
1121 BUG();
13e1add1 1122
13e1add1 1123 this->ecc.size = 512;
9467114e 1124 this->ecc.layout = oob_smallpage;
13e1add1 1125
34f6e157
SH		 1126 if (pdata->hw_ecc) {
1127 this->ecc.calculate = mxc_nand_calculate_ecc;
1128 this->ecc.hwctl = mxc_nand_enable_hwecc;
94f77e50
SH		 1129 if (nfc_is_v1())
1130 this->ecc.correct = mxc_nand_correct_data_v1;
1131 else
1132 this->ecc.correct = mxc_nand_correct_data_v2_v3;
34f6e157 1133 this->ecc.mode = NAND_ECC_HW;
34f6e157 1134 } else {
34f6e157 1135 this->ecc.mode = NAND_ECC_SOFT;
34f6e157
SH		 1136 }
1137
34f6e157 1138 /* NAND bus width determines access funtions used by upper layer */
13e1add1 1139 if (pdata->width == 2)
34f6e157 1140 this->options |= NAND_BUSWIDTH_16;
34f6e157 1141
f1372055
SH		 1142 if (pdata->flash_bbt) {
1143 this->bbt_td = &bbt_main_descr;
1144 this->bbt_md = &bbt_mirror_descr;
1145 /* update flash based bbt */
1146 this->options |= NAND_USE_FLASH_BBT;
34f6e157
SH		 1147 }
1148
63f1474c 1149 init_completion(&host->op_completion);
d4840180
IC		 1150
1151 host->irq = platform_get_irq(pdev, 0);
1152
63f1474c
SH		 1153 /*
1154 * mask the interrupt. For i.MX21 explicitely call
1155 * irq_control_v1_v2 to use the mask bit. We can't call
1156 * disable_irq_nosync() for an interrupt we do not own yet.
1157 */
1158 if (cpu_is_mx21())
1159 irq_control_v1_v2(host, 0);
1160 else
1161 host->irq_control(host, 0);
1162
a47bfd2e 1163 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
d4840180
IC		 1164 if (err)
1165 goto eirq;
1166
63f1474c
SH		 1167 host->irq_control(host, 0);
1168
1169 /*
1170 * Now that the interrupt is disabled make sure the interrupt
1171 * mask bit is cleared on i.MX21. Otherwise we can't read
1172 * the interrupt status bit on this machine.
1173 */
1174 if (cpu_is_mx21())
1175 irq_control_v1_v2(host, 1);
1176
bd3fd62e 1177 /* first scan to find the device and get the page size */
5e81e88a 1178 if (nand_scan_ident(mtd, 1, NULL)) {
bd3fd62e
VB		 1179 err = -ENXIO;
1180 goto escan;
1181 }
34f6e157 1182
6e85dfdc
SH		 1183 /* Call preset again, with correct writesize this time */
1184 host->preset(mtd);
1185
2d69c7fa 1186 if (mtd->writesize == 2048)
9467114e 1187 this->ecc.layout = oob_largepage;
bd3fd62e
VB		 1188
1189 /* second phase scan */
1190 if (nand_scan_tail(mtd)) {
34f6e157
SH		 1191 err = -ENXIO;
1192 goto escan;
1193 }
1194
1195 /* Register the partitions */
1196#ifdef CONFIG_MTD_PARTITIONS
1197 nr_parts =
1198 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1199 if (nr_parts > 0)
1200 add_mtd_partitions(mtd, host->parts, nr_parts);
cce02464
BS		 1201 else if (pdata->parts)
1202 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
34f6e157
SH		 1203 else
1204#endif
1205 {
1206 pr_info("Registering %s as whole device\n", mtd->name);
1207 add_mtd_device(mtd);
1208 }
1209
1210 platform_set_drvdata(pdev, host);
1211
1212 return 0;
1213
1214escan:
b258fd8d 1215 free_irq(host->irq, host);
34f6e157 1216eirq:
71ec5155
SH		 1217 if (host->regs_ip)
1218 iounmap(host->regs_ip);
c6de7e1b 1219 iounmap(host->base);
34f6e157
SH		 1220eres:
1221 clk_put(host->clk);
1222eclk:
1223 kfree(host);
1224
1225 return err;
1226}
1227
51eeb878 1228static int __devexit mxcnd_remove(struct platform_device *pdev)
34f6e157
SH		 1229{
1230 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1231
1232 clk_put(host->clk);
1233
1234 platform_set_drvdata(pdev, NULL);
1235
1236 nand_release(&host->mtd);
b258fd8d 1237 free_irq(host->irq, host);
71ec5155
SH		 1238 if (host->regs_ip)
1239 iounmap(host->regs_ip);
c6de7e1b 1240 iounmap(host->base);
34f6e157
SH		 1241 kfree(host);
1242
1243 return 0;
1244}
1245
34f6e157
SH		 1246static struct platform_driver mxcnd_driver = {
1247 .driver = {
1248 .name = DRIVER_NAME,
04dd0d3a 1249 },
daa0f15a 1250 .remove = __devexit_p(mxcnd_remove),
34f6e157
SH		 1251};
1252
1253static int __init mxc_nd_init(void)
1254{
8541c118 1255 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
34f6e157
SH		 1256}
1257
1258static void __exit mxc_nd_cleanup(void)
1259{
1260 /* Unregister the device structure */
1261 platform_driver_unregister(&mxcnd_driver);
1262}
1263
1264module_init(mxc_nd_init);
1265module_exit(mxc_nd_cleanup);
1266
1267MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1268MODULE_DESCRIPTION("MXC NAND MTD driver");
1269MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)