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2944a44d RS |
1 | /* |
2 | * NXP LPC32XX NAND SLC driver | |
3 | * | |
4 | * Authors: | |
5 | * Kevin Wells <kevin.wells@nxp.com> | |
6 | * Roland Stigge <stigge@antcom.de> | |
7 | * | |
8 | * Copyright © 2011 NXP Semiconductors | |
9 | * Copyright © 2012 Roland Stigge | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
21 | ||
22 | #include <linux/slab.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/mtd/mtd.h> | |
26 | #include <linux/mtd/nand.h> | |
27 | #include <linux/mtd/partitions.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/dmaengine.h> | |
35 | #include <linux/mtd/nand_ecc.h> | |
36 | #include <linux/gpio.h> | |
37 | #include <linux/of.h> | |
38 | #include <linux/of_mtd.h> | |
39 | #include <linux/of_gpio.h> | |
de20c22d | 40 | #include <linux/mtd/lpc32xx_slc.h> |
2944a44d RS |
41 | |
42 | #define LPC32XX_MODNAME "lpc32xx-nand" | |
43 | ||
44 | /********************************************************************** | |
45 | * SLC NAND controller register offsets | |
46 | **********************************************************************/ | |
47 | ||
48 | #define SLC_DATA(x) (x + 0x000) | |
49 | #define SLC_ADDR(x) (x + 0x004) | |
50 | #define SLC_CMD(x) (x + 0x008) | |
51 | #define SLC_STOP(x) (x + 0x00C) | |
52 | #define SLC_CTRL(x) (x + 0x010) | |
53 | #define SLC_CFG(x) (x + 0x014) | |
54 | #define SLC_STAT(x) (x + 0x018) | |
55 | #define SLC_INT_STAT(x) (x + 0x01C) | |
56 | #define SLC_IEN(x) (x + 0x020) | |
57 | #define SLC_ISR(x) (x + 0x024) | |
58 | #define SLC_ICR(x) (x + 0x028) | |
59 | #define SLC_TAC(x) (x + 0x02C) | |
60 | #define SLC_TC(x) (x + 0x030) | |
61 | #define SLC_ECC(x) (x + 0x034) | |
62 | #define SLC_DMA_DATA(x) (x + 0x038) | |
63 | ||
64 | /********************************************************************** | |
65 | * slc_ctrl register definitions | |
66 | **********************************************************************/ | |
67 | #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */ | |
68 | #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ | |
69 | #define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */ | |
70 | ||
71 | /********************************************************************** | |
72 | * slc_cfg register definitions | |
73 | **********************************************************************/ | |
74 | #define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */ | |
75 | #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ | |
76 | #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */ | |
77 | #define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */ | |
78 | #define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ | |
79 | #define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */ | |
80 | ||
81 | /********************************************************************** | |
82 | * slc_stat register definitions | |
83 | **********************************************************************/ | |
84 | #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ | |
85 | #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */ | |
86 | #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */ | |
87 | ||
88 | /********************************************************************** | |
89 | * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions | |
90 | **********************************************************************/ | |
91 | #define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */ | |
92 | #define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */ | |
93 | ||
94 | /********************************************************************** | |
95 | * slc_tac register definitions | |
96 | **********************************************************************/ | |
641f6342 | 97 | /* Computation of clock cycles on basis of controller and device clock rates */ |
d54e8801 | 98 | #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s) |
641f6342 | 99 | |
2944a44d RS |
100 | /* Clock setting for RDY write sample wait time in 2*n clocks */ |
101 | #define SLCTAC_WDR(n) (((n) & 0xF) << 28) | |
102 | /* Write pulse width in clock cycles, 1 to 16 clocks */ | |
641f6342 | 103 | #define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24)) |
2944a44d | 104 | /* Write hold time of control and data signals, 1 to 16 clocks */ |
641f6342 | 105 | #define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20)) |
2944a44d | 106 | /* Write setup time of control and data signals, 1 to 16 clocks */ |
641f6342 | 107 | #define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16)) |
2944a44d RS |
108 | /* Clock setting for RDY read sample wait time in 2*n clocks */ |
109 | #define SLCTAC_RDR(n) (((n) & 0xF) << 12) | |
110 | /* Read pulse width in clock cycles, 1 to 16 clocks */ | |
641f6342 | 111 | #define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8)) |
2944a44d | 112 | /* Read hold time of control and data signals, 1 to 16 clocks */ |
641f6342 | 113 | #define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4)) |
2944a44d | 114 | /* Read setup time of control and data signals, 1 to 16 clocks */ |
641f6342 | 115 | #define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0)) |
2944a44d RS |
116 | |
117 | /********************************************************************** | |
118 | * slc_ecc register definitions | |
119 | **********************************************************************/ | |
120 | /* ECC line party fetch macro */ | |
121 | #define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF) | |
122 | #define SLCECC_TO_COLPAR(n) ((n) & 0x3F) | |
123 | ||
124 | /* | |
125 | * DMA requires storage space for the DMA local buffer and the hardware ECC | |
126 | * storage area. The DMA local buffer is only used if DMA mapping fails | |
127 | * during runtime. | |
128 | */ | |
129 | #define LPC32XX_DMA_DATA_SIZE 4096 | |
130 | #define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4) | |
131 | ||
132 | /* Number of bytes used for ECC stored in NAND per 256 bytes */ | |
133 | #define LPC32XX_SLC_DEV_ECC_BYTES 3 | |
134 | ||
135 | /* | |
136 | * If the NAND base clock frequency can't be fetched, this frequency will be | |
137 | * used instead as the base. This rate is used to setup the timing registers | |
138 | * used for NAND accesses. | |
139 | */ | |
140 | #define LPC32XX_DEF_BUS_RATE 133250000 | |
141 | ||
142 | /* Milliseconds for DMA FIFO timeout (unlikely anyway) */ | |
143 | #define LPC32XX_DMA_TIMEOUT 100 | |
144 | ||
145 | /* | |
146 | * NAND ECC Layout for small page NAND devices | |
147 | * Note: For large and huge page devices, the default layouts are used | |
148 | */ | |
149 | static struct nand_ecclayout lpc32xx_nand_oob_16 = { | |
150 | .eccbytes = 6, | |
151 | .eccpos = {10, 11, 12, 13, 14, 15}, | |
152 | .oobfree = { | |
153 | { .offset = 0, .length = 4 }, | |
154 | { .offset = 6, .length = 4 }, | |
155 | }, | |
156 | }; | |
157 | ||
158 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
159 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
160 | ||
161 | /* | |
162 | * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6 | |
163 | * Note: Large page devices used the default layout | |
164 | */ | |
165 | static struct nand_bbt_descr bbt_smallpage_main_descr = { | |
166 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
167 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
168 | .offs = 0, | |
169 | .len = 4, | |
170 | .veroffs = 6, | |
171 | .maxblocks = 4, | |
172 | .pattern = bbt_pattern | |
173 | }; | |
174 | ||
175 | static struct nand_bbt_descr bbt_smallpage_mirror_descr = { | |
176 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
177 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
178 | .offs = 0, | |
179 | .len = 4, | |
180 | .veroffs = 6, | |
181 | .maxblocks = 4, | |
182 | .pattern = mirror_pattern | |
183 | }; | |
184 | ||
185 | /* | |
186 | * NAND platform configuration structure | |
187 | */ | |
188 | struct lpc32xx_nand_cfg_slc { | |
189 | uint32_t wdr_clks; | |
190 | uint32_t wwidth; | |
191 | uint32_t whold; | |
192 | uint32_t wsetup; | |
193 | uint32_t rdr_clks; | |
194 | uint32_t rwidth; | |
195 | uint32_t rhold; | |
196 | uint32_t rsetup; | |
197 | bool use_bbt; | |
df63fe76 | 198 | int wp_gpio; |
2944a44d RS |
199 | struct mtd_partition *parts; |
200 | unsigned num_parts; | |
201 | }; | |
202 | ||
203 | struct lpc32xx_nand_host { | |
204 | struct nand_chip nand_chip; | |
de20c22d | 205 | struct lpc32xx_slc_platform_data *pdata; |
2944a44d RS |
206 | struct clk *clk; |
207 | struct mtd_info mtd; | |
208 | void __iomem *io_base; | |
209 | struct lpc32xx_nand_cfg_slc *ncfg; | |
210 | ||
211 | struct completion comp; | |
212 | struct dma_chan *dma_chan; | |
213 | uint32_t dma_buf_len; | |
214 | struct dma_slave_config dma_slave_config; | |
215 | struct scatterlist sgl; | |
216 | ||
217 | /* | |
218 | * DMA and CPU addresses of ECC work area and data buffer | |
219 | */ | |
220 | uint32_t *ecc_buf; | |
221 | uint8_t *data_buf; | |
222 | dma_addr_t io_base_dma; | |
223 | }; | |
224 | ||
225 | static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) | |
226 | { | |
227 | uint32_t clkrate, tmp; | |
228 | ||
229 | /* Reset SLC controller */ | |
230 | writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); | |
231 | udelay(1000); | |
232 | ||
233 | /* Basic setup */ | |
234 | writel(0, SLC_CFG(host->io_base)); | |
235 | writel(0, SLC_IEN(host->io_base)); | |
236 | writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN), | |
237 | SLC_ICR(host->io_base)); | |
238 | ||
239 | /* Get base clock for SLC block */ | |
240 | clkrate = clk_get_rate(host->clk); | |
241 | if (clkrate == 0) | |
242 | clkrate = LPC32XX_DEF_BUS_RATE; | |
243 | ||
244 | /* Compute clock setup values */ | |
245 | tmp = SLCTAC_WDR(host->ncfg->wdr_clks) | | |
641f6342 VZ |
246 | SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) | |
247 | SLCTAC_WHOLD(clkrate, host->ncfg->whold) | | |
248 | SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) | | |
2944a44d | 249 | SLCTAC_RDR(host->ncfg->rdr_clks) | |
641f6342 VZ |
250 | SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) | |
251 | SLCTAC_RHOLD(clkrate, host->ncfg->rhold) | | |
252 | SLCTAC_RSETUP(clkrate, host->ncfg->rsetup); | |
2944a44d RS |
253 | writel(tmp, SLC_TAC(host->io_base)); |
254 | } | |
255 | ||
256 | /* | |
257 | * Hardware specific access to control lines | |
258 | */ | |
259 | static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | |
260 | unsigned int ctrl) | |
261 | { | |
262 | uint32_t tmp; | |
263 | struct nand_chip *chip = mtd->priv; | |
264 | struct lpc32xx_nand_host *host = chip->priv; | |
265 | ||
266 | /* Does CE state need to be changed? */ | |
267 | tmp = readl(SLC_CFG(host->io_base)); | |
268 | if (ctrl & NAND_NCE) | |
269 | tmp |= SLCCFG_CE_LOW; | |
270 | else | |
271 | tmp &= ~SLCCFG_CE_LOW; | |
272 | writel(tmp, SLC_CFG(host->io_base)); | |
273 | ||
274 | if (cmd != NAND_CMD_NONE) { | |
275 | if (ctrl & NAND_CLE) | |
276 | writel(cmd, SLC_CMD(host->io_base)); | |
277 | else | |
278 | writel(cmd, SLC_ADDR(host->io_base)); | |
279 | } | |
280 | } | |
281 | ||
282 | /* | |
283 | * Read the Device Ready pin | |
284 | */ | |
285 | static int lpc32xx_nand_device_ready(struct mtd_info *mtd) | |
286 | { | |
287 | struct nand_chip *chip = mtd->priv; | |
288 | struct lpc32xx_nand_host *host = chip->priv; | |
289 | int rdy = 0; | |
290 | ||
291 | if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0) | |
292 | rdy = 1; | |
293 | ||
294 | return rdy; | |
295 | } | |
296 | ||
297 | /* | |
298 | * Enable NAND write protect | |
299 | */ | |
300 | static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) | |
301 | { | |
df63fe76 APS |
302 | if (gpio_is_valid(host->ncfg->wp_gpio)) |
303 | gpio_set_value(host->ncfg->wp_gpio, 0); | |
2944a44d RS |
304 | } |
305 | ||
306 | /* | |
307 | * Disable NAND write protect | |
308 | */ | |
309 | static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) | |
310 | { | |
df63fe76 APS |
311 | if (gpio_is_valid(host->ncfg->wp_gpio)) |
312 | gpio_set_value(host->ncfg->wp_gpio, 1); | |
2944a44d RS |
313 | } |
314 | ||
315 | /* | |
316 | * Prepares SLC for transfers with H/W ECC enabled | |
317 | */ | |
318 | static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode) | |
319 | { | |
320 | /* Hardware ECC is enabled automatically in hardware as needed */ | |
321 | } | |
322 | ||
323 | /* | |
324 | * Calculates the ECC for the data | |
325 | */ | |
326 | static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd, | |
327 | const unsigned char *buf, | |
328 | unsigned char *code) | |
329 | { | |
330 | /* | |
331 | * ECC is calculated automatically in hardware during syndrome read | |
332 | * and write operations, so it doesn't need to be calculated here. | |
333 | */ | |
334 | return 0; | |
335 | } | |
336 | ||
337 | /* | |
338 | * Read a single byte from NAND device | |
339 | */ | |
340 | static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd) | |
341 | { | |
342 | struct nand_chip *chip = mtd->priv; | |
343 | struct lpc32xx_nand_host *host = chip->priv; | |
344 | ||
345 | return (uint8_t)readl(SLC_DATA(host->io_base)); | |
346 | } | |
347 | ||
348 | /* | |
349 | * Simple device read without ECC | |
350 | */ | |
351 | static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
352 | { | |
353 | struct nand_chip *chip = mtd->priv; | |
354 | struct lpc32xx_nand_host *host = chip->priv; | |
355 | ||
356 | /* Direct device read with no ECC */ | |
357 | while (len-- > 0) | |
358 | *buf++ = (uint8_t)readl(SLC_DATA(host->io_base)); | |
359 | } | |
360 | ||
361 | /* | |
362 | * Simple device write without ECC | |
363 | */ | |
364 | static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
365 | { | |
366 | struct nand_chip *chip = mtd->priv; | |
367 | struct lpc32xx_nand_host *host = chip->priv; | |
368 | ||
369 | /* Direct device write with no ECC */ | |
370 | while (len-- > 0) | |
371 | writel((uint32_t)*buf++, SLC_DATA(host->io_base)); | |
372 | } | |
373 | ||
2944a44d RS |
374 | /* |
375 | * Read the OOB data from the device without ECC using FIFO method | |
376 | */ | |
377 | static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd, | |
378 | struct nand_chip *chip, int page) | |
379 | { | |
380 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
381 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | /* | |
387 | * Write the OOB data to the device without ECC using FIFO method | |
388 | */ | |
389 | static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd, | |
390 | struct nand_chip *chip, int page) | |
391 | { | |
392 | int status; | |
393 | ||
394 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
395 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
396 | ||
397 | /* Send command to program the OOB data */ | |
398 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
399 | ||
400 | status = chip->waitfunc(mtd, chip); | |
401 | ||
402 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
403 | } | |
404 | ||
405 | /* | |
406 | * Fills in the ECC fields in the OOB buffer with the hardware generated ECC | |
407 | */ | |
408 | static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count) | |
409 | { | |
410 | int i; | |
411 | ||
412 | for (i = 0; i < (count * 3); i += 3) { | |
413 | uint32_t ce = ecc[i / 3]; | |
414 | ce = ~(ce << 2) & 0xFFFFFF; | |
415 | spare[i + 2] = (uint8_t)(ce & 0xFF); | |
416 | ce >>= 8; | |
417 | spare[i + 1] = (uint8_t)(ce & 0xFF); | |
418 | ce >>= 8; | |
419 | spare[i] = (uint8_t)(ce & 0xFF); | |
420 | } | |
421 | } | |
422 | ||
423 | static void lpc32xx_dma_complete_func(void *completion) | |
424 | { | |
425 | complete(completion); | |
426 | } | |
427 | ||
428 | static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma, | |
429 | void *mem, int len, enum dma_transfer_direction dir) | |
430 | { | |
431 | struct nand_chip *chip = mtd->priv; | |
432 | struct lpc32xx_nand_host *host = chip->priv; | |
433 | struct dma_async_tx_descriptor *desc; | |
434 | int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; | |
435 | int res; | |
436 | ||
437 | host->dma_slave_config.direction = dir; | |
438 | host->dma_slave_config.src_addr = dma; | |
439 | host->dma_slave_config.dst_addr = dma; | |
440 | host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
441 | host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
442 | host->dma_slave_config.src_maxburst = 4; | |
443 | host->dma_slave_config.dst_maxburst = 4; | |
444 | /* DMA controller does flow control: */ | |
445 | host->dma_slave_config.device_fc = false; | |
446 | if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { | |
447 | dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); | |
448 | return -ENXIO; | |
449 | } | |
450 | ||
451 | sg_init_one(&host->sgl, mem, len); | |
452 | ||
453 | res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, | |
454 | DMA_BIDIRECTIONAL); | |
455 | if (res != 1) { | |
456 | dev_err(mtd->dev.parent, "Failed to map sg list\n"); | |
457 | return -ENXIO; | |
458 | } | |
459 | desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, | |
460 | flags); | |
461 | if (!desc) { | |
462 | dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); | |
463 | goto out1; | |
464 | } | |
465 | ||
466 | init_completion(&host->comp); | |
467 | desc->callback = lpc32xx_dma_complete_func; | |
468 | desc->callback_param = &host->comp; | |
469 | ||
470 | dmaengine_submit(desc); | |
471 | dma_async_issue_pending(host->dma_chan); | |
472 | ||
473 | wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000)); | |
474 | ||
475 | dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, | |
476 | DMA_BIDIRECTIONAL); | |
477 | ||
478 | return 0; | |
479 | out1: | |
480 | dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, | |
481 | DMA_BIDIRECTIONAL); | |
482 | return -ENXIO; | |
483 | } | |
484 | ||
485 | /* | |
486 | * DMA read/write transfers with ECC support | |
487 | */ | |
488 | static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages, | |
489 | int read) | |
490 | { | |
491 | struct nand_chip *chip = mtd->priv; | |
492 | struct lpc32xx_nand_host *host = chip->priv; | |
493 | int i, status = 0; | |
494 | unsigned long timeout; | |
495 | int res; | |
496 | enum dma_transfer_direction dir = | |
497 | read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; | |
498 | uint8_t *dma_buf; | |
499 | bool dma_mapped; | |
500 | ||
501 | if ((void *)buf <= high_memory) { | |
502 | dma_buf = buf; | |
503 | dma_mapped = true; | |
504 | } else { | |
505 | dma_buf = host->data_buf; | |
506 | dma_mapped = false; | |
507 | if (!read) | |
508 | memcpy(host->data_buf, buf, mtd->writesize); | |
509 | } | |
510 | ||
511 | if (read) { | |
512 | writel(readl(SLC_CFG(host->io_base)) | | |
513 | SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | | |
514 | SLCCFG_DMA_BURST, SLC_CFG(host->io_base)); | |
515 | } else { | |
516 | writel((readl(SLC_CFG(host->io_base)) | | |
517 | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) & | |
518 | ~SLCCFG_DMA_DIR, | |
519 | SLC_CFG(host->io_base)); | |
520 | } | |
521 | ||
522 | /* Clear initial ECC */ | |
523 | writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base)); | |
524 | ||
525 | /* Transfer size is data area only */ | |
526 | writel(mtd->writesize, SLC_TC(host->io_base)); | |
527 | ||
528 | /* Start transfer in the NAND controller */ | |
529 | writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START, | |
530 | SLC_CTRL(host->io_base)); | |
531 | ||
532 | for (i = 0; i < chip->ecc.steps; i++) { | |
533 | /* Data */ | |
534 | res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma), | |
535 | dma_buf + i * chip->ecc.size, | |
536 | mtd->writesize / chip->ecc.steps, dir); | |
537 | if (res) | |
538 | return res; | |
539 | ||
540 | /* Always _read_ ECC */ | |
541 | if (i == chip->ecc.steps - 1) | |
542 | break; | |
543 | if (!read) /* ECC availability delayed on write */ | |
544 | udelay(10); | |
545 | res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma), | |
546 | &host->ecc_buf[i], 4, DMA_DEV_TO_MEM); | |
547 | if (res) | |
548 | return res; | |
549 | } | |
550 | ||
551 | /* | |
552 | * According to NXP, the DMA can be finished here, but the NAND | |
553 | * controller may still have buffered data. After porting to using the | |
554 | * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty) | |
555 | * appears to be always true, according to tests. Keeping the check for | |
556 | * safety reasons for now. | |
557 | */ | |
558 | if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) { | |
559 | dev_warn(mtd->dev.parent, "FIFO not empty!\n"); | |
560 | timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT); | |
561 | while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) && | |
562 | time_before(jiffies, timeout)) | |
563 | cpu_relax(); | |
564 | if (!time_before(jiffies, timeout)) { | |
565 | dev_err(mtd->dev.parent, "FIFO held data too long\n"); | |
566 | status = -EIO; | |
567 | } | |
568 | } | |
569 | ||
570 | /* Read last calculated ECC value */ | |
571 | if (!read) | |
572 | udelay(10); | |
573 | host->ecc_buf[chip->ecc.steps - 1] = | |
574 | readl(SLC_ECC(host->io_base)); | |
575 | ||
576 | /* Flush DMA */ | |
577 | dmaengine_terminate_all(host->dma_chan); | |
578 | ||
579 | if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO || | |
580 | readl(SLC_TC(host->io_base))) { | |
581 | /* Something is left in the FIFO, something is wrong */ | |
582 | dev_err(mtd->dev.parent, "DMA FIFO failure\n"); | |
583 | status = -EIO; | |
584 | } | |
585 | ||
586 | /* Stop DMA & HW ECC */ | |
587 | writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START, | |
588 | SLC_CTRL(host->io_base)); | |
589 | writel(readl(SLC_CFG(host->io_base)) & | |
590 | ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC | | |
591 | SLCCFG_DMA_BURST), SLC_CFG(host->io_base)); | |
592 | ||
593 | if (!dma_mapped && read) | |
594 | memcpy(buf, host->data_buf, mtd->writesize); | |
595 | ||
596 | return status; | |
597 | } | |
598 | ||
599 | /* | |
600 | * Read the data and OOB data from the device, use ECC correction with the | |
601 | * data, disable ECC for the OOB data | |
602 | */ | |
603 | static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd, | |
604 | struct nand_chip *chip, uint8_t *buf, | |
605 | int oob_required, int page) | |
606 | { | |
607 | struct lpc32xx_nand_host *host = chip->priv; | |
608 | int stat, i, status; | |
609 | uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE]; | |
610 | ||
611 | /* Issue read command */ | |
612 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
613 | ||
614 | /* Read data and oob, calculate ECC */ | |
615 | status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1); | |
616 | ||
617 | /* Get OOB data */ | |
618 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
619 | ||
620 | /* Convert to stored ECC format */ | |
621 | lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps); | |
622 | ||
623 | /* Pointer to ECC data retrieved from NAND spare area */ | |
624 | oobecc = chip->oob_poi + chip->ecc.layout->eccpos[0]; | |
625 | ||
626 | for (i = 0; i < chip->ecc.steps; i++) { | |
627 | stat = chip->ecc.correct(mtd, buf, oobecc, | |
628 | &tmpecc[i * chip->ecc.bytes]); | |
629 | if (stat < 0) | |
630 | mtd->ecc_stats.failed++; | |
631 | else | |
632 | mtd->ecc_stats.corrected += stat; | |
633 | ||
634 | buf += chip->ecc.size; | |
635 | oobecc += chip->ecc.bytes; | |
636 | } | |
637 | ||
638 | return status; | |
639 | } | |
640 | ||
641 | /* | |
642 | * Read the data and OOB data from the device, no ECC correction with the | |
643 | * data or OOB data | |
644 | */ | |
645 | static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd, | |
646 | struct nand_chip *chip, | |
647 | uint8_t *buf, int oob_required, | |
648 | int page) | |
649 | { | |
650 | /* Issue read command */ | |
651 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
652 | ||
653 | /* Raw reads can just use the FIFO interface */ | |
654 | chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps); | |
655 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | /* | |
661 | * Write the data and OOB data to the device, use ECC with the data, | |
662 | * disable ECC for the OOB data | |
663 | */ | |
664 | static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd, | |
665 | struct nand_chip *chip, | |
45aaeff9 BB |
666 | const uint8_t *buf, |
667 | int oob_required, int page) | |
2944a44d RS |
668 | { |
669 | struct lpc32xx_nand_host *host = chip->priv; | |
670 | uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0]; | |
671 | int error; | |
672 | ||
673 | /* Write data, calculate ECC on outbound data */ | |
674 | error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0); | |
675 | if (error) | |
676 | return error; | |
677 | ||
678 | /* | |
679 | * The calculated ECC needs some manual work done to it before | |
680 | * committing it to NAND. Process the calculated ECC and place | |
681 | * the resultant values directly into the OOB buffer. */ | |
682 | lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps); | |
683 | ||
684 | /* Write ECC data to device */ | |
685 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
686 | return 0; | |
687 | } | |
688 | ||
689 | /* | |
690 | * Write the data and OOB data to the device, no ECC correction with the | |
691 | * data or OOB data | |
692 | */ | |
693 | static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd, | |
694 | struct nand_chip *chip, | |
695 | const uint8_t *buf, | |
45aaeff9 | 696 | int oob_required, int page) |
2944a44d RS |
697 | { |
698 | /* Raw writes can just use the FIFO interface */ | |
699 | chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps); | |
700 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
701 | return 0; | |
702 | } | |
703 | ||
2944a44d RS |
704 | static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host) |
705 | { | |
706 | struct mtd_info *mtd = &host->mtd; | |
707 | dma_cap_mask_t mask; | |
708 | ||
de20c22d RS |
709 | if (!host->pdata || !host->pdata->dma_filter) { |
710 | dev_err(mtd->dev.parent, "no DMA platform data\n"); | |
711 | return -ENOENT; | |
712 | } | |
713 | ||
2944a44d RS |
714 | dma_cap_zero(mask); |
715 | dma_cap_set(DMA_SLAVE, mask); | |
de20c22d RS |
716 | host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, |
717 | "nand-slc"); | |
2944a44d RS |
718 | if (!host->dma_chan) { |
719 | dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); | |
720 | return -EBUSY; | |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
2944a44d RS |
726 | static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev) |
727 | { | |
10594f67 | 728 | struct lpc32xx_nand_cfg_slc *ncfg; |
2944a44d RS |
729 | struct device_node *np = dev->of_node; |
730 | ||
10594f67 | 731 | ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); |
8ecb66ba | 732 | if (!ncfg) |
2944a44d | 733 | return NULL; |
2944a44d | 734 | |
10594f67 RS |
735 | of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks); |
736 | of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth); | |
737 | of_property_read_u32(np, "nxp,whold", &ncfg->whold); | |
738 | of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup); | |
739 | of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks); | |
740 | of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth); | |
741 | of_property_read_u32(np, "nxp,rhold", &ncfg->rhold); | |
742 | of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup); | |
743 | ||
744 | if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold || | |
745 | !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth || | |
746 | !ncfg->rhold || !ncfg->rsetup) { | |
2944a44d RS |
747 | dev_err(dev, "chip parameters not specified correctly\n"); |
748 | return NULL; | |
749 | } | |
750 | ||
10594f67 RS |
751 | ncfg->use_bbt = of_get_nand_on_flash_bbt(np); |
752 | ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); | |
2944a44d | 753 | |
10594f67 | 754 | return ncfg; |
2944a44d | 755 | } |
2944a44d RS |
756 | |
757 | /* | |
758 | * Probe for NAND controller | |
759 | */ | |
06f25510 | 760 | static int lpc32xx_nand_probe(struct platform_device *pdev) |
2944a44d RS |
761 | { |
762 | struct lpc32xx_nand_host *host; | |
763 | struct mtd_info *mtd; | |
764 | struct nand_chip *chip; | |
765 | struct resource *rc; | |
766 | struct mtd_part_parser_data ppdata = {}; | |
767 | int res; | |
768 | ||
769 | rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
770 | if (rc == NULL) { | |
771 | dev_err(&pdev->dev, "No memory resource found for device\n"); | |
772 | return -EBUSY; | |
773 | } | |
774 | ||
775 | /* Allocate memory for the device structure (and zero it) */ | |
776 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); | |
8ecb66ba | 777 | if (!host) |
2944a44d | 778 | return -ENOMEM; |
2944a44d RS |
779 | host->io_base_dma = rc->start; |
780 | ||
b0de774c TR |
781 | host->io_base = devm_ioremap_resource(&pdev->dev, rc); |
782 | if (IS_ERR(host->io_base)) | |
783 | return PTR_ERR(host->io_base); | |
2944a44d RS |
784 | |
785 | if (pdev->dev.of_node) | |
786 | host->ncfg = lpc32xx_parse_dt(&pdev->dev); | |
2944a44d | 787 | if (!host->ncfg) { |
10594f67 RS |
788 | dev_err(&pdev->dev, |
789 | "Missing or bad NAND config from device tree\n"); | |
2944a44d RS |
790 | return -ENOENT; |
791 | } | |
d5842ab7 RS |
792 | if (host->ncfg->wp_gpio == -EPROBE_DEFER) |
793 | return -EPROBE_DEFER; | |
133432a7 JH |
794 | if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev, |
795 | host->ncfg->wp_gpio, "NAND WP")) { | |
2944a44d RS |
796 | dev_err(&pdev->dev, "GPIO not available\n"); |
797 | return -EBUSY; | |
798 | } | |
799 | lpc32xx_wp_disable(host); | |
800 | ||
453810b7 | 801 | host->pdata = dev_get_platdata(&pdev->dev); |
de20c22d | 802 | |
2944a44d RS |
803 | mtd = &host->mtd; |
804 | chip = &host->nand_chip; | |
805 | chip->priv = host; | |
806 | mtd->priv = chip; | |
807 | mtd->owner = THIS_MODULE; | |
808 | mtd->dev.parent = &pdev->dev; | |
809 | ||
810 | /* Get NAND clock */ | |
133432a7 | 811 | host->clk = devm_clk_get(&pdev->dev, NULL); |
2944a44d RS |
812 | if (IS_ERR(host->clk)) { |
813 | dev_err(&pdev->dev, "Clock failure\n"); | |
814 | res = -ENOENT; | |
815 | goto err_exit1; | |
816 | } | |
44cab9c9 | 817 | clk_prepare_enable(host->clk); |
2944a44d RS |
818 | |
819 | /* Set NAND IO addresses and command/ready functions */ | |
820 | chip->IO_ADDR_R = SLC_DATA(host->io_base); | |
821 | chip->IO_ADDR_W = SLC_DATA(host->io_base); | |
822 | chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; | |
823 | chip->dev_ready = lpc32xx_nand_device_ready; | |
824 | chip->chip_delay = 20; /* 20us command delay time */ | |
825 | ||
826 | /* Init NAND controller */ | |
827 | lpc32xx_nand_setup(host); | |
828 | ||
829 | platform_set_drvdata(pdev, host); | |
830 | ||
831 | /* NAND callbacks for LPC32xx SLC hardware */ | |
832 | chip->ecc.mode = NAND_ECC_HW_SYNDROME; | |
833 | chip->read_byte = lpc32xx_nand_read_byte; | |
834 | chip->read_buf = lpc32xx_nand_read_buf; | |
835 | chip->write_buf = lpc32xx_nand_write_buf; | |
836 | chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome; | |
837 | chip->ecc.read_page = lpc32xx_nand_read_page_syndrome; | |
838 | chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome; | |
839 | chip->ecc.write_page = lpc32xx_nand_write_page_syndrome; | |
840 | chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome; | |
841 | chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome; | |
842 | chip->ecc.calculate = lpc32xx_nand_ecc_calculate; | |
843 | chip->ecc.correct = nand_correct_data; | |
844 | chip->ecc.strength = 1; | |
845 | chip->ecc.hwctl = lpc32xx_nand_ecc_enable; | |
2944a44d | 846 | |
2944a44d RS |
847 | /* |
848 | * Allocate a large enough buffer for a single huge page plus | |
849 | * extra space for the spare area and ECC storage area | |
850 | */ | |
851 | host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE; | |
852 | host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, | |
853 | GFP_KERNEL); | |
854 | if (host->data_buf == NULL) { | |
2944a44d RS |
855 | res = -ENOMEM; |
856 | goto err_exit2; | |
857 | } | |
858 | ||
859 | res = lpc32xx_nand_dma_setup(host); | |
860 | if (res) { | |
861 | res = -EIO; | |
862 | goto err_exit2; | |
863 | } | |
864 | ||
865 | /* Find NAND device */ | |
866 | if (nand_scan_ident(mtd, 1, NULL)) { | |
867 | res = -ENXIO; | |
868 | goto err_exit3; | |
869 | } | |
870 | ||
871 | /* OOB and ECC CPU and DMA work areas */ | |
872 | host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE); | |
873 | ||
874 | /* | |
875 | * Small page FLASH has a unique OOB layout, but large and huge | |
876 | * page FLASH use the standard layout. Small page FLASH uses a | |
877 | * custom BBT marker layout. | |
878 | */ | |
879 | if (mtd->writesize <= 512) | |
880 | chip->ecc.layout = &lpc32xx_nand_oob_16; | |
881 | ||
882 | /* These sizes remain the same regardless of page size */ | |
883 | chip->ecc.size = 256; | |
884 | chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES; | |
885 | chip->ecc.prepad = chip->ecc.postpad = 0; | |
886 | ||
887 | /* Avoid extra scan if using BBT, setup BBT support */ | |
888 | if (host->ncfg->use_bbt) { | |
2944a44d RS |
889 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
890 | ||
891 | /* | |
892 | * Use a custom BBT marker setup for small page FLASH that | |
893 | * won't interfere with the ECC layout. Large and huge page | |
894 | * FLASH use the standard layout. | |
895 | */ | |
896 | if (mtd->writesize <= 512) { | |
897 | chip->bbt_td = &bbt_smallpage_main_descr; | |
898 | chip->bbt_md = &bbt_smallpage_mirror_descr; | |
899 | } | |
900 | } | |
901 | ||
902 | /* | |
903 | * Fills out all the uninitialized function pointers with the defaults | |
904 | */ | |
905 | if (nand_scan_tail(mtd)) { | |
906 | res = -ENXIO; | |
907 | goto err_exit3; | |
908 | } | |
909 | ||
2944a44d RS |
910 | mtd->name = "nxp_lpc3220_slc"; |
911 | ppdata.of_node = pdev->dev.of_node; | |
912 | res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts, | |
913 | host->ncfg->num_parts); | |
914 | if (!res) | |
915 | return res; | |
916 | ||
917 | nand_release(mtd); | |
918 | ||
919 | err_exit3: | |
920 | dma_release_channel(host->dma_chan); | |
921 | err_exit2: | |
44cab9c9 | 922 | clk_disable_unprepare(host->clk); |
2944a44d RS |
923 | err_exit1: |
924 | lpc32xx_wp_enable(host); | |
2944a44d RS |
925 | |
926 | return res; | |
927 | } | |
928 | ||
929 | /* | |
930 | * Remove NAND device. | |
931 | */ | |
810b7e06 | 932 | static int lpc32xx_nand_remove(struct platform_device *pdev) |
2944a44d RS |
933 | { |
934 | uint32_t tmp; | |
935 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); | |
936 | struct mtd_info *mtd = &host->mtd; | |
937 | ||
938 | nand_release(mtd); | |
939 | dma_release_channel(host->dma_chan); | |
940 | ||
941 | /* Force CE high */ | |
942 | tmp = readl(SLC_CTRL(host->io_base)); | |
943 | tmp &= ~SLCCFG_CE_LOW; | |
944 | writel(tmp, SLC_CTRL(host->io_base)); | |
945 | ||
44cab9c9 | 946 | clk_disable_unprepare(host->clk); |
2944a44d | 947 | lpc32xx_wp_enable(host); |
2944a44d RS |
948 | |
949 | return 0; | |
950 | } | |
951 | ||
952 | #ifdef CONFIG_PM | |
953 | static int lpc32xx_nand_resume(struct platform_device *pdev) | |
954 | { | |
955 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); | |
956 | ||
957 | /* Re-enable NAND clock */ | |
44cab9c9 | 958 | clk_prepare_enable(host->clk); |
2944a44d RS |
959 | |
960 | /* Fresh init of NAND controller */ | |
961 | lpc32xx_nand_setup(host); | |
962 | ||
963 | /* Disable write protect */ | |
964 | lpc32xx_wp_disable(host); | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) | |
970 | { | |
971 | uint32_t tmp; | |
972 | struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); | |
973 | ||
974 | /* Force CE high */ | |
975 | tmp = readl(SLC_CTRL(host->io_base)); | |
976 | tmp &= ~SLCCFG_CE_LOW; | |
977 | writel(tmp, SLC_CTRL(host->io_base)); | |
978 | ||
979 | /* Enable write protect for safety */ | |
980 | lpc32xx_wp_enable(host); | |
981 | ||
982 | /* Disable clock */ | |
44cab9c9 | 983 | clk_disable_unprepare(host->clk); |
2944a44d RS |
984 | |
985 | return 0; | |
986 | } | |
987 | ||
988 | #else | |
989 | #define lpc32xx_nand_resume NULL | |
990 | #define lpc32xx_nand_suspend NULL | |
991 | #endif | |
992 | ||
2944a44d RS |
993 | static const struct of_device_id lpc32xx_nand_match[] = { |
994 | { .compatible = "nxp,lpc3220-slc" }, | |
995 | { /* sentinel */ }, | |
996 | }; | |
997 | MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); | |
2944a44d RS |
998 | |
999 | static struct platform_driver lpc32xx_nand_driver = { | |
1000 | .probe = lpc32xx_nand_probe, | |
5153b88c | 1001 | .remove = lpc32xx_nand_remove, |
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1002 | .resume = lpc32xx_nand_resume, |
1003 | .suspend = lpc32xx_nand_suspend, | |
1004 | .driver = { | |
1005 | .name = LPC32XX_MODNAME, | |
fea7b569 | 1006 | .of_match_table = lpc32xx_nand_match, |
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1007 | }, |
1008 | }; | |
1009 | ||
1010 | module_platform_driver(lpc32xx_nand_driver); | |
1011 | ||
1012 | MODULE_LICENSE("GPL"); | |
1013 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); | |
1014 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); | |
1015 | MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller"); |