[linux-2.6-block.git] / drivers / mtd / nand / jz4740_nand.c

/*
 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *  JZ4740 SoC NAND controller driver
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

#include <linux/gpio.h>

#include <asm/mach-jz4740/gpio.h>
#include <asm/mach-jz4740/jz4740_nand.h>

#define JZ_REG_NAND_CTRL	0x50
#define JZ_REG_NAND_ECC_CTRL	0x100
#define JZ_REG_NAND_DATA	0x104
#define JZ_REG_NAND_PAR0	0x108
#define JZ_REG_NAND_PAR1	0x10C
#define JZ_REG_NAND_PAR2	0x110
#define JZ_REG_NAND_IRQ_STAT	0x114
#define JZ_REG_NAND_IRQ_CTRL	0x118
#define JZ_REG_NAND_ERR(x)	(0x11C + ((x) << 2))

#define JZ_NAND_ECC_CTRL_PAR_READY	BIT(4)
#define JZ_NAND_ECC_CTRL_ENCODING	BIT(3)
#define JZ_NAND_ECC_CTRL_RS		BIT(2)
#define JZ_NAND_ECC_CTRL_RESET		BIT(1)
#define JZ_NAND_ECC_CTRL_ENABLE		BIT(0)

#define JZ_NAND_STATUS_ERR_COUNT	(BIT(31) | BIT(30) | BIT(29))
#define JZ_NAND_STATUS_PAD_FINISH	BIT(4)
#define JZ_NAND_STATUS_DEC_FINISH	BIT(3)
#define JZ_NAND_STATUS_ENC_FINISH	BIT(2)
#define JZ_NAND_STATUS_UNCOR_ERROR	BIT(1)
#define JZ_NAND_STATUS_ERROR		BIT(0)

#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa

#define JZ_NAND_MEM_CMD_OFFSET 0x08000
#define JZ_NAND_MEM_ADDR_OFFSET 0x10000

struct jz_nand {
	struct nand_chip chip;
	void __iomem *base;
	struct resource *mem;

	unsigned char banks[JZ_NAND_NUM_BANKS];
	void __iomem *bank_base[JZ_NAND_NUM_BANKS];
	struct resource *bank_mem[JZ_NAND_NUM_BANKS];

	int selected_bank;

	struct gpio_desc *busy_gpio;
	bool is_reading;
};

static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
{
	return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
}

static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
{
	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	struct nand_chip *chip = mtd_to_nand(mtd);
	uint32_t ctrl;
	int banknr;

	ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
	ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;

	if (chipnr == -1) {
		banknr = -1;
	} else {
		banknr = nand->banks[chipnr] - 1;
		chip->IO_ADDR_R = nand->bank_base[banknr];
		chip->IO_ADDR_W = nand->bank_base[banknr];
	}
	writel(ctrl, nand->base + JZ_REG_NAND_CTRL);

	nand->selected_bank = banknr;
}

static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
{
	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	struct nand_chip *chip = mtd_to_nand(mtd);
	uint32_t reg;
	void __iomem *bank_base = nand->bank_base[nand->selected_bank];

	BUG_ON(nand->selected_bank < 0);

	if (ctrl & NAND_CTRL_CHANGE) {
		BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
		if (ctrl & NAND_ALE)
			bank_base += JZ_NAND_MEM_ADDR_OFFSET;
		else if (ctrl & NAND_CLE)
			bank_base += JZ_NAND_MEM_CMD_OFFSET;
		chip->IO_ADDR_W = bank_base;

		reg = readl(nand->base + JZ_REG_NAND_CTRL);
		if (ctrl & NAND_NCE)
			reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
		else
			reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
		writel(reg, nand->base + JZ_REG_NAND_CTRL);
	}
	if (dat != NAND_CMD_NONE)
		writeb(dat, chip->IO_ADDR_W);
}

static int jz_nand_dev_ready(struct mtd_info *mtd)
{
	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	return gpiod_get_value_cansleep(nand->busy_gpio);
}

static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
{
	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	uint32_t reg;

	writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);

	reg |= JZ_NAND_ECC_CTRL_RESET;
	reg |= JZ_NAND_ECC_CTRL_ENABLE;
	reg |= JZ_NAND_ECC_CTRL_RS;

	switch (mode) {
	case NAND_ECC_READ:
		reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
		nand->is_reading = true;
		break;
	case NAND_ECC_WRITE:
		reg |= JZ_NAND_ECC_CTRL_ENCODING;
		nand->is_reading = false;
		break;
	default:
		break;
	}

	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
}

static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
	uint8_t *ecc_code)
{
	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	uint32_t reg, status;
	int i;
	unsigned int timeout = 1000;
	static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
						0x8b, 0xff, 0xb7, 0x6f};

	if (nand->is_reading)
		return 0;

	do {
		status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
	} while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);

	if (timeout == 0)
	    return -1;

	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);

	for (i = 0; i < 9; ++i)
		ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);

	/* If the written data is completly 0xff, we also want to write 0xff as
	 * ecc, otherwise we will get in trouble when doing subpage writes. */
	if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
		memset(ecc_code, 0xff, 9);

	return 0;
}

static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
{
	int offset = index & 0x7;
	uint16_t data;

	index += (index >> 3);

	data = dat[index];
	data |= dat[index+1] << 8;

	mask ^= (data >> offset) & 0x1ff;
	data &= ~(0x1ff << offset);
	data |= (mask << offset);

	dat[index] = data & 0xff;
	dat[index+1] = (data >> 8) & 0xff;
}

static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
	uint8_t *read_ecc, uint8_t *calc_ecc)
{
	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	int i, error_count, index;
	uint32_t reg, status, error;
	uint32_t t;
	unsigned int timeout = 1000;

	for (i = 0; i < 9; ++i)
		writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);

	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	reg |= JZ_NAND_ECC_CTRL_PAR_READY;
	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);

	do {
		status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
	} while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);

	if (timeout == 0)
		return -ETIMEDOUT;

	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);

	if (status & JZ_NAND_STATUS_ERROR) {
		if (status & JZ_NAND_STATUS_UNCOR_ERROR)
			return -EBADMSG;

		error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;

		for (i = 0; i < error_count; ++i) {
			error = readl(nand->base + JZ_REG_NAND_ERR(i));
			index = ((error >> 16) & 0x1ff) - 1;
			if (index >= 0 && index < 512)
				jz_nand_correct_data(dat, index, error & 0x1ff);
		}

		return error_count;
	}

	return 0;
}

static int jz_nand_ioremap_resource(struct platform_device *pdev,
	const char *name, struct resource **res, void *__iomem *base)
{
	int ret;

	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	if (!*res) {
		dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
		ret = -ENXIO;
		goto err;
	}

	*res = request_mem_region((*res)->start, resource_size(*res),
				pdev->name);
	if (!*res) {
		dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
		ret = -EBUSY;
		goto err;
	}

	*base = ioremap((*res)->start, resource_size(*res));
	if (!*base) {
		dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
		ret = -EBUSY;
		goto err_release_mem;
	}

	return 0;

err_release_mem:
	release_mem_region((*res)->start, resource_size(*res));
err:
	*res = NULL;
	*base = NULL;
	return ret;
}

static inline void jz_nand_iounmap_resource(struct resource *res,
					    void __iomem *base)
{
	iounmap(base);
	release_mem_region(res->start, resource_size(res));
}

static int jz_nand_detect_bank(struct platform_device *pdev,
			       struct jz_nand *nand, unsigned char bank,
			       size_t chipnr, uint8_t *nand_maf_id,
			       uint8_t *nand_dev_id)
{
	int ret;
	int gpio;
	char gpio_name[9];
	char res_name[6];
	uint32_t ctrl;
	struct nand_chip *chip = &nand->chip;
	struct mtd_info *mtd = nand_to_mtd(chip);

	/* Request GPIO port. */
	gpio = JZ_GPIO_MEM_CS0 + bank - 1;
	sprintf(gpio_name, "NAND CS%d", bank);
	ret = gpio_request(gpio, gpio_name);
	if (ret) {
		dev_warn(&pdev->dev,
			"Failed to request %s gpio %d: %d\n",
			gpio_name, gpio, ret);
		goto notfound_gpio;
	}

	/* Request I/O resource. */
	sprintf(res_name, "bank%d", bank);
	ret = jz_nand_ioremap_resource(pdev, res_name,
					&nand->bank_mem[bank - 1],
					&nand->bank_base[bank - 1]);
	if (ret)
		goto notfound_resource;

	/* Enable chip in bank. */
	jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
	ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
	ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
	writel(ctrl, nand->base + JZ_REG_NAND_CTRL);

	if (chipnr == 0) {
		/* Detect first chip. */
		ret = nand_scan_ident(mtd, 1, NULL);
		if (ret)
			goto notfound_id;

		/* Retrieve the IDs from the first chip. */
		chip->select_chip(mtd, 0);
		chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
		chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
		*nand_maf_id = chip->read_byte(mtd);
		*nand_dev_id = chip->read_byte(mtd);
	} else {
		/* Detect additional chip. */
		chip->select_chip(mtd, chipnr);
		chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
		chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
		if (*nand_maf_id != chip->read_byte(mtd)
		 || *nand_dev_id != chip->read_byte(mtd)) {
			ret = -ENODEV;
			goto notfound_id;
		}

		/* Update size of the MTD. */
		chip->numchips++;
		mtd->size += chip->chipsize;
	}

	dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
	return 0;

notfound_id:
	dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
	ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
	writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
	jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
	jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
				 nand->bank_base[bank - 1]);
notfound_resource:
	gpio_free(gpio);
notfound_gpio:
	return ret;
}

static int jz_nand_probe(struct platform_device *pdev)
{
	int ret;
	struct jz_nand *nand;
	struct nand_chip *chip;
	struct mtd_info *mtd;
	struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
	size_t chipnr, bank_idx;
	uint8_t nand_maf_id = 0, nand_dev_id = 0;

	nand = kzalloc(sizeof(*nand), GFP_KERNEL);
	if (!nand)
		return -ENOMEM;

	ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
	if (ret)
		goto err_free;

	nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
	if (IS_ERR(nand->busy_gpio)) {
		ret = PTR_ERR(nand->busy_gpio);
		dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
		    ret);
		goto err_iounmap_mmio;
	}

	chip		= &nand->chip;
	mtd		= nand_to_mtd(chip);
	mtd->dev.parent = &pdev->dev;
	mtd->name	= "jz4740-nand";

	chip->ecc.hwctl		= jz_nand_hwctl;
	chip->ecc.calculate	= jz_nand_calculate_ecc_rs;
	chip->ecc.correct	= jz_nand_correct_ecc_rs;
	chip->ecc.mode		= NAND_ECC_HW_OOB_FIRST;
	chip->ecc.size		= 512;
	chip->ecc.bytes		= 9;
	chip->ecc.strength	= 4;
	chip->ecc.options	= NAND_ECC_GENERIC_ERASED_CHECK;

	chip->chip_delay = 50;
	chip->cmd_ctrl = jz_nand_cmd_ctrl;
	chip->select_chip = jz_nand_select_chip;

	if (nand->busy_gpio)
		chip->dev_ready = jz_nand_dev_ready;

	platform_set_drvdata(pdev, nand);

	/* We are going to autodetect NAND chips in the banks specified in the
	 * platform data. Although nand_scan_ident() can detect multiple chips,
	 * it requires those chips to be numbered consecuitively, which is not
	 * always the case for external memory banks. And a fixed chip-to-bank
	 * mapping is not practical either, since for example Dingoo units
	 * produced at different times have NAND chips in different banks.
	 */
	chipnr = 0;
	for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
		unsigned char bank;

		/* If there is no platform data, look for NAND in bank 1,
		 * which is the most likely bank since it is the only one
		 * that can be booted from.
		 */
		bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
		if (bank == 0)
			break;
		if (bank > JZ_NAND_NUM_BANKS) {
			dev_warn(&pdev->dev,
				"Skipping non-existing bank: %d\n", bank);
			continue;
		}
		/* The detection routine will directly or indirectly call
		 * jz_nand_select_chip(), so nand->banks has to contain the
		 * bank we're checking.
		 */
		nand->banks[chipnr] = bank;
		if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
					&nand_maf_id, &nand_dev_id) == 0)
			chipnr++;
		else
			nand->banks[chipnr] = 0;
	}
	if (chipnr == 0) {
		dev_err(&pdev->dev, "No NAND chips found\n");
		goto err_iounmap_mmio;
	}

	if (pdata && pdata->ident_callback) {
		pdata->ident_callback(pdev, chip, &pdata->partitions,
					&pdata->num_partitions);
	}

	ret = nand_scan_tail(mtd);
	if (ret) {
		dev_err(&pdev->dev,  "Failed to scan NAND\n");
		goto err_unclaim_banks;
	}

	ret = mtd_device_parse_register(mtd, NULL, NULL,
					pdata ? pdata->partitions : NULL,
					pdata ? pdata->num_partitions : 0);

	if (ret) {
		dev_err(&pdev->dev, "Failed to add mtd device\n");
		goto err_nand_release;
	}

	dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");

	return 0;

err_nand_release:
	nand_release(mtd);
err_unclaim_banks:
	while (chipnr--) {
		unsigned char bank = nand->banks[chipnr];
		gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
		jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
					 nand->bank_base[bank - 1]);
	}
	writel(0, nand->base + JZ_REG_NAND_CTRL);
err_iounmap_mmio:
	jz_nand_iounmap_resource(nand->mem, nand->base);
err_free:
	kfree(nand);
	return ret;
}

static int jz_nand_remove(struct platform_device *pdev)
{
	struct jz_nand *nand = platform_get_drvdata(pdev);
	size_t i;

	nand_release(nand_to_mtd(&nand->chip));

	/* Deassert and disable all chips */
	writel(0, nand->base + JZ_REG_NAND_CTRL);

	for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
		unsigned char bank = nand->banks[i];
		if (bank != 0) {
			jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
						 nand->bank_base[bank - 1]);
			gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
		}
	}

	jz_nand_iounmap_resource(nand->mem, nand->base);

	kfree(nand);

	return 0;
}

static struct platform_driver jz_nand_driver = {
	.probe = jz_nand_probe,
	.remove = jz_nand_remove,
	.driver = {
		.name = "jz4740-nand",
	},
};

module_platform_driver(jz_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
MODULE_ALIAS("platform:jz4740-nand");
Commit	Line	Data
ba01d6ec LPC	1	/*
	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
	3	* JZ4740 SoC NAND controller driver
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* You should have received a copy of the GNU General Public License along
	11	* with this program; if not, write to the Free Software Foundation, Inc.,
	12	* 675 Mass Ave, Cambridge, MA 02139, USA.
	13	*
	14	*/
	15
	16	#include <linux/ioport.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/slab.h>
	21
	22	#include <linux/mtd/mtd.h>
	23	#include <linux/mtd/nand.h>
	24	#include <linux/mtd/partitions.h>
	25
	26	#include <linux/gpio.h>
	27
96dd922c	28	#include <asm/mach-jz4740/gpio.h>
ba01d6ec LPC	29	#include <asm/mach-jz4740/jz4740_nand.h>
	30
	31	#define JZ_REG_NAND_CTRL 0x50
	32	#define JZ_REG_NAND_ECC_CTRL 0x100
	33	#define JZ_REG_NAND_DATA 0x104
	34	#define JZ_REG_NAND_PAR0 0x108
	35	#define JZ_REG_NAND_PAR1 0x10C
	36	#define JZ_REG_NAND_PAR2 0x110
	37	#define JZ_REG_NAND_IRQ_STAT 0x114
	38	#define JZ_REG_NAND_IRQ_CTRL 0x118
	39	#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
	40
	41	#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
	42	#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
	43	#define JZ_NAND_ECC_CTRL_RS BIT(2)
	44	#define JZ_NAND_ECC_CTRL_RESET BIT(1)
	45	#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
	46
	47	#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) \| BIT(30) \| BIT(29))
	48	#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
	49	#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
	50	#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
	51	#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
	52	#define JZ_NAND_STATUS_ERROR BIT(0)
	53
	54	#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
	55	#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
1471d41a	56	#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
ba01d6ec	57
ba01d6ec	58	#define JZ_NAND_MEM_CMD_OFFSET 0x08000
1471d41a	59	#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
ba01d6ec LPC	60
ba01d6ec LPC	61	struct jz_nand {
ba01d6ec LPC	62	struct nand_chip chip;
	63	void __iomem *base;
	64	struct resource *mem;
	65
1471d41a MH	66	unsigned char banks[JZ_NAND_NUM_BANKS];
	67	void __iomem *bank_base[JZ_NAND_NUM_BANKS];
	68	struct resource *bank_mem[JZ_NAND_NUM_BANKS];
	69
	70	int selected_bank;
ba01d6ec	71
cd145af9	72	struct gpio_desc *busy_gpio;
ba01d6ec LPC	73	bool is_reading;
	74	};
	75
	76	static inline struct jz_nand mtd_to_jz_nand(struct mtd_info mtd)
	77	{
d25cc7ab	78	return container_of(mtd_to_nand(mtd), struct jz_nand, chip);
ba01d6ec LPC	79	}
ba01d6ec LPC	80
1471d41a MH	81	static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
	82	{
	83	struct jz_nand *nand = mtd_to_jz_nand(mtd);
4bd4ebcc	84	struct nand_chip *chip = mtd_to_nand(mtd);
1471d41a MH	85	uint32_t ctrl;
	86	int banknr;
	87
	88	ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
	89	ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
	90
	91	if (chipnr == -1) {
	92	banknr = -1;
	93	} else {
	94	banknr = nand->banks[chipnr] - 1;
	95	chip->IO_ADDR_R = nand->bank_base[banknr];
	96	chip->IO_ADDR_W = nand->bank_base[banknr];
	97	}
	98	writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
	99
	100	nand->selected_bank = banknr;
	101	}
	102
ba01d6ec LPC	103	static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
	104	{
	105	struct jz_nand *nand = mtd_to_jz_nand(mtd);
4bd4ebcc	106	struct nand_chip *chip = mtd_to_nand(mtd);
ba01d6ec	107	uint32_t reg;
1471d41a MH	108	void __iomem *bank_base = nand->bank_base[nand->selected_bank];
	109
	110	BUG_ON(nand->selected_bank < 0);
ba01d6ec LPC	111
	112	if (ctrl & NAND_CTRL_CHANGE) {
	113	BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
	114	if (ctrl & NAND_ALE)
1471d41a	115	bank_base += JZ_NAND_MEM_ADDR_OFFSET;
ba01d6ec	116	else if (ctrl & NAND_CLE)
1471d41a MH	117	bank_base += JZ_NAND_MEM_CMD_OFFSET;
1471d41a MH	118	chip->IO_ADDR_W = bank_base;
ba01d6ec LPC	119
	120	reg = readl(nand->base + JZ_REG_NAND_CTRL);
	121	if (ctrl & NAND_NCE)
1471d41a	122	reg \|= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
ba01d6ec	123	else
1471d41a	124	reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
ba01d6ec LPC	125	writel(reg, nand->base + JZ_REG_NAND_CTRL);
	126	}
	127	if (dat != NAND_CMD_NONE)
	128	writeb(dat, chip->IO_ADDR_W);
	129	}
	130
	131	static int jz_nand_dev_ready(struct mtd_info *mtd)
	132	{
	133	struct jz_nand *nand = mtd_to_jz_nand(mtd);
cd145af9	134	return gpiod_get_value_cansleep(nand->busy_gpio);
ba01d6ec LPC	135	}
	136
	137	static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
	138	{
	139	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	140	uint32_t reg;
	141
	142	writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
	143	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	144
	145	reg \|= JZ_NAND_ECC_CTRL_RESET;
	146	reg \|= JZ_NAND_ECC_CTRL_ENABLE;
	147	reg \|= JZ_NAND_ECC_CTRL_RS;
	148
	149	switch (mode) {
	150	case NAND_ECC_READ:
	151	reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
	152	nand->is_reading = true;
	153	break;
	154	case NAND_ECC_WRITE:
	155	reg \|= JZ_NAND_ECC_CTRL_ENCODING;
	156	nand->is_reading = false;
	157	break;
	158	default:
	159	break;
	160	}
	161
	162	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
	163	}
	164
	165	static int jz_nand_calculate_ecc_rs(struct mtd_info mtd, const uint8_t dat,
	166	uint8_t *ecc_code)
	167	{
	168	struct jz_nand *nand = mtd_to_jz_nand(mtd);
	169	uint32_t reg, status;
	170	int i;
	171	unsigned int timeout = 1000;
	172	static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
	173	0x8b, 0xff, 0xb7, 0x6f};
	174
	175	if (nand->is_reading)
	176	return 0;
	177
	178	do {
	179	status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
	180	} while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
	181
	182	if (timeout == 0)
	183	return -1;
	184
	185	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	186	reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
	187	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
	188
	189	for (i = 0; i < 9; ++i)
	190	ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
	191
	192	/* If the written data is completly 0xff, we also want to write 0xff as
	193	* ecc, otherwise we will get in trouble when doing subpage writes. */
	194	if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
	195	memset(ecc_code, 0xff, 9);
	196
	197	return 0;
	198	}
199
200	static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
201	{
202	int offset = index & 0x7;
203	uint16_t data;
204
205	index += (index >> 3);
206
207	data = dat[index];
208	data \|= dat[index+1] << 8;
209
210	mask ^= (data >> offset) & 0x1ff;
211	data &= ~(0x1ff << offset);
212	data \|= (mask << offset);
213
214	dat[index] = data & 0xff;
215	dat[index+1] = (data >> 8) & 0xff;
216	}
217
218	static int jz_nand_correct_ecc_rs(struct mtd_info mtd, uint8_t dat,
219	uint8_t read_ecc, uint8_t calc_ecc)
220	{
221	struct jz_nand *nand = mtd_to_jz_nand(mtd);
222	int i, error_count, index;
223	uint32_t reg, status, error;
224	uint32_t t;
225	unsigned int timeout = 1000;
226
ba01d6ec LPC	227	for (i = 0; i < 9; ++i)
	228	writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
	229
	230	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	231	reg \|= JZ_NAND_ECC_CTRL_PAR_READY;
	232	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
	233
	234	do {
	235	status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
	236	} while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
	237
	238	if (timeout == 0)
6e941192	239	return -ETIMEDOUT;
ba01d6ec LPC	240
	241	reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
	242	reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
	243	writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
	244
	245	if (status & JZ_NAND_STATUS_ERROR) {
	246	if (status & JZ_NAND_STATUS_UNCOR_ERROR)
6e941192	247	return -EBADMSG;
ba01d6ec LPC	248
	249	error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
	250
	251	for (i = 0; i < error_count; ++i) {
	252	error = readl(nand->base + JZ_REG_NAND_ERR(i));
	253	index = ((error >> 16) & 0x1ff) - 1;
	254	if (index >= 0 && index < 512)
	255	jz_nand_correct_data(dat, index, error & 0x1ff);
	256	}
	257
	258	return error_count;
	259	}
	260
	261	return 0;
	262	}
	263
ba01d6ec	264	static int jz_nand_ioremap_resource(struct platform_device *pdev,
1471d41a	265	const char name, struct resource res, void __iomem *base)
ba01d6ec LPC	266	{
	267	int ret;
	268
	269	*res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	270	if (!*res) {
	271	dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
	272	ret = -ENXIO;
	273	goto err;
	274	}
	275
	276	res = request_mem_region((res)->start, resource_size(*res),
	277	pdev->name);
	278	if (!*res) {
	279	dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
	280	ret = -EBUSY;
	281	goto err;
	282	}
	283
	284	base = ioremap((res)->start, resource_size(*res));
	285	if (!*base) {
	286	dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
	287	ret = -EBUSY;
	288	goto err_release_mem;
	289	}
	290
	291	return 0;
	292
	293	err_release_mem:
	294	release_mem_region((res)->start, resource_size(res));
	295	err:
	296	*res = NULL;
	297	*base = NULL;
	298	return ret;
	299	}
	300
7bf350b7 AB	301	static inline void jz_nand_iounmap_resource(struct resource *res,
7bf350b7 AB	302	void __iomem *base)
1471d41a MH	303	{
	304	iounmap(base);
	305	release_mem_region(res->start, resource_size(res));
	306	}
	307
7bf350b7 AB	308	static int jz_nand_detect_bank(struct platform_device *pdev,
	309	struct jz_nand *nand, unsigned char bank,
	310	size_t chipnr, uint8_t *nand_maf_id,
d8929942 GKH	311	uint8_t *nand_dev_id)
d8929942 GKH	312	{
1471d41a MH	313	int ret;
	314	int gpio;
	315	char gpio_name[9];
	316	char res_name[6];
	317	uint32_t ctrl;
1471d41a	318	struct nand_chip *chip = &nand->chip;
d25cc7ab	319	struct mtd_info *mtd = nand_to_mtd(chip);
1471d41a MH	320
	321	/* Request GPIO port. */
	322	gpio = JZ_GPIO_MEM_CS0 + bank - 1;
	323	sprintf(gpio_name, "NAND CS%d", bank);
	324	ret = gpio_request(gpio, gpio_name);
	325	if (ret) {
	326	dev_warn(&pdev->dev,
	327	"Failed to request %s gpio %d: %d\n",
	328	gpio_name, gpio, ret);
	329	goto notfound_gpio;
	330	}
	331
	332	/* Request I/O resource. */
	333	sprintf(res_name, "bank%d", bank);
	334	ret = jz_nand_ioremap_resource(pdev, res_name,
	335	&nand->bank_mem[bank - 1],
	336	&nand->bank_base[bank - 1]);
	337	if (ret)
	338	goto notfound_resource;
	339
	340	/* Enable chip in bank. */
	341	jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
	342	ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
	343	ctrl \|= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
	344	writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
	345
	346	if (chipnr == 0) {
	347	/* Detect first chip. */
	348	ret = nand_scan_ident(mtd, 1, NULL);
	349	if (ret)
	350	goto notfound_id;
	351
	352	/* Retrieve the IDs from the first chip. */
	353	chip->select_chip(mtd, 0);
	354	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
	355	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
	356	*nand_maf_id = chip->read_byte(mtd);
	357	*nand_dev_id = chip->read_byte(mtd);
	358	} else {
	359	/* Detect additional chip. */
	360	chip->select_chip(mtd, chipnr);
	361	chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
	362	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
	363	if (*nand_maf_id != chip->read_byte(mtd)
	364	\|\| *nand_dev_id != chip->read_byte(mtd)) {
	365	ret = -ENODEV;
	366	goto notfound_id;
	367	}
	368
	369	/* Update size of the MTD. */
	370	chip->numchips++;
	371	mtd->size += chip->chipsize;
	372	}
	373
	374	dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
	375	return 0;
	376
	377	notfound_id:
	378	dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
	379	ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
	380	writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
	381	jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
	382	jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
	383	nand->bank_base[bank - 1]);
384	notfound_resource:
385	gpio_free(gpio);
386	notfound_gpio:
387	return ret;
388	}
389
06f25510	390	static int jz_nand_probe(struct platform_device *pdev)
ba01d6ec LPC	391	{
	392	int ret;
	393	struct jz_nand *nand;
	394	struct nand_chip *chip;
	395	struct mtd_info *mtd;
453810b7	396	struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1471d41a MH	397	size_t chipnr, bank_idx;
1471d41a MH	398	uint8_t nand_maf_id = 0, nand_dev_id = 0;
ba01d6ec LPC	399
ba01d6ec LPC	400	nand = kzalloc(sizeof(*nand), GFP_KERNEL);
51b37b8a	401	if (!nand)
ba01d6ec	402	return -ENOMEM;
ba01d6ec LPC	403
	404	ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
	405	if (ret)
	406	goto err_free;
ba01d6ec	407
cd145af9 LPC	408	nand->busy_gpio = devm_gpiod_get_optional(&pdev->dev, "busy", GPIOD_IN);
	409	if (IS_ERR(nand->busy_gpio)) {
	410	ret = PTR_ERR(nand->busy_gpio);
	411	dev_err(&pdev->dev, "Failed to request busy gpio %d\n",
	412	ret);
	413	goto err_iounmap_mmio;
ba01d6ec LPC	414	}
ba01d6ec LPC	415
ba01d6ec	416	chip = &nand->chip;
d25cc7ab	417	mtd = nand_to_mtd(chip);
249eab69	418	mtd->dev.parent = &pdev->dev;
ba01d6ec LPC	419	mtd->name = "jz4740-nand";
	420
	421	chip->ecc.hwctl = jz_nand_hwctl;
	422	chip->ecc.calculate = jz_nand_calculate_ecc_rs;
	423	chip->ecc.correct = jz_nand_correct_ecc_rs;
	424	chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	425	chip->ecc.size = 512;
	426	chip->ecc.bytes = 9;
44df4d11	427	chip->ecc.strength = 4;
48bf35de	428	chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
ba01d6ec	429
ba01d6ec LPC	430	chip->chip_delay = 50;
ba01d6ec LPC	431	chip->cmd_ctrl = jz_nand_cmd_ctrl;
1471d41a	432	chip->select_chip = jz_nand_select_chip;
ba01d6ec	433
cd145af9	434	if (nand->busy_gpio)
ba01d6ec LPC	435	chip->dev_ready = jz_nand_dev_ready;
ba01d6ec LPC	436
ba01d6ec LPC	437	platform_set_drvdata(pdev, nand);
ba01d6ec LPC	438
1471d41a MH	439	/* We are going to autodetect NAND chips in the banks specified in the
	440	* platform data. Although nand_scan_ident() can detect multiple chips,
	441	* it requires those chips to be numbered consecuitively, which is not
	442	* always the case for external memory banks. And a fixed chip-to-bank
	443	* mapping is not practical either, since for example Dingoo units
	444	* produced at different times have NAND chips in different banks.
	445	*/
	446	chipnr = 0;
	447	for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
	448	unsigned char bank;
	449
	450	/* If there is no platform data, look for NAND in bank 1,
	451	* which is the most likely bank since it is the only one
	452	* that can be booted from.
	453	*/
	454	bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
	455	if (bank == 0)
	456	break;
	457	if (bank > JZ_NAND_NUM_BANKS) {
	458	dev_warn(&pdev->dev,
	459	"Skipping non-existing bank: %d\n", bank);
	460	continue;
	461	}
	462	/* The detection routine will directly or indirectly call
	463	* jz_nand_select_chip(), so nand->banks has to contain the
	464	* bank we're checking.
	465	*/
	466	nand->banks[chipnr] = bank;
	467	if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
	468	&nand_maf_id, &nand_dev_id) == 0)
	469	chipnr++;
	470	else
	471	nand->banks[chipnr] = 0;
	472	}
	473	if (chipnr == 0) {
	474	dev_err(&pdev->dev, "No NAND chips found\n");
cd145af9	475	goto err_iounmap_mmio;
ba01d6ec LPC	476	}
	477
	478	if (pdata && pdata->ident_callback) {
	479	pdata->ident_callback(pdev, chip, &pdata->partitions,
	480	&pdata->num_partitions);
	481	}
	482
	483	ret = nand_scan_tail(mtd);
	484	if (ret) {
1471d41a MH	485	dev_err(&pdev->dev, "Failed to scan NAND\n");
1471d41a MH	486	goto err_unclaim_banks;
ba01d6ec LPC	487	}
ba01d6ec LPC	488
42d7fbe2 AB	489	ret = mtd_device_parse_register(mtd, NULL, NULL,
	490	pdata ? pdata->partitions : NULL,
	491	pdata ? pdata->num_partitions : 0);
ba01d6ec LPC	492
	493	if (ret) {
	494	dev_err(&pdev->dev, "Failed to add mtd device\n");
	495	goto err_nand_release;
	496	}
	497
	498	dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
	499
	500	return 0;
	501
	502	err_nand_release:
1471d41a MH	503	nand_release(mtd);
	504	err_unclaim_banks:
	505	while (chipnr--) {
	506	unsigned char bank = nand->banks[chipnr];
	507	gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
	508	jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
	509	nand->bank_base[bank - 1]);
	510	}
	511	writel(0, nand->base + JZ_REG_NAND_CTRL);
ba01d6ec	512	err_iounmap_mmio:
1471d41a	513	jz_nand_iounmap_resource(nand->mem, nand->base);
ba01d6ec LPC	514	err_free:
	515	kfree(nand);
	516	return ret;
	517	}
	518
810b7e06	519	static int jz_nand_remove(struct platform_device *pdev)
ba01d6ec LPC	520	{
ba01d6ec LPC	521	struct jz_nand *nand = platform_get_drvdata(pdev);
1471d41a	522	size_t i;
ba01d6ec	523
d25cc7ab	524	nand_release(nand_to_mtd(&nand->chip));
ba01d6ec LPC	525
	526	/* Deassert and disable all chips */
	527	writel(0, nand->base + JZ_REG_NAND_CTRL);
	528
1471d41a MH	529	for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
	530	unsigned char bank = nand->banks[i];
	531	if (bank != 0) {
	532	jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
	533	nand->bank_base[bank - 1]);
	534	gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
	535	}
	536	}
1471d41a MH	537
1471d41a MH	538	jz_nand_iounmap_resource(nand->mem, nand->base);
ba01d6ec	539
ba01d6ec LPC	540	kfree(nand);
	541
	542	return 0;
	543	}
	544
a338adaf	545	static struct platform_driver jz_nand_driver = {
ba01d6ec	546	.probe = jz_nand_probe,
5153b88c	547	.remove = jz_nand_remove,
ba01d6ec LPC	548	.driver = {
ba01d6ec LPC	549	.name = "jz4740-nand",
ba01d6ec LPC	550	},
	551	};
	552
f99640de	553	module_platform_driver(jz_nand_driver);
ba01d6ec LPC	554
	555	MODULE_LICENSE("GPL");
	556	MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
	557	MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
	558	MODULE_ALIAS("platform:jz4740-nand");