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mtd: nand: Add missing copyright information
[linux-2.6-block.git] / drivers / mtd / nand / fsmc_nand.c
CommitLineData
6c009ab8 1/*
6c009ab8
LW		 2 * ST Microelectronics
3 * Flexible Static Memory Controller (FSMC)
4 * Driver for NAND portions
5 *
6 * Copyright © 2010 ST Microelectronics
7 * Vipin Kumar <vipin.kumar@st.com>
8 * Ashish Priyadarshi
9 *
187c5448 10 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
7b6afee7
BB		 11 * Copyright © 2007 STMicroelectronics Pvt. Ltd.
12 * Copyright © 2009 Alessandro Rubini
6c009ab8
LW		 13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19#include <linux/clk.h>
4774fb0a
VK		 20#include <linux/completion.h>
21#include <linux/dmaengine.h>
22#include <linux/dma-direction.h>
23#include <linux/dma-mapping.h>
6c009ab8
LW		 24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/resource.h>
28#include <linux/sched.h>
29#include <linux/types.h>
30#include <linux/mtd/mtd.h>
d4092d76 31#include <linux/mtd/rawnand.h>
6c009ab8
LW		 32#include <linux/mtd/nand_ecc.h>
33#include <linux/platform_device.h>
eea62819 34#include <linux/of.h>
6c009ab8
LW		 35#include <linux/mtd/partitions.h>
36#include <linux/io.h>
37#include <linux/slab.h>
593cd871 38#include <linux/amba/bus.h>
6c009ab8
LW		 39#include <mtd/mtd-abi.h>
40
4404d7d8
LW		 41/* fsmc controller registers for NOR flash */
42#define CTRL 0x0
43 /* ctrl register definitions */
44 #define BANK_ENABLE (1 << 0)
45 #define MUXED (1 << 1)
46 #define NOR_DEV (2 << 2)
47 #define WIDTH_8 (0 << 4)
48 #define WIDTH_16 (1 << 4)
49 #define RSTPWRDWN (1 << 6)
50 #define WPROT (1 << 7)
51 #define WRT_ENABLE (1 << 12)
52 #define WAIT_ENB (1 << 13)
53
54#define CTRL_TIM 0x4
55 /* ctrl_tim register definitions */
56
57#define FSMC_NOR_BANK_SZ 0x8
58#define FSMC_NOR_REG_SIZE 0x40
59
60#define FSMC_NOR_REG(base, bank, reg) (base + \
61 FSMC_NOR_BANK_SZ * (bank) + \
62 reg)
63
64/* fsmc controller registers for NAND flash */
65#define PC 0x00
66 /* pc register definitions */
67 #define FSMC_RESET (1 << 0)
68 #define FSMC_WAITON (1 << 1)
69 #define FSMC_ENABLE (1 << 2)
70 #define FSMC_DEVTYPE_NAND (1 << 3)
71 #define FSMC_DEVWID_8 (0 << 4)
72 #define FSMC_DEVWID_16 (1 << 4)
73 #define FSMC_ECCEN (1 << 6)
74 #define FSMC_ECCPLEN_512 (0 << 7)
75 #define FSMC_ECCPLEN_256 (1 << 7)
76 #define FSMC_TCLR_1 (1)
77 #define FSMC_TCLR_SHIFT (9)
78 #define FSMC_TCLR_MASK (0xF)
79 #define FSMC_TAR_1 (1)
80 #define FSMC_TAR_SHIFT (13)
81 #define FSMC_TAR_MASK (0xF)
82#define STS 0x04
83 /* sts register definitions */
84 #define FSMC_CODE_RDY (1 << 15)
85#define COMM 0x08
86 /* comm register definitions */
87 #define FSMC_TSET_0 0
88 #define FSMC_TSET_SHIFT 0
89 #define FSMC_TSET_MASK 0xFF
90 #define FSMC_TWAIT_6 6
91 #define FSMC_TWAIT_SHIFT 8
92 #define FSMC_TWAIT_MASK 0xFF
93 #define FSMC_THOLD_4 4
94 #define FSMC_THOLD_SHIFT 16
95 #define FSMC_THOLD_MASK 0xFF
96 #define FSMC_THIZ_1 1
97 #define FSMC_THIZ_SHIFT 24
98 #define FSMC_THIZ_MASK 0xFF
99#define ATTRIB 0x0C
100#define IOATA 0x10
101#define ECC1 0x14
102#define ECC2 0x18
103#define ECC3 0x1C
104#define FSMC_NAND_BANK_SZ 0x20
105
106#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
107 (FSMC_NAND_BANK_SZ * (bank)) + \
108 reg)
109
110#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
111
112struct fsmc_nand_timings {
113 uint8_t tclr;
114 uint8_t tar;
115 uint8_t thiz;
116 uint8_t thold;
117 uint8_t twait;
118 uint8_t tset;
119};
120
121enum access_mode {
122 USE_DMA_ACCESS = 1,
123 USE_WORD_ACCESS,
124};
125
e7cda017
TP		 126/**
127 * struct fsmc_nand_data - structure for FSMC NAND device state
128 *
129 * @pid: Part ID on the AMBA PrimeCell format
130 * @mtd: MTD info for a NAND flash.
131 * @nand: Chip related info for a NAND flash.
132 * @partitions: Partition info for a NAND Flash.
133 * @nr_partitions: Total number of partition of a NAND flash.
134 *
135 * @bank: Bank number for probed device.
136 * @clk: Clock structure for FSMC.
137 *
138 * @read_dma_chan: DMA channel for read access
139 * @write_dma_chan: DMA channel for write access to NAND
140 * @dma_access_complete: Completion structure
141 *
142 * @data_pa: NAND Physical port for Data.
143 * @data_va: NAND port for Data.
144 * @cmd_va: NAND port for Command.
145 * @addr_va: NAND port for Address.
146 * @regs_va: FSMC regs base address.
147 */
148struct fsmc_nand_data {
149 u32 pid;
150 struct nand_chip nand;
e7cda017
TP		 151
152 unsigned int bank;
153 struct device *dev;
154 enum access_mode mode;
155 struct clk *clk;
156
157 /* DMA related objects */
158 struct dma_chan *read_dma_chan;
159 struct dma_chan *write_dma_chan;
160 struct completion dma_access_complete;
161
162 struct fsmc_nand_timings *dev_timings;
163
164 dma_addr_t data_pa;
165 void __iomem *data_va;
166 void __iomem *cmd_va;
167 void __iomem *addr_va;
168 void __iomem *regs_va;
e7cda017
TP		 169};
170
22b46957
BB		 171static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
172 struct mtd_oob_region *oobregion)
173{
174 struct nand_chip *chip = mtd_to_nand(mtd);
175
176 if (section >= chip->ecc.steps)
177 return -ERANGE;
178
179 oobregion->offset = (section * 16) + 2;
180 oobregion->length = 3;
181
182 return 0;
183}
184
185static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
186 struct mtd_oob_region *oobregion)
187{
188 struct nand_chip *chip = mtd_to_nand(mtd);
189
190 if (section >= chip->ecc.steps)
191 return -ERANGE;
192
193 oobregion->offset = (section * 16) + 8;
194
195 if (section < chip->ecc.steps - 1)
196 oobregion->length = 8;
197 else
198 oobregion->length = mtd->oobsize - oobregion->offset;
199
200 return 0;
201}
202
203static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
204 .ecc = fsmc_ecc1_ooblayout_ecc,
205 .free = fsmc_ecc1_ooblayout_free,
206};
207
04a123a9
BB		 208/*
209 * ECC placement definitions in oobfree type format.
210 * There are 13 bytes of ecc for every 512 byte block and it has to be read
211 * consecutively and immediately after the 512 byte data block for hardware to
212 * generate the error bit offsets in 512 byte data.
213 */
22b46957
BB		 214static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
215 struct mtd_oob_region *oobregion)
216{
217 struct nand_chip *chip = mtd_to_nand(mtd);
218
219 if (section >= chip->ecc.steps)
220 return -ERANGE;
221
222 oobregion->length = chip->ecc.bytes;
223
224 if (!section && mtd->writesize <= 512)
225 oobregion->offset = 0;
226 else
227 oobregion->offset = (section * 16) + 2;
228
229 return 0;
230}
231
232static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
233 struct mtd_oob_region *oobregion)
234{
235 struct nand_chip *chip = mtd_to_nand(mtd);
236
237 if (section >= chip->ecc.steps)
238 return -ERANGE;
239
240 oobregion->offset = (section * 16) + 15;
241
242 if (section < chip->ecc.steps - 1)
243 oobregion->length = 3;
244 else
245 oobregion->length = mtd->oobsize - oobregion->offset;
246
247 return 0;
248}
249
250static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
251 .ecc = fsmc_ecc4_ooblayout_ecc,
252 .free = fsmc_ecc4_ooblayout_free,
253};
254
277af429
BB		 255static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
256{
bdf3a555 257 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
277af429
BB		 258}
259
6c009ab8
LW		 260/*
261 * fsmc_cmd_ctrl - For facilitaing Hardware access
262 * This routine allows hardware specific access to control-lines(ALE,CLE)
263 */
264static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
265{
4bd4ebcc 266 struct nand_chip *this = mtd_to_nand(mtd);
277af429 267 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
605add7d 268 void __iomem *regs = host->regs_va;
6c009ab8
LW		 269 unsigned int bank = host->bank;
270
271 if (ctrl & NAND_CTRL_CHANGE) {
2a5dbead
VK		 272 u32 pc;
273
6c009ab8 274 if (ctrl & NAND_CLE) {
2a5dbead
VK		 275 this->IO_ADDR_R = host->cmd_va;
276 this->IO_ADDR_W = host->cmd_va;
6c009ab8 277 } else if (ctrl & NAND_ALE) {
2a5dbead
VK		 278 this->IO_ADDR_R = host->addr_va;
279 this->IO_ADDR_W = host->addr_va;
6c009ab8 280 } else {
2a5dbead
VK		 281 this->IO_ADDR_R = host->data_va;
282 this->IO_ADDR_W = host->data_va;
6c009ab8
LW		 283 }
284
2a5dbead
VK		 285 pc = readl(FSMC_NAND_REG(regs, bank, PC));
286 if (ctrl & NAND_NCE)
287 pc |= FSMC_ENABLE;
288 else
289 pc &= ~FSMC_ENABLE;
a4742d51 290 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
6c009ab8
LW		 291 }
292
293 mb();
294
295 if (cmd != NAND_CMD_NONE)
a4742d51 296 writeb_relaxed(cmd, this->IO_ADDR_W);
6c009ab8
LW		 297}
298
299/*
300 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
301 *
302 * This routine initializes timing parameters related to NAND memory access in
303 * FSMC registers
304 */
6335b509 305static void fsmc_nand_setup(struct fsmc_nand_data *host,
1debdb96 306 struct fsmc_nand_timings *tims)
6c009ab8
LW		 307{
308 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
e2f6bce8 309 uint32_t tclr, tar, thiz, thold, twait, tset;
6335b509
TP		 310 unsigned int bank = host->bank;
311 void __iomem *regs = host->regs_va;
e2f6bce8
VK		 312
313 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
314 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
315 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
316 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
317 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
318 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
6c009ab8 319
6335b509 320 if (host->nand.options & NAND_BUSWIDTH_16)
a4742d51
VK		 321 writel_relaxed(value | FSMC_DEVWID_16,
322 FSMC_NAND_REG(regs, bank, PC));
6c009ab8 323 else
a4742d51
VK		 324 writel_relaxed(value | FSMC_DEVWID_8,
325 FSMC_NAND_REG(regs, bank, PC));
6c009ab8 326
a4742d51 327 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
2a5dbead 328 FSMC_NAND_REG(regs, bank, PC));
a4742d51
VK		 329 writel_relaxed(thiz | thold | twait | tset,
330 FSMC_NAND_REG(regs, bank, COMM));
331 writel_relaxed(thiz | thold | twait | tset,
332 FSMC_NAND_REG(regs, bank, ATTRIB));
6c009ab8
LW		 333}
334
d9fb0795
TP		 335static int fsmc_calc_timings(struct fsmc_nand_data *host,
336 const struct nand_sdr_timings *sdrt,
337 struct fsmc_nand_timings *tims)
338{
339 unsigned long hclk = clk_get_rate(host->clk);
340 unsigned long hclkn = NSEC_PER_SEC / hclk;
341 uint32_t thiz, thold, twait, tset;
342
343 if (sdrt->tRC_min < 30000)
344 return -EOPNOTSUPP;
345
346 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
347 if (tims->tar > FSMC_TAR_MASK)
348 tims->tar = FSMC_TAR_MASK;
349 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
350 if (tims->tclr > FSMC_TCLR_MASK)
351 tims->tclr = FSMC_TCLR_MASK;
352
353 thiz = sdrt->tCS_min - sdrt->tWP_min;
354 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
355
356 thold = sdrt->tDH_min;
357 if (thold < sdrt->tCH_min)
358 thold = sdrt->tCH_min;
359 if (thold < sdrt->tCLH_min)
360 thold = sdrt->tCLH_min;
361 if (thold < sdrt->tWH_min)
362 thold = sdrt->tWH_min;
363 if (thold < sdrt->tALH_min)
364 thold = sdrt->tALH_min;
365 if (thold < sdrt->tREH_min)
366 thold = sdrt->tREH_min;
367 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
368 if (tims->thold == 0)
369 tims->thold = 1;
370 else if (tims->thold > FSMC_THOLD_MASK)
371 tims->thold = FSMC_THOLD_MASK;
372
373 twait = max(sdrt->tRP_min, sdrt->tWP_min);
374 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
375 if (tims->twait == 0)
376 tims->twait = 1;
377 else if (tims->twait > FSMC_TWAIT_MASK)
378 tims->twait = FSMC_TWAIT_MASK;
379
380 tset = max(sdrt->tCS_min - sdrt->tWP_min,
381 sdrt->tCEA_max - sdrt->tREA_max);
382 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
383 if (tims->tset == 0)
384 tims->tset = 1;
385 else if (tims->tset > FSMC_TSET_MASK)
386 tims->tset = FSMC_TSET_MASK;
387
388 return 0;
389}
390
104e442a
BB		 391static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
392 const struct nand_data_interface *conf)
d9fb0795
TP		 393{
394 struct nand_chip *nand = mtd_to_nand(mtd);
395 struct fsmc_nand_data *host = nand_get_controller_data(nand);
396 struct fsmc_nand_timings tims;
397 const struct nand_sdr_timings *sdrt;
398 int ret;
399
400 sdrt = nand_get_sdr_timings(conf);
401 if (IS_ERR(sdrt))
402 return PTR_ERR(sdrt);
403
404 ret = fsmc_calc_timings(host, sdrt, &tims);
405 if (ret)
406 return ret;
407
104e442a 408 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
d9fb0795
TP		 409 return 0;
410
411 fsmc_nand_setup(host, &tims);
412
413 return 0;
414}
415
6c009ab8
LW		 416/*
417 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
418 */
419static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
420{
277af429 421 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
2a5dbead 422 void __iomem *regs = host->regs_va;
6c009ab8
LW		 423 uint32_t bank = host->bank;
424
a4742d51 425 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
2a5dbead 426 FSMC_NAND_REG(regs, bank, PC));
a4742d51 427 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
2a5dbead 428 FSMC_NAND_REG(regs, bank, PC));
a4742d51 429 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
2a5dbead 430 FSMC_NAND_REG(regs, bank, PC));
6c009ab8
LW		 431}
432
433/*
434 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
25985edc 435 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
6c009ab8
LW		 436 * max of 8-bits)
437 */
438static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
439 uint8_t *ecc)
440{
277af429 441 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
2a5dbead 442 void __iomem *regs = host->regs_va;
6c009ab8
LW		 443 uint32_t bank = host->bank;
444 uint32_t ecc_tmp;
445 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
446
447 do {
a4742d51 448 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
6c009ab8
LW		 449 break;
450 else
451 cond_resched();
452 } while (!time_after_eq(jiffies, deadline));
453
712c4add
VK		 454 if (time_after_eq(jiffies, deadline)) {
455 dev_err(host->dev, "calculate ecc timed out\n");
456 return -ETIMEDOUT;
457 }
458
a4742d51 459 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
6c009ab8
LW		 460 ecc[0] = (uint8_t) (ecc_tmp >> 0);
461 ecc[1] = (uint8_t) (ecc_tmp >> 8);
462 ecc[2] = (uint8_t) (ecc_tmp >> 16);
463 ecc[3] = (uint8_t) (ecc_tmp >> 24);
464
a4742d51 465 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
6c009ab8
LW		 466 ecc[4] = (uint8_t) (ecc_tmp >> 0);
467 ecc[5] = (uint8_t) (ecc_tmp >> 8);
468 ecc[6] = (uint8_t) (ecc_tmp >> 16);
469 ecc[7] = (uint8_t) (ecc_tmp >> 24);
470
a4742d51 471 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
6c009ab8
LW		 472 ecc[8] = (uint8_t) (ecc_tmp >> 0);
473 ecc[9] = (uint8_t) (ecc_tmp >> 8);
474 ecc[10] = (uint8_t) (ecc_tmp >> 16);
475 ecc[11] = (uint8_t) (ecc_tmp >> 24);
476
a4742d51 477 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
6c009ab8
LW		 478 ecc[12] = (uint8_t) (ecc_tmp >> 16);
479
480 return 0;
481}
482
483/*
484 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
25985edc 485 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
6c009ab8
LW		 486 * max of 1-bit)
487 */
488static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
489 uint8_t *ecc)
490{
277af429 491 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
2a5dbead 492 void __iomem *regs = host->regs_va;
6c009ab8
LW		 493 uint32_t bank = host->bank;
494 uint32_t ecc_tmp;
495
a4742d51 496 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
6c009ab8
LW		 497 ecc[0] = (uint8_t) (ecc_tmp >> 0);
498 ecc[1] = (uint8_t) (ecc_tmp >> 8);
499 ecc[2] = (uint8_t) (ecc_tmp >> 16);
500
501 return 0;
502}
503
519300cf
VK		 504/* Count the number of 0's in buff upto a max of max_bits */
505static int count_written_bits(uint8_t *buff, int size, int max_bits)
506{
507 int k, written_bits = 0;
508
509 for (k = 0; k < size; k++) {
510 written_bits += hweight8(~buff[k]);
511 if (written_bits > max_bits)
512 break;
513 }
514
515 return written_bits;
516}
517
4774fb0a
VK		 518static void dma_complete(void *param)
519{
520 struct fsmc_nand_data *host = param;
521
522 complete(&host->dma_access_complete);
523}
524
525static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
526 enum dma_data_direction direction)
527{
528 struct dma_chan *chan;
529 struct dma_device *dma_dev;
530 struct dma_async_tx_descriptor *tx;
531 dma_addr_t dma_dst, dma_src, dma_addr;
532 dma_cookie_t cookie;
533 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
534 int ret;
818a45b1 535 unsigned long time_left;
4774fb0a
VK		 536
537 if (direction == DMA_TO_DEVICE)
538 chan = host->write_dma_chan;
539 else if (direction == DMA_FROM_DEVICE)
540 chan = host->read_dma_chan;
541 else
542 return -EINVAL;
543
544 dma_dev = chan->device;
545 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
546
547 if (direction == DMA_TO_DEVICE) {
548 dma_src = dma_addr;
549 dma_dst = host->data_pa;
4774fb0a
VK		 550 } else {
551 dma_src = host->data_pa;
552 dma_dst = dma_addr;
4774fb0a
VK		 553 }
554
555 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
556 len, flags);
4774fb0a
VK		 557 if (!tx) {
558 dev_err(host->dev, "device_prep_dma_memcpy error\n");
d1806a5c
BZ		 559 ret = -EIO;
560 goto unmap_dma;
4774fb0a
VK		 561 }
562
563 tx->callback = dma_complete;
564 tx->callback_param = host;
565 cookie = tx->tx_submit(tx);
566
567 ret = dma_submit_error(cookie);
568 if (ret) {
569 dev_err(host->dev, "dma_submit_error %d\n", cookie);
d1806a5c 570 goto unmap_dma;
4774fb0a
VK		 571 }
572
573 dma_async_issue_pending(chan);
574
818a45b1 575 time_left =
928aa2ae 576 wait_for_completion_timeout(&host->dma_access_complete,
4774fb0a 577 msecs_to_jiffies(3000));
818a45b1 578 if (time_left == 0) {
b177ea34 579 dmaengine_terminate_all(chan);
4774fb0a 580 dev_err(host->dev, "wait_for_completion_timeout\n");
0bda3e19 581 ret = -ETIMEDOUT;
d1806a5c 582 goto unmap_dma;
4774fb0a
VK		 583 }
584
d1806a5c
BZ		 585 ret = 0;
586
587unmap_dma:
588 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
589
590 return ret;
4774fb0a
VK		 591}
592
604e7544
VK		 593/*
594 * fsmc_write_buf - write buffer to chip
595 * @mtd: MTD device structure
596 * @buf: data buffer
597 * @len: number of bytes to write
598 */
599static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
600{
601 int i;
4bd4ebcc 602 struct nand_chip *chip = mtd_to_nand(mtd);
604e7544
VK		 603
604 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
605 IS_ALIGNED(len, sizeof(uint32_t))) {
606 uint32_t *p = (uint32_t *)buf;
607 len = len >> 2;
608 for (i = 0; i < len; i++)
a4742d51 609 writel_relaxed(p[i], chip->IO_ADDR_W);
604e7544
VK		 610 } else {
611 for (i = 0; i < len; i++)
a4742d51 612 writeb_relaxed(buf[i], chip->IO_ADDR_W);
604e7544
VK		 613 }
614}
615
616/*
617 * fsmc_read_buf - read chip data into buffer
618 * @mtd: MTD device structure
619 * @buf: buffer to store date
620 * @len: number of bytes to read
621 */
622static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
623{
624 int i;
4bd4ebcc 625 struct nand_chip *chip = mtd_to_nand(mtd);
604e7544
VK		 626
627 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
628 IS_ALIGNED(len, sizeof(uint32_t))) {
629 uint32_t *p = (uint32_t *)buf;
630 len = len >> 2;
631 for (i = 0; i < len; i++)
a4742d51 632 p[i] = readl_relaxed(chip->IO_ADDR_R);
604e7544
VK		 633 } else {
634 for (i = 0; i < len; i++)
a4742d51 635 buf[i] = readb_relaxed(chip->IO_ADDR_R);
604e7544
VK		 636 }
637}
638
4774fb0a
VK		 639/*
640 * fsmc_read_buf_dma - read chip data into buffer
641 * @mtd: MTD device structure
642 * @buf: buffer to store date
643 * @len: number of bytes to read
644 */
645static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
646{
277af429 647 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
4774fb0a 648
4774fb0a
VK		 649 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
650}
651
652/*
653 * fsmc_write_buf_dma - write buffer to chip
654 * @mtd: MTD device structure
655 * @buf: data buffer
656 * @len: number of bytes to write
657 */
658static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
659 int len)
660{
277af429 661 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
4774fb0a 662
4774fb0a
VK		 663 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
664}
665
6c009ab8
LW		 666/*
667 * fsmc_read_page_hwecc
668 * @mtd: mtd info structure
669 * @chip: nand chip info structure
670 * @buf: buffer to store read data
1fbb938d 671 * @oob_required: caller expects OOB data read to chip->oob_poi
6c009ab8
LW		 672 * @page: page number to read
673 *
25985edc 674 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
6c009ab8
LW		 675 * performed in a strict sequence as follows:
676 * data(512 byte) -> ecc(13 byte)
25985edc 677 * After this read, fsmc hardware generates and reports error data bits(up to a
6c009ab8
LW		 678 * max of 8 bits)
679 */
680static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 681 uint8_t *buf, int oob_required, int page)
6c009ab8 682{
6c009ab8
LW		 683 int i, j, s, stat, eccsize = chip->ecc.size;
684 int eccbytes = chip->ecc.bytes;
685 int eccsteps = chip->ecc.steps;
686 uint8_t *p = buf;
c0313b96
MY		 687 uint8_t *ecc_calc = chip->ecc.calc_buf;
688 uint8_t *ecc_code = chip->ecc.code_buf;
6c009ab8
LW		 689 int off, len, group = 0;
690 /*
691 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
692 * end up reading 14 bytes (7 words) from oob. The local array is
693 * to maintain word alignment
694 */
695 uint16_t ecc_oob[7];
696 uint8_t *oob = (uint8_t *)&ecc_oob[0];
3f91e94f 697 unsigned int max_bitflips = 0;
6c009ab8
LW		 698
699 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
97d90da8 700 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
6c009ab8
LW		 701 chip->ecc.hwctl(mtd, NAND_ECC_READ);
702 chip->read_buf(mtd, p, eccsize);
703
704 for (j = 0; j < eccbytes;) {
04a123a9
BB		 705 struct mtd_oob_region oobregion;
706 int ret;
707
708 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
709 if (ret)
710 return ret;
711
712 off = oobregion.offset;
713 len = oobregion.length;
6c009ab8
LW		 714
715 /*
4cbe1bf0
VK		 716 * length is intentionally kept a higher multiple of 2
717 * to read at least 13 bytes even in case of 16 bit NAND
718 * devices
719 */
aea686b4
VK		 720 if (chip->options & NAND_BUSWIDTH_16)
721 len = roundup(len, 2);
722
97d90da8 723 nand_read_oob_op(chip, page, off, oob + j, len);
6c009ab8
LW		 724 j += len;
725 }
726
519300cf 727 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
6c009ab8
LW		 728 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
729
730 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 731 if (stat < 0) {
6c009ab8 732 mtd->ecc_stats.failed++;
3f91e94f 733 } else {
6c009ab8 734 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 735 max_bitflips = max_t(unsigned int, max_bitflips, stat);
736 }
6c009ab8
LW		 737 }
738
3f91e94f 739 return max_bitflips;
6c009ab8
LW		 740}
741
742/*
753e0139 743 * fsmc_bch8_correct_data
6c009ab8
LW		 744 * @mtd: mtd info structure
745 * @dat: buffer of read data
746 * @read_ecc: ecc read from device spare area
747 * @calc_ecc: ecc calculated from read data
748 *
749 * calc_ecc is a 104 bit information containing maximum of 8 error
750 * offset informations of 13 bits each in 512 bytes of read data.
751 */
753e0139 752static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
6c009ab8
LW		 753 uint8_t *read_ecc, uint8_t *calc_ecc)
754{
4bd4ebcc 755 struct nand_chip *chip = mtd_to_nand(mtd);
277af429 756 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
2a5dbead 757 void __iomem *regs = host->regs_va;
6c009ab8 758 unsigned int bank = host->bank;
a612c2ae 759 uint32_t err_idx[8];
6c009ab8 760 uint32_t num_err, i;
753e0139 761 uint32_t ecc1, ecc2, ecc3, ecc4;
6c009ab8 762
a4742d51 763 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
519300cf
VK		 764
765 /* no bit flipping */
766 if (likely(num_err == 0))
767 return 0;
768
769 /* too many errors */
770 if (unlikely(num_err > 8)) {
771 /*
772 * This is a temporary erase check. A newly erased page read
773 * would result in an ecc error because the oob data is also
774 * erased to FF and the calculated ecc for an FF data is not
775 * FF..FF.
776 * This is a workaround to skip performing correction in case
777 * data is FF..FF
778 *
779 * Logic:
780 * For every page, each bit written as 0 is counted until these
781 * number of bits are greater than 8 (the maximum correction
782 * capability of FSMC for each 512 + 13 bytes)
783 */
784
785 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
786 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
787
788 if ((bits_ecc + bits_data) <= 8) {
789 if (bits_data)
790 memset(dat, 0xff, chip->ecc.size);
791 return bits_data;
792 }
793
794 return -EBADMSG;
795 }
796
6c009ab8
LW		 797 /*
798 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
799 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
800 *
801 * calc_ecc is a 104 bit information containing maximum of 8 error
802 * offset informations of 13 bits each. calc_ecc is copied into a
803 * uint64_t array and error offset indexes are populated in err_idx
804 * array
805 */
a4742d51
VK		 806 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
807 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
808 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
809 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
753e0139
AV		 810
811 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
812 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
813 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
814 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
815 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
816 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
817 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
818 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
6c009ab8
LW		 819
820 i = 0;
821 while (num_err--) {
822 change_bit(0, (unsigned long *)&err_idx[i]);
823 change_bit(1, (unsigned long *)&err_idx[i]);
824
b533f8d8 825 if (err_idx[i] < chip->ecc.size * 8) {
6c009ab8
LW		 826 change_bit(err_idx[i], (unsigned long *)dat);
827 i++;
828 }
829 }
830 return i;
831}
832
4774fb0a
VK		 833static bool filter(struct dma_chan *chan, void *slave)
834{
835 chan->private = slave;
836 return true;
837}
838
06f25510 839static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
a1b1e1d5
TP		 840 struct fsmc_nand_data *host,
841 struct nand_chip *nand)
eea62819 842{
a1b1e1d5 843 struct device_node *np = pdev->dev.of_node;
eea62819 844 u32 val;
62b57f4c 845 int ret;
eea62819 846
a1b1e1d5 847 nand->options = 0;
ee56874f 848
eea62819
SR		 849 if (!of_property_read_u32(np, "bank-width", &val)) {
850 if (val == 2) {
a1b1e1d5 851 nand->options |= NAND_BUSWIDTH_16;
eea62819
SR		 852 } else if (val != 1) {
853 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
854 return -EINVAL;
855 }
856 }
ee56874f 857
eea62819 858 if (of_get_property(np, "nand-skip-bbtscan", NULL))
a1b1e1d5 859 nand->options |= NAND_SKIP_BBTSCAN;
eea62819 860
a1b1e1d5
TP		 861 host->dev_timings = devm_kzalloc(&pdev->dev,
862 sizeof(*host->dev_timings), GFP_KERNEL);
863 if (!host->dev_timings)
64ddba4d 864 return -ENOMEM;
a1b1e1d5
TP		 865 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
866 sizeof(*host->dev_timings));
d9fb0795 867 if (ret)
a1b1e1d5 868 host->dev_timings = NULL;
64ddba4d
MYK		 869
870 /* Set default NAND bank to 0 */
a1b1e1d5 871 host->bank = 0;
64ddba4d
MYK		 872 if (!of_property_read_u32(np, "bank", &val)) {
873 if (val > 3) {
874 dev_err(&pdev->dev, "invalid bank %u\n", val);
875 return -EINVAL;
876 }
a1b1e1d5 877 host->bank = val;
64ddba4d 878 }
eea62819
SR		 879 return 0;
880}
eea62819 881
6c009ab8
LW		 882/*
883 * fsmc_nand_probe - Probe function
884 * @pdev: platform device structure
885 */
886static int __init fsmc_nand_probe(struct platform_device *pdev)
887{
6c009ab8
LW		 888 struct fsmc_nand_data *host;
889 struct mtd_info *mtd;
890 struct nand_chip *nand;
6c009ab8 891 struct resource *res;
4774fb0a 892 dma_cap_mask_t mask;
4ad916bc 893 int ret = 0;
593cd871
LW		 894 u32 pid;
895 int i;
6c009ab8 896
6c009ab8 897 /* Allocate memory for the device structure (and zero it) */
82b9dbe2 898 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
d9a21ae8 899 if (!host)
6c009ab8 900 return -ENOMEM;
6c009ab8 901
a1b1e1d5
TP		 902 nand = &host->nand;
903
904 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
905 if (ret)
906 return ret;
907
6c009ab8 908 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
b0de774c
TR		 909 host->data_va = devm_ioremap_resource(&pdev->dev, res);
910 if (IS_ERR(host->data_va))
911 return PTR_ERR(host->data_va);
cbf29b83 912
6d7b42a4 913 host->data_pa = (dma_addr_t)res->start;
6c009ab8 914
6d7b42a4 915 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
b0de774c
TR		 916 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(host->addr_va))
918 return PTR_ERR(host->addr_va);
6c009ab8 919
6d7b42a4 920 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
b0de774c
TR		 921 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
922 if (IS_ERR(host->cmd_va))
923 return PTR_ERR(host->cmd_va);
6c009ab8
LW		 924
925 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
b0de774c
TR		 926 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
927 if (IS_ERR(host->regs_va))
928 return PTR_ERR(host->regs_va);
6c009ab8 929
fb8ed2ca 930 host->clk = devm_clk_get(&pdev->dev, NULL);
6c009ab8
LW		 931 if (IS_ERR(host->clk)) {
932 dev_err(&pdev->dev, "failed to fetch block clock\n");
82b9dbe2 933 return PTR_ERR(host->clk);
6c009ab8
LW		 934 }
935
e25da1c0 936 ret = clk_prepare_enable(host->clk);
6c009ab8 937 if (ret)
fb8ed2ca 938 return ret;
6c009ab8 939
593cd871
LW		 940 /*
941 * This device ID is actually a common AMBA ID as used on the
942 * AMBA PrimeCell bus. However it is not a PrimeCell.
943 */
944 for (pid = 0, i = 0; i < 4; i++)
945 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
946 host->pid = pid;
947 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
948 "revision %02x, config %02x\n",
949 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
950 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
951
712c4add 952 host->dev = &pdev->dev;
4774fb0a
VK		 953
954 if (host->mode == USE_DMA_ACCESS)
955 init_completion(&host->dma_access_complete);
956
6c009ab8 957 /* Link all private pointers */
bdf3a555 958 mtd = nand_to_mtd(&host->nand);
d699ed25 959 nand_set_controller_data(nand, host);
a1b1e1d5 960 nand_set_flash_node(nand, pdev->dev.of_node);
6c009ab8 961
bdf3a555 962 mtd->dev.parent = &pdev->dev;
6c009ab8
LW		 963 nand->IO_ADDR_R = host->data_va;
964 nand->IO_ADDR_W = host->data_va;
965 nand->cmd_ctrl = fsmc_cmd_ctrl;
966 nand->chip_delay = 30;
967
e278fc71
SR		 968 /*
969 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
970 * can overwrite this value if the DT provides a different value.
971 */
6c009ab8
LW		 972 nand->ecc.mode = NAND_ECC_HW;
973 nand->ecc.hwctl = fsmc_enable_hwecc;
974 nand->ecc.size = 512;
467e6e7b 975 nand->badblockbits = 7;
6c009ab8 976
4774fb0a
VK		 977 switch (host->mode) {
978 case USE_DMA_ACCESS:
979 dma_cap_zero(mask);
980 dma_cap_set(DMA_MEMCPY, mask);
feb1e57e 981 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
4774fb0a
VK		 982 if (!host->read_dma_chan) {
983 dev_err(&pdev->dev, "Unable to get read dma channel\n");
984 goto err_req_read_chnl;
985 }
feb1e57e 986 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
4774fb0a
VK		 987 if (!host->write_dma_chan) {
988 dev_err(&pdev->dev, "Unable to get write dma channel\n");
989 goto err_req_write_chnl;
990 }
991 nand->read_buf = fsmc_read_buf_dma;
992 nand->write_buf = fsmc_write_buf_dma;
993 break;
994
995 default:
996 case USE_WORD_ACCESS:
604e7544
VK		 997 nand->read_buf = fsmc_read_buf;
998 nand->write_buf = fsmc_write_buf;
4774fb0a 999 break;
604e7544
VK		 1000 }
1001
d9fb0795
TP		 1002 if (host->dev_timings)
1003 fsmc_nand_setup(host, host->dev_timings);
1004 else
1005 nand->setup_data_interface = fsmc_setup_data_interface;
6c009ab8 1006
593cd871 1007 if (AMBA_REV_BITS(host->pid) >= 8) {
6c009ab8
LW		 1008 nand->ecc.read_page = fsmc_read_page_hwecc;
1009 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
753e0139 1010 nand->ecc.correct = fsmc_bch8_correct_data;
6c009ab8 1011 nand->ecc.bytes = 13;
6a918bad 1012 nand->ecc.strength = 8;
6c009ab8
LW		 1013 }
1014
1015 /*
25985edc 1016 * Scan to find existence of the device
6c009ab8 1017 */
ad5678ec
MY		 1018 ret = nand_scan_ident(mtd, 1, NULL);
1019 if (ret) {
6c009ab8 1020 dev_err(&pdev->dev, "No NAND Device found!\n");
82b9dbe2 1021 goto err_scan_ident;
6c009ab8
LW		 1022 }
1023
593cd871 1024 if (AMBA_REV_BITS(host->pid) >= 8) {
bdf3a555 1025 switch (mtd->oobsize) {
e29ee57b 1026 case 16:
e29ee57b 1027 case 64:
e29ee57b 1028 case 128:
0c78e93b 1029 case 224:
e29ee57b 1030 case 256:
e29ee57b
BY		 1031 break;
1032 default:
67b19a63
JH		 1033 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1034 mtd->oobsize);
6efadcf9
SR		 1035 ret = -EINVAL;
1036 goto err_probe;
6c009ab8 1037 }
22b46957
BB		 1038
1039 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
6c009ab8 1040 } else {
e278fc71
SR		 1041 switch (nand->ecc.mode) {
1042 case NAND_ECC_HW:
1043 dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1044 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1045 nand->ecc.correct = nand_correct_data;
1046 nand->ecc.bytes = 3;
1047 nand->ecc.strength = 1;
e29ee57b 1048 break;
e278fc71 1049
ef296dc9 1050 case NAND_ECC_SOFT:
ef296dc9
RM		 1051 if (nand->ecc.algo == NAND_ECC_BCH) {
1052 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1053 break;
1054 }
e278fc71 1055
838ff7b3
TP		 1056 case NAND_ECC_ON_DIE:
1057 break;
1058
e29ee57b 1059 default:
e278fc71 1060 dev_err(&pdev->dev, "Unsupported ECC mode!\n");
6efadcf9 1061 goto err_probe;
e29ee57b 1062 }
e278fc71
SR		 1063
1064 /*
1065 * Don't set layout for BCH4 SW ECC. This will be
1066 * generated later in nand_bch_init() later.
1067 */
e4225ae8 1068 if (nand->ecc.mode == NAND_ECC_HW) {
bdf3a555 1069 switch (mtd->oobsize) {
e278fc71 1070 case 16:
e278fc71 1071 case 64:
e278fc71 1072 case 128:
22b46957
BB		 1073 mtd_set_ooblayout(mtd,
1074 &fsmc_ecc1_ooblayout_ops);
e278fc71
SR		 1075 break;
1076 default:
1077 dev_warn(&pdev->dev,
1078 "No oob scheme defined for oobsize %d\n",
1079 mtd->oobsize);
1080 ret = -EINVAL;
1081 goto err_probe;
1082 }
1083 }
6c009ab8
LW		 1084 }
1085
1086 /* Second stage of scan to fill MTD data-structures */
ad5678ec
MY		 1087 ret = nand_scan_tail(mtd);
1088 if (ret)
6c009ab8 1089 goto err_probe;
6c009ab8 1090
bdf3a555 1091 mtd->name = "nand";
ede29a02 1092 ret = mtd_device_register(mtd, NULL, 0);
99335d00 1093 if (ret)
6c009ab8 1094 goto err_probe;
6c009ab8
LW		 1095
1096 platform_set_drvdata(pdev, host);
1097 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1098 return 0;
1099
1100err_probe:
82b9dbe2 1101err_scan_ident:
4774fb0a
VK		 1102 if (host->mode == USE_DMA_ACCESS)
1103 dma_release_channel(host->write_dma_chan);
1104err_req_write_chnl:
1105 if (host->mode == USE_DMA_ACCESS)
1106 dma_release_channel(host->read_dma_chan);
1107err_req_read_chnl:
e25da1c0 1108 clk_disable_unprepare(host->clk);
6c009ab8
LW		 1109 return ret;
1110}
1111
1112/*
1113 * Clean up routine
1114 */
1115static int fsmc_nand_remove(struct platform_device *pdev)
1116{
1117 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1118
6c009ab8 1119 if (host) {
bdf3a555 1120 nand_release(nand_to_mtd(&host->nand));
4774fb0a
VK		 1121
1122 if (host->mode == USE_DMA_ACCESS) {
1123 dma_release_channel(host->write_dma_chan);
1124 dma_release_channel(host->read_dma_chan);
1125 }
e25da1c0 1126 clk_disable_unprepare(host->clk);
6c009ab8 1127 }
82b9dbe2 1128
6c009ab8
LW		 1129 return 0;
1130}
1131
80ce4dde 1132#ifdef CONFIG_PM_SLEEP
6c009ab8
LW		 1133static int fsmc_nand_suspend(struct device *dev)
1134{
1135 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1136 if (host)
e25da1c0 1137 clk_disable_unprepare(host->clk);
6c009ab8
LW		 1138 return 0;
1139}
1140
1141static int fsmc_nand_resume(struct device *dev)
1142{
1143 struct fsmc_nand_data *host = dev_get_drvdata(dev);
f63acb75 1144 if (host) {
e25da1c0 1145 clk_prepare_enable(host->clk);
d9fb0795
TP		 1146 if (host->dev_timings)
1147 fsmc_nand_setup(host, host->dev_timings);
f63acb75 1148 }
6c009ab8
LW		 1149 return 0;
1150}
80ce4dde 1151#endif
6c009ab8 1152
f63acb75 1153static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
6c009ab8 1154
eea62819
SR		 1155static const struct of_device_id fsmc_nand_id_table[] = {
1156 { .compatible = "st,spear600-fsmc-nand" },
ba785205 1157 { .compatible = "stericsson,fsmc-nand" },
eea62819
SR		 1158 {}
1159};
1160MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
eea62819 1161
6c009ab8
LW		 1162static struct platform_driver fsmc_nand_driver = {
1163 .remove = fsmc_nand_remove,
1164 .driver = {
6c009ab8 1165 .name = "fsmc-nand",
33575b25 1166 .of_match_table = fsmc_nand_id_table,
6c009ab8 1167 .pm = &fsmc_nand_pm_ops,
6c009ab8
LW		 1168 },
1169};
1170
307d2a51 1171module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
6c009ab8
LW		 1172
1173MODULE_LICENSE("GPL");
1174MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1175MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
Linux 6.x block layer and io_uring tree(s)