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mtd: nand/fsmc: Use dev_err to report error scenario
[linux-2.6-block.git] / drivers / mtd / nand / fsmc_nand.c
CommitLineData
6c009ab8
LW		 1/*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/resource.h>
24#include <linux/sched.h>
25#include <linux/types.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/platform_device.h>
30#include <linux/mtd/partitions.h>
31#include <linux/io.h>
32#include <linux/slab.h>
33#include <linux/mtd/fsmc.h>
593cd871 34#include <linux/amba/bus.h>
6c009ab8
LW		 35#include <mtd/mtd-abi.h>
36
e29ee57b 37static struct nand_ecclayout fsmc_ecc1_128_layout = {
6c009ab8
LW		 38 .eccbytes = 24,
39 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
41 .oobfree = {
42 {.offset = 8, .length = 8},
43 {.offset = 24, .length = 8},
44 {.offset = 40, .length = 8},
45 {.offset = 56, .length = 8},
46 {.offset = 72, .length = 8},
47 {.offset = 88, .length = 8},
48 {.offset = 104, .length = 8},
49 {.offset = 120, .length = 8}
50 }
51};
52
e29ee57b
BY		 53static struct nand_ecclayout fsmc_ecc1_64_layout = {
54 .eccbytes = 12,
55 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
56 .oobfree = {
57 {.offset = 8, .length = 8},
58 {.offset = 24, .length = 8},
59 {.offset = 40, .length = 8},
60 {.offset = 56, .length = 8},
61 }
62};
63
64static struct nand_ecclayout fsmc_ecc1_16_layout = {
65 .eccbytes = 3,
66 .eccpos = {2, 3, 4},
67 .oobfree = {
68 {.offset = 8, .length = 8},
69 }
70};
71
72/*
73 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
74 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
75 * bytes are free for use.
76 */
77static struct nand_ecclayout fsmc_ecc4_256_layout = {
78 .eccbytes = 208,
79 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
80 9, 10, 11, 12, 13, 14,
81 18, 19, 20, 21, 22, 23, 24,
82 25, 26, 27, 28, 29, 30,
83 34, 35, 36, 37, 38, 39, 40,
84 41, 42, 43, 44, 45, 46,
85 50, 51, 52, 53, 54, 55, 56,
86 57, 58, 59, 60, 61, 62,
87 66, 67, 68, 69, 70, 71, 72,
88 73, 74, 75, 76, 77, 78,
89 82, 83, 84, 85, 86, 87, 88,
90 89, 90, 91, 92, 93, 94,
91 98, 99, 100, 101, 102, 103, 104,
92 105, 106, 107, 108, 109, 110,
93 114, 115, 116, 117, 118, 119, 120,
94 121, 122, 123, 124, 125, 126,
95 130, 131, 132, 133, 134, 135, 136,
96 137, 138, 139, 140, 141, 142,
97 146, 147, 148, 149, 150, 151, 152,
98 153, 154, 155, 156, 157, 158,
99 162, 163, 164, 165, 166, 167, 168,
100 169, 170, 171, 172, 173, 174,
101 178, 179, 180, 181, 182, 183, 184,
102 185, 186, 187, 188, 189, 190,
103 194, 195, 196, 197, 198, 199, 200,
104 201, 202, 203, 204, 205, 206,
105 210, 211, 212, 213, 214, 215, 216,
106 217, 218, 219, 220, 221, 222,
107 226, 227, 228, 229, 230, 231, 232,
108 233, 234, 235, 236, 237, 238,
109 242, 243, 244, 245, 246, 247, 248,
110 249, 250, 251, 252, 253, 254
111 },
112 .oobfree = {
113 {.offset = 15, .length = 3},
114 {.offset = 31, .length = 3},
115 {.offset = 47, .length = 3},
116 {.offset = 63, .length = 3},
117 {.offset = 79, .length = 3},
118 {.offset = 95, .length = 3},
119 {.offset = 111, .length = 3},
120 {.offset = 127, .length = 3},
121 {.offset = 143, .length = 3},
122 {.offset = 159, .length = 3},
123 {.offset = 175, .length = 3},
124 {.offset = 191, .length = 3},
125 {.offset = 207, .length = 3},
126 {.offset = 223, .length = 3},
127 {.offset = 239, .length = 3},
128 {.offset = 255, .length = 1}
129 }
130};
131
0c78e93b
AV		 132/*
133 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
134 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
135 * bytes are free for use.
136 */
137static struct nand_ecclayout fsmc_ecc4_224_layout = {
138 .eccbytes = 104,
139 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
140 9, 10, 11, 12, 13, 14,
141 18, 19, 20, 21, 22, 23, 24,
142 25, 26, 27, 28, 29, 30,
143 34, 35, 36, 37, 38, 39, 40,
144 41, 42, 43, 44, 45, 46,
145 50, 51, 52, 53, 54, 55, 56,
146 57, 58, 59, 60, 61, 62,
147 66, 67, 68, 69, 70, 71, 72,
148 73, 74, 75, 76, 77, 78,
149 82, 83, 84, 85, 86, 87, 88,
150 89, 90, 91, 92, 93, 94,
151 98, 99, 100, 101, 102, 103, 104,
152 105, 106, 107, 108, 109, 110,
153 114, 115, 116, 117, 118, 119, 120,
154 121, 122, 123, 124, 125, 126
155 },
156 .oobfree = {
157 {.offset = 15, .length = 3},
158 {.offset = 31, .length = 3},
159 {.offset = 47, .length = 3},
160 {.offset = 63, .length = 3},
161 {.offset = 79, .length = 3},
162 {.offset = 95, .length = 3},
163 {.offset = 111, .length = 3},
164 {.offset = 127, .length = 97}
165 }
166};
167
e29ee57b
BY		 168/*
169 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
170 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
171 * bytes are free for use.
172 */
173static struct nand_ecclayout fsmc_ecc4_128_layout = {
6c009ab8
LW		 174 .eccbytes = 104,
175 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
176 9, 10, 11, 12, 13, 14,
177 18, 19, 20, 21, 22, 23, 24,
178 25, 26, 27, 28, 29, 30,
179 34, 35, 36, 37, 38, 39, 40,
180 41, 42, 43, 44, 45, 46,
181 50, 51, 52, 53, 54, 55, 56,
182 57, 58, 59, 60, 61, 62,
183 66, 67, 68, 69, 70, 71, 72,
184 73, 74, 75, 76, 77, 78,
185 82, 83, 84, 85, 86, 87, 88,
186 89, 90, 91, 92, 93, 94,
187 98, 99, 100, 101, 102, 103, 104,
188 105, 106, 107, 108, 109, 110,
189 114, 115, 116, 117, 118, 119, 120,
190 121, 122, 123, 124, 125, 126
191 },
192 .oobfree = {
193 {.offset = 15, .length = 3},
194 {.offset = 31, .length = 3},
195 {.offset = 47, .length = 3},
196 {.offset = 63, .length = 3},
197 {.offset = 79, .length = 3},
198 {.offset = 95, .length = 3},
199 {.offset = 111, .length = 3},
200 {.offset = 127, .length = 1}
201 }
202};
203
e29ee57b
BY		 204/*
205 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
206 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
207 * bytes are free for use.
208 */
209static struct nand_ecclayout fsmc_ecc4_64_layout = {
210 .eccbytes = 52,
211 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
212 9, 10, 11, 12, 13, 14,
213 18, 19, 20, 21, 22, 23, 24,
214 25, 26, 27, 28, 29, 30,
215 34, 35, 36, 37, 38, 39, 40,
216 41, 42, 43, 44, 45, 46,
217 50, 51, 52, 53, 54, 55, 56,
218 57, 58, 59, 60, 61, 62,
219 },
220 .oobfree = {
221 {.offset = 15, .length = 3},
222 {.offset = 31, .length = 3},
223 {.offset = 47, .length = 3},
224 {.offset = 63, .length = 1},
225 }
226};
227
228/*
229 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
230 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
231 * byte is free for use.
232 */
233static struct nand_ecclayout fsmc_ecc4_16_layout = {
234 .eccbytes = 13,
235 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
236 9, 10, 11, 12, 13, 14
237 },
238 .oobfree = {
239 {.offset = 15, .length = 1},
240 }
241};
242
6c009ab8
LW		 243/*
244 * ECC placement definitions in oobfree type format.
245 * There are 13 bytes of ecc for every 512 byte block and it has to be read
246 * consecutively and immediately after the 512 byte data block for hardware to
247 * generate the error bit offsets in 512 byte data.
248 * Managing the ecc bytes in the following way makes it easier for software to
249 * read ecc bytes consecutive to data bytes. This way is similar to
250 * oobfree structure maintained already in generic nand driver
251 */
252static struct fsmc_eccplace fsmc_ecc4_lp_place = {
253 .eccplace = {
254 {.offset = 2, .length = 13},
255 {.offset = 18, .length = 13},
256 {.offset = 34, .length = 13},
257 {.offset = 50, .length = 13},
258 {.offset = 66, .length = 13},
259 {.offset = 82, .length = 13},
260 {.offset = 98, .length = 13},
261 {.offset = 114, .length = 13}
262 }
263};
264
6c009ab8
LW		 265static struct fsmc_eccplace fsmc_ecc4_sp_place = {
266 .eccplace = {
267 {.offset = 0, .length = 4},
268 {.offset = 6, .length = 9}
269 }
270};
271
6c009ab8 272/**
593cd871 273 * struct fsmc_nand_data - structure for FSMC NAND device state
6c009ab8 274 *
593cd871 275 * @pid: Part ID on the AMBA PrimeCell format
6c009ab8
LW		 276 * @mtd: MTD info for a NAND flash.
277 * @nand: Chip related info for a NAND flash.
71470324
VK		 278 * @partitions: Partition info for a NAND Flash.
279 * @nr_partitions: Total number of partition of a NAND flash.
6c009ab8
LW		 280 *
281 * @ecc_place: ECC placing locations in oobfree type format.
282 * @bank: Bank number for probed device.
283 * @clk: Clock structure for FSMC.
284 *
285 * @data_va: NAND port for Data.
286 * @cmd_va: NAND port for Command.
287 * @addr_va: NAND port for Address.
288 * @regs_va: FSMC regs base address.
289 */
290struct fsmc_nand_data {
593cd871 291 u32 pid;
6c009ab8
LW		 292 struct mtd_info mtd;
293 struct nand_chip nand;
71470324
VK		 294 struct mtd_partition *partitions;
295 unsigned int nr_partitions;
6c009ab8
LW		 296
297 struct fsmc_eccplace *ecc_place;
298 unsigned int bank;
712c4add 299 struct device *dev;
6c009ab8
LW		 300 struct clk *clk;
301
e2f6bce8
VK		 302 struct fsmc_nand_timings *dev_timings;
303
6c009ab8
LW		 304 void __iomem *data_va;
305 void __iomem *cmd_va;
306 void __iomem *addr_va;
307 void __iomem *regs_va;
308
309 void (*select_chip)(uint32_t bank, uint32_t busw);
310};
311
312/* Assert CS signal based on chipnr */
313static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
314{
315 struct nand_chip *chip = mtd->priv;
316 struct fsmc_nand_data *host;
317
318 host = container_of(mtd, struct fsmc_nand_data, mtd);
319
320 switch (chipnr) {
321 case -1:
322 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
323 break;
324 case 0:
325 case 1:
326 case 2:
327 case 3:
328 if (host->select_chip)
329 host->select_chip(chipnr,
330 chip->options & NAND_BUSWIDTH_16);
331 break;
332
333 default:
334 BUG();
335 }
336}
337
338/*
339 * fsmc_cmd_ctrl - For facilitaing Hardware access
340 * This routine allows hardware specific access to control-lines(ALE,CLE)
341 */
342static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
343{
344 struct nand_chip *this = mtd->priv;
345 struct fsmc_nand_data *host = container_of(mtd,
346 struct fsmc_nand_data, mtd);
347 struct fsmc_regs *regs = host->regs_va;
348 unsigned int bank = host->bank;
349
350 if (ctrl & NAND_CTRL_CHANGE) {
351 if (ctrl & NAND_CLE) {
352 this->IO_ADDR_R = (void __iomem *)host->cmd_va;
353 this->IO_ADDR_W = (void __iomem *)host->cmd_va;
354 } else if (ctrl & NAND_ALE) {
355 this->IO_ADDR_R = (void __iomem *)host->addr_va;
356 this->IO_ADDR_W = (void __iomem *)host->addr_va;
357 } else {
358 this->IO_ADDR_R = (void __iomem *)host->data_va;
359 this->IO_ADDR_W = (void __iomem *)host->data_va;
360 }
361
362 if (ctrl & NAND_NCE) {
363 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ENABLE,
364 &regs->bank_regs[bank].pc);
365 } else {
366 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ENABLE,
367 &regs->bank_regs[bank].pc);
368 }
369 }
370
371 mb();
372
373 if (cmd != NAND_CMD_NONE)
374 writeb(cmd, this->IO_ADDR_W);
375}
376
377/*
378 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
379 *
380 * This routine initializes timing parameters related to NAND memory access in
381 * FSMC registers
382 */
f63acb75 383static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
e2f6bce8 384 uint32_t busw, struct fsmc_nand_timings *timings)
6c009ab8
LW		 385{
386 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
e2f6bce8
VK		 387 uint32_t tclr, tar, thiz, thold, twait, tset;
388 struct fsmc_nand_timings *tims;
389 struct fsmc_nand_timings default_timings = {
390 .tclr = FSMC_TCLR_1,
391 .tar = FSMC_TAR_1,
392 .thiz = FSMC_THIZ_1,
393 .thold = FSMC_THOLD_4,
394 .twait = FSMC_TWAIT_6,
395 .tset = FSMC_TSET_0,
396 };
397
398 if (timings)
399 tims = timings;
400 else
401 tims = &default_timings;
402
403 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
404 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
405 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
406 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
407 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
408 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
6c009ab8
LW		 409
410 if (busw)
411 writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc);
412 else
413 writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc);
414
e2f6bce8 415 writel(readl(&regs->bank_regs[bank].pc) | tclr | tar,
6c009ab8 416 &regs->bank_regs[bank].pc);
e2f6bce8
VK		 417 writel(thiz | thold | twait | tset, &regs->bank_regs[bank].comm);
418 writel(thiz | thold | twait | tset, &regs->bank_regs[bank].attrib);
6c009ab8
LW		 419}
420
421/*
422 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
423 */
424static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
425{
426 struct fsmc_nand_data *host = container_of(mtd,
427 struct fsmc_nand_data, mtd);
428 struct fsmc_regs *regs = host->regs_va;
429 uint32_t bank = host->bank;
430
431 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
432 &regs->bank_regs[bank].pc);
433 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCEN,
434 &regs->bank_regs[bank].pc);
435 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ECCEN,
436 &regs->bank_regs[bank].pc);
437}
438
439/*
440 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
25985edc 441 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
6c009ab8
LW		 442 * max of 8-bits)
443 */
444static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
445 uint8_t *ecc)
446{
447 struct fsmc_nand_data *host = container_of(mtd,
448 struct fsmc_nand_data, mtd);
449 struct fsmc_regs *regs = host->regs_va;
450 uint32_t bank = host->bank;
451 uint32_t ecc_tmp;
452 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
453
454 do {
455 if (readl(&regs->bank_regs[bank].sts) & FSMC_CODE_RDY)
456 break;
457 else
458 cond_resched();
459 } while (!time_after_eq(jiffies, deadline));
460
712c4add
VK		 461 if (time_after_eq(jiffies, deadline)) {
462 dev_err(host->dev, "calculate ecc timed out\n");
463 return -ETIMEDOUT;
464 }
465
6c009ab8
LW		 466 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
467 ecc[0] = (uint8_t) (ecc_tmp >> 0);
468 ecc[1] = (uint8_t) (ecc_tmp >> 8);
469 ecc[2] = (uint8_t) (ecc_tmp >> 16);
470 ecc[3] = (uint8_t) (ecc_tmp >> 24);
471
472 ecc_tmp = readl(&regs->bank_regs[bank].ecc2);
473 ecc[4] = (uint8_t) (ecc_tmp >> 0);
474 ecc[5] = (uint8_t) (ecc_tmp >> 8);
475 ecc[6] = (uint8_t) (ecc_tmp >> 16);
476 ecc[7] = (uint8_t) (ecc_tmp >> 24);
477
478 ecc_tmp = readl(&regs->bank_regs[bank].ecc3);
479 ecc[8] = (uint8_t) (ecc_tmp >> 0);
480 ecc[9] = (uint8_t) (ecc_tmp >> 8);
481 ecc[10] = (uint8_t) (ecc_tmp >> 16);
482 ecc[11] = (uint8_t) (ecc_tmp >> 24);
483
484 ecc_tmp = readl(&regs->bank_regs[bank].sts);
485 ecc[12] = (uint8_t) (ecc_tmp >> 16);
486
487 return 0;
488}
489
490/*
491 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
25985edc 492 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
6c009ab8
LW		 493 * max of 1-bit)
494 */
495static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
496 uint8_t *ecc)
497{
498 struct fsmc_nand_data *host = container_of(mtd,
499 struct fsmc_nand_data, mtd);
500 struct fsmc_regs *regs = host->regs_va;
501 uint32_t bank = host->bank;
502 uint32_t ecc_tmp;
503
504 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
505 ecc[0] = (uint8_t) (ecc_tmp >> 0);
506 ecc[1] = (uint8_t) (ecc_tmp >> 8);
507 ecc[2] = (uint8_t) (ecc_tmp >> 16);
508
509 return 0;
510}
511
519300cf
VK		 512/* Count the number of 0's in buff upto a max of max_bits */
513static int count_written_bits(uint8_t *buff, int size, int max_bits)
514{
515 int k, written_bits = 0;
516
517 for (k = 0; k < size; k++) {
518 written_bits += hweight8(~buff[k]);
519 if (written_bits > max_bits)
520 break;
521 }
522
523 return written_bits;
524}
525
6c009ab8
LW		 526/*
527 * fsmc_read_page_hwecc
528 * @mtd: mtd info structure
529 * @chip: nand chip info structure
530 * @buf: buffer to store read data
531 * @page: page number to read
532 *
25985edc 533 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
6c009ab8
LW		 534 * performed in a strict sequence as follows:
535 * data(512 byte) -> ecc(13 byte)
25985edc 536 * After this read, fsmc hardware generates and reports error data bits(up to a
6c009ab8
LW		 537 * max of 8 bits)
538 */
539static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
540 uint8_t *buf, int page)
541{
542 struct fsmc_nand_data *host = container_of(mtd,
543 struct fsmc_nand_data, mtd);
544 struct fsmc_eccplace *ecc_place = host->ecc_place;
545 int i, j, s, stat, eccsize = chip->ecc.size;
546 int eccbytes = chip->ecc.bytes;
547 int eccsteps = chip->ecc.steps;
548 uint8_t *p = buf;
549 uint8_t *ecc_calc = chip->buffers->ecccalc;
550 uint8_t *ecc_code = chip->buffers->ecccode;
551 int off, len, group = 0;
552 /*
553 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
554 * end up reading 14 bytes (7 words) from oob. The local array is
555 * to maintain word alignment
556 */
557 uint16_t ecc_oob[7];
558 uint8_t *oob = (uint8_t *)&ecc_oob[0];
559
560 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
6c009ab8
LW		 561 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
562 chip->ecc.hwctl(mtd, NAND_ECC_READ);
563 chip->read_buf(mtd, p, eccsize);
564
565 for (j = 0; j < eccbytes;) {
566 off = ecc_place->eccplace[group].offset;
567 len = ecc_place->eccplace[group].length;
568 group++;
569
570 /*
4cbe1bf0
VK		 571 * length is intentionally kept a higher multiple of 2
572 * to read at least 13 bytes even in case of 16 bit NAND
573 * devices
574 */
aea686b4
VK		 575 if (chip->options & NAND_BUSWIDTH_16)
576 len = roundup(len, 2);
577
6c009ab8
LW		 578 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
579 chip->read_buf(mtd, oob + j, len);
580 j += len;
581 }
582
519300cf 583 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
6c009ab8
LW		 584 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
585
586 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
587 if (stat < 0)
588 mtd->ecc_stats.failed++;
589 else
590 mtd->ecc_stats.corrected += stat;
591 }
592
593 return 0;
594}
595
596/*
753e0139 597 * fsmc_bch8_correct_data
6c009ab8
LW		 598 * @mtd: mtd info structure
599 * @dat: buffer of read data
600 * @read_ecc: ecc read from device spare area
601 * @calc_ecc: ecc calculated from read data
602 *
603 * calc_ecc is a 104 bit information containing maximum of 8 error
604 * offset informations of 13 bits each in 512 bytes of read data.
605 */
753e0139 606static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
6c009ab8
LW		 607 uint8_t *read_ecc, uint8_t *calc_ecc)
608{
609 struct fsmc_nand_data *host = container_of(mtd,
610 struct fsmc_nand_data, mtd);
519300cf 611 struct nand_chip *chip = mtd->priv;
6c009ab8
LW		 612 struct fsmc_regs *regs = host->regs_va;
613 unsigned int bank = host->bank;
a612c2ae 614 uint32_t err_idx[8];
6c009ab8 615 uint32_t num_err, i;
753e0139 616 uint32_t ecc1, ecc2, ecc3, ecc4;
6c009ab8 617
519300cf
VK		 618 num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
619
620 /* no bit flipping */
621 if (likely(num_err == 0))
622 return 0;
623
624 /* too many errors */
625 if (unlikely(num_err > 8)) {
626 /*
627 * This is a temporary erase check. A newly erased page read
628 * would result in an ecc error because the oob data is also
629 * erased to FF and the calculated ecc for an FF data is not
630 * FF..FF.
631 * This is a workaround to skip performing correction in case
632 * data is FF..FF
633 *
634 * Logic:
635 * For every page, each bit written as 0 is counted until these
636 * number of bits are greater than 8 (the maximum correction
637 * capability of FSMC for each 512 + 13 bytes)
638 */
639
640 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
641 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
642
643 if ((bits_ecc + bits_data) <= 8) {
644 if (bits_data)
645 memset(dat, 0xff, chip->ecc.size);
646 return bits_data;
647 }
648
649 return -EBADMSG;
650 }
651
6c009ab8
LW		 652 /*
653 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
654 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
655 *
656 * calc_ecc is a 104 bit information containing maximum of 8 error
657 * offset informations of 13 bits each. calc_ecc is copied into a
658 * uint64_t array and error offset indexes are populated in err_idx
659 * array
660 */
753e0139
AV		 661 ecc1 = readl(&regs->bank_regs[bank].ecc1);
662 ecc2 = readl(&regs->bank_regs[bank].ecc2);
663 ecc3 = readl(&regs->bank_regs[bank].ecc3);
664 ecc4 = readl(&regs->bank_regs[bank].sts);
665
666 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
667 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
668 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
669 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
670 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
671 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
672 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
673 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
6c009ab8
LW		 674
675 i = 0;
676 while (num_err--) {
677 change_bit(0, (unsigned long *)&err_idx[i]);
678 change_bit(1, (unsigned long *)&err_idx[i]);
679
b533f8d8 680 if (err_idx[i] < chip->ecc.size * 8) {
6c009ab8
LW		 681 change_bit(err_idx[i], (unsigned long *)dat);
682 i++;
683 }
684 }
685 return i;
686}
687
688/*
689 * fsmc_nand_probe - Probe function
690 * @pdev: platform device structure
691 */
692static int __init fsmc_nand_probe(struct platform_device *pdev)
693{
694 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
695 struct fsmc_nand_data *host;
696 struct mtd_info *mtd;
697 struct nand_chip *nand;
698 struct fsmc_regs *regs;
699 struct resource *res;
4ad916bc 700 int ret = 0;
593cd871
LW		 701 u32 pid;
702 int i;
6c009ab8
LW		 703
704 if (!pdata) {
705 dev_err(&pdev->dev, "platform data is NULL\n");
706 return -EINVAL;
707 }
708
709 /* Allocate memory for the device structure (and zero it) */
82b9dbe2 710 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
6c009ab8
LW		 711 if (!host) {
712 dev_err(&pdev->dev, "failed to allocate device structure\n");
713 return -ENOMEM;
714 }
715
716 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
82b9dbe2
VK		 717 if (!res)
718 return -EINVAL;
6c009ab8 719
82b9dbe2
VK		 720 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
721 pdev->name)) {
722 dev_err(&pdev->dev, "Failed to get memory data resourse\n");
723 return -ENOENT;
6c009ab8
LW		 724 }
725
82b9dbe2
VK		 726 host->data_va = devm_ioremap(&pdev->dev, res->start,
727 resource_size(res));
6c009ab8 728 if (!host->data_va) {
82b9dbe2
VK		 729 dev_err(&pdev->dev, "data ioremap failed\n");
730 return -ENOMEM;
6c009ab8
LW		 731 }
732
82b9dbe2
VK		 733 if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off,
734 resource_size(res), pdev->name)) {
735 dev_err(&pdev->dev, "Failed to get memory ale resourse\n");
736 return -ENOENT;
6c009ab8
LW		 737 }
738
82b9dbe2 739 host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off,
b2acc92e 740 resource_size(res));
6c009ab8 741 if (!host->addr_va) {
82b9dbe2
VK		 742 dev_err(&pdev->dev, "ale ioremap failed\n");
743 return -ENOMEM;
6c009ab8
LW		 744 }
745
82b9dbe2
VK		 746 if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off,
747 resource_size(res), pdev->name)) {
748 dev_err(&pdev->dev, "Failed to get memory cle resourse\n");
749 return -ENOENT;
6c009ab8
LW		 750 }
751
82b9dbe2
VK		 752 host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off,
753 resource_size(res));
6c009ab8 754 if (!host->cmd_va) {
82b9dbe2
VK		 755 dev_err(&pdev->dev, "ale ioremap failed\n");
756 return -ENOMEM;
6c009ab8
LW		 757 }
758
759 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
82b9dbe2
VK		 760 if (!res)
761 return -EINVAL;
6c009ab8 762
82b9dbe2
VK		 763 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
764 pdev->name)) {
765 dev_err(&pdev->dev, "Failed to get memory regs resourse\n");
766 return -ENOENT;
6c009ab8
LW		 767 }
768
82b9dbe2
VK		 769 host->regs_va = devm_ioremap(&pdev->dev, res->start,
770 resource_size(res));
6c009ab8 771 if (!host->regs_va) {
82b9dbe2
VK		 772 dev_err(&pdev->dev, "regs ioremap failed\n");
773 return -ENOMEM;
6c009ab8
LW		 774 }
775
776 host->clk = clk_get(&pdev->dev, NULL);
777 if (IS_ERR(host->clk)) {
778 dev_err(&pdev->dev, "failed to fetch block clock\n");
82b9dbe2 779 return PTR_ERR(host->clk);
6c009ab8
LW		 780 }
781
782 ret = clk_enable(host->clk);
783 if (ret)
82b9dbe2 784 goto err_clk_enable;
6c009ab8 785
593cd871
LW		 786 /*
787 * This device ID is actually a common AMBA ID as used on the
788 * AMBA PrimeCell bus. However it is not a PrimeCell.
789 */
790 for (pid = 0, i = 0; i < 4; i++)
791 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
792 host->pid = pid;
793 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
794 "revision %02x, config %02x\n",
795 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
796 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
797
6c009ab8
LW		 798 host->bank = pdata->bank;
799 host->select_chip = pdata->select_bank;
71470324
VK		 800 host->partitions = pdata->partitions;
801 host->nr_partitions = pdata->nr_partitions;
712c4add 802 host->dev = &pdev->dev;
e2f6bce8 803 host->dev_timings = pdata->nand_timings;
6c009ab8
LW		 804 regs = host->regs_va;
805
806 /* Link all private pointers */
807 mtd = &host->mtd;
808 nand = &host->nand;
809 mtd->priv = nand;
810 nand->priv = host;
811
812 host->mtd.owner = THIS_MODULE;
813 nand->IO_ADDR_R = host->data_va;
814 nand->IO_ADDR_W = host->data_va;
815 nand->cmd_ctrl = fsmc_cmd_ctrl;
816 nand->chip_delay = 30;
817
818 nand->ecc.mode = NAND_ECC_HW;
819 nand->ecc.hwctl = fsmc_enable_hwecc;
820 nand->ecc.size = 512;
821 nand->options = pdata->options;
822 nand->select_chip = fsmc_select_chip;
467e6e7b 823 nand->badblockbits = 7;
6c009ab8
LW		 824
825 if (pdata->width == FSMC_NAND_BW16)
826 nand->options |= NAND_BUSWIDTH_16;
827
e2f6bce8
VK		 828 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
829 host->dev_timings);
6c009ab8 830
593cd871 831 if (AMBA_REV_BITS(host->pid) >= 8) {
6c009ab8
LW		 832 nand->ecc.read_page = fsmc_read_page_hwecc;
833 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
753e0139 834 nand->ecc.correct = fsmc_bch8_correct_data;
6c009ab8 835 nand->ecc.bytes = 13;
6a918bad 836 nand->ecc.strength = 8;
6c009ab8
LW		 837 } else {
838 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
839 nand->ecc.correct = nand_correct_data;
840 nand->ecc.bytes = 3;
6a918bad 841 nand->ecc.strength = 1;
6c009ab8
LW		 842 }
843
844 /*
25985edc 845 * Scan to find existence of the device
6c009ab8
LW		 846 */
847 if (nand_scan_ident(&host->mtd, 1, NULL)) {
848 ret = -ENXIO;
849 dev_err(&pdev->dev, "No NAND Device found!\n");
82b9dbe2 850 goto err_scan_ident;
6c009ab8
LW		 851 }
852
593cd871 853 if (AMBA_REV_BITS(host->pid) >= 8) {
e29ee57b
BY		 854 switch (host->mtd.oobsize) {
855 case 16:
856 nand->ecc.layout = &fsmc_ecc4_16_layout;
6c009ab8 857 host->ecc_place = &fsmc_ecc4_sp_place;
e29ee57b
BY		 858 break;
859 case 64:
860 nand->ecc.layout = &fsmc_ecc4_64_layout;
861 host->ecc_place = &fsmc_ecc4_lp_place;
862 break;
863 case 128:
864 nand->ecc.layout = &fsmc_ecc4_128_layout;
865 host->ecc_place = &fsmc_ecc4_lp_place;
866 break;
0c78e93b
AV		 867 case 224:
868 nand->ecc.layout = &fsmc_ecc4_224_layout;
869 host->ecc_place = &fsmc_ecc4_lp_place;
870 break;
e29ee57b
BY		 871 case 256:
872 nand->ecc.layout = &fsmc_ecc4_256_layout;
6c009ab8 873 host->ecc_place = &fsmc_ecc4_lp_place;
e29ee57b
BY		 874 break;
875 default:
876 printk(KERN_WARNING "No oob scheme defined for "
877 "oobsize %d\n", mtd->oobsize);
878 BUG();
6c009ab8
LW		 879 }
880 } else {
e29ee57b
BY		 881 switch (host->mtd.oobsize) {
882 case 16:
883 nand->ecc.layout = &fsmc_ecc1_16_layout;
884 break;
885 case 64:
886 nand->ecc.layout = &fsmc_ecc1_64_layout;
887 break;
888 case 128:
889 nand->ecc.layout = &fsmc_ecc1_128_layout;
890 break;
891 default:
892 printk(KERN_WARNING "No oob scheme defined for "
893 "oobsize %d\n", mtd->oobsize);
894 BUG();
895 }
6c009ab8
LW		 896 }
897
898 /* Second stage of scan to fill MTD data-structures */
899 if (nand_scan_tail(&host->mtd)) {
900 ret = -ENXIO;
901 goto err_probe;
902 }
903
904 /*
905 * The partition information can is accessed by (in the same precedence)
906 *
907 * command line through Bootloader,
908 * platform data,
909 * default partition information present in driver.
910 */
6c009ab8 911 /*
8d3f8bb8 912 * Check for partition info passed
6c009ab8
LW		 913 */
914 host->mtd.name = "nand";
42d7fbe2 915 ret = mtd_device_parse_register(&host->mtd, NULL, NULL,
71470324 916 host->partitions, host->nr_partitions);
99335d00 917 if (ret)
6c009ab8 918 goto err_probe;
6c009ab8
LW		 919
920 platform_set_drvdata(pdev, host);
921 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
922 return 0;
923
924err_probe:
82b9dbe2 925err_scan_ident:
6c009ab8 926 clk_disable(host->clk);
82b9dbe2
VK		 927err_clk_enable:
928 clk_put(host->clk);
6c009ab8
LW		 929 return ret;
930}
931
932/*
933 * Clean up routine
934 */
935static int fsmc_nand_remove(struct platform_device *pdev)
936{
937 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
938
939 platform_set_drvdata(pdev, NULL);
940
941 if (host) {
82e023ab 942 nand_release(&host->mtd);
6c009ab8
LW		 943 clk_disable(host->clk);
944 clk_put(host->clk);
6c009ab8 945 }
82b9dbe2 946
6c009ab8
LW		 947 return 0;
948}
949
950#ifdef CONFIG_PM
951static int fsmc_nand_suspend(struct device *dev)
952{
953 struct fsmc_nand_data *host = dev_get_drvdata(dev);
954 if (host)
955 clk_disable(host->clk);
956 return 0;
957}
958
959static int fsmc_nand_resume(struct device *dev)
960{
961 struct fsmc_nand_data *host = dev_get_drvdata(dev);
f63acb75 962 if (host) {
6c009ab8 963 clk_enable(host->clk);
f63acb75 964 fsmc_nand_setup(host->regs_va, host->bank,
e2f6bce8
VK		 965 host->nand.options & NAND_BUSWIDTH_16,
966 host->dev_timings);
f63acb75 967 }
6c009ab8
LW		 968 return 0;
969}
970
f63acb75 971static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
6c009ab8
LW		 972#endif
973
974static struct platform_driver fsmc_nand_driver = {
975 .remove = fsmc_nand_remove,
976 .driver = {
977 .owner = THIS_MODULE,
978 .name = "fsmc-nand",
979#ifdef CONFIG_PM
980 .pm = &fsmc_nand_pm_ops,
981#endif
982 },
983};
984
985static int __init fsmc_nand_init(void)
986{
987 return platform_driver_probe(&fsmc_nand_driver,
988 fsmc_nand_probe);
989}
990module_init(fsmc_nand_init);
991
992static void __exit fsmc_nand_exit(void)
993{
994 platform_driver_unregister(&fsmc_nand_driver);
995}
996module_exit(fsmc_nand_exit);
997
998MODULE_LICENSE("GPL");
999MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1000MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
Linux 6.x block layer and io_uring tree(s)