Commit | Line | Data |
---|---|---|
6c009ab8 LW |
1 | /* |
2 | * drivers/mtd/nand/fsmc_nand.c | |
3 | * | |
4 | * ST Microelectronics | |
5 | * Flexible Static Memory Controller (FSMC) | |
6 | * Driver for NAND portions | |
7 | * | |
8 | * Copyright © 2010 ST Microelectronics | |
9 | * Vipin Kumar <vipin.kumar@st.com> | |
10 | * Ashish Priyadarshi | |
11 | * | |
12 | * Based on drivers/mtd/nand/nomadik_nand.c | |
13 | * | |
14 | * This file is licensed under the terms of the GNU General Public | |
15 | * License version 2. This program is licensed "as is" without any | |
16 | * warranty of any kind, whether express or implied. | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
4774fb0a VK |
20 | #include <linux/completion.h> |
21 | #include <linux/dmaengine.h> | |
22 | #include <linux/dma-direction.h> | |
23 | #include <linux/dma-mapping.h> | |
6c009ab8 LW |
24 | #include <linux/err.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/resource.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/mtd/mtd.h> | |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/nand_ecc.h> | |
33 | #include <linux/platform_device.h> | |
eea62819 | 34 | #include <linux/of.h> |
6c009ab8 LW |
35 | #include <linux/mtd/partitions.h> |
36 | #include <linux/io.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/mtd/fsmc.h> | |
593cd871 | 39 | #include <linux/amba/bus.h> |
6c009ab8 LW |
40 | #include <mtd/mtd-abi.h> |
41 | ||
e29ee57b | 42 | static struct nand_ecclayout fsmc_ecc1_128_layout = { |
6c009ab8 LW |
43 | .eccbytes = 24, |
44 | .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, | |
45 | 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, | |
46 | .oobfree = { | |
47 | {.offset = 8, .length = 8}, | |
48 | {.offset = 24, .length = 8}, | |
49 | {.offset = 40, .length = 8}, | |
50 | {.offset = 56, .length = 8}, | |
51 | {.offset = 72, .length = 8}, | |
52 | {.offset = 88, .length = 8}, | |
53 | {.offset = 104, .length = 8}, | |
54 | {.offset = 120, .length = 8} | |
55 | } | |
56 | }; | |
57 | ||
e29ee57b BY |
58 | static struct nand_ecclayout fsmc_ecc1_64_layout = { |
59 | .eccbytes = 12, | |
60 | .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52}, | |
61 | .oobfree = { | |
62 | {.offset = 8, .length = 8}, | |
63 | {.offset = 24, .length = 8}, | |
64 | {.offset = 40, .length = 8}, | |
65 | {.offset = 56, .length = 8}, | |
66 | } | |
67 | }; | |
68 | ||
69 | static struct nand_ecclayout fsmc_ecc1_16_layout = { | |
70 | .eccbytes = 3, | |
71 | .eccpos = {2, 3, 4}, | |
72 | .oobfree = { | |
73 | {.offset = 8, .length = 8}, | |
74 | } | |
75 | }; | |
76 | ||
77 | /* | |
78 | * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes | |
79 | * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46 | |
80 | * bytes are free for use. | |
81 | */ | |
82 | static struct nand_ecclayout fsmc_ecc4_256_layout = { | |
83 | .eccbytes = 208, | |
84 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
85 | 9, 10, 11, 12, 13, 14, | |
86 | 18, 19, 20, 21, 22, 23, 24, | |
87 | 25, 26, 27, 28, 29, 30, | |
88 | 34, 35, 36, 37, 38, 39, 40, | |
89 | 41, 42, 43, 44, 45, 46, | |
90 | 50, 51, 52, 53, 54, 55, 56, | |
91 | 57, 58, 59, 60, 61, 62, | |
92 | 66, 67, 68, 69, 70, 71, 72, | |
93 | 73, 74, 75, 76, 77, 78, | |
94 | 82, 83, 84, 85, 86, 87, 88, | |
95 | 89, 90, 91, 92, 93, 94, | |
96 | 98, 99, 100, 101, 102, 103, 104, | |
97 | 105, 106, 107, 108, 109, 110, | |
98 | 114, 115, 116, 117, 118, 119, 120, | |
99 | 121, 122, 123, 124, 125, 126, | |
100 | 130, 131, 132, 133, 134, 135, 136, | |
101 | 137, 138, 139, 140, 141, 142, | |
102 | 146, 147, 148, 149, 150, 151, 152, | |
103 | 153, 154, 155, 156, 157, 158, | |
104 | 162, 163, 164, 165, 166, 167, 168, | |
105 | 169, 170, 171, 172, 173, 174, | |
106 | 178, 179, 180, 181, 182, 183, 184, | |
107 | 185, 186, 187, 188, 189, 190, | |
108 | 194, 195, 196, 197, 198, 199, 200, | |
109 | 201, 202, 203, 204, 205, 206, | |
110 | 210, 211, 212, 213, 214, 215, 216, | |
111 | 217, 218, 219, 220, 221, 222, | |
112 | 226, 227, 228, 229, 230, 231, 232, | |
113 | 233, 234, 235, 236, 237, 238, | |
114 | 242, 243, 244, 245, 246, 247, 248, | |
115 | 249, 250, 251, 252, 253, 254 | |
116 | }, | |
117 | .oobfree = { | |
118 | {.offset = 15, .length = 3}, | |
119 | {.offset = 31, .length = 3}, | |
120 | {.offset = 47, .length = 3}, | |
121 | {.offset = 63, .length = 3}, | |
122 | {.offset = 79, .length = 3}, | |
123 | {.offset = 95, .length = 3}, | |
124 | {.offset = 111, .length = 3}, | |
125 | {.offset = 127, .length = 3}, | |
126 | {.offset = 143, .length = 3}, | |
127 | {.offset = 159, .length = 3}, | |
128 | {.offset = 175, .length = 3}, | |
129 | {.offset = 191, .length = 3}, | |
130 | {.offset = 207, .length = 3}, | |
131 | {.offset = 223, .length = 3}, | |
132 | {.offset = 239, .length = 3}, | |
133 | {.offset = 255, .length = 1} | |
134 | } | |
135 | }; | |
136 | ||
0c78e93b AV |
137 | /* |
138 | * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes | |
139 | * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 | |
140 | * bytes are free for use. | |
141 | */ | |
142 | static struct nand_ecclayout fsmc_ecc4_224_layout = { | |
143 | .eccbytes = 104, | |
144 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
145 | 9, 10, 11, 12, 13, 14, | |
146 | 18, 19, 20, 21, 22, 23, 24, | |
147 | 25, 26, 27, 28, 29, 30, | |
148 | 34, 35, 36, 37, 38, 39, 40, | |
149 | 41, 42, 43, 44, 45, 46, | |
150 | 50, 51, 52, 53, 54, 55, 56, | |
151 | 57, 58, 59, 60, 61, 62, | |
152 | 66, 67, 68, 69, 70, 71, 72, | |
153 | 73, 74, 75, 76, 77, 78, | |
154 | 82, 83, 84, 85, 86, 87, 88, | |
155 | 89, 90, 91, 92, 93, 94, | |
156 | 98, 99, 100, 101, 102, 103, 104, | |
157 | 105, 106, 107, 108, 109, 110, | |
158 | 114, 115, 116, 117, 118, 119, 120, | |
159 | 121, 122, 123, 124, 125, 126 | |
160 | }, | |
161 | .oobfree = { | |
162 | {.offset = 15, .length = 3}, | |
163 | {.offset = 31, .length = 3}, | |
164 | {.offset = 47, .length = 3}, | |
165 | {.offset = 63, .length = 3}, | |
166 | {.offset = 79, .length = 3}, | |
167 | {.offset = 95, .length = 3}, | |
168 | {.offset = 111, .length = 3}, | |
169 | {.offset = 127, .length = 97} | |
170 | } | |
171 | }; | |
172 | ||
e29ee57b BY |
173 | /* |
174 | * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes | |
175 | * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22 | |
176 | * bytes are free for use. | |
177 | */ | |
178 | static struct nand_ecclayout fsmc_ecc4_128_layout = { | |
6c009ab8 LW |
179 | .eccbytes = 104, |
180 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
181 | 9, 10, 11, 12, 13, 14, | |
182 | 18, 19, 20, 21, 22, 23, 24, | |
183 | 25, 26, 27, 28, 29, 30, | |
184 | 34, 35, 36, 37, 38, 39, 40, | |
185 | 41, 42, 43, 44, 45, 46, | |
186 | 50, 51, 52, 53, 54, 55, 56, | |
187 | 57, 58, 59, 60, 61, 62, | |
188 | 66, 67, 68, 69, 70, 71, 72, | |
189 | 73, 74, 75, 76, 77, 78, | |
190 | 82, 83, 84, 85, 86, 87, 88, | |
191 | 89, 90, 91, 92, 93, 94, | |
192 | 98, 99, 100, 101, 102, 103, 104, | |
193 | 105, 106, 107, 108, 109, 110, | |
194 | 114, 115, 116, 117, 118, 119, 120, | |
195 | 121, 122, 123, 124, 125, 126 | |
196 | }, | |
197 | .oobfree = { | |
198 | {.offset = 15, .length = 3}, | |
199 | {.offset = 31, .length = 3}, | |
200 | {.offset = 47, .length = 3}, | |
201 | {.offset = 63, .length = 3}, | |
202 | {.offset = 79, .length = 3}, | |
203 | {.offset = 95, .length = 3}, | |
204 | {.offset = 111, .length = 3}, | |
205 | {.offset = 127, .length = 1} | |
206 | } | |
207 | }; | |
208 | ||
e29ee57b BY |
209 | /* |
210 | * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of | |
211 | * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10 | |
212 | * bytes are free for use. | |
213 | */ | |
214 | static struct nand_ecclayout fsmc_ecc4_64_layout = { | |
215 | .eccbytes = 52, | |
216 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
217 | 9, 10, 11, 12, 13, 14, | |
218 | 18, 19, 20, 21, 22, 23, 24, | |
219 | 25, 26, 27, 28, 29, 30, | |
220 | 34, 35, 36, 37, 38, 39, 40, | |
221 | 41, 42, 43, 44, 45, 46, | |
222 | 50, 51, 52, 53, 54, 55, 56, | |
223 | 57, 58, 59, 60, 61, 62, | |
224 | }, | |
225 | .oobfree = { | |
226 | {.offset = 15, .length = 3}, | |
227 | {.offset = 31, .length = 3}, | |
228 | {.offset = 47, .length = 3}, | |
229 | {.offset = 63, .length = 1}, | |
230 | } | |
231 | }; | |
232 | ||
233 | /* | |
234 | * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of | |
235 | * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One | |
236 | * byte is free for use. | |
237 | */ | |
238 | static struct nand_ecclayout fsmc_ecc4_16_layout = { | |
239 | .eccbytes = 13, | |
240 | .eccpos = { 0, 1, 2, 3, 6, 7, 8, | |
241 | 9, 10, 11, 12, 13, 14 | |
242 | }, | |
243 | .oobfree = { | |
244 | {.offset = 15, .length = 1}, | |
245 | } | |
246 | }; | |
247 | ||
6c009ab8 LW |
248 | /* |
249 | * ECC placement definitions in oobfree type format. | |
250 | * There are 13 bytes of ecc for every 512 byte block and it has to be read | |
251 | * consecutively and immediately after the 512 byte data block for hardware to | |
252 | * generate the error bit offsets in 512 byte data. | |
253 | * Managing the ecc bytes in the following way makes it easier for software to | |
254 | * read ecc bytes consecutive to data bytes. This way is similar to | |
255 | * oobfree structure maintained already in generic nand driver | |
256 | */ | |
257 | static struct fsmc_eccplace fsmc_ecc4_lp_place = { | |
258 | .eccplace = { | |
259 | {.offset = 2, .length = 13}, | |
260 | {.offset = 18, .length = 13}, | |
261 | {.offset = 34, .length = 13}, | |
262 | {.offset = 50, .length = 13}, | |
263 | {.offset = 66, .length = 13}, | |
264 | {.offset = 82, .length = 13}, | |
265 | {.offset = 98, .length = 13}, | |
266 | {.offset = 114, .length = 13} | |
267 | } | |
268 | }; | |
269 | ||
6c009ab8 LW |
270 | static struct fsmc_eccplace fsmc_ecc4_sp_place = { |
271 | .eccplace = { | |
272 | {.offset = 0, .length = 4}, | |
273 | {.offset = 6, .length = 9} | |
274 | } | |
275 | }; | |
276 | ||
6c009ab8 | 277 | /** |
593cd871 | 278 | * struct fsmc_nand_data - structure for FSMC NAND device state |
6c009ab8 | 279 | * |
593cd871 | 280 | * @pid: Part ID on the AMBA PrimeCell format |
6c009ab8 LW |
281 | * @mtd: MTD info for a NAND flash. |
282 | * @nand: Chip related info for a NAND flash. | |
71470324 VK |
283 | * @partitions: Partition info for a NAND Flash. |
284 | * @nr_partitions: Total number of partition of a NAND flash. | |
6c009ab8 LW |
285 | * |
286 | * @ecc_place: ECC placing locations in oobfree type format. | |
287 | * @bank: Bank number for probed device. | |
288 | * @clk: Clock structure for FSMC. | |
289 | * | |
4774fb0a VK |
290 | * @read_dma_chan: DMA channel for read access |
291 | * @write_dma_chan: DMA channel for write access to NAND | |
292 | * @dma_access_complete: Completion structure | |
293 | * | |
294 | * @data_pa: NAND Physical port for Data. | |
6c009ab8 LW |
295 | * @data_va: NAND port for Data. |
296 | * @cmd_va: NAND port for Command. | |
297 | * @addr_va: NAND port for Address. | |
298 | * @regs_va: FSMC regs base address. | |
299 | */ | |
300 | struct fsmc_nand_data { | |
593cd871 | 301 | u32 pid; |
6c009ab8 LW |
302 | struct mtd_info mtd; |
303 | struct nand_chip nand; | |
71470324 VK |
304 | struct mtd_partition *partitions; |
305 | unsigned int nr_partitions; | |
6c009ab8 LW |
306 | |
307 | struct fsmc_eccplace *ecc_place; | |
308 | unsigned int bank; | |
712c4add | 309 | struct device *dev; |
4774fb0a | 310 | enum access_mode mode; |
6c009ab8 LW |
311 | struct clk *clk; |
312 | ||
4774fb0a VK |
313 | /* DMA related objects */ |
314 | struct dma_chan *read_dma_chan; | |
315 | struct dma_chan *write_dma_chan; | |
316 | struct completion dma_access_complete; | |
317 | ||
e2f6bce8 VK |
318 | struct fsmc_nand_timings *dev_timings; |
319 | ||
4774fb0a | 320 | dma_addr_t data_pa; |
6c009ab8 LW |
321 | void __iomem *data_va; |
322 | void __iomem *cmd_va; | |
323 | void __iomem *addr_va; | |
324 | void __iomem *regs_va; | |
325 | ||
326 | void (*select_chip)(uint32_t bank, uint32_t busw); | |
327 | }; | |
328 | ||
277af429 BB |
329 | static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd) |
330 | { | |
331 | return container_of(mtd, struct fsmc_nand_data, mtd); | |
332 | } | |
333 | ||
6c009ab8 LW |
334 | /* Assert CS signal based on chipnr */ |
335 | static void fsmc_select_chip(struct mtd_info *mtd, int chipnr) | |
336 | { | |
4bd4ebcc | 337 | struct nand_chip *chip = mtd_to_nand(mtd); |
6c009ab8 LW |
338 | struct fsmc_nand_data *host; |
339 | ||
277af429 | 340 | host = mtd_to_fsmc(mtd); |
6c009ab8 LW |
341 | |
342 | switch (chipnr) { | |
343 | case -1: | |
344 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); | |
345 | break; | |
346 | case 0: | |
347 | case 1: | |
348 | case 2: | |
349 | case 3: | |
350 | if (host->select_chip) | |
351 | host->select_chip(chipnr, | |
352 | chip->options & NAND_BUSWIDTH_16); | |
353 | break; | |
354 | ||
355 | default: | |
6efadcf9 | 356 | dev_err(host->dev, "unsupported chip-select %d\n", chipnr); |
6c009ab8 LW |
357 | } |
358 | } | |
359 | ||
360 | /* | |
361 | * fsmc_cmd_ctrl - For facilitaing Hardware access | |
362 | * This routine allows hardware specific access to control-lines(ALE,CLE) | |
363 | */ | |
364 | static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
365 | { | |
4bd4ebcc | 366 | struct nand_chip *this = mtd_to_nand(mtd); |
277af429 | 367 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
605add7d | 368 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
369 | unsigned int bank = host->bank; |
370 | ||
371 | if (ctrl & NAND_CTRL_CHANGE) { | |
2a5dbead VK |
372 | u32 pc; |
373 | ||
6c009ab8 | 374 | if (ctrl & NAND_CLE) { |
2a5dbead VK |
375 | this->IO_ADDR_R = host->cmd_va; |
376 | this->IO_ADDR_W = host->cmd_va; | |
6c009ab8 | 377 | } else if (ctrl & NAND_ALE) { |
2a5dbead VK |
378 | this->IO_ADDR_R = host->addr_va; |
379 | this->IO_ADDR_W = host->addr_va; | |
6c009ab8 | 380 | } else { |
2a5dbead VK |
381 | this->IO_ADDR_R = host->data_va; |
382 | this->IO_ADDR_W = host->data_va; | |
6c009ab8 LW |
383 | } |
384 | ||
2a5dbead VK |
385 | pc = readl(FSMC_NAND_REG(regs, bank, PC)); |
386 | if (ctrl & NAND_NCE) | |
387 | pc |= FSMC_ENABLE; | |
388 | else | |
389 | pc &= ~FSMC_ENABLE; | |
a4742d51 | 390 | writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC)); |
6c009ab8 LW |
391 | } |
392 | ||
393 | mb(); | |
394 | ||
395 | if (cmd != NAND_CMD_NONE) | |
a4742d51 | 396 | writeb_relaxed(cmd, this->IO_ADDR_W); |
6c009ab8 LW |
397 | } |
398 | ||
399 | /* | |
400 | * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine | |
401 | * | |
402 | * This routine initializes timing parameters related to NAND memory access in | |
403 | * FSMC registers | |
404 | */ | |
2a5dbead | 405 | static void fsmc_nand_setup(void __iomem *regs, uint32_t bank, |
e2f6bce8 | 406 | uint32_t busw, struct fsmc_nand_timings *timings) |
6c009ab8 LW |
407 | { |
408 | uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; | |
e2f6bce8 VK |
409 | uint32_t tclr, tar, thiz, thold, twait, tset; |
410 | struct fsmc_nand_timings *tims; | |
411 | struct fsmc_nand_timings default_timings = { | |
412 | .tclr = FSMC_TCLR_1, | |
413 | .tar = FSMC_TAR_1, | |
414 | .thiz = FSMC_THIZ_1, | |
415 | .thold = FSMC_THOLD_4, | |
416 | .twait = FSMC_TWAIT_6, | |
417 | .tset = FSMC_TSET_0, | |
418 | }; | |
419 | ||
420 | if (timings) | |
421 | tims = timings; | |
422 | else | |
423 | tims = &default_timings; | |
424 | ||
425 | tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; | |
426 | tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; | |
427 | thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; | |
428 | thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; | |
429 | twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; | |
430 | tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; | |
6c009ab8 LW |
431 | |
432 | if (busw) | |
a4742d51 VK |
433 | writel_relaxed(value | FSMC_DEVWID_16, |
434 | FSMC_NAND_REG(regs, bank, PC)); | |
6c009ab8 | 435 | else |
a4742d51 VK |
436 | writel_relaxed(value | FSMC_DEVWID_8, |
437 | FSMC_NAND_REG(regs, bank, PC)); | |
6c009ab8 | 438 | |
a4742d51 | 439 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar, |
2a5dbead | 440 | FSMC_NAND_REG(regs, bank, PC)); |
a4742d51 VK |
441 | writel_relaxed(thiz | thold | twait | tset, |
442 | FSMC_NAND_REG(regs, bank, COMM)); | |
443 | writel_relaxed(thiz | thold | twait | tset, | |
444 | FSMC_NAND_REG(regs, bank, ATTRIB)); | |
6c009ab8 LW |
445 | } |
446 | ||
447 | /* | |
448 | * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers | |
449 | */ | |
450 | static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) | |
451 | { | |
277af429 | 452 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 453 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
454 | uint32_t bank = host->bank; |
455 | ||
a4742d51 | 456 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256, |
2a5dbead | 457 | FSMC_NAND_REG(regs, bank, PC)); |
a4742d51 | 458 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN, |
2a5dbead | 459 | FSMC_NAND_REG(regs, bank, PC)); |
a4742d51 | 460 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN, |
2a5dbead | 461 | FSMC_NAND_REG(regs, bank, PC)); |
6c009ab8 LW |
462 | } |
463 | ||
464 | /* | |
465 | * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by | |
25985edc | 466 | * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
467 | * max of 8-bits) |
468 | */ | |
469 | static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, | |
470 | uint8_t *ecc) | |
471 | { | |
277af429 | 472 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 473 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
474 | uint32_t bank = host->bank; |
475 | uint32_t ecc_tmp; | |
476 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; | |
477 | ||
478 | do { | |
a4742d51 | 479 | if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY) |
6c009ab8 LW |
480 | break; |
481 | else | |
482 | cond_resched(); | |
483 | } while (!time_after_eq(jiffies, deadline)); | |
484 | ||
712c4add VK |
485 | if (time_after_eq(jiffies, deadline)) { |
486 | dev_err(host->dev, "calculate ecc timed out\n"); | |
487 | return -ETIMEDOUT; | |
488 | } | |
489 | ||
a4742d51 | 490 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
6c009ab8 LW |
491 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
492 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | |
493 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | |
494 | ecc[3] = (uint8_t) (ecc_tmp >> 24); | |
495 | ||
a4742d51 | 496 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); |
6c009ab8 LW |
497 | ecc[4] = (uint8_t) (ecc_tmp >> 0); |
498 | ecc[5] = (uint8_t) (ecc_tmp >> 8); | |
499 | ecc[6] = (uint8_t) (ecc_tmp >> 16); | |
500 | ecc[7] = (uint8_t) (ecc_tmp >> 24); | |
501 | ||
a4742d51 | 502 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); |
6c009ab8 LW |
503 | ecc[8] = (uint8_t) (ecc_tmp >> 0); |
504 | ecc[9] = (uint8_t) (ecc_tmp >> 8); | |
505 | ecc[10] = (uint8_t) (ecc_tmp >> 16); | |
506 | ecc[11] = (uint8_t) (ecc_tmp >> 24); | |
507 | ||
a4742d51 | 508 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); |
6c009ab8 LW |
509 | ecc[12] = (uint8_t) (ecc_tmp >> 16); |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | /* | |
515 | * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by | |
25985edc | 516 | * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
517 | * max of 1-bit) |
518 | */ | |
519 | static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data, | |
520 | uint8_t *ecc) | |
521 | { | |
277af429 | 522 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 523 | void __iomem *regs = host->regs_va; |
6c009ab8 LW |
524 | uint32_t bank = host->bank; |
525 | uint32_t ecc_tmp; | |
526 | ||
a4742d51 | 527 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
6c009ab8 LW |
528 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
529 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | |
530 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
519300cf VK |
535 | /* Count the number of 0's in buff upto a max of max_bits */ |
536 | static int count_written_bits(uint8_t *buff, int size, int max_bits) | |
537 | { | |
538 | int k, written_bits = 0; | |
539 | ||
540 | for (k = 0; k < size; k++) { | |
541 | written_bits += hweight8(~buff[k]); | |
542 | if (written_bits > max_bits) | |
543 | break; | |
544 | } | |
545 | ||
546 | return written_bits; | |
547 | } | |
548 | ||
4774fb0a VK |
549 | static void dma_complete(void *param) |
550 | { | |
551 | struct fsmc_nand_data *host = param; | |
552 | ||
553 | complete(&host->dma_access_complete); | |
554 | } | |
555 | ||
556 | static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, | |
557 | enum dma_data_direction direction) | |
558 | { | |
559 | struct dma_chan *chan; | |
560 | struct dma_device *dma_dev; | |
561 | struct dma_async_tx_descriptor *tx; | |
562 | dma_addr_t dma_dst, dma_src, dma_addr; | |
563 | dma_cookie_t cookie; | |
564 | unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; | |
565 | int ret; | |
818a45b1 | 566 | unsigned long time_left; |
4774fb0a VK |
567 | |
568 | if (direction == DMA_TO_DEVICE) | |
569 | chan = host->write_dma_chan; | |
570 | else if (direction == DMA_FROM_DEVICE) | |
571 | chan = host->read_dma_chan; | |
572 | else | |
573 | return -EINVAL; | |
574 | ||
575 | dma_dev = chan->device; | |
576 | dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); | |
577 | ||
578 | if (direction == DMA_TO_DEVICE) { | |
579 | dma_src = dma_addr; | |
580 | dma_dst = host->data_pa; | |
4774fb0a VK |
581 | } else { |
582 | dma_src = host->data_pa; | |
583 | dma_dst = dma_addr; | |
4774fb0a VK |
584 | } |
585 | ||
586 | tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, | |
587 | len, flags); | |
4774fb0a VK |
588 | if (!tx) { |
589 | dev_err(host->dev, "device_prep_dma_memcpy error\n"); | |
d1806a5c BZ |
590 | ret = -EIO; |
591 | goto unmap_dma; | |
4774fb0a VK |
592 | } |
593 | ||
594 | tx->callback = dma_complete; | |
595 | tx->callback_param = host; | |
596 | cookie = tx->tx_submit(tx); | |
597 | ||
598 | ret = dma_submit_error(cookie); | |
599 | if (ret) { | |
600 | dev_err(host->dev, "dma_submit_error %d\n", cookie); | |
d1806a5c | 601 | goto unmap_dma; |
4774fb0a VK |
602 | } |
603 | ||
604 | dma_async_issue_pending(chan); | |
605 | ||
818a45b1 | 606 | time_left = |
928aa2ae | 607 | wait_for_completion_timeout(&host->dma_access_complete, |
4774fb0a | 608 | msecs_to_jiffies(3000)); |
818a45b1 | 609 | if (time_left == 0) { |
b177ea34 | 610 | dmaengine_terminate_all(chan); |
4774fb0a | 611 | dev_err(host->dev, "wait_for_completion_timeout\n"); |
0bda3e19 | 612 | ret = -ETIMEDOUT; |
d1806a5c | 613 | goto unmap_dma; |
4774fb0a VK |
614 | } |
615 | ||
d1806a5c BZ |
616 | ret = 0; |
617 | ||
618 | unmap_dma: | |
619 | dma_unmap_single(dma_dev->dev, dma_addr, len, direction); | |
620 | ||
621 | return ret; | |
4774fb0a VK |
622 | } |
623 | ||
604e7544 VK |
624 | /* |
625 | * fsmc_write_buf - write buffer to chip | |
626 | * @mtd: MTD device structure | |
627 | * @buf: data buffer | |
628 | * @len: number of bytes to write | |
629 | */ | |
630 | static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
631 | { | |
632 | int i; | |
4bd4ebcc | 633 | struct nand_chip *chip = mtd_to_nand(mtd); |
604e7544 VK |
634 | |
635 | if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && | |
636 | IS_ALIGNED(len, sizeof(uint32_t))) { | |
637 | uint32_t *p = (uint32_t *)buf; | |
638 | len = len >> 2; | |
639 | for (i = 0; i < len; i++) | |
a4742d51 | 640 | writel_relaxed(p[i], chip->IO_ADDR_W); |
604e7544 VK |
641 | } else { |
642 | for (i = 0; i < len; i++) | |
a4742d51 | 643 | writeb_relaxed(buf[i], chip->IO_ADDR_W); |
604e7544 VK |
644 | } |
645 | } | |
646 | ||
647 | /* | |
648 | * fsmc_read_buf - read chip data into buffer | |
649 | * @mtd: MTD device structure | |
650 | * @buf: buffer to store date | |
651 | * @len: number of bytes to read | |
652 | */ | |
653 | static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
654 | { | |
655 | int i; | |
4bd4ebcc | 656 | struct nand_chip *chip = mtd_to_nand(mtd); |
604e7544 VK |
657 | |
658 | if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && | |
659 | IS_ALIGNED(len, sizeof(uint32_t))) { | |
660 | uint32_t *p = (uint32_t *)buf; | |
661 | len = len >> 2; | |
662 | for (i = 0; i < len; i++) | |
a4742d51 | 663 | p[i] = readl_relaxed(chip->IO_ADDR_R); |
604e7544 VK |
664 | } else { |
665 | for (i = 0; i < len; i++) | |
a4742d51 | 666 | buf[i] = readb_relaxed(chip->IO_ADDR_R); |
604e7544 VK |
667 | } |
668 | } | |
669 | ||
4774fb0a VK |
670 | /* |
671 | * fsmc_read_buf_dma - read chip data into buffer | |
672 | * @mtd: MTD device structure | |
673 | * @buf: buffer to store date | |
674 | * @len: number of bytes to read | |
675 | */ | |
676 | static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len) | |
677 | { | |
277af429 | 678 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
4774fb0a | 679 | |
4774fb0a VK |
680 | dma_xfer(host, buf, len, DMA_FROM_DEVICE); |
681 | } | |
682 | ||
683 | /* | |
684 | * fsmc_write_buf_dma - write buffer to chip | |
685 | * @mtd: MTD device structure | |
686 | * @buf: data buffer | |
687 | * @len: number of bytes to write | |
688 | */ | |
689 | static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf, | |
690 | int len) | |
691 | { | |
277af429 | 692 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
4774fb0a | 693 | |
4774fb0a VK |
694 | dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); |
695 | } | |
696 | ||
6c009ab8 LW |
697 | /* |
698 | * fsmc_read_page_hwecc | |
699 | * @mtd: mtd info structure | |
700 | * @chip: nand chip info structure | |
701 | * @buf: buffer to store read data | |
1fbb938d | 702 | * @oob_required: caller expects OOB data read to chip->oob_poi |
6c009ab8 LW |
703 | * @page: page number to read |
704 | * | |
25985edc | 705 | * This routine is needed for fsmc version 8 as reading from NAND chip has to be |
6c009ab8 LW |
706 | * performed in a strict sequence as follows: |
707 | * data(512 byte) -> ecc(13 byte) | |
25985edc | 708 | * After this read, fsmc hardware generates and reports error data bits(up to a |
6c009ab8 LW |
709 | * max of 8 bits) |
710 | */ | |
711 | static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 712 | uint8_t *buf, int oob_required, int page) |
6c009ab8 | 713 | { |
277af429 | 714 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
6c009ab8 LW |
715 | struct fsmc_eccplace *ecc_place = host->ecc_place; |
716 | int i, j, s, stat, eccsize = chip->ecc.size; | |
717 | int eccbytes = chip->ecc.bytes; | |
718 | int eccsteps = chip->ecc.steps; | |
719 | uint8_t *p = buf; | |
720 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
721 | uint8_t *ecc_code = chip->buffers->ecccode; | |
722 | int off, len, group = 0; | |
723 | /* | |
724 | * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we | |
725 | * end up reading 14 bytes (7 words) from oob. The local array is | |
726 | * to maintain word alignment | |
727 | */ | |
728 | uint16_t ecc_oob[7]; | |
729 | uint8_t *oob = (uint8_t *)&ecc_oob[0]; | |
3f91e94f | 730 | unsigned int max_bitflips = 0; |
6c009ab8 LW |
731 | |
732 | for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { | |
6c009ab8 LW |
733 | chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); |
734 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
735 | chip->read_buf(mtd, p, eccsize); | |
736 | ||
737 | for (j = 0; j < eccbytes;) { | |
738 | off = ecc_place->eccplace[group].offset; | |
739 | len = ecc_place->eccplace[group].length; | |
740 | group++; | |
741 | ||
742 | /* | |
4cbe1bf0 VK |
743 | * length is intentionally kept a higher multiple of 2 |
744 | * to read at least 13 bytes even in case of 16 bit NAND | |
745 | * devices | |
746 | */ | |
aea686b4 VK |
747 | if (chip->options & NAND_BUSWIDTH_16) |
748 | len = roundup(len, 2); | |
749 | ||
6c009ab8 LW |
750 | chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); |
751 | chip->read_buf(mtd, oob + j, len); | |
752 | j += len; | |
753 | } | |
754 | ||
519300cf | 755 | memcpy(&ecc_code[i], oob, chip->ecc.bytes); |
6c009ab8 LW |
756 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
757 | ||
758 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 759 | if (stat < 0) { |
6c009ab8 | 760 | mtd->ecc_stats.failed++; |
3f91e94f | 761 | } else { |
6c009ab8 | 762 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
763 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
764 | } | |
6c009ab8 LW |
765 | } |
766 | ||
3f91e94f | 767 | return max_bitflips; |
6c009ab8 LW |
768 | } |
769 | ||
770 | /* | |
753e0139 | 771 | * fsmc_bch8_correct_data |
6c009ab8 LW |
772 | * @mtd: mtd info structure |
773 | * @dat: buffer of read data | |
774 | * @read_ecc: ecc read from device spare area | |
775 | * @calc_ecc: ecc calculated from read data | |
776 | * | |
777 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
778 | * offset informations of 13 bits each in 512 bytes of read data. | |
779 | */ | |
753e0139 | 780 | static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat, |
6c009ab8 LW |
781 | uint8_t *read_ecc, uint8_t *calc_ecc) |
782 | { | |
4bd4ebcc | 783 | struct nand_chip *chip = mtd_to_nand(mtd); |
277af429 | 784 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
2a5dbead | 785 | void __iomem *regs = host->regs_va; |
6c009ab8 | 786 | unsigned int bank = host->bank; |
a612c2ae | 787 | uint32_t err_idx[8]; |
6c009ab8 | 788 | uint32_t num_err, i; |
753e0139 | 789 | uint32_t ecc1, ecc2, ecc3, ecc4; |
6c009ab8 | 790 | |
a4742d51 | 791 | num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF; |
519300cf VK |
792 | |
793 | /* no bit flipping */ | |
794 | if (likely(num_err == 0)) | |
795 | return 0; | |
796 | ||
797 | /* too many errors */ | |
798 | if (unlikely(num_err > 8)) { | |
799 | /* | |
800 | * This is a temporary erase check. A newly erased page read | |
801 | * would result in an ecc error because the oob data is also | |
802 | * erased to FF and the calculated ecc for an FF data is not | |
803 | * FF..FF. | |
804 | * This is a workaround to skip performing correction in case | |
805 | * data is FF..FF | |
806 | * | |
807 | * Logic: | |
808 | * For every page, each bit written as 0 is counted until these | |
809 | * number of bits are greater than 8 (the maximum correction | |
810 | * capability of FSMC for each 512 + 13 bytes) | |
811 | */ | |
812 | ||
813 | int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); | |
814 | int bits_data = count_written_bits(dat, chip->ecc.size, 8); | |
815 | ||
816 | if ((bits_ecc + bits_data) <= 8) { | |
817 | if (bits_data) | |
818 | memset(dat, 0xff, chip->ecc.size); | |
819 | return bits_data; | |
820 | } | |
821 | ||
822 | return -EBADMSG; | |
823 | } | |
824 | ||
6c009ab8 LW |
825 | /* |
826 | * ------------------- calc_ecc[] bit wise -----------|--13 bits--| | |
827 | * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| | |
828 | * | |
829 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
830 | * offset informations of 13 bits each. calc_ecc is copied into a | |
831 | * uint64_t array and error offset indexes are populated in err_idx | |
832 | * array | |
833 | */ | |
a4742d51 VK |
834 | ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
835 | ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); | |
836 | ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); | |
837 | ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); | |
753e0139 AV |
838 | |
839 | err_idx[0] = (ecc1 >> 0) & 0x1FFF; | |
840 | err_idx[1] = (ecc1 >> 13) & 0x1FFF; | |
841 | err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); | |
842 | err_idx[3] = (ecc2 >> 7) & 0x1FFF; | |
843 | err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); | |
844 | err_idx[5] = (ecc3 >> 1) & 0x1FFF; | |
845 | err_idx[6] = (ecc3 >> 14) & 0x1FFF; | |
846 | err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); | |
6c009ab8 LW |
847 | |
848 | i = 0; | |
849 | while (num_err--) { | |
850 | change_bit(0, (unsigned long *)&err_idx[i]); | |
851 | change_bit(1, (unsigned long *)&err_idx[i]); | |
852 | ||
b533f8d8 | 853 | if (err_idx[i] < chip->ecc.size * 8) { |
6c009ab8 LW |
854 | change_bit(err_idx[i], (unsigned long *)dat); |
855 | i++; | |
856 | } | |
857 | } | |
858 | return i; | |
859 | } | |
860 | ||
4774fb0a VK |
861 | static bool filter(struct dma_chan *chan, void *slave) |
862 | { | |
863 | chan->private = slave; | |
864 | return true; | |
865 | } | |
866 | ||
eea62819 | 867 | #ifdef CONFIG_OF |
06f25510 | 868 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
d8929942 | 869 | struct device_node *np) |
eea62819 SR |
870 | { |
871 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
872 | u32 val; | |
62b57f4c | 873 | int ret; |
eea62819 SR |
874 | |
875 | /* Set default NAND width to 8 bits */ | |
876 | pdata->width = 8; | |
877 | if (!of_property_read_u32(np, "bank-width", &val)) { | |
878 | if (val == 2) { | |
879 | pdata->width = 16; | |
880 | } else if (val != 1) { | |
881 | dev_err(&pdev->dev, "invalid bank-width %u\n", val); | |
882 | return -EINVAL; | |
883 | } | |
884 | } | |
eea62819 SR |
885 | if (of_get_property(np, "nand-skip-bbtscan", NULL)) |
886 | pdata->options = NAND_SKIP_BBTSCAN; | |
887 | ||
64ddba4d MYK |
888 | pdata->nand_timings = devm_kzalloc(&pdev->dev, |
889 | sizeof(*pdata->nand_timings), GFP_KERNEL); | |
d9a21ae8 | 890 | if (!pdata->nand_timings) |
64ddba4d | 891 | return -ENOMEM; |
62b57f4c | 892 | ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings, |
64ddba4d | 893 | sizeof(*pdata->nand_timings)); |
62b57f4c SR |
894 | if (ret) { |
895 | dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n"); | |
896 | pdata->nand_timings = NULL; | |
897 | } | |
64ddba4d MYK |
898 | |
899 | /* Set default NAND bank to 0 */ | |
900 | pdata->bank = 0; | |
901 | if (!of_property_read_u32(np, "bank", &val)) { | |
902 | if (val > 3) { | |
903 | dev_err(&pdev->dev, "invalid bank %u\n", val); | |
904 | return -EINVAL; | |
905 | } | |
906 | pdata->bank = val; | |
907 | } | |
eea62819 SR |
908 | return 0; |
909 | } | |
910 | #else | |
06f25510 | 911 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
d8929942 | 912 | struct device_node *np) |
eea62819 SR |
913 | { |
914 | return -ENOSYS; | |
915 | } | |
916 | #endif | |
917 | ||
6c009ab8 LW |
918 | /* |
919 | * fsmc_nand_probe - Probe function | |
920 | * @pdev: platform device structure | |
921 | */ | |
922 | static int __init fsmc_nand_probe(struct platform_device *pdev) | |
923 | { | |
924 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
eea62819 | 925 | struct device_node __maybe_unused *np = pdev->dev.of_node; |
6c009ab8 LW |
926 | struct fsmc_nand_data *host; |
927 | struct mtd_info *mtd; | |
928 | struct nand_chip *nand; | |
6c009ab8 | 929 | struct resource *res; |
4774fb0a | 930 | dma_cap_mask_t mask; |
4ad916bc | 931 | int ret = 0; |
593cd871 LW |
932 | u32 pid; |
933 | int i; | |
6c009ab8 | 934 | |
eea62819 SR |
935 | if (np) { |
936 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
937 | pdev->dev.platform_data = pdata; | |
938 | ret = fsmc_nand_probe_config_dt(pdev, np); | |
939 | if (ret) { | |
940 | dev_err(&pdev->dev, "no platform data\n"); | |
941 | return -ENODEV; | |
942 | } | |
943 | } | |
944 | ||
6c009ab8 LW |
945 | if (!pdata) { |
946 | dev_err(&pdev->dev, "platform data is NULL\n"); | |
947 | return -EINVAL; | |
948 | } | |
949 | ||
950 | /* Allocate memory for the device structure (and zero it) */ | |
82b9dbe2 | 951 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
d9a21ae8 | 952 | if (!host) |
6c009ab8 | 953 | return -ENOMEM; |
6c009ab8 LW |
954 | |
955 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); | |
b0de774c TR |
956 | host->data_va = devm_ioremap_resource(&pdev->dev, res); |
957 | if (IS_ERR(host->data_va)) | |
958 | return PTR_ERR(host->data_va); | |
cbf29b83 | 959 | |
6d7b42a4 | 960 | host->data_pa = (dma_addr_t)res->start; |
6c009ab8 | 961 | |
6d7b42a4 | 962 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); |
b0de774c TR |
963 | host->addr_va = devm_ioremap_resource(&pdev->dev, res); |
964 | if (IS_ERR(host->addr_va)) | |
965 | return PTR_ERR(host->addr_va); | |
6c009ab8 | 966 | |
6d7b42a4 | 967 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); |
b0de774c TR |
968 | host->cmd_va = devm_ioremap_resource(&pdev->dev, res); |
969 | if (IS_ERR(host->cmd_va)) | |
970 | return PTR_ERR(host->cmd_va); | |
6c009ab8 LW |
971 | |
972 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); | |
b0de774c TR |
973 | host->regs_va = devm_ioremap_resource(&pdev->dev, res); |
974 | if (IS_ERR(host->regs_va)) | |
975 | return PTR_ERR(host->regs_va); | |
6c009ab8 LW |
976 | |
977 | host->clk = clk_get(&pdev->dev, NULL); | |
978 | if (IS_ERR(host->clk)) { | |
979 | dev_err(&pdev->dev, "failed to fetch block clock\n"); | |
82b9dbe2 | 980 | return PTR_ERR(host->clk); |
6c009ab8 LW |
981 | } |
982 | ||
e25da1c0 | 983 | ret = clk_prepare_enable(host->clk); |
6c009ab8 | 984 | if (ret) |
e25da1c0 | 985 | goto err_clk_prepare_enable; |
6c009ab8 | 986 | |
593cd871 LW |
987 | /* |
988 | * This device ID is actually a common AMBA ID as used on the | |
989 | * AMBA PrimeCell bus. However it is not a PrimeCell. | |
990 | */ | |
991 | for (pid = 0, i = 0; i < 4; i++) | |
992 | pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8); | |
993 | host->pid = pid; | |
994 | dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, " | |
995 | "revision %02x, config %02x\n", | |
996 | AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), | |
997 | AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); | |
998 | ||
6c009ab8 LW |
999 | host->bank = pdata->bank; |
1000 | host->select_chip = pdata->select_bank; | |
71470324 VK |
1001 | host->partitions = pdata->partitions; |
1002 | host->nr_partitions = pdata->nr_partitions; | |
712c4add | 1003 | host->dev = &pdev->dev; |
e2f6bce8 | 1004 | host->dev_timings = pdata->nand_timings; |
4774fb0a VK |
1005 | host->mode = pdata->mode; |
1006 | ||
1007 | if (host->mode == USE_DMA_ACCESS) | |
1008 | init_completion(&host->dma_access_complete); | |
1009 | ||
6c009ab8 LW |
1010 | /* Link all private pointers */ |
1011 | mtd = &host->mtd; | |
1012 | nand = &host->nand; | |
1013 | mtd->priv = nand; | |
1014 | nand->priv = host; | |
a61ae81a | 1015 | nand_set_flash_node(nand, np); |
6c009ab8 | 1016 | |
ddece7b6 | 1017 | host->mtd.dev.parent = &pdev->dev; |
6c009ab8 LW |
1018 | nand->IO_ADDR_R = host->data_va; |
1019 | nand->IO_ADDR_W = host->data_va; | |
1020 | nand->cmd_ctrl = fsmc_cmd_ctrl; | |
1021 | nand->chip_delay = 30; | |
1022 | ||
e278fc71 SR |
1023 | /* |
1024 | * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() | |
1025 | * can overwrite this value if the DT provides a different value. | |
1026 | */ | |
6c009ab8 LW |
1027 | nand->ecc.mode = NAND_ECC_HW; |
1028 | nand->ecc.hwctl = fsmc_enable_hwecc; | |
1029 | nand->ecc.size = 512; | |
1030 | nand->options = pdata->options; | |
1031 | nand->select_chip = fsmc_select_chip; | |
467e6e7b | 1032 | nand->badblockbits = 7; |
63752199 | 1033 | nand_set_flash_node(nand, np); |
6c009ab8 LW |
1034 | |
1035 | if (pdata->width == FSMC_NAND_BW16) | |
1036 | nand->options |= NAND_BUSWIDTH_16; | |
1037 | ||
4774fb0a VK |
1038 | switch (host->mode) { |
1039 | case USE_DMA_ACCESS: | |
1040 | dma_cap_zero(mask); | |
1041 | dma_cap_set(DMA_MEMCPY, mask); | |
1042 | host->read_dma_chan = dma_request_channel(mask, filter, | |
1043 | pdata->read_dma_priv); | |
1044 | if (!host->read_dma_chan) { | |
1045 | dev_err(&pdev->dev, "Unable to get read dma channel\n"); | |
1046 | goto err_req_read_chnl; | |
1047 | } | |
1048 | host->write_dma_chan = dma_request_channel(mask, filter, | |
1049 | pdata->write_dma_priv); | |
1050 | if (!host->write_dma_chan) { | |
1051 | dev_err(&pdev->dev, "Unable to get write dma channel\n"); | |
1052 | goto err_req_write_chnl; | |
1053 | } | |
1054 | nand->read_buf = fsmc_read_buf_dma; | |
1055 | nand->write_buf = fsmc_write_buf_dma; | |
1056 | break; | |
1057 | ||
1058 | default: | |
1059 | case USE_WORD_ACCESS: | |
604e7544 VK |
1060 | nand->read_buf = fsmc_read_buf; |
1061 | nand->write_buf = fsmc_write_buf; | |
4774fb0a | 1062 | break; |
604e7544 VK |
1063 | } |
1064 | ||
2a5dbead VK |
1065 | fsmc_nand_setup(host->regs_va, host->bank, |
1066 | nand->options & NAND_BUSWIDTH_16, | |
e2f6bce8 | 1067 | host->dev_timings); |
6c009ab8 | 1068 | |
593cd871 | 1069 | if (AMBA_REV_BITS(host->pid) >= 8) { |
6c009ab8 LW |
1070 | nand->ecc.read_page = fsmc_read_page_hwecc; |
1071 | nand->ecc.calculate = fsmc_read_hwecc_ecc4; | |
753e0139 | 1072 | nand->ecc.correct = fsmc_bch8_correct_data; |
6c009ab8 | 1073 | nand->ecc.bytes = 13; |
6a918bad | 1074 | nand->ecc.strength = 8; |
6c009ab8 LW |
1075 | } |
1076 | ||
1077 | /* | |
25985edc | 1078 | * Scan to find existence of the device |
6c009ab8 LW |
1079 | */ |
1080 | if (nand_scan_ident(&host->mtd, 1, NULL)) { | |
1081 | ret = -ENXIO; | |
1082 | dev_err(&pdev->dev, "No NAND Device found!\n"); | |
82b9dbe2 | 1083 | goto err_scan_ident; |
6c009ab8 LW |
1084 | } |
1085 | ||
593cd871 | 1086 | if (AMBA_REV_BITS(host->pid) >= 8) { |
e29ee57b BY |
1087 | switch (host->mtd.oobsize) { |
1088 | case 16: | |
1089 | nand->ecc.layout = &fsmc_ecc4_16_layout; | |
6c009ab8 | 1090 | host->ecc_place = &fsmc_ecc4_sp_place; |
e29ee57b BY |
1091 | break; |
1092 | case 64: | |
1093 | nand->ecc.layout = &fsmc_ecc4_64_layout; | |
1094 | host->ecc_place = &fsmc_ecc4_lp_place; | |
1095 | break; | |
1096 | case 128: | |
1097 | nand->ecc.layout = &fsmc_ecc4_128_layout; | |
1098 | host->ecc_place = &fsmc_ecc4_lp_place; | |
1099 | break; | |
0c78e93b AV |
1100 | case 224: |
1101 | nand->ecc.layout = &fsmc_ecc4_224_layout; | |
1102 | host->ecc_place = &fsmc_ecc4_lp_place; | |
1103 | break; | |
e29ee57b BY |
1104 | case 256: |
1105 | nand->ecc.layout = &fsmc_ecc4_256_layout; | |
6c009ab8 | 1106 | host->ecc_place = &fsmc_ecc4_lp_place; |
e29ee57b BY |
1107 | break; |
1108 | default: | |
67b19a63 JH |
1109 | dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n", |
1110 | mtd->oobsize); | |
6efadcf9 SR |
1111 | ret = -EINVAL; |
1112 | goto err_probe; | |
6c009ab8 LW |
1113 | } |
1114 | } else { | |
e278fc71 SR |
1115 | switch (nand->ecc.mode) { |
1116 | case NAND_ECC_HW: | |
1117 | dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n"); | |
1118 | nand->ecc.calculate = fsmc_read_hwecc_ecc1; | |
1119 | nand->ecc.correct = nand_correct_data; | |
1120 | nand->ecc.bytes = 3; | |
1121 | nand->ecc.strength = 1; | |
e29ee57b | 1122 | break; |
e278fc71 SR |
1123 | |
1124 | case NAND_ECC_SOFT_BCH: | |
1125 | dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n"); | |
e29ee57b | 1126 | break; |
e278fc71 | 1127 | |
e29ee57b | 1128 | default: |
e278fc71 | 1129 | dev_err(&pdev->dev, "Unsupported ECC mode!\n"); |
6efadcf9 | 1130 | goto err_probe; |
e29ee57b | 1131 | } |
e278fc71 SR |
1132 | |
1133 | /* | |
1134 | * Don't set layout for BCH4 SW ECC. This will be | |
1135 | * generated later in nand_bch_init() later. | |
1136 | */ | |
1137 | if (nand->ecc.mode != NAND_ECC_SOFT_BCH) { | |
1138 | switch (host->mtd.oobsize) { | |
1139 | case 16: | |
1140 | nand->ecc.layout = &fsmc_ecc1_16_layout; | |
1141 | break; | |
1142 | case 64: | |
1143 | nand->ecc.layout = &fsmc_ecc1_64_layout; | |
1144 | break; | |
1145 | case 128: | |
1146 | nand->ecc.layout = &fsmc_ecc1_128_layout; | |
1147 | break; | |
1148 | default: | |
1149 | dev_warn(&pdev->dev, | |
1150 | "No oob scheme defined for oobsize %d\n", | |
1151 | mtd->oobsize); | |
1152 | ret = -EINVAL; | |
1153 | goto err_probe; | |
1154 | } | |
1155 | } | |
6c009ab8 LW |
1156 | } |
1157 | ||
1158 | /* Second stage of scan to fill MTD data-structures */ | |
1159 | if (nand_scan_tail(&host->mtd)) { | |
1160 | ret = -ENXIO; | |
1161 | goto err_probe; | |
1162 | } | |
1163 | ||
1164 | /* | |
1165 | * The partition information can is accessed by (in the same precedence) | |
1166 | * | |
1167 | * command line through Bootloader, | |
1168 | * platform data, | |
1169 | * default partition information present in driver. | |
1170 | */ | |
6c009ab8 | 1171 | /* |
8d3f8bb8 | 1172 | * Check for partition info passed |
6c009ab8 LW |
1173 | */ |
1174 | host->mtd.name = "nand"; | |
a61ae81a BN |
1175 | ret = mtd_device_register(&host->mtd, host->partitions, |
1176 | host->nr_partitions); | |
99335d00 | 1177 | if (ret) |
6c009ab8 | 1178 | goto err_probe; |
6c009ab8 LW |
1179 | |
1180 | platform_set_drvdata(pdev, host); | |
1181 | dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); | |
1182 | return 0; | |
1183 | ||
1184 | err_probe: | |
82b9dbe2 | 1185 | err_scan_ident: |
4774fb0a VK |
1186 | if (host->mode == USE_DMA_ACCESS) |
1187 | dma_release_channel(host->write_dma_chan); | |
1188 | err_req_write_chnl: | |
1189 | if (host->mode == USE_DMA_ACCESS) | |
1190 | dma_release_channel(host->read_dma_chan); | |
1191 | err_req_read_chnl: | |
e25da1c0 VK |
1192 | clk_disable_unprepare(host->clk); |
1193 | err_clk_prepare_enable: | |
82b9dbe2 | 1194 | clk_put(host->clk); |
6c009ab8 LW |
1195 | return ret; |
1196 | } | |
1197 | ||
1198 | /* | |
1199 | * Clean up routine | |
1200 | */ | |
1201 | static int fsmc_nand_remove(struct platform_device *pdev) | |
1202 | { | |
1203 | struct fsmc_nand_data *host = platform_get_drvdata(pdev); | |
1204 | ||
6c009ab8 | 1205 | if (host) { |
82e023ab | 1206 | nand_release(&host->mtd); |
4774fb0a VK |
1207 | |
1208 | if (host->mode == USE_DMA_ACCESS) { | |
1209 | dma_release_channel(host->write_dma_chan); | |
1210 | dma_release_channel(host->read_dma_chan); | |
1211 | } | |
e25da1c0 | 1212 | clk_disable_unprepare(host->clk); |
6c009ab8 | 1213 | clk_put(host->clk); |
6c009ab8 | 1214 | } |
82b9dbe2 | 1215 | |
6c009ab8 LW |
1216 | return 0; |
1217 | } | |
1218 | ||
80ce4dde | 1219 | #ifdef CONFIG_PM_SLEEP |
6c009ab8 LW |
1220 | static int fsmc_nand_suspend(struct device *dev) |
1221 | { | |
1222 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
1223 | if (host) | |
e25da1c0 | 1224 | clk_disable_unprepare(host->clk); |
6c009ab8 LW |
1225 | return 0; |
1226 | } | |
1227 | ||
1228 | static int fsmc_nand_resume(struct device *dev) | |
1229 | { | |
1230 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
f63acb75 | 1231 | if (host) { |
e25da1c0 | 1232 | clk_prepare_enable(host->clk); |
f63acb75 | 1233 | fsmc_nand_setup(host->regs_va, host->bank, |
e2f6bce8 VK |
1234 | host->nand.options & NAND_BUSWIDTH_16, |
1235 | host->dev_timings); | |
f63acb75 | 1236 | } |
6c009ab8 LW |
1237 | return 0; |
1238 | } | |
80ce4dde | 1239 | #endif |
6c009ab8 | 1240 | |
f63acb75 | 1241 | static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); |
6c009ab8 | 1242 | |
eea62819 SR |
1243 | #ifdef CONFIG_OF |
1244 | static const struct of_device_id fsmc_nand_id_table[] = { | |
1245 | { .compatible = "st,spear600-fsmc-nand" }, | |
ba785205 | 1246 | { .compatible = "stericsson,fsmc-nand" }, |
eea62819 SR |
1247 | {} |
1248 | }; | |
1249 | MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); | |
1250 | #endif | |
1251 | ||
6c009ab8 LW |
1252 | static struct platform_driver fsmc_nand_driver = { |
1253 | .remove = fsmc_nand_remove, | |
1254 | .driver = { | |
6c009ab8 | 1255 | .name = "fsmc-nand", |
eea62819 | 1256 | .of_match_table = of_match_ptr(fsmc_nand_id_table), |
6c009ab8 | 1257 | .pm = &fsmc_nand_pm_ops, |
6c009ab8 LW |
1258 | }, |
1259 | }; | |
1260 | ||
307d2a51 | 1261 | module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); |
6c009ab8 LW |
1262 | |
1263 | MODULE_LICENSE("GPL"); | |
1264 | MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); | |
1265 | MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); |