Commit | Line | Data |
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6c009ab8 LW |
1 | /* |
2 | * drivers/mtd/nand/fsmc_nand.c | |
3 | * | |
4 | * ST Microelectronics | |
5 | * Flexible Static Memory Controller (FSMC) | |
6 | * Driver for NAND portions | |
7 | * | |
8 | * Copyright © 2010 ST Microelectronics | |
9 | * Vipin Kumar <vipin.kumar@st.com> | |
10 | * Ashish Priyadarshi | |
11 | * | |
12 | * Based on drivers/mtd/nand/nomadik_nand.c | |
13 | * | |
14 | * This file is licensed under the terms of the GNU General Public | |
15 | * License version 2. This program is licensed "as is" without any | |
16 | * warranty of any kind, whether express or implied. | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/resource.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/mtd/mtd.h> | |
27 | #include <linux/mtd/nand.h> | |
28 | #include <linux/mtd/nand_ecc.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/mtd/partitions.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/mtd/fsmc.h> | |
593cd871 | 34 | #include <linux/amba/bus.h> |
6c009ab8 LW |
35 | #include <mtd/mtd-abi.h> |
36 | ||
e29ee57b | 37 | static struct nand_ecclayout fsmc_ecc1_128_layout = { |
6c009ab8 LW |
38 | .eccbytes = 24, |
39 | .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, | |
40 | 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, | |
41 | .oobfree = { | |
42 | {.offset = 8, .length = 8}, | |
43 | {.offset = 24, .length = 8}, | |
44 | {.offset = 40, .length = 8}, | |
45 | {.offset = 56, .length = 8}, | |
46 | {.offset = 72, .length = 8}, | |
47 | {.offset = 88, .length = 8}, | |
48 | {.offset = 104, .length = 8}, | |
49 | {.offset = 120, .length = 8} | |
50 | } | |
51 | }; | |
52 | ||
e29ee57b BY |
53 | static struct nand_ecclayout fsmc_ecc1_64_layout = { |
54 | .eccbytes = 12, | |
55 | .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52}, | |
56 | .oobfree = { | |
57 | {.offset = 8, .length = 8}, | |
58 | {.offset = 24, .length = 8}, | |
59 | {.offset = 40, .length = 8}, | |
60 | {.offset = 56, .length = 8}, | |
61 | } | |
62 | }; | |
63 | ||
64 | static struct nand_ecclayout fsmc_ecc1_16_layout = { | |
65 | .eccbytes = 3, | |
66 | .eccpos = {2, 3, 4}, | |
67 | .oobfree = { | |
68 | {.offset = 8, .length = 8}, | |
69 | } | |
70 | }; | |
71 | ||
72 | /* | |
73 | * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes | |
74 | * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46 | |
75 | * bytes are free for use. | |
76 | */ | |
77 | static struct nand_ecclayout fsmc_ecc4_256_layout = { | |
78 | .eccbytes = 208, | |
79 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
80 | 9, 10, 11, 12, 13, 14, | |
81 | 18, 19, 20, 21, 22, 23, 24, | |
82 | 25, 26, 27, 28, 29, 30, | |
83 | 34, 35, 36, 37, 38, 39, 40, | |
84 | 41, 42, 43, 44, 45, 46, | |
85 | 50, 51, 52, 53, 54, 55, 56, | |
86 | 57, 58, 59, 60, 61, 62, | |
87 | 66, 67, 68, 69, 70, 71, 72, | |
88 | 73, 74, 75, 76, 77, 78, | |
89 | 82, 83, 84, 85, 86, 87, 88, | |
90 | 89, 90, 91, 92, 93, 94, | |
91 | 98, 99, 100, 101, 102, 103, 104, | |
92 | 105, 106, 107, 108, 109, 110, | |
93 | 114, 115, 116, 117, 118, 119, 120, | |
94 | 121, 122, 123, 124, 125, 126, | |
95 | 130, 131, 132, 133, 134, 135, 136, | |
96 | 137, 138, 139, 140, 141, 142, | |
97 | 146, 147, 148, 149, 150, 151, 152, | |
98 | 153, 154, 155, 156, 157, 158, | |
99 | 162, 163, 164, 165, 166, 167, 168, | |
100 | 169, 170, 171, 172, 173, 174, | |
101 | 178, 179, 180, 181, 182, 183, 184, | |
102 | 185, 186, 187, 188, 189, 190, | |
103 | 194, 195, 196, 197, 198, 199, 200, | |
104 | 201, 202, 203, 204, 205, 206, | |
105 | 210, 211, 212, 213, 214, 215, 216, | |
106 | 217, 218, 219, 220, 221, 222, | |
107 | 226, 227, 228, 229, 230, 231, 232, | |
108 | 233, 234, 235, 236, 237, 238, | |
109 | 242, 243, 244, 245, 246, 247, 248, | |
110 | 249, 250, 251, 252, 253, 254 | |
111 | }, | |
112 | .oobfree = { | |
113 | {.offset = 15, .length = 3}, | |
114 | {.offset = 31, .length = 3}, | |
115 | {.offset = 47, .length = 3}, | |
116 | {.offset = 63, .length = 3}, | |
117 | {.offset = 79, .length = 3}, | |
118 | {.offset = 95, .length = 3}, | |
119 | {.offset = 111, .length = 3}, | |
120 | {.offset = 127, .length = 3}, | |
121 | {.offset = 143, .length = 3}, | |
122 | {.offset = 159, .length = 3}, | |
123 | {.offset = 175, .length = 3}, | |
124 | {.offset = 191, .length = 3}, | |
125 | {.offset = 207, .length = 3}, | |
126 | {.offset = 223, .length = 3}, | |
127 | {.offset = 239, .length = 3}, | |
128 | {.offset = 255, .length = 1} | |
129 | } | |
130 | }; | |
131 | ||
132 | /* | |
133 | * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes | |
134 | * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22 | |
135 | * bytes are free for use. | |
136 | */ | |
137 | static struct nand_ecclayout fsmc_ecc4_128_layout = { | |
6c009ab8 LW |
138 | .eccbytes = 104, |
139 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
140 | 9, 10, 11, 12, 13, 14, | |
141 | 18, 19, 20, 21, 22, 23, 24, | |
142 | 25, 26, 27, 28, 29, 30, | |
143 | 34, 35, 36, 37, 38, 39, 40, | |
144 | 41, 42, 43, 44, 45, 46, | |
145 | 50, 51, 52, 53, 54, 55, 56, | |
146 | 57, 58, 59, 60, 61, 62, | |
147 | 66, 67, 68, 69, 70, 71, 72, | |
148 | 73, 74, 75, 76, 77, 78, | |
149 | 82, 83, 84, 85, 86, 87, 88, | |
150 | 89, 90, 91, 92, 93, 94, | |
151 | 98, 99, 100, 101, 102, 103, 104, | |
152 | 105, 106, 107, 108, 109, 110, | |
153 | 114, 115, 116, 117, 118, 119, 120, | |
154 | 121, 122, 123, 124, 125, 126 | |
155 | }, | |
156 | .oobfree = { | |
157 | {.offset = 15, .length = 3}, | |
158 | {.offset = 31, .length = 3}, | |
159 | {.offset = 47, .length = 3}, | |
160 | {.offset = 63, .length = 3}, | |
161 | {.offset = 79, .length = 3}, | |
162 | {.offset = 95, .length = 3}, | |
163 | {.offset = 111, .length = 3}, | |
164 | {.offset = 127, .length = 1} | |
165 | } | |
166 | }; | |
167 | ||
e29ee57b BY |
168 | /* |
169 | * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of | |
170 | * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10 | |
171 | * bytes are free for use. | |
172 | */ | |
173 | static struct nand_ecclayout fsmc_ecc4_64_layout = { | |
174 | .eccbytes = 52, | |
175 | .eccpos = { 2, 3, 4, 5, 6, 7, 8, | |
176 | 9, 10, 11, 12, 13, 14, | |
177 | 18, 19, 20, 21, 22, 23, 24, | |
178 | 25, 26, 27, 28, 29, 30, | |
179 | 34, 35, 36, 37, 38, 39, 40, | |
180 | 41, 42, 43, 44, 45, 46, | |
181 | 50, 51, 52, 53, 54, 55, 56, | |
182 | 57, 58, 59, 60, 61, 62, | |
183 | }, | |
184 | .oobfree = { | |
185 | {.offset = 15, .length = 3}, | |
186 | {.offset = 31, .length = 3}, | |
187 | {.offset = 47, .length = 3}, | |
188 | {.offset = 63, .length = 1}, | |
189 | } | |
190 | }; | |
191 | ||
192 | /* | |
193 | * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of | |
194 | * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One | |
195 | * byte is free for use. | |
196 | */ | |
197 | static struct nand_ecclayout fsmc_ecc4_16_layout = { | |
198 | .eccbytes = 13, | |
199 | .eccpos = { 0, 1, 2, 3, 6, 7, 8, | |
200 | 9, 10, 11, 12, 13, 14 | |
201 | }, | |
202 | .oobfree = { | |
203 | {.offset = 15, .length = 1}, | |
204 | } | |
205 | }; | |
206 | ||
6c009ab8 LW |
207 | /* |
208 | * ECC placement definitions in oobfree type format. | |
209 | * There are 13 bytes of ecc for every 512 byte block and it has to be read | |
210 | * consecutively and immediately after the 512 byte data block for hardware to | |
211 | * generate the error bit offsets in 512 byte data. | |
212 | * Managing the ecc bytes in the following way makes it easier for software to | |
213 | * read ecc bytes consecutive to data bytes. This way is similar to | |
214 | * oobfree structure maintained already in generic nand driver | |
215 | */ | |
216 | static struct fsmc_eccplace fsmc_ecc4_lp_place = { | |
217 | .eccplace = { | |
218 | {.offset = 2, .length = 13}, | |
219 | {.offset = 18, .length = 13}, | |
220 | {.offset = 34, .length = 13}, | |
221 | {.offset = 50, .length = 13}, | |
222 | {.offset = 66, .length = 13}, | |
223 | {.offset = 82, .length = 13}, | |
224 | {.offset = 98, .length = 13}, | |
225 | {.offset = 114, .length = 13} | |
226 | } | |
227 | }; | |
228 | ||
6c009ab8 LW |
229 | static struct fsmc_eccplace fsmc_ecc4_sp_place = { |
230 | .eccplace = { | |
231 | {.offset = 0, .length = 4}, | |
232 | {.offset = 6, .length = 9} | |
233 | } | |
234 | }; | |
235 | ||
6c009ab8 | 236 | /* |
4ad916bc LW |
237 | * Default partition tables to be used if the partition information not |
238 | * provided through platform data. | |
239 | * | |
6c009ab8 LW |
240 | * Default partition layout for small page(= 512 bytes) devices |
241 | * Size for "Root file system" is updated in driver based on actual device size | |
242 | */ | |
243 | static struct mtd_partition partition_info_16KB_blk[] = { | |
4ad916bc LW |
244 | { |
245 | .name = "X-loader", | |
246 | .offset = 0, | |
247 | .size = 4*0x4000, | |
248 | }, | |
249 | { | |
250 | .name = "U-Boot", | |
251 | .offset = 0x10000, | |
252 | .size = 20*0x4000, | |
253 | }, | |
254 | { | |
255 | .name = "Kernel", | |
256 | .offset = 0x60000, | |
257 | .size = 256*0x4000, | |
258 | }, | |
259 | { | |
260 | .name = "Root File System", | |
261 | .offset = 0x460000, | |
0d04eda1 | 262 | .size = MTDPART_SIZ_FULL, |
4ad916bc | 263 | }, |
6c009ab8 LW |
264 | }; |
265 | ||
266 | /* | |
267 | * Default partition layout for large page(> 512 bytes) devices | |
268 | * Size for "Root file system" is updated in driver based on actual device size | |
269 | */ | |
270 | static struct mtd_partition partition_info_128KB_blk[] = { | |
4ad916bc LW |
271 | { |
272 | .name = "X-loader", | |
273 | .offset = 0, | |
274 | .size = 4*0x20000, | |
275 | }, | |
276 | { | |
277 | .name = "U-Boot", | |
278 | .offset = 0x80000, | |
279 | .size = 12*0x20000, | |
280 | }, | |
281 | { | |
282 | .name = "Kernel", | |
283 | .offset = 0x200000, | |
284 | .size = 48*0x20000, | |
285 | }, | |
286 | { | |
287 | .name = "Root File System", | |
288 | .offset = 0x800000, | |
0d04eda1 | 289 | .size = MTDPART_SIZ_FULL, |
4ad916bc | 290 | }, |
6c009ab8 LW |
291 | }; |
292 | ||
6c009ab8 LW |
293 | |
294 | /** | |
593cd871 | 295 | * struct fsmc_nand_data - structure for FSMC NAND device state |
6c009ab8 | 296 | * |
593cd871 | 297 | * @pid: Part ID on the AMBA PrimeCell format |
6c009ab8 LW |
298 | * @mtd: MTD info for a NAND flash. |
299 | * @nand: Chip related info for a NAND flash. | |
6c009ab8 LW |
300 | * |
301 | * @ecc_place: ECC placing locations in oobfree type format. | |
302 | * @bank: Bank number for probed device. | |
303 | * @clk: Clock structure for FSMC. | |
304 | * | |
305 | * @data_va: NAND port for Data. | |
306 | * @cmd_va: NAND port for Command. | |
307 | * @addr_va: NAND port for Address. | |
308 | * @regs_va: FSMC regs base address. | |
309 | */ | |
310 | struct fsmc_nand_data { | |
593cd871 | 311 | u32 pid; |
6c009ab8 LW |
312 | struct mtd_info mtd; |
313 | struct nand_chip nand; | |
6c009ab8 LW |
314 | |
315 | struct fsmc_eccplace *ecc_place; | |
316 | unsigned int bank; | |
317 | struct clk *clk; | |
318 | ||
319 | struct resource *resregs; | |
320 | struct resource *rescmd; | |
321 | struct resource *resaddr; | |
322 | struct resource *resdata; | |
323 | ||
324 | void __iomem *data_va; | |
325 | void __iomem *cmd_va; | |
326 | void __iomem *addr_va; | |
327 | void __iomem *regs_va; | |
328 | ||
329 | void (*select_chip)(uint32_t bank, uint32_t busw); | |
330 | }; | |
331 | ||
332 | /* Assert CS signal based on chipnr */ | |
333 | static void fsmc_select_chip(struct mtd_info *mtd, int chipnr) | |
334 | { | |
335 | struct nand_chip *chip = mtd->priv; | |
336 | struct fsmc_nand_data *host; | |
337 | ||
338 | host = container_of(mtd, struct fsmc_nand_data, mtd); | |
339 | ||
340 | switch (chipnr) { | |
341 | case -1: | |
342 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); | |
343 | break; | |
344 | case 0: | |
345 | case 1: | |
346 | case 2: | |
347 | case 3: | |
348 | if (host->select_chip) | |
349 | host->select_chip(chipnr, | |
350 | chip->options & NAND_BUSWIDTH_16); | |
351 | break; | |
352 | ||
353 | default: | |
354 | BUG(); | |
355 | } | |
356 | } | |
357 | ||
358 | /* | |
359 | * fsmc_cmd_ctrl - For facilitaing Hardware access | |
360 | * This routine allows hardware specific access to control-lines(ALE,CLE) | |
361 | */ | |
362 | static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
363 | { | |
364 | struct nand_chip *this = mtd->priv; | |
365 | struct fsmc_nand_data *host = container_of(mtd, | |
366 | struct fsmc_nand_data, mtd); | |
367 | struct fsmc_regs *regs = host->regs_va; | |
368 | unsigned int bank = host->bank; | |
369 | ||
370 | if (ctrl & NAND_CTRL_CHANGE) { | |
371 | if (ctrl & NAND_CLE) { | |
372 | this->IO_ADDR_R = (void __iomem *)host->cmd_va; | |
373 | this->IO_ADDR_W = (void __iomem *)host->cmd_va; | |
374 | } else if (ctrl & NAND_ALE) { | |
375 | this->IO_ADDR_R = (void __iomem *)host->addr_va; | |
376 | this->IO_ADDR_W = (void __iomem *)host->addr_va; | |
377 | } else { | |
378 | this->IO_ADDR_R = (void __iomem *)host->data_va; | |
379 | this->IO_ADDR_W = (void __iomem *)host->data_va; | |
380 | } | |
381 | ||
382 | if (ctrl & NAND_NCE) { | |
383 | writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE, | |
384 | ®s->bank_regs[bank].pc); | |
385 | } else { | |
386 | writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE, | |
387 | ®s->bank_regs[bank].pc); | |
388 | } | |
389 | } | |
390 | ||
391 | mb(); | |
392 | ||
393 | if (cmd != NAND_CMD_NONE) | |
394 | writeb(cmd, this->IO_ADDR_W); | |
395 | } | |
396 | ||
397 | /* | |
398 | * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine | |
399 | * | |
400 | * This routine initializes timing parameters related to NAND memory access in | |
401 | * FSMC registers | |
402 | */ | |
403 | static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank, | |
404 | uint32_t busw) | |
405 | { | |
406 | uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; | |
407 | ||
408 | if (busw) | |
409 | writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc); | |
410 | else | |
411 | writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc); | |
412 | ||
413 | writel(readl(®s->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1, | |
414 | ®s->bank_regs[bank].pc); | |
415 | writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, | |
416 | ®s->bank_regs[bank].comm); | |
417 | writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, | |
418 | ®s->bank_regs[bank].attrib); | |
419 | } | |
420 | ||
421 | /* | |
422 | * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers | |
423 | */ | |
424 | static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) | |
425 | { | |
426 | struct fsmc_nand_data *host = container_of(mtd, | |
427 | struct fsmc_nand_data, mtd); | |
428 | struct fsmc_regs *regs = host->regs_va; | |
429 | uint32_t bank = host->bank; | |
430 | ||
431 | writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256, | |
432 | ®s->bank_regs[bank].pc); | |
433 | writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN, | |
434 | ®s->bank_regs[bank].pc); | |
435 | writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN, | |
436 | ®s->bank_regs[bank].pc); | |
437 | } | |
438 | ||
439 | /* | |
440 | * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by | |
25985edc | 441 | * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
442 | * max of 8-bits) |
443 | */ | |
444 | static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, | |
445 | uint8_t *ecc) | |
446 | { | |
447 | struct fsmc_nand_data *host = container_of(mtd, | |
448 | struct fsmc_nand_data, mtd); | |
449 | struct fsmc_regs *regs = host->regs_va; | |
450 | uint32_t bank = host->bank; | |
451 | uint32_t ecc_tmp; | |
452 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; | |
453 | ||
454 | do { | |
455 | if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY) | |
456 | break; | |
457 | else | |
458 | cond_resched(); | |
459 | } while (!time_after_eq(jiffies, deadline)); | |
460 | ||
461 | ecc_tmp = readl(®s->bank_regs[bank].ecc1); | |
462 | ecc[0] = (uint8_t) (ecc_tmp >> 0); | |
463 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | |
464 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | |
465 | ecc[3] = (uint8_t) (ecc_tmp >> 24); | |
466 | ||
467 | ecc_tmp = readl(®s->bank_regs[bank].ecc2); | |
468 | ecc[4] = (uint8_t) (ecc_tmp >> 0); | |
469 | ecc[5] = (uint8_t) (ecc_tmp >> 8); | |
470 | ecc[6] = (uint8_t) (ecc_tmp >> 16); | |
471 | ecc[7] = (uint8_t) (ecc_tmp >> 24); | |
472 | ||
473 | ecc_tmp = readl(®s->bank_regs[bank].ecc3); | |
474 | ecc[8] = (uint8_t) (ecc_tmp >> 0); | |
475 | ecc[9] = (uint8_t) (ecc_tmp >> 8); | |
476 | ecc[10] = (uint8_t) (ecc_tmp >> 16); | |
477 | ecc[11] = (uint8_t) (ecc_tmp >> 24); | |
478 | ||
479 | ecc_tmp = readl(®s->bank_regs[bank].sts); | |
480 | ecc[12] = (uint8_t) (ecc_tmp >> 16); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | /* | |
486 | * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by | |
25985edc | 487 | * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
488 | * max of 1-bit) |
489 | */ | |
490 | static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data, | |
491 | uint8_t *ecc) | |
492 | { | |
493 | struct fsmc_nand_data *host = container_of(mtd, | |
494 | struct fsmc_nand_data, mtd); | |
495 | struct fsmc_regs *regs = host->regs_va; | |
496 | uint32_t bank = host->bank; | |
497 | uint32_t ecc_tmp; | |
498 | ||
499 | ecc_tmp = readl(®s->bank_regs[bank].ecc1); | |
500 | ecc[0] = (uint8_t) (ecc_tmp >> 0); | |
501 | ecc[1] = (uint8_t) (ecc_tmp >> 8); | |
502 | ecc[2] = (uint8_t) (ecc_tmp >> 16); | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
519300cf VK |
507 | /* Count the number of 0's in buff upto a max of max_bits */ |
508 | static int count_written_bits(uint8_t *buff, int size, int max_bits) | |
509 | { | |
510 | int k, written_bits = 0; | |
511 | ||
512 | for (k = 0; k < size; k++) { | |
513 | written_bits += hweight8(~buff[k]); | |
514 | if (written_bits > max_bits) | |
515 | break; | |
516 | } | |
517 | ||
518 | return written_bits; | |
519 | } | |
520 | ||
6c009ab8 LW |
521 | /* |
522 | * fsmc_read_page_hwecc | |
523 | * @mtd: mtd info structure | |
524 | * @chip: nand chip info structure | |
525 | * @buf: buffer to store read data | |
526 | * @page: page number to read | |
527 | * | |
25985edc | 528 | * This routine is needed for fsmc version 8 as reading from NAND chip has to be |
6c009ab8 LW |
529 | * performed in a strict sequence as follows: |
530 | * data(512 byte) -> ecc(13 byte) | |
25985edc | 531 | * After this read, fsmc hardware generates and reports error data bits(up to a |
6c009ab8 LW |
532 | * max of 8 bits) |
533 | */ | |
534 | static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
535 | uint8_t *buf, int page) | |
536 | { | |
537 | struct fsmc_nand_data *host = container_of(mtd, | |
538 | struct fsmc_nand_data, mtd); | |
539 | struct fsmc_eccplace *ecc_place = host->ecc_place; | |
540 | int i, j, s, stat, eccsize = chip->ecc.size; | |
541 | int eccbytes = chip->ecc.bytes; | |
542 | int eccsteps = chip->ecc.steps; | |
543 | uint8_t *p = buf; | |
544 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
545 | uint8_t *ecc_code = chip->buffers->ecccode; | |
546 | int off, len, group = 0; | |
547 | /* | |
548 | * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we | |
549 | * end up reading 14 bytes (7 words) from oob. The local array is | |
550 | * to maintain word alignment | |
551 | */ | |
552 | uint16_t ecc_oob[7]; | |
553 | uint8_t *oob = (uint8_t *)&ecc_oob[0]; | |
554 | ||
555 | for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { | |
6c009ab8 LW |
556 | chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); |
557 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
558 | chip->read_buf(mtd, p, eccsize); | |
559 | ||
560 | for (j = 0; j < eccbytes;) { | |
561 | off = ecc_place->eccplace[group].offset; | |
562 | len = ecc_place->eccplace[group].length; | |
563 | group++; | |
564 | ||
565 | /* | |
566 | * length is intentionally kept a higher multiple of 2 | |
567 | * to read at least 13 bytes even in case of 16 bit NAND | |
568 | * devices | |
569 | */ | |
570 | len = roundup(len, 2); | |
571 | chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); | |
572 | chip->read_buf(mtd, oob + j, len); | |
573 | j += len; | |
574 | } | |
575 | ||
519300cf | 576 | memcpy(&ecc_code[i], oob, chip->ecc.bytes); |
6c009ab8 LW |
577 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
578 | ||
579 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
580 | if (stat < 0) | |
581 | mtd->ecc_stats.failed++; | |
582 | else | |
583 | mtd->ecc_stats.corrected += stat; | |
584 | } | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | /* | |
590 | * fsmc_correct_data | |
591 | * @mtd: mtd info structure | |
592 | * @dat: buffer of read data | |
593 | * @read_ecc: ecc read from device spare area | |
594 | * @calc_ecc: ecc calculated from read data | |
595 | * | |
596 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
597 | * offset informations of 13 bits each in 512 bytes of read data. | |
598 | */ | |
599 | static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat, | |
600 | uint8_t *read_ecc, uint8_t *calc_ecc) | |
601 | { | |
602 | struct fsmc_nand_data *host = container_of(mtd, | |
603 | struct fsmc_nand_data, mtd); | |
519300cf | 604 | struct nand_chip *chip = mtd->priv; |
6c009ab8 LW |
605 | struct fsmc_regs *regs = host->regs_va; |
606 | unsigned int bank = host->bank; | |
607 | uint16_t err_idx[8]; | |
608 | uint64_t ecc_data[2]; | |
609 | uint32_t num_err, i; | |
610 | ||
519300cf VK |
611 | num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF; |
612 | ||
613 | /* no bit flipping */ | |
614 | if (likely(num_err == 0)) | |
615 | return 0; | |
616 | ||
617 | /* too many errors */ | |
618 | if (unlikely(num_err > 8)) { | |
619 | /* | |
620 | * This is a temporary erase check. A newly erased page read | |
621 | * would result in an ecc error because the oob data is also | |
622 | * erased to FF and the calculated ecc for an FF data is not | |
623 | * FF..FF. | |
624 | * This is a workaround to skip performing correction in case | |
625 | * data is FF..FF | |
626 | * | |
627 | * Logic: | |
628 | * For every page, each bit written as 0 is counted until these | |
629 | * number of bits are greater than 8 (the maximum correction | |
630 | * capability of FSMC for each 512 + 13 bytes) | |
631 | */ | |
632 | ||
633 | int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); | |
634 | int bits_data = count_written_bits(dat, chip->ecc.size, 8); | |
635 | ||
636 | if ((bits_ecc + bits_data) <= 8) { | |
637 | if (bits_data) | |
638 | memset(dat, 0xff, chip->ecc.size); | |
639 | return bits_data; | |
640 | } | |
641 | ||
642 | return -EBADMSG; | |
643 | } | |
644 | ||
6c009ab8 | 645 | /* The calculated ecc is actually the correction index in data */ |
519300cf | 646 | memcpy(ecc_data, calc_ecc, chip->ecc.bytes); |
6c009ab8 LW |
647 | |
648 | /* | |
649 | * ------------------- calc_ecc[] bit wise -----------|--13 bits--| | |
650 | * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| | |
651 | * | |
652 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
653 | * offset informations of 13 bits each. calc_ecc is copied into a | |
654 | * uint64_t array and error offset indexes are populated in err_idx | |
655 | * array | |
656 | */ | |
657 | for (i = 0; i < 8; i++) { | |
658 | if (i == 4) { | |
659 | err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0]; | |
660 | ecc_data[1] >>= 1; | |
661 | continue; | |
662 | } | |
663 | err_idx[i] = (ecc_data[i/4] & 0x1FFF); | |
664 | ecc_data[i/4] >>= 13; | |
665 | } | |
666 | ||
667 | num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF; | |
668 | ||
669 | if (num_err == 0xF) | |
670 | return -EBADMSG; | |
671 | ||
672 | i = 0; | |
673 | while (num_err--) { | |
674 | change_bit(0, (unsigned long *)&err_idx[i]); | |
675 | change_bit(1, (unsigned long *)&err_idx[i]); | |
676 | ||
519300cf | 677 | if (err_idx[i] <= chip->ecc.size * 8) { |
6c009ab8 LW |
678 | change_bit(err_idx[i], (unsigned long *)dat); |
679 | i++; | |
680 | } | |
681 | } | |
682 | return i; | |
683 | } | |
684 | ||
685 | /* | |
686 | * fsmc_nand_probe - Probe function | |
687 | * @pdev: platform device structure | |
688 | */ | |
689 | static int __init fsmc_nand_probe(struct platform_device *pdev) | |
690 | { | |
691 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
692 | struct fsmc_nand_data *host; | |
693 | struct mtd_info *mtd; | |
694 | struct nand_chip *nand; | |
695 | struct fsmc_regs *regs; | |
696 | struct resource *res; | |
4ad916bc | 697 | int ret = 0; |
593cd871 LW |
698 | u32 pid; |
699 | int i; | |
6c009ab8 LW |
700 | |
701 | if (!pdata) { | |
702 | dev_err(&pdev->dev, "platform data is NULL\n"); | |
703 | return -EINVAL; | |
704 | } | |
705 | ||
706 | /* Allocate memory for the device structure (and zero it) */ | |
707 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
708 | if (!host) { | |
709 | dev_err(&pdev->dev, "failed to allocate device structure\n"); | |
710 | return -ENOMEM; | |
711 | } | |
712 | ||
713 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); | |
714 | if (!res) { | |
715 | ret = -EIO; | |
716 | goto err_probe1; | |
717 | } | |
718 | ||
719 | host->resdata = request_mem_region(res->start, resource_size(res), | |
720 | pdev->name); | |
721 | if (!host->resdata) { | |
722 | ret = -EIO; | |
723 | goto err_probe1; | |
724 | } | |
725 | ||
726 | host->data_va = ioremap(res->start, resource_size(res)); | |
727 | if (!host->data_va) { | |
728 | ret = -EIO; | |
729 | goto err_probe1; | |
730 | } | |
731 | ||
b2acc92e | 732 | host->resaddr = request_mem_region(res->start + pdata->ale_off, |
6c009ab8 LW |
733 | resource_size(res), pdev->name); |
734 | if (!host->resaddr) { | |
735 | ret = -EIO; | |
736 | goto err_probe1; | |
737 | } | |
738 | ||
b2acc92e SH |
739 | host->addr_va = ioremap(res->start + pdata->ale_off, |
740 | resource_size(res)); | |
6c009ab8 LW |
741 | if (!host->addr_va) { |
742 | ret = -EIO; | |
743 | goto err_probe1; | |
744 | } | |
745 | ||
b2acc92e | 746 | host->rescmd = request_mem_region(res->start + pdata->cle_off, |
6c009ab8 LW |
747 | resource_size(res), pdev->name); |
748 | if (!host->rescmd) { | |
749 | ret = -EIO; | |
750 | goto err_probe1; | |
751 | } | |
752 | ||
b2acc92e | 753 | host->cmd_va = ioremap(res->start + pdata->cle_off, resource_size(res)); |
6c009ab8 LW |
754 | if (!host->cmd_va) { |
755 | ret = -EIO; | |
756 | goto err_probe1; | |
757 | } | |
758 | ||
759 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); | |
760 | if (!res) { | |
761 | ret = -EIO; | |
762 | goto err_probe1; | |
763 | } | |
764 | ||
765 | host->resregs = request_mem_region(res->start, resource_size(res), | |
766 | pdev->name); | |
767 | if (!host->resregs) { | |
768 | ret = -EIO; | |
769 | goto err_probe1; | |
770 | } | |
771 | ||
772 | host->regs_va = ioremap(res->start, resource_size(res)); | |
773 | if (!host->regs_va) { | |
774 | ret = -EIO; | |
775 | goto err_probe1; | |
776 | } | |
777 | ||
778 | host->clk = clk_get(&pdev->dev, NULL); | |
779 | if (IS_ERR(host->clk)) { | |
780 | dev_err(&pdev->dev, "failed to fetch block clock\n"); | |
781 | ret = PTR_ERR(host->clk); | |
782 | host->clk = NULL; | |
783 | goto err_probe1; | |
784 | } | |
785 | ||
786 | ret = clk_enable(host->clk); | |
787 | if (ret) | |
788 | goto err_probe1; | |
789 | ||
593cd871 LW |
790 | /* |
791 | * This device ID is actually a common AMBA ID as used on the | |
792 | * AMBA PrimeCell bus. However it is not a PrimeCell. | |
793 | */ | |
794 | for (pid = 0, i = 0; i < 4; i++) | |
795 | pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8); | |
796 | host->pid = pid; | |
797 | dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, " | |
798 | "revision %02x, config %02x\n", | |
799 | AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), | |
800 | AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); | |
801 | ||
6c009ab8 LW |
802 | host->bank = pdata->bank; |
803 | host->select_chip = pdata->select_bank; | |
804 | regs = host->regs_va; | |
805 | ||
806 | /* Link all private pointers */ | |
807 | mtd = &host->mtd; | |
808 | nand = &host->nand; | |
809 | mtd->priv = nand; | |
810 | nand->priv = host; | |
811 | ||
812 | host->mtd.owner = THIS_MODULE; | |
813 | nand->IO_ADDR_R = host->data_va; | |
814 | nand->IO_ADDR_W = host->data_va; | |
815 | nand->cmd_ctrl = fsmc_cmd_ctrl; | |
816 | nand->chip_delay = 30; | |
817 | ||
818 | nand->ecc.mode = NAND_ECC_HW; | |
819 | nand->ecc.hwctl = fsmc_enable_hwecc; | |
820 | nand->ecc.size = 512; | |
821 | nand->options = pdata->options; | |
822 | nand->select_chip = fsmc_select_chip; | |
823 | ||
824 | if (pdata->width == FSMC_NAND_BW16) | |
825 | nand->options |= NAND_BUSWIDTH_16; | |
826 | ||
827 | fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16); | |
828 | ||
593cd871 | 829 | if (AMBA_REV_BITS(host->pid) >= 8) { |
6c009ab8 LW |
830 | nand->ecc.read_page = fsmc_read_page_hwecc; |
831 | nand->ecc.calculate = fsmc_read_hwecc_ecc4; | |
832 | nand->ecc.correct = fsmc_correct_data; | |
833 | nand->ecc.bytes = 13; | |
834 | } else { | |
835 | nand->ecc.calculate = fsmc_read_hwecc_ecc1; | |
836 | nand->ecc.correct = nand_correct_data; | |
837 | nand->ecc.bytes = 3; | |
838 | } | |
839 | ||
840 | /* | |
25985edc | 841 | * Scan to find existence of the device |
6c009ab8 LW |
842 | */ |
843 | if (nand_scan_ident(&host->mtd, 1, NULL)) { | |
844 | ret = -ENXIO; | |
845 | dev_err(&pdev->dev, "No NAND Device found!\n"); | |
846 | goto err_probe; | |
847 | } | |
848 | ||
593cd871 | 849 | if (AMBA_REV_BITS(host->pid) >= 8) { |
e29ee57b BY |
850 | switch (host->mtd.oobsize) { |
851 | case 16: | |
852 | nand->ecc.layout = &fsmc_ecc4_16_layout; | |
6c009ab8 | 853 | host->ecc_place = &fsmc_ecc4_sp_place; |
e29ee57b BY |
854 | break; |
855 | case 64: | |
856 | nand->ecc.layout = &fsmc_ecc4_64_layout; | |
857 | host->ecc_place = &fsmc_ecc4_lp_place; | |
858 | break; | |
859 | case 128: | |
860 | nand->ecc.layout = &fsmc_ecc4_128_layout; | |
861 | host->ecc_place = &fsmc_ecc4_lp_place; | |
862 | break; | |
863 | case 256: | |
864 | nand->ecc.layout = &fsmc_ecc4_256_layout; | |
6c009ab8 | 865 | host->ecc_place = &fsmc_ecc4_lp_place; |
e29ee57b BY |
866 | break; |
867 | default: | |
868 | printk(KERN_WARNING "No oob scheme defined for " | |
869 | "oobsize %d\n", mtd->oobsize); | |
870 | BUG(); | |
6c009ab8 LW |
871 | } |
872 | } else { | |
e29ee57b BY |
873 | switch (host->mtd.oobsize) { |
874 | case 16: | |
875 | nand->ecc.layout = &fsmc_ecc1_16_layout; | |
876 | break; | |
877 | case 64: | |
878 | nand->ecc.layout = &fsmc_ecc1_64_layout; | |
879 | break; | |
880 | case 128: | |
881 | nand->ecc.layout = &fsmc_ecc1_128_layout; | |
882 | break; | |
883 | default: | |
884 | printk(KERN_WARNING "No oob scheme defined for " | |
885 | "oobsize %d\n", mtd->oobsize); | |
886 | BUG(); | |
887 | } | |
6c009ab8 LW |
888 | } |
889 | ||
890 | /* Second stage of scan to fill MTD data-structures */ | |
891 | if (nand_scan_tail(&host->mtd)) { | |
892 | ret = -ENXIO; | |
893 | goto err_probe; | |
894 | } | |
895 | ||
896 | /* | |
897 | * The partition information can is accessed by (in the same precedence) | |
898 | * | |
899 | * command line through Bootloader, | |
900 | * platform data, | |
901 | * default partition information present in driver. | |
902 | */ | |
6c009ab8 | 903 | /* |
8d3f8bb8 | 904 | * Check for partition info passed |
6c009ab8 LW |
905 | */ |
906 | host->mtd.name = "nand"; | |
0d04eda1 DES |
907 | ret = mtd_device_parse_register(&host->mtd, NULL, 0, |
908 | host->mtd.size <= 0x04000000 ? | |
909 | partition_info_16KB_blk : | |
910 | partition_info_128KB_blk, | |
911 | host->mtd.size <= 0x04000000 ? | |
912 | ARRAY_SIZE(partition_info_16KB_blk) : | |
913 | ARRAY_SIZE(partition_info_128KB_blk)); | |
99335d00 | 914 | if (ret) |
6c009ab8 | 915 | goto err_probe; |
6c009ab8 LW |
916 | |
917 | platform_set_drvdata(pdev, host); | |
918 | dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); | |
919 | return 0; | |
920 | ||
921 | err_probe: | |
922 | clk_disable(host->clk); | |
923 | err_probe1: | |
924 | if (host->clk) | |
925 | clk_put(host->clk); | |
926 | if (host->regs_va) | |
927 | iounmap(host->regs_va); | |
928 | if (host->resregs) | |
929 | release_mem_region(host->resregs->start, | |
930 | resource_size(host->resregs)); | |
931 | if (host->cmd_va) | |
932 | iounmap(host->cmd_va); | |
933 | if (host->rescmd) | |
934 | release_mem_region(host->rescmd->start, | |
935 | resource_size(host->rescmd)); | |
936 | if (host->addr_va) | |
937 | iounmap(host->addr_va); | |
938 | if (host->resaddr) | |
939 | release_mem_region(host->resaddr->start, | |
940 | resource_size(host->resaddr)); | |
941 | if (host->data_va) | |
942 | iounmap(host->data_va); | |
943 | if (host->resdata) | |
944 | release_mem_region(host->resdata->start, | |
945 | resource_size(host->resdata)); | |
946 | ||
947 | kfree(host); | |
948 | return ret; | |
949 | } | |
950 | ||
951 | /* | |
952 | * Clean up routine | |
953 | */ | |
954 | static int fsmc_nand_remove(struct platform_device *pdev) | |
955 | { | |
956 | struct fsmc_nand_data *host = platform_get_drvdata(pdev); | |
957 | ||
958 | platform_set_drvdata(pdev, NULL); | |
959 | ||
960 | if (host) { | |
82e023ab | 961 | nand_release(&host->mtd); |
6c009ab8 LW |
962 | clk_disable(host->clk); |
963 | clk_put(host->clk); | |
964 | ||
965 | iounmap(host->regs_va); | |
966 | release_mem_region(host->resregs->start, | |
967 | resource_size(host->resregs)); | |
968 | iounmap(host->cmd_va); | |
969 | release_mem_region(host->rescmd->start, | |
970 | resource_size(host->rescmd)); | |
971 | iounmap(host->addr_va); | |
972 | release_mem_region(host->resaddr->start, | |
973 | resource_size(host->resaddr)); | |
974 | iounmap(host->data_va); | |
975 | release_mem_region(host->resdata->start, | |
976 | resource_size(host->resdata)); | |
977 | ||
978 | kfree(host); | |
979 | } | |
980 | return 0; | |
981 | } | |
982 | ||
983 | #ifdef CONFIG_PM | |
984 | static int fsmc_nand_suspend(struct device *dev) | |
985 | { | |
986 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
987 | if (host) | |
988 | clk_disable(host->clk); | |
989 | return 0; | |
990 | } | |
991 | ||
992 | static int fsmc_nand_resume(struct device *dev) | |
993 | { | |
994 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
995 | if (host) | |
996 | clk_enable(host->clk); | |
997 | return 0; | |
998 | } | |
999 | ||
1000 | static const struct dev_pm_ops fsmc_nand_pm_ops = { | |
1001 | .suspend = fsmc_nand_suspend, | |
1002 | .resume = fsmc_nand_resume, | |
1003 | }; | |
1004 | #endif | |
1005 | ||
1006 | static struct platform_driver fsmc_nand_driver = { | |
1007 | .remove = fsmc_nand_remove, | |
1008 | .driver = { | |
1009 | .owner = THIS_MODULE, | |
1010 | .name = "fsmc-nand", | |
1011 | #ifdef CONFIG_PM | |
1012 | .pm = &fsmc_nand_pm_ops, | |
1013 | #endif | |
1014 | }, | |
1015 | }; | |
1016 | ||
1017 | static int __init fsmc_nand_init(void) | |
1018 | { | |
1019 | return platform_driver_probe(&fsmc_nand_driver, | |
1020 | fsmc_nand_probe); | |
1021 | } | |
1022 | module_init(fsmc_nand_init); | |
1023 | ||
1024 | static void __exit fsmc_nand_exit(void) | |
1025 | { | |
1026 | platform_driver_unregister(&fsmc_nand_driver); | |
1027 | } | |
1028 | module_exit(fsmc_nand_exit); | |
1029 | ||
1030 | MODULE_LICENSE("GPL"); | |
1031 | MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); | |
1032 | MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); |