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mtd: bitflip_threshold added to mtd_info and sysfs
[linux-2.6-block.git] / drivers / mtd / nand / fsl_ifc_nand.c
CommitLineData
82771882
PK		 1/*
2 * Freescale Integrated Flash Controller NAND driver
3 *
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/slab.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/nand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/mtd/nand_ecc.h>
32#include <asm/fsl_ifc.h>
33
34#define ERR_BYTE 0xFF /* Value returned for read
35 bytes when read failed */
36#define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
37 for IFC NAND Machine */
38
39struct fsl_ifc_ctrl;
40
41/* mtd information per set */
42struct fsl_ifc_mtd {
43 struct mtd_info mtd;
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
46
47 struct device *dev;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
51};
52
53/* overview of the fsl ifc controller */
54struct fsl_ifc_nand_ctrl {
55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
57
58 u8 __iomem *addr; /* Address of assigned IFC buffer */
59 unsigned int page; /* Last page written to / read from */
60 unsigned int read_bytes;/* Number of bytes read during command */
61 unsigned int column; /* Saved column from SEQIN */
62 unsigned int index; /* Pointer to next byte to 'read' */
63 unsigned int oob; /* Non zero if operating on OOB data */
64 unsigned int eccread; /* Non zero for a full-page ECC read */
65 unsigned int counter; /* counter for the initializations */
66};
67
68static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
69
70/* 512-byte page with 4-bit ECC, 8-bit */
71static struct nand_ecclayout oob_512_8bit_ecc4 = {
72 .eccbytes = 8,
73 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
74 .oobfree = { {0, 5}, {6, 2} },
75};
76
77/* 512-byte page with 4-bit ECC, 16-bit */
78static struct nand_ecclayout oob_512_16bit_ecc4 = {
79 .eccbytes = 8,
80 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
81 .oobfree = { {2, 6}, },
82};
83
84/* 2048-byte page size with 4-bit ECC */
85static struct nand_ecclayout oob_2048_ecc4 = {
86 .eccbytes = 32,
87 .eccpos = {
88 8, 9, 10, 11, 12, 13, 14, 15,
89 16, 17, 18, 19, 20, 21, 22, 23,
90 24, 25, 26, 27, 28, 29, 30, 31,
91 32, 33, 34, 35, 36, 37, 38, 39,
92 },
93 .oobfree = { {2, 6}, {40, 24} },
94};
95
96/* 4096-byte page size with 4-bit ECC */
97static struct nand_ecclayout oob_4096_ecc4 = {
98 .eccbytes = 64,
99 .eccpos = {
100 8, 9, 10, 11, 12, 13, 14, 15,
101 16, 17, 18, 19, 20, 21, 22, 23,
102 24, 25, 26, 27, 28, 29, 30, 31,
103 32, 33, 34, 35, 36, 37, 38, 39,
104 40, 41, 42, 43, 44, 45, 46, 47,
105 48, 49, 50, 51, 52, 53, 54, 55,
106 56, 57, 58, 59, 60, 61, 62, 63,
107 64, 65, 66, 67, 68, 69, 70, 71,
108 },
109 .oobfree = { {2, 6}, {72, 56} },
110};
111
112/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
113static struct nand_ecclayout oob_4096_ecc8 = {
114 .eccbytes = 128,
115 .eccpos = {
116 8, 9, 10, 11, 12, 13, 14, 15,
117 16, 17, 18, 19, 20, 21, 22, 23,
118 24, 25, 26, 27, 28, 29, 30, 31,
119 32, 33, 34, 35, 36, 37, 38, 39,
120 40, 41, 42, 43, 44, 45, 46, 47,
121 48, 49, 50, 51, 52, 53, 54, 55,
122 56, 57, 58, 59, 60, 61, 62, 63,
123 64, 65, 66, 67, 68, 69, 70, 71,
124 72, 73, 74, 75, 76, 77, 78, 79,
125 80, 81, 82, 83, 84, 85, 86, 87,
126 88, 89, 90, 91, 92, 93, 94, 95,
127 96, 97, 98, 99, 100, 101, 102, 103,
128 104, 105, 106, 107, 108, 109, 110, 111,
129 112, 113, 114, 115, 116, 117, 118, 119,
130 120, 121, 122, 123, 124, 125, 126, 127,
131 128, 129, 130, 131, 132, 133, 134, 135,
132 },
133 .oobfree = { {2, 6}, {136, 82} },
134};
135
136
137/*
138 * Generic flash bbt descriptors
139 */
140static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
141static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
142
143static struct nand_bbt_descr bbt_main_descr = {
144 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
145 NAND_BBT_2BIT | NAND_BBT_VERSION,
146 .offs = 2, /* 0 on 8-bit small page */
147 .len = 4,
148 .veroffs = 6,
149 .maxblocks = 4,
150 .pattern = bbt_pattern,
151};
152
153static struct nand_bbt_descr bbt_mirror_descr = {
154 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
155 NAND_BBT_2BIT | NAND_BBT_VERSION,
156 .offs = 2, /* 0 on 8-bit small page */
157 .len = 4,
158 .veroffs = 6,
159 .maxblocks = 4,
160 .pattern = mirror_pattern,
161};
162
163/*
164 * Set up the IFC hardware block and page address fields, and the ifc nand
165 * structure addr field to point to the correct IFC buffer in memory
166 */
167static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
168{
169 struct nand_chip *chip = mtd->priv;
170 struct fsl_ifc_mtd *priv = chip->priv;
171 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
172 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
173 int buf_num;
174
175 ifc_nand_ctrl->page = page_addr;
176 /* Program ROW0/COL0 */
177 out_be32(&ifc->ifc_nand.row0, page_addr);
178 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
179
180 buf_num = page_addr & priv->bufnum_mask;
181
182 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
183 ifc_nand_ctrl->index = column;
184
185 /* for OOB data point to the second half of the buffer */
186 if (oob)
187 ifc_nand_ctrl->index += mtd->writesize;
188}
189
190static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
191{
192 struct nand_chip *chip = mtd->priv;
193 struct fsl_ifc_mtd *priv = chip->priv;
194 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
195 u32 __iomem *mainarea = (u32 *)addr;
196 u8 __iomem *oob = addr + mtd->writesize;
197 int i;
198
199 for (i = 0; i < mtd->writesize / 4; i++) {
200 if (__raw_readl(&mainarea[i]) != 0xffffffff)
201 return 0;
202 }
203
204 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
205 int pos = chip->ecc.layout->eccpos[i];
206
207 if (__raw_readb(&oob[pos]) != 0xff)
208 return 0;
209 }
210
211 return 1;
212}
213
214/* returns nonzero if entire page is blank */
215static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
216 u32 *eccstat, unsigned int bufnum)
217{
218 u32 reg = eccstat[bufnum / 4];
219 int errors;
220
221 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
222
223 return errors;
224}
225
226/*
227 * execute IFC NAND command and wait for it to complete
228 */
229static void fsl_ifc_run_command(struct mtd_info *mtd)
230{
231 struct nand_chip *chip = mtd->priv;
232 struct fsl_ifc_mtd *priv = chip->priv;
233 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
234 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
235 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
236 u32 eccstat[4];
237 int i;
238
239 /* set the chip select for NAND Transaction */
240 out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
241
242 dev_vdbg(priv->dev,
243 "%s: fir0=%08x fcr0=%08x\n",
244 __func__,
245 in_be32(&ifc->ifc_nand.nand_fir0),
246 in_be32(&ifc->ifc_nand.nand_fcr0));
247
248 ctrl->nand_stat = 0;
249
250 /* start read/write seq */
251 out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
252
253 /* wait for command complete flag or timeout */
254 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
255 IFC_TIMEOUT_MSECS * HZ/1000);
256
257 /* ctrl->nand_stat will be updated from IRQ context */
258 if (!ctrl->nand_stat)
259 dev_err(priv->dev, "Controller is not responding\n");
260 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
261 dev_err(priv->dev, "NAND Flash Timeout Error\n");
262 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
263 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
264
265 if (nctrl->eccread) {
266 int errors;
267 int bufnum = nctrl->page & priv->bufnum_mask;
268 int sector = bufnum * chip->ecc.steps;
269 int sector_end = sector + chip->ecc.steps - 1;
270
271 for (i = sector / 4; i <= sector_end / 4; i++)
272 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
273
274 for (i = sector; i <= sector_end; i++) {
275 errors = check_read_ecc(mtd, ctrl, eccstat, i);
276
277 if (errors == 15) {
278 /*
279 * Uncorrectable error.
280 * OK only if the whole page is blank.
281 *
282 * We disable ECCER reporting due to...
283 * erratum IFC-A002770 -- so report it now if we
284 * see an uncorrectable error in ECCSTAT.
285 */
286 if (!is_blank(mtd, bufnum))
287 ctrl->nand_stat |=
288 IFC_NAND_EVTER_STAT_ECCER;
289 break;
290 }
291
292 mtd->ecc_stats.corrected += errors;
293 }
294
295 nctrl->eccread = 0;
296 }
297}
298
299static void fsl_ifc_do_read(struct nand_chip *chip,
300 int oob,
301 struct mtd_info *mtd)
302{
303 struct fsl_ifc_mtd *priv = chip->priv;
304 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
305 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
306
307 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
308 if (mtd->writesize > 512) {
309 out_be32(&ifc->ifc_nand.nand_fir0,
310 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
311 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
312 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
313 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
314 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
315 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
316
317 out_be32(&ifc->ifc_nand.nand_fcr0,
318 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
319 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
320 } else {
321 out_be32(&ifc->ifc_nand.nand_fir0,
322 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
323 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
324 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
325 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
326 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
327
328 if (oob)
329 out_be32(&ifc->ifc_nand.nand_fcr0,
330 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
331 else
332 out_be32(&ifc->ifc_nand.nand_fcr0,
333 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
334 }
335}
336
337/* cmdfunc send commands to the IFC NAND Machine */
338static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
339 int column, int page_addr) {
340 struct nand_chip *chip = mtd->priv;
341 struct fsl_ifc_mtd *priv = chip->priv;
342 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
343 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
344
345 /* clear the read buffer */
346 ifc_nand_ctrl->read_bytes = 0;
347 if (command != NAND_CMD_PAGEPROG)
348 ifc_nand_ctrl->index = 0;
349
350 switch (command) {
351 /* READ0 read the entire buffer to use hardware ECC. */
352 case NAND_CMD_READ0:
353 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
354 set_addr(mtd, 0, page_addr, 0);
355
356 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
357 ifc_nand_ctrl->index += column;
358
359 if (chip->ecc.mode == NAND_ECC_HW)
360 ifc_nand_ctrl->eccread = 1;
361
362 fsl_ifc_do_read(chip, 0, mtd);
363 fsl_ifc_run_command(mtd);
364 return;
365
366 /* READOOB reads only the OOB because no ECC is performed. */
367 case NAND_CMD_READOOB:
368 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
369 set_addr(mtd, column, page_addr, 1);
370
371 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
372
373 fsl_ifc_do_read(chip, 1, mtd);
374 fsl_ifc_run_command(mtd);
375
376 return;
377
82771882 378 case NAND_CMD_READID:
59fdd5b9
PK		 379 case NAND_CMD_PARAM: {
380 int timing = IFC_FIR_OP_RB;
381 if (command == NAND_CMD_PARAM)
382 timing = IFC_FIR_OP_RBCD;
383
82771882
PK		 384 out_be32(&ifc->ifc_nand.nand_fir0,
385 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
386 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
59fdd5b9 387 (timing << IFC_NAND_FIR0_OP2_SHIFT));
82771882 388 out_be32(&ifc->ifc_nand.nand_fcr0,
59fdd5b9
PK		 389 command << IFC_NAND_FCR0_CMD0_SHIFT);
390 out_be32(&ifc->ifc_nand.row3, column);
391
392 /*
393 * although currently it's 8 bytes for READID, we always read
394 * the maximum 256 bytes(for PARAM)
395 */
396 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
397 ifc_nand_ctrl->read_bytes = 256;
82771882
PK		 398
399 set_addr(mtd, 0, 0, 0);
400 fsl_ifc_run_command(mtd);
401 return;
59fdd5b9 402 }
82771882
PK		 403
404 /* ERASE1 stores the block and page address */
405 case NAND_CMD_ERASE1:
406 set_addr(mtd, 0, page_addr, 0);
407 return;
408
409 /* ERASE2 uses the block and page address from ERASE1 */
410 case NAND_CMD_ERASE2:
411 out_be32(&ifc->ifc_nand.nand_fir0,
412 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
413 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
414 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
415
416 out_be32(&ifc->ifc_nand.nand_fcr0,
417 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
418 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
419
420 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
421 ifc_nand_ctrl->read_bytes = 0;
422 fsl_ifc_run_command(mtd);
423 return;
424
425 /* SEQIN sets up the addr buffer and all registers except the length */
426 case NAND_CMD_SEQIN: {
427 u32 nand_fcr0;
428 ifc_nand_ctrl->column = column;
429 ifc_nand_ctrl->oob = 0;
430
431 if (mtd->writesize > 512) {
432 nand_fcr0 =
433 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
434 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
435
436 out_be32(&ifc->ifc_nand.nand_fir0,
437 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
438 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
439 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
440 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
441 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
442 } else {
443 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
444 IFC_NAND_FCR0_CMD1_SHIFT) |
445 (NAND_CMD_SEQIN <<
446 IFC_NAND_FCR0_CMD2_SHIFT));
447
448 out_be32(&ifc->ifc_nand.nand_fir0,
449 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
450 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
451 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
452 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
453 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
454 out_be32(&ifc->ifc_nand.nand_fir1,
455 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
456
457 if (column >= mtd->writesize)
458 nand_fcr0 |=
459 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
460 else
461 nand_fcr0 |=
462 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
463 }
464
465 if (column >= mtd->writesize) {
466 /* OOB area --> READOOB */
467 column -= mtd->writesize;
468 ifc_nand_ctrl->oob = 1;
469 }
470 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
471 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
472 return;
473 }
474
475 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
476 case NAND_CMD_PAGEPROG: {
477 if (ifc_nand_ctrl->oob) {
478 out_be32(&ifc->ifc_nand.nand_fbcr,
479 ifc_nand_ctrl->index - ifc_nand_ctrl->column);
480 } else {
481 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
482 }
483
484 fsl_ifc_run_command(mtd);
485 return;
486 }
487
488 case NAND_CMD_STATUS:
489 out_be32(&ifc->ifc_nand.nand_fir0,
490 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
491 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
492 out_be32(&ifc->ifc_nand.nand_fcr0,
493 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
494 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
495 set_addr(mtd, 0, 0, 0);
496 ifc_nand_ctrl->read_bytes = 1;
497
498 fsl_ifc_run_command(mtd);
499
500 /*
501 * The chip always seems to report that it is
502 * write-protected, even when it is not.
503 */
504 setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
505 return;
506
507 case NAND_CMD_RESET:
508 out_be32(&ifc->ifc_nand.nand_fir0,
509 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
510 out_be32(&ifc->ifc_nand.nand_fcr0,
511 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
512 fsl_ifc_run_command(mtd);
513 return;
514
515 default:
516 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
517 __func__, command);
518 }
519}
520
521static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
522{
523 /* The hardware does not seem to support multiple
524 * chips per bank.
525 */
526}
527
528/*
529 * Write buf to the IFC NAND Controller Data Buffer
530 */
531static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
532{
533 struct nand_chip *chip = mtd->priv;
534 struct fsl_ifc_mtd *priv = chip->priv;
535 unsigned int bufsize = mtd->writesize + mtd->oobsize;
536
537 if (len <= 0) {
538 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
539 return;
540 }
541
542 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
543 dev_err(priv->dev,
544 "%s: beyond end of buffer (%d requested, %u available)\n",
545 __func__, len, bufsize - ifc_nand_ctrl->index);
546 len = bufsize - ifc_nand_ctrl->index;
547 }
548
549 memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
550 ifc_nand_ctrl->index += len;
551}
552
553/*
554 * Read a byte from either the IFC hardware buffer
555 * read function for 8-bit buswidth
556 */
557static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
558{
559 struct nand_chip *chip = mtd->priv;
560 struct fsl_ifc_mtd *priv = chip->priv;
561
562 /*
563 * If there are still bytes in the IFC buffer, then use the
564 * next byte.
565 */
566 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
567 return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
568
569 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
570 return ERR_BYTE;
571}
572
573/*
574 * Read two bytes from the IFC hardware buffer
575 * read function for 16-bit buswith
576 */
577static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
578{
579 struct nand_chip *chip = mtd->priv;
580 struct fsl_ifc_mtd *priv = chip->priv;
581 uint16_t data;
582
583 /*
584 * If there are still bytes in the IFC buffer, then use the
585 * next byte.
586 */
587 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
588 data = in_be16((uint16_t *)&ifc_nand_ctrl->
589 addr[ifc_nand_ctrl->index]);
590 ifc_nand_ctrl->index += 2;
591 return (uint8_t) data;
592 }
593
594 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
595 return ERR_BYTE;
596}
597
598/*
599 * Read from the IFC Controller Data Buffer
600 */
601static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
602{
603 struct nand_chip *chip = mtd->priv;
604 struct fsl_ifc_mtd *priv = chip->priv;
605 int avail;
606
607 if (len < 0) {
608 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
609 return;
610 }
611
612 avail = min((unsigned int)len,
613 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
614 memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
615 ifc_nand_ctrl->index += avail;
616
617 if (len > avail)
618 dev_err(priv->dev,
619 "%s: beyond end of buffer (%d requested, %d available)\n",
620 __func__, len, avail);
621}
622
623/*
624 * Verify buffer against the IFC Controller Data Buffer
625 */
626static int fsl_ifc_verify_buf(struct mtd_info *mtd,
627 const u_char *buf, int len)
628{
629 struct nand_chip *chip = mtd->priv;
630 struct fsl_ifc_mtd *priv = chip->priv;
631 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
632 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
633 int i;
634
635 if (len < 0) {
636 dev_err(priv->dev, "%s: write_buf of %d bytes", __func__, len);
637 return -EINVAL;
638 }
639
640 if ((unsigned int)len > nctrl->read_bytes - nctrl->index) {
641 dev_err(priv->dev,
642 "%s: beyond end of buffer (%d requested, %u available)\n",
643 __func__, len, nctrl->read_bytes - nctrl->index);
644
645 nctrl->index = nctrl->read_bytes;
646 return -EINVAL;
647 }
648
649 for (i = 0; i < len; i++)
650 if (in_8(&nctrl->addr[nctrl->index + i]) != buf[i])
651 break;
652
653 nctrl->index += len;
654
655 if (i != len)
656 return -EIO;
657 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
658 return -EIO;
659
660 return 0;
661}
662
663/*
664 * This function is called after Program and Erase Operations to
665 * check for success or failure.
666 */
667static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
668{
669 struct fsl_ifc_mtd *priv = chip->priv;
670 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
671 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
672 u32 nand_fsr;
673
674 /* Use READ_STATUS command, but wait for the device to be ready */
675 out_be32(&ifc->ifc_nand.nand_fir0,
676 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
677 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
678 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
679 IFC_NAND_FCR0_CMD0_SHIFT);
680 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
681 set_addr(mtd, 0, 0, 0);
682 ifc_nand_ctrl->read_bytes = 1;
683
684 fsl_ifc_run_command(mtd);
685
686 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
687
688 /*
689 * The chip always seems to report that it is
690 * write-protected, even when it is not.
691 */
692 return nand_fsr | NAND_STATUS_WP;
693}
694
695static int fsl_ifc_read_page(struct mtd_info *mtd,
696 struct nand_chip *chip,
697 uint8_t *buf, int page)
698{
699 struct fsl_ifc_mtd *priv = chip->priv;
700 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
701
702 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
703 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
704
705 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
706 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
707
708 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
709 mtd->ecc_stats.failed++;
710
711 return 0;
712}
713
714/* ECC will be calculated automatically, and errors will be detected in
715 * waitfunc.
716 */
717static void fsl_ifc_write_page(struct mtd_info *mtd,
718 struct nand_chip *chip,
719 const uint8_t *buf)
720{
721 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
722 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
723}
724
725static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
726{
727 struct nand_chip *chip = mtd->priv;
728 struct fsl_ifc_mtd *priv = chip->priv;
729
730 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
731 chip->numchips);
732 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
733 chip->chipsize);
734 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
735 chip->pagemask);
736 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
737 chip->chip_delay);
738 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
739 chip->badblockpos);
740 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
741 chip->chip_shift);
742 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
743 chip->page_shift);
744 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
745 chip->phys_erase_shift);
746 dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__,
747 chip->ecclayout);
748 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
749 chip->ecc.mode);
750 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
751 chip->ecc.steps);
752 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
753 chip->ecc.bytes);
754 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
755 chip->ecc.total);
756 dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
757 chip->ecc.layout);
758 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
759 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
760 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
761 mtd->erasesize);
762 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
763 mtd->writesize);
764 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
765 mtd->oobsize);
766
767 return 0;
768}
769
770static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
771{
772 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
773 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
774 struct nand_chip *chip = &priv->chip;
775 struct nand_ecclayout *layout;
776 u32 csor;
777
778 /* Fill in fsl_ifc_mtd structure */
779 priv->mtd.priv = chip;
780 priv->mtd.owner = THIS_MODULE;
781
782 /* fill in nand_chip structure */
783 /* set up function call table */
784 if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
785 chip->read_byte = fsl_ifc_read_byte16;
786 else
787 chip->read_byte = fsl_ifc_read_byte;
788
789 chip->write_buf = fsl_ifc_write_buf;
790 chip->read_buf = fsl_ifc_read_buf;
791 chip->verify_buf = fsl_ifc_verify_buf;
792 chip->select_chip = fsl_ifc_select_chip;
793 chip->cmdfunc = fsl_ifc_cmdfunc;
794 chip->waitfunc = fsl_ifc_wait;
795
796 chip->bbt_td = &bbt_main_descr;
797 chip->bbt_md = &bbt_mirror_descr;
798
799 out_be32(&ifc->ifc_nand.ncfgr, 0x0);
800
801 /* set up nand options */
802 chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
803 chip->bbt_options = NAND_BBT_USE_FLASH;
804
805
806 if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
807 chip->read_byte = fsl_ifc_read_byte16;
808 chip->options |= NAND_BUSWIDTH_16;
809 } else {
810 chip->read_byte = fsl_ifc_read_byte;
811 }
812
813 chip->controller = &ifc_nand_ctrl->controller;
814 chip->priv = priv;
815
816 chip->ecc.read_page = fsl_ifc_read_page;
817 chip->ecc.write_page = fsl_ifc_write_page;
818
819 csor = in_be32(&ifc->csor_cs[priv->bank].csor);
820
821 /* Hardware generates ECC per 512 Bytes */
822 chip->ecc.size = 512;
823 chip->ecc.bytes = 8;
44df4d11 824 chip->ecc.strength = 4;
82771882
PK		 825
826 switch (csor & CSOR_NAND_PGS_MASK) {
827 case CSOR_NAND_PGS_512:
828 if (chip->options & NAND_BUSWIDTH_16) {
829 layout = &oob_512_16bit_ecc4;
830 } else {
831 layout = &oob_512_8bit_ecc4;
832
833 /* Avoid conflict with bad block marker */
834 bbt_main_descr.offs = 0;
835 bbt_mirror_descr.offs = 0;
836 }
837
838 priv->bufnum_mask = 15;
839 break;
840
841 case CSOR_NAND_PGS_2K:
842 layout = &oob_2048_ecc4;
843 priv->bufnum_mask = 3;
844 break;
845
846 case CSOR_NAND_PGS_4K:
847 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
848 CSOR_NAND_ECC_MODE_4) {
849 layout = &oob_4096_ecc4;
850 } else {
851 layout = &oob_4096_ecc8;
852 chip->ecc.bytes = 16;
853 }
854
855 priv->bufnum_mask = 1;
856 break;
857
858 default:
859 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
860 return -ENODEV;
861 }
862
863 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
864 if (csor & CSOR_NAND_ECC_DEC_EN) {
865 chip->ecc.mode = NAND_ECC_HW;
866 chip->ecc.layout = layout;
867 } else {
868 chip->ecc.mode = NAND_ECC_SOFT;
869 }
870
871 return 0;
872}
873
874static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
875{
876 nand_release(&priv->mtd);
877
878 kfree(priv->mtd.name);
879
880 if (priv->vbase)
881 iounmap(priv->vbase);
882
883 ifc_nand_ctrl->chips[priv->bank] = NULL;
884 dev_set_drvdata(priv->dev, NULL);
885 kfree(priv);
886
887 return 0;
888}
889
890static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
891 phys_addr_t addr)
892{
893 u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr);
894
895 if (!(cspr & CSPR_V))
896 return 0;
897 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
898 return 0;
899
900 return (cspr & CSPR_BA) == convert_ifc_address(addr);
901}
902
903static DEFINE_MUTEX(fsl_ifc_nand_mutex);
904
905static int __devinit fsl_ifc_nand_probe(struct platform_device *dev)
906{
907 struct fsl_ifc_regs __iomem *ifc;
908 struct fsl_ifc_mtd *priv;
909 struct resource res;
910 static const char *part_probe_types[]
911 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
912 int ret;
913 int bank;
914 struct device_node *node = dev->dev.of_node;
915 struct mtd_part_parser_data ppdata;
916
917 ppdata.of_node = dev->dev.of_node;
918 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
919 return -ENODEV;
920 ifc = fsl_ifc_ctrl_dev->regs;
921
922 /* get, allocate and map the memory resource */
923 ret = of_address_to_resource(node, 0, &res);
924 if (ret) {
925 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
926 return ret;
927 }
928
929 /* find which chip select it is connected to */
930 for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
931 if (match_bank(ifc, bank, res.start))
932 break;
933 }
934
935 if (bank >= FSL_IFC_BANK_COUNT) {
936 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
937 __func__);
938 return -ENODEV;
939 }
940
941 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
942 if (!priv)
943 return -ENOMEM;
944
945 mutex_lock(&fsl_ifc_nand_mutex);
946 if (!fsl_ifc_ctrl_dev->nand) {
947 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
948 if (!ifc_nand_ctrl) {
949 dev_err(&dev->dev, "failed to allocate memory\n");
950 mutex_unlock(&fsl_ifc_nand_mutex);
951 return -ENOMEM;
952 }
953
954 ifc_nand_ctrl->read_bytes = 0;
955 ifc_nand_ctrl->index = 0;
956 ifc_nand_ctrl->addr = NULL;
957 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
958
959 spin_lock_init(&ifc_nand_ctrl->controller.lock);
960 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
961 } else {
962 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
963 }
964 mutex_unlock(&fsl_ifc_nand_mutex);
965
966 ifc_nand_ctrl->chips[bank] = priv;
967 priv->bank = bank;
968 priv->ctrl = fsl_ifc_ctrl_dev;
969 priv->dev = &dev->dev;
970
971 priv->vbase = ioremap(res.start, resource_size(&res));
972 if (!priv->vbase) {
973 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
974 ret = -ENOMEM;
975 goto err;
976 }
977
978 dev_set_drvdata(priv->dev, priv);
979
980 out_be32(&ifc->ifc_nand.nand_evter_en,
981 IFC_NAND_EVTER_EN_OPC_EN |
982 IFC_NAND_EVTER_EN_FTOER_EN |
983 IFC_NAND_EVTER_EN_WPER_EN);
984
985 /* enable NAND Machine Interrupts */
986 out_be32(&ifc->ifc_nand.nand_evter_intr_en,
987 IFC_NAND_EVTER_INTR_OPCIR_EN |
988 IFC_NAND_EVTER_INTR_FTOERIR_EN |
989 IFC_NAND_EVTER_INTR_WPERIR_EN);
990
991 priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
992 if (!priv->mtd.name) {
993 ret = -ENOMEM;
994 goto err;
995 }
996
997 ret = fsl_ifc_chip_init(priv);
998 if (ret)
999 goto err;
1000
1001 ret = nand_scan_ident(&priv->mtd, 1, NULL);
1002 if (ret)
1003 goto err;
1004
1005 ret = fsl_ifc_chip_init_tail(&priv->mtd);
1006 if (ret)
1007 goto err;
1008
1009 ret = nand_scan_tail(&priv->mtd);
1010 if (ret)
1011 goto err;
1012
1013 /* First look for RedBoot table or partitions on the command
1014 * line, these take precedence over device tree information */
1015 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1016 NULL, 0);
1017
1018 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1019 (unsigned long long)res.start, priv->bank);
1020 return 0;
1021
1022err:
1023 fsl_ifc_chip_remove(priv);
1024 return ret;
1025}
1026
1027static int fsl_ifc_nand_remove(struct platform_device *dev)
1028{
1029 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1030
1031 fsl_ifc_chip_remove(priv);
1032
1033 mutex_lock(&fsl_ifc_nand_mutex);
1034 ifc_nand_ctrl->counter--;
1035 if (!ifc_nand_ctrl->counter) {
1036 fsl_ifc_ctrl_dev->nand = NULL;
1037 kfree(ifc_nand_ctrl);
1038 }
1039 mutex_unlock(&fsl_ifc_nand_mutex);
1040
1041 return 0;
1042}
1043
1044static const struct of_device_id fsl_ifc_nand_match[] = {
1045 {
1046 .compatible = "fsl,ifc-nand",
1047 },
1048 {}
1049};
1050
1051static struct platform_driver fsl_ifc_nand_driver = {
1052 .driver = {
1053 .name = "fsl,ifc-nand",
1054 .owner = THIS_MODULE,
1055 .of_match_table = fsl_ifc_nand_match,
1056 },
1057 .probe = fsl_ifc_nand_probe,
1058 .remove = fsl_ifc_nand_remove,
1059};
1060
1061static int __init fsl_ifc_nand_init(void)
1062{
1063 int ret;
1064
1065 ret = platform_driver_register(&fsl_ifc_nand_driver);
1066 if (ret)
1067 printk(KERN_ERR "fsl-ifc: Failed to register platform"
1068 "driver\n");
1069
1070 return ret;
1071}
1072
1073static void __exit fsl_ifc_nand_exit(void)
1074{
1075 platform_driver_unregister(&fsl_ifc_nand_driver);
1076}
1077
1078module_init(fsl_ifc_nand_init);
1079module_exit(fsl_ifc_nand_exit);
1080
1081MODULE_LICENSE("GPL");
1082MODULE_AUTHOR("Freescale");
1083MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
Linux 6.x block layer and io_uring tree(s)