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82771882 PK |
1 | /* |
2 | * Freescale Integrated Flash Controller NAND driver | |
3 | * | |
4 | * Copyright 2011-2012 Freescale Semiconductor, Inc | |
5 | * | |
6 | * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/types.h> | |
82771882 | 25 | #include <linux/kernel.h> |
5af50730 | 26 | #include <linux/of_address.h> |
82771882 PK |
27 | #include <linux/slab.h> |
28 | #include <linux/mtd/mtd.h> | |
d4092d76 | 29 | #include <linux/mtd/rawnand.h> |
82771882 PK |
30 | #include <linux/mtd/partitions.h> |
31 | #include <linux/mtd/nand_ecc.h> | |
d2ae2e20 | 32 | #include <linux/fsl_ifc.h> |
82771882 PK |
33 | |
34 | #define ERR_BYTE 0xFF /* Value returned for read | |
35 | bytes when read failed */ | |
36 | #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait | |
37 | for IFC NAND Machine */ | |
38 | ||
39 | struct fsl_ifc_ctrl; | |
40 | ||
41 | /* mtd information per set */ | |
42 | struct fsl_ifc_mtd { | |
82771882 PK |
43 | struct nand_chip chip; |
44 | struct fsl_ifc_ctrl *ctrl; | |
45 | ||
46 | struct device *dev; | |
47 | int bank; /* Chip select bank number */ | |
48 | unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ | |
49 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
50 | }; | |
51 | ||
52 | /* overview of the fsl ifc controller */ | |
53 | struct fsl_ifc_nand_ctrl { | |
54 | struct nand_hw_control controller; | |
55 | struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT]; | |
56 | ||
4454406e | 57 | void __iomem *addr; /* Address of assigned IFC buffer */ |
82771882 PK |
58 | unsigned int page; /* Last page written to / read from */ |
59 | unsigned int read_bytes;/* Number of bytes read during command */ | |
60 | unsigned int column; /* Saved column from SEQIN */ | |
61 | unsigned int index; /* Pointer to next byte to 'read' */ | |
62 | unsigned int oob; /* Non zero if operating on OOB data */ | |
63 | unsigned int eccread; /* Non zero for a full-page ECC read */ | |
64 | unsigned int counter; /* counter for the initializations */ | |
3f91e94f | 65 | unsigned int max_bitflips; /* Saved during READ0 cmd */ |
82771882 PK |
66 | }; |
67 | ||
68 | static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl; | |
69 | ||
82771882 PK |
70 | /* |
71 | * Generic flash bbt descriptors | |
72 | */ | |
73 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
74 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
75 | ||
76 | static struct nand_bbt_descr bbt_main_descr = { | |
77 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
78 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
79 | .offs = 2, /* 0 on 8-bit small page */ | |
80 | .len = 4, | |
81 | .veroffs = 6, | |
82 | .maxblocks = 4, | |
83 | .pattern = bbt_pattern, | |
84 | }; | |
85 | ||
86 | static struct nand_bbt_descr bbt_mirror_descr = { | |
87 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
88 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
89 | .offs = 2, /* 0 on 8-bit small page */ | |
90 | .len = 4, | |
91 | .veroffs = 6, | |
92 | .maxblocks = 4, | |
93 | .pattern = mirror_pattern, | |
94 | }; | |
95 | ||
caf5129e BB |
96 | static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section, |
97 | struct mtd_oob_region *oobregion) | |
98 | { | |
99 | struct nand_chip *chip = mtd_to_nand(mtd); | |
100 | ||
101 | if (section) | |
102 | return -ERANGE; | |
103 | ||
104 | oobregion->offset = 8; | |
105 | oobregion->length = chip->ecc.total; | |
106 | ||
107 | return 0; | |
108 | } | |
109 | ||
110 | static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section, | |
111 | struct mtd_oob_region *oobregion) | |
112 | { | |
113 | struct nand_chip *chip = mtd_to_nand(mtd); | |
114 | ||
115 | if (section > 1) | |
116 | return -ERANGE; | |
117 | ||
118 | if (mtd->writesize == 512 && | |
119 | !(chip->options & NAND_BUSWIDTH_16)) { | |
120 | if (!section) { | |
121 | oobregion->offset = 0; | |
122 | oobregion->length = 5; | |
123 | } else { | |
124 | oobregion->offset = 6; | |
125 | oobregion->length = 2; | |
126 | } | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | if (!section) { | |
132 | oobregion->offset = 2; | |
133 | oobregion->length = 6; | |
134 | } else { | |
135 | oobregion->offset = chip->ecc.total + 8; | |
136 | oobregion->length = mtd->oobsize - oobregion->offset; | |
137 | } | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = { | |
143 | .ecc = fsl_ifc_ooblayout_ecc, | |
144 | .free = fsl_ifc_ooblayout_free, | |
145 | }; | |
146 | ||
82771882 PK |
147 | /* |
148 | * Set up the IFC hardware block and page address fields, and the ifc nand | |
149 | * structure addr field to point to the correct IFC buffer in memory | |
150 | */ | |
151 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
152 | { | |
4bd4ebcc | 153 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 154 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 155 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 156 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
157 | int buf_num; |
158 | ||
159 | ifc_nand_ctrl->page = page_addr; | |
160 | /* Program ROW0/COL0 */ | |
cf184dc2 JS |
161 | ifc_out32(page_addr, &ifc->ifc_nand.row0); |
162 | ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); | |
82771882 PK |
163 | |
164 | buf_num = page_addr & priv->bufnum_mask; | |
165 | ||
166 | ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); | |
167 | ifc_nand_ctrl->index = column; | |
168 | ||
169 | /* for OOB data point to the second half of the buffer */ | |
170 | if (oob) | |
171 | ifc_nand_ctrl->index += mtd->writesize; | |
172 | } | |
173 | ||
82771882 PK |
174 | /* returns nonzero if entire page is blank */ |
175 | static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, | |
843c3a59 | 176 | u32 eccstat, unsigned int bufnum) |
82771882 | 177 | { |
843c3a59 | 178 | return (eccstat >> ((3 - bufnum % 4) * 8)) & 15; |
82771882 PK |
179 | } |
180 | ||
181 | /* | |
182 | * execute IFC NAND command and wait for it to complete | |
183 | */ | |
184 | static void fsl_ifc_run_command(struct mtd_info *mtd) | |
185 | { | |
4bd4ebcc | 186 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 187 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
188 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
189 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; | |
7a654172 | 190 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
843c3a59 | 191 | u32 eccstat; |
82771882 PK |
192 | int i; |
193 | ||
194 | /* set the chip select for NAND Transaction */ | |
cf184dc2 JS |
195 | ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT, |
196 | &ifc->ifc_nand.nand_csel); | |
82771882 PK |
197 | |
198 | dev_vdbg(priv->dev, | |
199 | "%s: fir0=%08x fcr0=%08x\n", | |
200 | __func__, | |
cf184dc2 JS |
201 | ifc_in32(&ifc->ifc_nand.nand_fir0), |
202 | ifc_in32(&ifc->ifc_nand.nand_fcr0)); | |
82771882 PK |
203 | |
204 | ctrl->nand_stat = 0; | |
205 | ||
206 | /* start read/write seq */ | |
cf184dc2 | 207 | ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); |
82771882 PK |
208 | |
209 | /* wait for command complete flag or timeout */ | |
210 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
95d70665 | 211 | msecs_to_jiffies(IFC_TIMEOUT_MSECS)); |
82771882 PK |
212 | |
213 | /* ctrl->nand_stat will be updated from IRQ context */ | |
214 | if (!ctrl->nand_stat) | |
215 | dev_err(priv->dev, "Controller is not responding\n"); | |
216 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER) | |
217 | dev_err(priv->dev, "NAND Flash Timeout Error\n"); | |
218 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER) | |
219 | dev_err(priv->dev, "NAND Flash Write Protect Error\n"); | |
220 | ||
3f91e94f MD |
221 | nctrl->max_bitflips = 0; |
222 | ||
82771882 PK |
223 | if (nctrl->eccread) { |
224 | int errors; | |
225 | int bufnum = nctrl->page & priv->bufnum_mask; | |
843c3a59 JG |
226 | int sector_start = bufnum * chip->ecc.steps; |
227 | int sector_end = sector_start + chip->ecc.steps - 1; | |
65644147 MM |
228 | __be32 *eccstat_regs; |
229 | ||
6b00c351 | 230 | eccstat_regs = ifc->ifc_nand.nand_eccstat; |
843c3a59 JG |
231 | eccstat = ifc_in32(&eccstat_regs[sector_start / 4]); |
232 | ||
233 | for (i = sector_start; i <= sector_end; i++) { | |
234 | if (i != sector_start && !(i % 4)) | |
235 | eccstat = ifc_in32(&eccstat_regs[i / 4]); | |
82771882 | 236 | |
82771882 PK |
237 | errors = check_read_ecc(mtd, ctrl, eccstat, i); |
238 | ||
239 | if (errors == 15) { | |
240 | /* | |
241 | * Uncorrectable error. | |
d45e5316 | 242 | * We'll check for blank pages later. |
82771882 PK |
243 | * |
244 | * We disable ECCER reporting due to... | |
245 | * erratum IFC-A002770 -- so report it now if we | |
246 | * see an uncorrectable error in ECCSTAT. | |
247 | */ | |
d45e5316 BB |
248 | ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER; |
249 | continue; | |
82771882 PK |
250 | } |
251 | ||
252 | mtd->ecc_stats.corrected += errors; | |
3f91e94f MD |
253 | nctrl->max_bitflips = max_t(unsigned int, |
254 | nctrl->max_bitflips, | |
255 | errors); | |
82771882 PK |
256 | } |
257 | ||
258 | nctrl->eccread = 0; | |
259 | } | |
260 | } | |
261 | ||
262 | static void fsl_ifc_do_read(struct nand_chip *chip, | |
263 | int oob, | |
264 | struct mtd_info *mtd) | |
265 | { | |
d699ed25 | 266 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 267 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 268 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
269 | |
270 | /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ | |
271 | if (mtd->writesize > 512) { | |
cf184dc2 JS |
272 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
273 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
274 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
275 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | | |
276 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
277 | &ifc->ifc_nand.nand_fir0); | |
278 | ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); | |
279 | ||
280 | ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | | |
281 | (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), | |
282 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 283 | } else { |
cf184dc2 JS |
284 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
285 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
286 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
287 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), | |
288 | &ifc->ifc_nand.nand_fir0); | |
289 | ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
290 | |
291 | if (oob) | |
cf184dc2 JS |
292 | ifc_out32(NAND_CMD_READOOB << |
293 | IFC_NAND_FCR0_CMD0_SHIFT, | |
294 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 295 | else |
cf184dc2 JS |
296 | ifc_out32(NAND_CMD_READ0 << |
297 | IFC_NAND_FCR0_CMD0_SHIFT, | |
298 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
299 | } |
300 | } | |
301 | ||
302 | /* cmdfunc send commands to the IFC NAND Machine */ | |
303 | static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
304 | int column, int page_addr) { | |
4bd4ebcc | 305 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 306 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 307 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 308 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
309 | |
310 | /* clear the read buffer */ | |
311 | ifc_nand_ctrl->read_bytes = 0; | |
312 | if (command != NAND_CMD_PAGEPROG) | |
313 | ifc_nand_ctrl->index = 0; | |
314 | ||
315 | switch (command) { | |
316 | /* READ0 read the entire buffer to use hardware ECC. */ | |
317 | case NAND_CMD_READ0: | |
cf184dc2 | 318 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
319 | set_addr(mtd, 0, page_addr, 0); |
320 | ||
321 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
322 | ifc_nand_ctrl->index += column; | |
323 | ||
324 | if (chip->ecc.mode == NAND_ECC_HW) | |
325 | ifc_nand_ctrl->eccread = 1; | |
326 | ||
327 | fsl_ifc_do_read(chip, 0, mtd); | |
328 | fsl_ifc_run_command(mtd); | |
329 | return; | |
330 | ||
331 | /* READOOB reads only the OOB because no ECC is performed. */ | |
332 | case NAND_CMD_READOOB: | |
cf184dc2 | 333 | ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
334 | set_addr(mtd, column, page_addr, 1); |
335 | ||
336 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
337 | ||
338 | fsl_ifc_do_read(chip, 1, mtd); | |
339 | fsl_ifc_run_command(mtd); | |
340 | ||
341 | return; | |
342 | ||
82771882 | 343 | case NAND_CMD_READID: |
59fdd5b9 PK |
344 | case NAND_CMD_PARAM: { |
345 | int timing = IFC_FIR_OP_RB; | |
346 | if (command == NAND_CMD_PARAM) | |
347 | timing = IFC_FIR_OP_RBCD; | |
348 | ||
cf184dc2 JS |
349 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
350 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | | |
351 | (timing << IFC_NAND_FIR0_OP2_SHIFT), | |
352 | &ifc->ifc_nand.nand_fir0); | |
353 | ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT, | |
354 | &ifc->ifc_nand.nand_fcr0); | |
355 | ifc_out32(column, &ifc->ifc_nand.row3); | |
59fdd5b9 PK |
356 | |
357 | /* | |
358 | * although currently it's 8 bytes for READID, we always read | |
359 | * the maximum 256 bytes(for PARAM) | |
360 | */ | |
cf184dc2 | 361 | ifc_out32(256, &ifc->ifc_nand.nand_fbcr); |
59fdd5b9 | 362 | ifc_nand_ctrl->read_bytes = 256; |
82771882 PK |
363 | |
364 | set_addr(mtd, 0, 0, 0); | |
365 | fsl_ifc_run_command(mtd); | |
366 | return; | |
59fdd5b9 | 367 | } |
82771882 PK |
368 | |
369 | /* ERASE1 stores the block and page address */ | |
370 | case NAND_CMD_ERASE1: | |
371 | set_addr(mtd, 0, page_addr, 0); | |
372 | return; | |
373 | ||
374 | /* ERASE2 uses the block and page address from ERASE1 */ | |
375 | case NAND_CMD_ERASE2: | |
cf184dc2 JS |
376 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
377 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
378 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), | |
379 | &ifc->ifc_nand.nand_fir0); | |
82771882 | 380 | |
cf184dc2 JS |
381 | ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | |
382 | (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), | |
383 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 384 | |
cf184dc2 | 385 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
386 | ifc_nand_ctrl->read_bytes = 0; |
387 | fsl_ifc_run_command(mtd); | |
388 | return; | |
389 | ||
390 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
391 | case NAND_CMD_SEQIN: { | |
392 | u32 nand_fcr0; | |
393 | ifc_nand_ctrl->column = column; | |
394 | ifc_nand_ctrl->oob = 0; | |
395 | ||
396 | if (mtd->writesize > 512) { | |
397 | nand_fcr0 = | |
398 | (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | | |
4af98749 PK |
399 | (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | |
400 | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); | |
82771882 | 401 | |
cf184dc2 JS |
402 | ifc_out32( |
403 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
404 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
405 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
406 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | | |
407 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT), | |
408 | &ifc->ifc_nand.nand_fir0); | |
409 | ifc_out32( | |
410 | (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | | |
411 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | | |
412 | (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT), | |
413 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
414 | } else { |
415 | nand_fcr0 = ((NAND_CMD_PAGEPROG << | |
416 | IFC_NAND_FCR0_CMD1_SHIFT) | | |
417 | (NAND_CMD_SEQIN << | |
4af98749 PK |
418 | IFC_NAND_FCR0_CMD2_SHIFT) | |
419 | (NAND_CMD_STATUS << | |
420 | IFC_NAND_FCR0_CMD3_SHIFT)); | |
82771882 | 421 | |
cf184dc2 | 422 | ifc_out32( |
0c69fb03 KP |
423 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
424 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | | |
425 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
426 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | | |
427 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
428 | &ifc->ifc_nand.nand_fir0); | |
cf184dc2 JS |
429 | ifc_out32( |
430 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | | |
431 | (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | | |
432 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | | |
433 | (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT), | |
434 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
435 | |
436 | if (column >= mtd->writesize) | |
437 | nand_fcr0 |= | |
438 | NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT; | |
439 | else | |
440 | nand_fcr0 |= | |
441 | NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT; | |
442 | } | |
443 | ||
444 | if (column >= mtd->writesize) { | |
445 | /* OOB area --> READOOB */ | |
446 | column -= mtd->writesize; | |
447 | ifc_nand_ctrl->oob = 1; | |
448 | } | |
cf184dc2 | 449 | ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0); |
82771882 PK |
450 | set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); |
451 | return; | |
452 | } | |
453 | ||
454 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
455 | case NAND_CMD_PAGEPROG: { | |
456 | if (ifc_nand_ctrl->oob) { | |
cf184dc2 JS |
457 | ifc_out32(ifc_nand_ctrl->index - |
458 | ifc_nand_ctrl->column, | |
459 | &ifc->ifc_nand.nand_fbcr); | |
82771882 | 460 | } else { |
cf184dc2 | 461 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
462 | } |
463 | ||
464 | fsl_ifc_run_command(mtd); | |
465 | return; | |
466 | } | |
467 | ||
cf184dc2 JS |
468 | case NAND_CMD_STATUS: { |
469 | void __iomem *addr; | |
470 | ||
471 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
472 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), | |
473 | &ifc->ifc_nand.nand_fir0); | |
474 | ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
475 | &ifc->ifc_nand.nand_fcr0); | |
476 | ifc_out32(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
477 | set_addr(mtd, 0, 0, 0); |
478 | ifc_nand_ctrl->read_bytes = 1; | |
479 | ||
480 | fsl_ifc_run_command(mtd); | |
481 | ||
482 | /* | |
483 | * The chip always seems to report that it is | |
484 | * write-protected, even when it is not. | |
485 | */ | |
cf184dc2 | 486 | addr = ifc_nand_ctrl->addr; |
21704804 | 487 | if (chip->options & NAND_BUSWIDTH_16) |
cf184dc2 | 488 | ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr); |
21704804 | 489 | else |
cf184dc2 | 490 | ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr); |
82771882 | 491 | return; |
cf184dc2 | 492 | } |
82771882 PK |
493 | |
494 | case NAND_CMD_RESET: | |
cf184dc2 JS |
495 | ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, |
496 | &ifc->ifc_nand.nand_fir0); | |
497 | ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, | |
498 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
499 | fsl_ifc_run_command(mtd); |
500 | return; | |
501 | ||
502 | default: | |
503 | dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n", | |
504 | __func__, command); | |
505 | } | |
506 | } | |
507 | ||
508 | static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) | |
509 | { | |
510 | /* The hardware does not seem to support multiple | |
511 | * chips per bank. | |
512 | */ | |
513 | } | |
514 | ||
515 | /* | |
516 | * Write buf to the IFC NAND Controller Data Buffer | |
517 | */ | |
518 | static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
519 | { | |
4bd4ebcc | 520 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 521 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
522 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
523 | ||
524 | if (len <= 0) { | |
525 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
526 | return; | |
527 | } | |
528 | ||
529 | if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) { | |
530 | dev_err(priv->dev, | |
531 | "%s: beyond end of buffer (%d requested, %u available)\n", | |
532 | __func__, len, bufsize - ifc_nand_ctrl->index); | |
533 | len = bufsize - ifc_nand_ctrl->index; | |
534 | } | |
535 | ||
4454406e | 536 | memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len); |
82771882 PK |
537 | ifc_nand_ctrl->index += len; |
538 | } | |
539 | ||
540 | /* | |
541 | * Read a byte from either the IFC hardware buffer | |
542 | * read function for 8-bit buswidth | |
543 | */ | |
544 | static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd) | |
545 | { | |
4bd4ebcc | 546 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 547 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
4454406e | 548 | unsigned int offset; |
82771882 PK |
549 | |
550 | /* | |
551 | * If there are still bytes in the IFC buffer, then use the | |
552 | * next byte. | |
553 | */ | |
4454406e AS |
554 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { |
555 | offset = ifc_nand_ctrl->index++; | |
cf184dc2 | 556 | return ifc_in8(ifc_nand_ctrl->addr + offset); |
4454406e | 557 | } |
82771882 PK |
558 | |
559 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
560 | return ERR_BYTE; | |
561 | } | |
562 | ||
563 | /* | |
564 | * Read two bytes from the IFC hardware buffer | |
565 | * read function for 16-bit buswith | |
566 | */ | |
567 | static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) | |
568 | { | |
4bd4ebcc | 569 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 570 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
571 | uint16_t data; |
572 | ||
573 | /* | |
574 | * If there are still bytes in the IFC buffer, then use the | |
575 | * next byte. | |
576 | */ | |
577 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { | |
cf184dc2 | 578 | data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index); |
82771882 PK |
579 | ifc_nand_ctrl->index += 2; |
580 | return (uint8_t) data; | |
581 | } | |
582 | ||
583 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
584 | return ERR_BYTE; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Read from the IFC Controller Data Buffer | |
589 | */ | |
590 | static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
591 | { | |
4bd4ebcc | 592 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 593 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
594 | int avail; |
595 | ||
596 | if (len < 0) { | |
597 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
598 | return; | |
599 | } | |
600 | ||
601 | avail = min((unsigned int)len, | |
602 | ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index); | |
4454406e | 603 | memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail); |
82771882 PK |
604 | ifc_nand_ctrl->index += avail; |
605 | ||
606 | if (len > avail) | |
607 | dev_err(priv->dev, | |
608 | "%s: beyond end of buffer (%d requested, %d available)\n", | |
609 | __func__, len, avail); | |
610 | } | |
611 | ||
82771882 PK |
612 | /* |
613 | * This function is called after Program and Erase Operations to | |
614 | * check for success or failure. | |
615 | */ | |
616 | static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
617 | { | |
d699ed25 | 618 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 619 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 620 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 | 621 | u32 nand_fsr; |
fa8e6d58 | 622 | int status; |
82771882 PK |
623 | |
624 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
cf184dc2 JS |
625 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
626 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), | |
627 | &ifc->ifc_nand.nand_fir0); | |
628 | ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
629 | &ifc->ifc_nand.nand_fcr0); | |
630 | ifc_out32(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
631 | set_addr(mtd, 0, 0, 0); |
632 | ifc_nand_ctrl->read_bytes = 1; | |
633 | ||
634 | fsl_ifc_run_command(mtd); | |
635 | ||
cf184dc2 | 636 | nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); |
fa8e6d58 | 637 | status = nand_fsr >> 24; |
82771882 PK |
638 | /* |
639 | * The chip always seems to report that it is | |
640 | * write-protected, even when it is not. | |
641 | */ | |
fa8e6d58 | 642 | return status | NAND_STATUS_WP; |
82771882 PK |
643 | } |
644 | ||
d45e5316 BB |
645 | /* |
646 | * The controller does not check for bitflips in erased pages, | |
647 | * therefore software must check instead. | |
648 | */ | |
649 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
650 | { | |
651 | struct mtd_info *mtd = nand_to_mtd(chip); | |
652 | u8 *ecc = chip->oob_poi; | |
653 | const int ecc_size = chip->ecc.bytes; | |
654 | const int pkt_size = chip->ecc.size; | |
655 | int i, res, bitflips = 0; | |
656 | struct mtd_oob_region oobregion = { }; | |
657 | ||
658 | mtd_ooblayout_ecc(mtd, 0, &oobregion); | |
659 | ecc += oobregion.offset; | |
660 | ||
661 | for (i = 0; i < chip->ecc.steps; ++i) { | |
662 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
663 | NULL, 0, | |
664 | chip->ecc.strength); | |
665 | if (res < 0) | |
666 | mtd->ecc_stats.failed++; | |
667 | else | |
668 | mtd->ecc_stats.corrected += res; | |
669 | ||
670 | bitflips = max(res, bitflips); | |
671 | buf += pkt_size; | |
672 | ecc += ecc_size; | |
673 | } | |
674 | ||
675 | return bitflips; | |
676 | } | |
677 | ||
1fbb938d BN |
678 | static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip, |
679 | uint8_t *buf, int oob_required, int page) | |
82771882 | 680 | { |
d699ed25 | 681 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 682 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
3f91e94f | 683 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; |
82771882 | 684 | |
25f815f6 | 685 | nand_read_page_op(chip, page, 0, buf, mtd->writesize); |
a6976cdf BN |
686 | if (oob_required) |
687 | fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
82771882 | 688 | |
d45e5316 BB |
689 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) { |
690 | if (!oob_required) | |
691 | fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
692 | ||
693 | return check_erased_page(chip, buf); | |
694 | } | |
82771882 PK |
695 | |
696 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
697 | mtd->ecc_stats.failed++; | |
698 | ||
3f91e94f | 699 | return nctrl->max_bitflips; |
82771882 PK |
700 | } |
701 | ||
702 | /* ECC will be calculated automatically, and errors will be detected in | |
703 | * waitfunc. | |
704 | */ | |
fdbad98d | 705 | static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 706 | const uint8_t *buf, int oob_required, int page) |
82771882 | 707 | { |
25f815f6 | 708 | nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); |
82771882 | 709 | fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize); |
fdbad98d | 710 | |
25f815f6 | 711 | return nand_prog_page_end_op(chip); |
82771882 PK |
712 | } |
713 | ||
714 | static int fsl_ifc_chip_init_tail(struct mtd_info *mtd) | |
715 | { | |
4bd4ebcc | 716 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 717 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
718 | |
719 | dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__, | |
720 | chip->numchips); | |
721 | dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__, | |
722 | chip->chipsize); | |
723 | dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__, | |
724 | chip->pagemask); | |
725 | dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__, | |
726 | chip->chip_delay); | |
727 | dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__, | |
728 | chip->badblockpos); | |
729 | dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__, | |
730 | chip->chip_shift); | |
731 | dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__, | |
732 | chip->page_shift); | |
733 | dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, | |
734 | chip->phys_erase_shift); | |
82771882 PK |
735 | dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, |
736 | chip->ecc.mode); | |
737 | dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, | |
738 | chip->ecc.steps); | |
739 | dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, | |
740 | chip->ecc.bytes); | |
741 | dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__, | |
742 | chip->ecc.total); | |
caf5129e BB |
743 | dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__, |
744 | mtd->ooblayout); | |
82771882 PK |
745 | dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags); |
746 | dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size); | |
747 | dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__, | |
748 | mtd->erasesize); | |
749 | dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__, | |
750 | mtd->writesize); | |
751 | dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__, | |
752 | mtd->oobsize); | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
10bfa766 PK |
757 | static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) |
758 | { | |
759 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
7a654172 RD |
760 | struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; |
761 | struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; | |
10bfa766 PK |
762 | uint32_t csor = 0, csor_8k = 0, csor_ext = 0; |
763 | uint32_t cs = priv->bank; | |
764 | ||
765 | /* Save CSOR and CSOR_ext */ | |
7a654172 RD |
766 | csor = ifc_in32(&ifc_global->csor_cs[cs].csor); |
767 | csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
768 | |
769 | /* chage PageSize 8K and SpareSize 1K*/ | |
770 | csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; | |
7a654172 RD |
771 | ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor); |
772 | ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
773 | |
774 | /* READID */ | |
cf184dc2 | 775 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
7a654172 RD |
776 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | |
777 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), | |
778 | &ifc_runtime->ifc_nand.nand_fir0); | |
cf184dc2 | 779 | ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, |
7a654172 RD |
780 | &ifc_runtime->ifc_nand.nand_fcr0); |
781 | ifc_out32(0x0, &ifc_runtime->ifc_nand.row3); | |
10bfa766 | 782 | |
7a654172 | 783 | ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr); |
10bfa766 PK |
784 | |
785 | /* Program ROW0/COL0 */ | |
7a654172 RD |
786 | ifc_out32(0x0, &ifc_runtime->ifc_nand.row0); |
787 | ifc_out32(0x0, &ifc_runtime->ifc_nand.col0); | |
10bfa766 PK |
788 | |
789 | /* set the chip select for NAND Transaction */ | |
7a654172 RD |
790 | ifc_out32(cs << IFC_NAND_CSEL_SHIFT, |
791 | &ifc_runtime->ifc_nand.nand_csel); | |
10bfa766 PK |
792 | |
793 | /* start read seq */ | |
7a654172 RD |
794 | ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, |
795 | &ifc_runtime->ifc_nand.nandseq_strt); | |
10bfa766 PK |
796 | |
797 | /* wait for command complete flag or timeout */ | |
798 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
95d70665 | 799 | msecs_to_jiffies(IFC_TIMEOUT_MSECS)); |
10bfa766 PK |
800 | |
801 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
802 | printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); | |
803 | ||
804 | /* Restore CSOR and CSOR_ext */ | |
7a654172 RD |
805 | ifc_out32(csor, &ifc_global->csor_cs[cs].csor); |
806 | ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
807 | } |
808 | ||
82771882 PK |
809 | static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) |
810 | { | |
811 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
7a654172 RD |
812 | struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; |
813 | struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; | |
82771882 | 814 | struct nand_chip *chip = &priv->chip; |
5e9fb93d | 815 | struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
09691661 | 816 | u32 csor; |
82771882 PK |
817 | |
818 | /* Fill in fsl_ifc_mtd structure */ | |
5e9fb93d | 819 | mtd->dev.parent = priv->dev; |
a61ae81a | 820 | nand_set_flash_node(chip, priv->dev->of_node); |
82771882 PK |
821 | |
822 | /* fill in nand_chip structure */ | |
823 | /* set up function call table */ | |
7a654172 RD |
824 | if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) |
825 | & CSPR_PORT_SIZE_16) | |
82771882 PK |
826 | chip->read_byte = fsl_ifc_read_byte16; |
827 | else | |
828 | chip->read_byte = fsl_ifc_read_byte; | |
829 | ||
830 | chip->write_buf = fsl_ifc_write_buf; | |
831 | chip->read_buf = fsl_ifc_read_buf; | |
82771882 PK |
832 | chip->select_chip = fsl_ifc_select_chip; |
833 | chip->cmdfunc = fsl_ifc_cmdfunc; | |
834 | chip->waitfunc = fsl_ifc_wait; | |
4a78cc64 BB |
835 | chip->onfi_set_features = nand_onfi_get_set_features_notsupp; |
836 | chip->onfi_get_features = nand_onfi_get_set_features_notsupp; | |
82771882 PK |
837 | |
838 | chip->bbt_td = &bbt_main_descr; | |
839 | chip->bbt_md = &bbt_mirror_descr; | |
840 | ||
7a654172 | 841 | ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr); |
82771882 PK |
842 | |
843 | /* set up nand options */ | |
82771882 | 844 | chip->bbt_options = NAND_BBT_USE_FLASH; |
20cd0008 | 845 | chip->options = NAND_NO_SUBPAGE_WRITE; |
82771882 | 846 | |
7a654172 RD |
847 | if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) |
848 | & CSPR_PORT_SIZE_16) { | |
82771882 PK |
849 | chip->read_byte = fsl_ifc_read_byte16; |
850 | chip->options |= NAND_BUSWIDTH_16; | |
851 | } else { | |
852 | chip->read_byte = fsl_ifc_read_byte; | |
853 | } | |
854 | ||
855 | chip->controller = &ifc_nand_ctrl->controller; | |
d699ed25 | 856 | nand_set_controller_data(chip, priv); |
82771882 PK |
857 | |
858 | chip->ecc.read_page = fsl_ifc_read_page; | |
859 | chip->ecc.write_page = fsl_ifc_write_page; | |
860 | ||
7a654172 | 861 | csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor); |
82771882 | 862 | |
82771882 PK |
863 | switch (csor & CSOR_NAND_PGS_MASK) { |
864 | case CSOR_NAND_PGS_512: | |
caf5129e | 865 | if (!(chip->options & NAND_BUSWIDTH_16)) { |
82771882 PK |
866 | /* Avoid conflict with bad block marker */ |
867 | bbt_main_descr.offs = 0; | |
868 | bbt_mirror_descr.offs = 0; | |
869 | } | |
870 | ||
871 | priv->bufnum_mask = 15; | |
872 | break; | |
873 | ||
874 | case CSOR_NAND_PGS_2K: | |
82771882 PK |
875 | priv->bufnum_mask = 3; |
876 | break; | |
877 | ||
878 | case CSOR_NAND_PGS_4K: | |
82771882 PK |
879 | priv->bufnum_mask = 1; |
880 | break; | |
881 | ||
ebff90b2 | 882 | case CSOR_NAND_PGS_8K: |
ebff90b2 | 883 | priv->bufnum_mask = 0; |
caf5129e | 884 | break; |
ebff90b2 | 885 | |
82771882 PK |
886 | default: |
887 | dev_err(priv->dev, "bad csor %#x: bad page size\n", csor); | |
888 | return -ENODEV; | |
889 | } | |
890 | ||
891 | /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ | |
892 | if (csor & CSOR_NAND_ECC_DEC_EN) { | |
893 | chip->ecc.mode = NAND_ECC_HW; | |
caf5129e BB |
894 | mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops); |
895 | ||
896 | /* Hardware generates ECC per 512 Bytes */ | |
897 | chip->ecc.size = 512; | |
898 | if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) { | |
899 | chip->ecc.bytes = 8; | |
900 | chip->ecc.strength = 4; | |
901 | } else { | |
902 | chip->ecc.bytes = 16; | |
903 | chip->ecc.strength = 8; | |
904 | } | |
82771882 PK |
905 | } else { |
906 | chip->ecc.mode = NAND_ECC_SOFT; | |
ff1ef350 | 907 | chip->ecc.algo = NAND_ECC_HAMMING; |
82771882 PK |
908 | } |
909 | ||
d1ab0da8 | 910 | if (ctrl->version >= FSL_IFC_VERSION_1_1_0) |
10bfa766 PK |
911 | fsl_ifc_sram_init(priv); |
912 | ||
bccb06c3 JG |
913 | /* |
914 | * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older | |
915 | * versions which had 8KB. Hence bufnum mask needs to be updated. | |
916 | */ | |
917 | if (ctrl->version >= FSL_IFC_VERSION_2_0_0) | |
918 | priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; | |
919 | ||
82771882 PK |
920 | return 0; |
921 | } | |
922 | ||
923 | static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) | |
924 | { | |
5e9fb93d | 925 | struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
82771882 | 926 | |
5e9fb93d BB |
927 | nand_release(mtd); |
928 | ||
929 | kfree(mtd->name); | |
82771882 PK |
930 | |
931 | if (priv->vbase) | |
932 | iounmap(priv->vbase); | |
933 | ||
934 | ifc_nand_ctrl->chips[priv->bank] = NULL; | |
82771882 PK |
935 | |
936 | return 0; | |
937 | } | |
938 | ||
7a654172 | 939 | static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank, |
82771882 PK |
940 | phys_addr_t addr) |
941 | { | |
7a654172 | 942 | u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr); |
82771882 PK |
943 | |
944 | if (!(cspr & CSPR_V)) | |
945 | return 0; | |
946 | if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND) | |
947 | return 0; | |
948 | ||
949 | return (cspr & CSPR_BA) == convert_ifc_address(addr); | |
950 | } | |
951 | ||
952 | static DEFINE_MUTEX(fsl_ifc_nand_mutex); | |
953 | ||
06f25510 | 954 | static int fsl_ifc_nand_probe(struct platform_device *dev) |
82771882 | 955 | { |
7a654172 | 956 | struct fsl_ifc_runtime __iomem *ifc; |
82771882 PK |
957 | struct fsl_ifc_mtd *priv; |
958 | struct resource res; | |
959 | static const char *part_probe_types[] | |
960 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; | |
961 | int ret; | |
962 | int bank; | |
963 | struct device_node *node = dev->dev.of_node; | |
5e9fb93d | 964 | struct mtd_info *mtd; |
82771882 | 965 | |
7a654172 | 966 | if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs) |
82771882 | 967 | return -ENODEV; |
7a654172 | 968 | ifc = fsl_ifc_ctrl_dev->rregs; |
82771882 PK |
969 | |
970 | /* get, allocate and map the memory resource */ | |
971 | ret = of_address_to_resource(node, 0, &res); | |
972 | if (ret) { | |
973 | dev_err(&dev->dev, "%s: failed to get resource\n", __func__); | |
974 | return ret; | |
975 | } | |
976 | ||
977 | /* find which chip select it is connected to */ | |
09691661 | 978 | for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { |
7a654172 | 979 | if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start)) |
82771882 PK |
980 | break; |
981 | } | |
982 | ||
09691661 | 983 | if (bank >= fsl_ifc_ctrl_dev->banks) { |
82771882 PK |
984 | dev_err(&dev->dev, "%s: address did not match any chip selects\n", |
985 | __func__); | |
986 | return -ENODEV; | |
987 | } | |
988 | ||
989 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); | |
990 | if (!priv) | |
991 | return -ENOMEM; | |
992 | ||
993 | mutex_lock(&fsl_ifc_nand_mutex); | |
994 | if (!fsl_ifc_ctrl_dev->nand) { | |
995 | ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL); | |
996 | if (!ifc_nand_ctrl) { | |
82771882 PK |
997 | mutex_unlock(&fsl_ifc_nand_mutex); |
998 | return -ENOMEM; | |
999 | } | |
1000 | ||
1001 | ifc_nand_ctrl->read_bytes = 0; | |
1002 | ifc_nand_ctrl->index = 0; | |
1003 | ifc_nand_ctrl->addr = NULL; | |
1004 | fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; | |
1005 | ||
d45bc58d | 1006 | nand_hw_control_init(&ifc_nand_ctrl->controller); |
82771882 PK |
1007 | } else { |
1008 | ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; | |
1009 | } | |
1010 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1011 | ||
1012 | ifc_nand_ctrl->chips[bank] = priv; | |
1013 | priv->bank = bank; | |
1014 | priv->ctrl = fsl_ifc_ctrl_dev; | |
1015 | priv->dev = &dev->dev; | |
1016 | ||
1017 | priv->vbase = ioremap(res.start, resource_size(&res)); | |
1018 | if (!priv->vbase) { | |
1019 | dev_err(priv->dev, "%s: failed to map chip region\n", __func__); | |
1020 | ret = -ENOMEM; | |
1021 | goto err; | |
1022 | } | |
1023 | ||
1024 | dev_set_drvdata(priv->dev, priv); | |
1025 | ||
cf184dc2 JS |
1026 | ifc_out32(IFC_NAND_EVTER_EN_OPC_EN | |
1027 | IFC_NAND_EVTER_EN_FTOER_EN | | |
1028 | IFC_NAND_EVTER_EN_WPER_EN, | |
1029 | &ifc->ifc_nand.nand_evter_en); | |
82771882 PK |
1030 | |
1031 | /* enable NAND Machine Interrupts */ | |
cf184dc2 JS |
1032 | ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN | |
1033 | IFC_NAND_EVTER_INTR_FTOERIR_EN | | |
1034 | IFC_NAND_EVTER_INTR_WPERIR_EN, | |
1035 | &ifc->ifc_nand.nand_evter_intr_en); | |
5e9fb93d BB |
1036 | |
1037 | mtd = nand_to_mtd(&priv->chip); | |
1038 | mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); | |
1039 | if (!mtd->name) { | |
82771882 PK |
1040 | ret = -ENOMEM; |
1041 | goto err; | |
1042 | } | |
1043 | ||
1044 | ret = fsl_ifc_chip_init(priv); | |
1045 | if (ret) | |
1046 | goto err; | |
1047 | ||
5e9fb93d | 1048 | ret = nand_scan_ident(mtd, 1, NULL); |
82771882 PK |
1049 | if (ret) |
1050 | goto err; | |
1051 | ||
5e9fb93d | 1052 | ret = fsl_ifc_chip_init_tail(mtd); |
82771882 PK |
1053 | if (ret) |
1054 | goto err; | |
1055 | ||
5e9fb93d | 1056 | ret = nand_scan_tail(mtd); |
82771882 PK |
1057 | if (ret) |
1058 | goto err; | |
1059 | ||
1060 | /* First look for RedBoot table or partitions on the command | |
1061 | * line, these take precedence over device tree information */ | |
5e9fb93d | 1062 | mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); |
82771882 PK |
1063 | |
1064 | dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n", | |
1065 | (unsigned long long)res.start, priv->bank); | |
1066 | return 0; | |
1067 | ||
1068 | err: | |
1069 | fsl_ifc_chip_remove(priv); | |
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | static int fsl_ifc_nand_remove(struct platform_device *dev) | |
1074 | { | |
1075 | struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev); | |
1076 | ||
1077 | fsl_ifc_chip_remove(priv); | |
1078 | ||
1079 | mutex_lock(&fsl_ifc_nand_mutex); | |
1080 | ifc_nand_ctrl->counter--; | |
1081 | if (!ifc_nand_ctrl->counter) { | |
1082 | fsl_ifc_ctrl_dev->nand = NULL; | |
1083 | kfree(ifc_nand_ctrl); | |
1084 | } | |
1085 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | static const struct of_device_id fsl_ifc_nand_match[] = { | |
1091 | { | |
1092 | .compatible = "fsl,ifc-nand", | |
1093 | }, | |
1094 | {} | |
1095 | }; | |
3f7f7a5f | 1096 | MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match); |
82771882 PK |
1097 | |
1098 | static struct platform_driver fsl_ifc_nand_driver = { | |
1099 | .driver = { | |
1100 | .name = "fsl,ifc-nand", | |
82771882 PK |
1101 | .of_match_table = fsl_ifc_nand_match, |
1102 | }, | |
1103 | .probe = fsl_ifc_nand_probe, | |
1104 | .remove = fsl_ifc_nand_remove, | |
1105 | }; | |
1106 | ||
c69ad0ef | 1107 | module_platform_driver(fsl_ifc_nand_driver); |
82771882 PK |
1108 | |
1109 | MODULE_LICENSE("GPL"); | |
1110 | MODULE_AUTHOR("Freescale"); | |
1111 | MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver"); |