Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
ce082596 JR |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/module.h> | |
26 | ||
27 | #include "denali.h" | |
28 | ||
29 | MODULE_LICENSE("GPL"); | |
30 | ||
43914a2d MY |
31 | /* |
32 | * We define a module parameter that allows the user to override | |
ce082596 JR |
33 | * the hardware and decide what timing mode should be used. |
34 | */ | |
35 | #define NAND_DEFAULT_TIMINGS -1 | |
36 | ||
37 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
38 | module_param(onfi_timing_mode, int, S_IRUGO); | |
8125450c MY |
39 | MODULE_PARM_DESC(onfi_timing_mode, |
40 | "Overrides default ONFI setting. -1 indicates use default timings"); | |
ce082596 JR |
41 | |
42 | #define DENALI_NAND_NAME "denali-nand" | |
43 | ||
43914a2d MY |
44 | /* |
45 | * We define a macro here that combines all interrupts this driver uses into | |
46 | * a single constant value, for convenience. | |
47 | */ | |
9589bf5b JI |
48 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
49 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
50 | INTR_STATUS__ECC_ERR | \ | |
51 | INTR_STATUS__PROGRAM_FAIL | \ | |
52 | INTR_STATUS__LOAD_COMP | \ | |
53 | INTR_STATUS__PROGRAM_COMP | \ | |
54 | INTR_STATUS__TIME_OUT | \ | |
55 | INTR_STATUS__ERASE_FAIL | \ | |
56 | INTR_STATUS__RST_COMP | \ | |
57 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 58 | |
43914a2d MY |
59 | /* |
60 | * indicates whether or not the internal value for the flash bank is | |
61 | * valid or not | |
62 | */ | |
5bac3acf | 63 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
64 | |
65 | #define SUPPORT_8BITECC 1 | |
66 | ||
43914a2d MY |
67 | /* |
68 | * This macro divides two integers and rounds fractional values up | |
69 | * to the nearest integer value. | |
70 | */ | |
ce082596 JR |
71 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
72 | ||
43914a2d MY |
73 | /* |
74 | * this macro allows us to convert from an MTD structure to our own | |
ce082596 JR |
75 | * device context (denali) structure. |
76 | */ | |
442f201b BB |
77 | static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) |
78 | { | |
79 | return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); | |
80 | } | |
ce082596 | 81 | |
43914a2d MY |
82 | /* |
83 | * These constants are defined by the driver to enable common driver | |
84 | * configuration options. | |
85 | */ | |
ce082596 JR |
86 | #define SPARE_ACCESS 0x41 |
87 | #define MAIN_ACCESS 0x42 | |
88 | #define MAIN_SPARE_ACCESS 0x43 | |
2902330e | 89 | #define PIPELINE_ACCESS 0x2000 |
ce082596 JR |
90 | |
91 | #define DENALI_READ 0 | |
92 | #define DENALI_WRITE 0x100 | |
93 | ||
94 | /* types of device accesses. We can issue commands and get status */ | |
95 | #define COMMAND_CYCLE 0 | |
96 | #define ADDR_CYCLE 1 | |
97 | #define STATUS_CYCLE 2 | |
98 | ||
43914a2d MY |
99 | /* |
100 | * this is a helper macro that allows us to | |
101 | * format the bank into the proper bits for the controller | |
102 | */ | |
ce082596 JR |
103 | #define BANK(x) ((x) << 24) |
104 | ||
ce082596 JR |
105 | /* forward declarations */ |
106 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
107 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
108 | uint32_t irq_mask); | |
109 | static void denali_irq_enable(struct denali_nand_info *denali, | |
110 | uint32_t int_mask); | |
ce082596 JR |
111 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
112 | ||
43914a2d MY |
113 | /* |
114 | * Certain operations for the denali NAND controller use an indexed mode to | |
115 | * read/write data. The operation is performed by writing the address value | |
116 | * of the command to the device memory followed by the data. This function | |
bdca6dae | 117 | * abstracts this common operation. |
43914a2d | 118 | */ |
bdca6dae CD |
119 | static void index_addr(struct denali_nand_info *denali, |
120 | uint32_t address, uint32_t data) | |
ce082596 | 121 | { |
24c3fa36 CD |
122 | iowrite32(address, denali->flash_mem); |
123 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
124 | } |
125 | ||
126 | /* Perform an indexed read of the device */ | |
127 | static void index_addr_read_data(struct denali_nand_info *denali, | |
128 | uint32_t address, uint32_t *pdata) | |
129 | { | |
24c3fa36 | 130 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
131 | *pdata = ioread32(denali->flash_mem + 0x10); |
132 | } | |
133 | ||
43914a2d MY |
134 | /* |
135 | * We need to buffer some data for some of the NAND core routines. | |
136 | * The operations manage buffering that data. | |
137 | */ | |
ce082596 JR |
138 | static void reset_buf(struct denali_nand_info *denali) |
139 | { | |
140 | denali->buf.head = denali->buf.tail = 0; | |
141 | } | |
142 | ||
143 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
144 | { | |
ce082596 JR |
145 | denali->buf.buf[denali->buf.tail++] = byte; |
146 | } | |
147 | ||
148 | /* reads the status of the device */ | |
149 | static void read_status(struct denali_nand_info *denali) | |
150 | { | |
5637b69d | 151 | uint32_t cmd; |
ce082596 JR |
152 | |
153 | /* initialize the data buffer to store status */ | |
154 | reset_buf(denali); | |
155 | ||
f0bc0c77 CD |
156 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
157 | if (cmd) | |
158 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
159 | else | |
160 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
161 | } |
162 | ||
163 | /* resets a specific device connected to the core */ | |
164 | static void reset_bank(struct denali_nand_info *denali) | |
165 | { | |
5637b69d | 166 | uint32_t irq_status; |
8125450c | 167 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
ce082596 JR |
168 | |
169 | clear_interrupts(denali); | |
170 | ||
9589bf5b | 171 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
172 | |
173 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 174 | |
9589bf5b | 175 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 176 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
177 | } |
178 | ||
179 | /* Reset the flash controller */ | |
eda936ef | 180 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 | 181 | { |
93e3c8ad | 182 | int i; |
ce082596 | 183 | |
84457949 | 184 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 185 | __FILE__, __LINE__, __func__); |
ce082596 | 186 | |
8125450c | 187 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b JI |
188 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
189 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 | 190 | |
8125450c | 191 | for (i = 0; i < denali->max_banks; i++) { |
9589bf5b | 192 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
8125450c | 193 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
9589bf5b | 194 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
628bfd41 | 195 | cpu_relax(); |
9589bf5b JI |
196 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
197 | INTR_STATUS__TIME_OUT) | |
84457949 | 198 | dev_dbg(denali->dev, |
ce082596 JR |
199 | "NAND Reset operation timed out on bank %d\n", i); |
200 | } | |
201 | ||
c89eeda8 | 202 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b | 203 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
8125450c | 204 | denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
205 | |
206 | return PASS; | |
207 | } | |
208 | ||
43914a2d MY |
209 | /* |
210 | * this routine calculates the ONFI timing values for a given mode and | |
bdca6dae CD |
211 | * programs the clocking register accordingly. The mode is determined by |
212 | * the get_onfi_nand_para routine. | |
ce082596 | 213 | */ |
eda936ef | 214 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 215 | uint16_t mode) |
ce082596 JR |
216 | { |
217 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
218 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
219 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
220 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
221 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
222 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
223 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
224 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
225 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
226 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
227 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
228 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
229 | ||
ce082596 JR |
230 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
231 | uint16_t dv_window = 0; | |
232 | uint16_t en_lo, en_hi; | |
233 | uint16_t acc_clks; | |
234 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
235 | ||
84457949 | 236 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 237 | __FILE__, __LINE__, __func__); |
ce082596 JR |
238 | |
239 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | |
240 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
241 | #if ONFI_BLOOM_TIME | |
242 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
243 | en_hi++; | |
244 | #endif | |
245 | ||
246 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
247 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
248 | ||
249 | if ((en_lo + en_hi) < CLK_MULTI) | |
250 | en_lo += CLK_MULTI - en_lo - en_hi; | |
251 | ||
252 | while (dv_window < 8) { | |
253 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
254 | ||
255 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
256 | ||
8125450c MY |
257 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
258 | data_invalid_rhoh : data_invalid_rloh; | |
ce082596 JR |
259 | |
260 | dv_window = data_invalid - Trea[mode]; | |
261 | ||
262 | if (dv_window < 8) | |
263 | en_lo++; | |
264 | } | |
265 | ||
266 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
267 | ||
7d14ecd0 | 268 | while (acc_clks * CLK_X - Trea[mode] < 3) |
ce082596 JR |
269 | acc_clks++; |
270 | ||
7d14ecd0 | 271 | if (data_invalid - acc_clks * CLK_X < 2) |
84457949 | 272 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
8125450c | 273 | __FILE__, __LINE__); |
ce082596 JR |
274 | |
275 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
276 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
277 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
278 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
279 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
ce082596 JR |
280 | if (cs_cnt == 0) |
281 | cs_cnt = 1; | |
282 | ||
283 | if (Tcea[mode]) { | |
7d14ecd0 | 284 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
ce082596 JR |
285 | cs_cnt++; |
286 | } | |
287 | ||
288 | #if MODE5_WORKAROUND | |
289 | if (mode == 5) | |
290 | acc_clks = 5; | |
291 | #endif | |
292 | ||
293 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
7d14ecd0 MY |
294 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
295 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) | |
ce082596 JR |
296 | acc_clks = 6; |
297 | ||
24c3fa36 CD |
298 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
299 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
300 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
301 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
302 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
303 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
304 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
305 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
306 | } |
307 | ||
ce082596 JR |
308 | /* queries the NAND device to see what ONFI modes it supports. */ |
309 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
310 | { | |
311 | int i; | |
43914a2d MY |
312 | |
313 | /* | |
314 | * we needn't to do a reset here because driver has already | |
4c03bbdf | 315 | * reset all the banks before |
43914a2d | 316 | */ |
ce082596 JR |
317 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
318 | ONFI_TIMING_MODE__VALUE)) | |
319 | return FAIL; | |
320 | ||
321 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
322 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
323 | (0x01 << i)) | |
ce082596 JR |
324 | break; |
325 | } | |
326 | ||
eda936ef | 327 | nand_onfi_timing_set(denali, i); |
ce082596 | 328 | |
43914a2d MY |
329 | /* |
330 | * By now, all the ONFI devices we know support the page cache | |
331 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
332 | */ | |
ce082596 JR |
333 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
334 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
335 | ||
336 | return PASS; | |
337 | } | |
338 | ||
4c03bbdf CD |
339 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
340 | uint8_t device_id) | |
ce082596 | 341 | { |
4c03bbdf | 342 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 343 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
344 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
345 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
346 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
347 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
348 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
349 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
350 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 351 | } |
ce082596 JR |
352 | } |
353 | ||
354 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
355 | { | |
ce082596 JR |
356 | uint32_t tmp; |
357 | ||
43914a2d MY |
358 | /* |
359 | * Workaround to fix a controller bug which reports a wrong | |
360 | * spare area size for some kind of Toshiba NAND device | |
361 | */ | |
ce082596 JR |
362 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
363 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 364 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
365 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
366 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 367 | iowrite32(tmp, |
bdca6dae | 368 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 369 | #if SUPPORT_15BITECC |
24c3fa36 | 370 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 371 | #elif SUPPORT_8BITECC |
24c3fa36 | 372 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
373 | #endif |
374 | } | |
ce082596 JR |
375 | } |
376 | ||
ef41e1bb CD |
377 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
378 | uint8_t device_id) | |
ce082596 | 379 | { |
ce082596 JR |
380 | uint32_t main_size, spare_size; |
381 | ||
ef41e1bb | 382 | switch (device_id) { |
ce082596 JR |
383 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
384 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
385 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
386 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
387 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
388 | main_size = 4096 * |
389 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
390 | spare_size = 224 * | |
391 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 392 | iowrite32(main_size, |
bdca6dae | 393 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 394 | iowrite32(spare_size, |
bdca6dae | 395 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 396 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 397 | #if SUPPORT_15BITECC |
24c3fa36 | 398 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 399 | #elif SUPPORT_8BITECC |
24c3fa36 | 400 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 401 | #endif |
ce082596 JR |
402 | break; |
403 | default: | |
84457949 | 404 | dev_warn(denali->dev, |
789ccf17 | 405 | "Unknown Hynix NAND (Device ID: 0x%x).\n" |
8125450c MY |
406 | "Will use default parameter values instead.\n", |
407 | device_id); | |
ce082596 JR |
408 | } |
409 | } | |
410 | ||
43914a2d MY |
411 | /* |
412 | * determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 413 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
414 | */ |
415 | static void find_valid_banks(struct denali_nand_info *denali) | |
416 | { | |
c89eeda8 | 417 | uint32_t id[denali->max_banks]; |
ce082596 JR |
418 | int i; |
419 | ||
420 | denali->total_used_banks = 1; | |
c89eeda8 | 421 | for (i = 0; i < denali->max_banks; i++) { |
3157d1ed MY |
422 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
423 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
8125450c | 424 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
ce082596 | 425 | |
84457949 | 426 | dev_dbg(denali->dev, |
ce082596 JR |
427 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
428 | ||
429 | if (i == 0) { | |
430 | if (!(id[i] & 0x0ff)) | |
431 | break; /* WTF? */ | |
432 | } else { | |
433 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
434 | denali->total_used_banks++; | |
435 | else | |
436 | break; | |
437 | } | |
438 | } | |
439 | ||
345b1d3b | 440 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
441 | /* |
442 | * Platform limitations of the CE4100 device limit | |
ce082596 | 443 | * users to a single chip solution for NAND. |
5bac3acf C |
444 | * Multichip support is not enabled. |
445 | */ | |
345b1d3b | 446 | if (denali->total_used_banks != 1) { |
84457949 | 447 | dev_err(denali->dev, |
8125450c | 448 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
ce082596 JR |
449 | BUG(); |
450 | } | |
451 | } | |
84457949 | 452 | dev_dbg(denali->dev, |
ce082596 JR |
453 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
454 | } | |
455 | ||
c89eeda8 JI |
456 | /* |
457 | * Use the configuration feature register to determine the maximum number of | |
458 | * banks that the hardware supports. | |
459 | */ | |
460 | static void detect_max_banks(struct denali_nand_info *denali) | |
461 | { | |
462 | uint32_t features = ioread32(denali->flash_reg + FEATURES); | |
271707b1 GM |
463 | /* |
464 | * Read the revision register, so we can calculate the max_banks | |
465 | * properly: the encoding changed from rev 5.0 to 5.1 | |
466 | */ | |
467 | u32 revision = MAKE_COMPARABLE_REVISION( | |
468 | ioread32(denali->flash_reg + REVISION)); | |
c89eeda8 | 469 | |
271707b1 GM |
470 | if (revision < REVISION_5_1) |
471 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
472 | else | |
473 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); | |
c89eeda8 JI |
474 | } |
475 | ||
eda936ef | 476 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
477 | { |
478 | uint16_t status = PASS; | |
d68a5c3d | 479 | uint32_t id_bytes[8], addr; |
93e3c8ad MY |
480 | uint8_t maf_id, device_id; |
481 | int i; | |
ce082596 | 482 | |
8125450c | 483 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
7cfffac0 | 484 | __FILE__, __LINE__, __func__); |
ce082596 | 485 | |
43914a2d MY |
486 | /* |
487 | * Use read id method to get device ID and other params. | |
488 | * For some NAND chips, controller can't report the correct | |
489 | * device ID by reading from DEVICE_ID register | |
490 | */ | |
3157d1ed MY |
491 | addr = MODE_11 | BANK(denali->flash_bank); |
492 | index_addr(denali, addr | 0, 0x90); | |
493 | index_addr(denali, addr | 1, 0); | |
d68a5c3d | 494 | for (i = 0; i < 8; i++) |
ef41e1bb CD |
495 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
496 | maf_id = id_bytes[0]; | |
497 | device_id = id_bytes[1]; | |
ce082596 JR |
498 | |
499 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
500 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
501 | if (FAIL == get_onfi_nand_para(denali)) | |
502 | return FAIL; | |
ef41e1bb | 503 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 504 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 505 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 506 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
507 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
508 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
509 | } |
510 | ||
84457949 | 511 | dev_info(denali->dev, |
8125450c | 512 | "Dump timing register values:\n" |
7cfffac0 CD |
513 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
514 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
515 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
516 | ioread32(denali->flash_reg + ACC_CLKS), | |
517 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 518 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
519 | ioread32(denali->flash_reg + WE_2_RE), |
520 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
521 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
522 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
523 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
524 | ||
ce082596 JR |
525 | find_valid_banks(denali); |
526 | ||
43914a2d MY |
527 | /* |
528 | * If the user specified to override the default timings | |
5bac3acf | 529 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
530 | */ |
531 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 532 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
533 | |
534 | return status; | |
535 | } | |
536 | ||
eda936ef | 537 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
538 | uint16_t INT_ENABLE) |
539 | { | |
84457949 | 540 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 541 | __FILE__, __LINE__, __func__); |
ce082596 JR |
542 | |
543 | if (INT_ENABLE) | |
24c3fa36 | 544 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 545 | else |
24c3fa36 | 546 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
547 | } |
548 | ||
43914a2d MY |
549 | /* |
550 | * validation function to verify that the controlling software is making | |
b292c341 | 551 | * a valid request |
ce082596 JR |
552 | */ |
553 | static inline bool is_flash_bank_valid(int flash_bank) | |
554 | { | |
7d14ecd0 | 555 | return flash_bank >= 0 && flash_bank < 4; |
ce082596 JR |
556 | } |
557 | ||
558 | static void denali_irq_init(struct denali_nand_info *denali) | |
559 | { | |
5637b69d | 560 | uint32_t int_mask; |
9589bf5b | 561 | int i; |
ce082596 JR |
562 | |
563 | /* Disable global interrupts */ | |
eda936ef | 564 | denali_set_intr_modes(denali, false); |
ce082596 JR |
565 | |
566 | int_mask = DENALI_IRQ_ALL; | |
567 | ||
568 | /* Clear all status bits */ | |
c89eeda8 | 569 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 570 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
571 | |
572 | denali_irq_enable(denali, int_mask); | |
573 | } | |
574 | ||
575 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
576 | { | |
eda936ef | 577 | denali_set_intr_modes(denali, false); |
ce082596 JR |
578 | free_irq(irqnum, denali); |
579 | } | |
580 | ||
bdca6dae CD |
581 | static void denali_irq_enable(struct denali_nand_info *denali, |
582 | uint32_t int_mask) | |
ce082596 | 583 | { |
9589bf5b JI |
584 | int i; |
585 | ||
c89eeda8 | 586 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 587 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
ce082596 JR |
588 | } |
589 | ||
43914a2d MY |
590 | /* |
591 | * This function only returns when an interrupt that this driver cares about | |
5bac3acf | 592 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
593 | */ |
594 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
595 | { | |
a99d1796 | 596 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
597 | } |
598 | ||
599 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
600 | static inline void clear_interrupt(struct denali_nand_info *denali, |
601 | uint32_t irq_mask) | |
ce082596 | 602 | { |
5637b69d | 603 | uint32_t intr_status_reg; |
ce082596 | 604 | |
9589bf5b | 605 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 606 | |
24c3fa36 | 607 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
608 | } |
609 | ||
610 | static void clear_interrupts(struct denali_nand_info *denali) | |
611 | { | |
5637b69d MY |
612 | uint32_t status; |
613 | ||
ce082596 JR |
614 | spin_lock_irq(&denali->irq_lock); |
615 | ||
616 | status = read_interrupt_status(denali); | |
8ae61ebd | 617 | clear_interrupt(denali, status); |
ce082596 | 618 | |
ce082596 JR |
619 | denali->irq_status = 0x0; |
620 | spin_unlock_irq(&denali->irq_lock); | |
621 | } | |
622 | ||
623 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
624 | { | |
5637b69d | 625 | uint32_t intr_status_reg; |
ce082596 | 626 | |
9589bf5b | 627 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
628 | |
629 | return ioread32(denali->flash_reg + intr_status_reg); | |
630 | } | |
631 | ||
43914a2d MY |
632 | /* |
633 | * This is the interrupt service routine. It handles all interrupts | |
634 | * sent to this device. Note that on CE4100, this is a shared interrupt. | |
ce082596 JR |
635 | */ |
636 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
637 | { | |
638 | struct denali_nand_info *denali = dev_id; | |
5637b69d | 639 | uint32_t irq_status; |
ce082596 JR |
640 | irqreturn_t result = IRQ_NONE; |
641 | ||
642 | spin_lock(&denali->irq_lock); | |
643 | ||
43914a2d | 644 | /* check to see if a valid NAND chip has been selected. */ |
345b1d3b | 645 | if (is_flash_bank_valid(denali->flash_bank)) { |
43914a2d MY |
646 | /* |
647 | * check to see if controller generated the interrupt, | |
648 | * since this is a shared interrupt | |
649 | */ | |
bdca6dae CD |
650 | irq_status = denali_irq_detected(denali); |
651 | if (irq_status != 0) { | |
ce082596 JR |
652 | /* handle interrupt */ |
653 | /* first acknowledge it */ | |
654 | clear_interrupt(denali, irq_status); | |
43914a2d MY |
655 | /* |
656 | * store the status in the device context for someone | |
657 | * to read | |
658 | */ | |
ce082596 JR |
659 | denali->irq_status |= irq_status; |
660 | /* notify anyone who cares that it happened */ | |
661 | complete(&denali->complete); | |
662 | /* tell the OS that we've handled this */ | |
663 | result = IRQ_HANDLED; | |
664 | } | |
665 | } | |
666 | spin_unlock(&denali->irq_lock); | |
667 | return result; | |
668 | } | |
669 | #define BANK(x) ((x) << 24) | |
670 | ||
671 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
672 | { | |
5637b69d MY |
673 | unsigned long comp_res; |
674 | uint32_t intr_status; | |
ce082596 JR |
675 | unsigned long timeout = msecs_to_jiffies(1000); |
676 | ||
345b1d3b | 677 | do { |
bdca6dae CD |
678 | comp_res = |
679 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
680 | spin_lock_irq(&denali->irq_lock); |
681 | intr_status = denali->irq_status; | |
682 | ||
345b1d3b | 683 | if (intr_status & irq_mask) { |
ce082596 JR |
684 | denali->irq_status &= ~irq_mask; |
685 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
686 | /* our interrupt was detected */ |
687 | break; | |
ce082596 | 688 | } |
8125450c MY |
689 | |
690 | /* | |
691 | * these are not the interrupts you are looking for - | |
692 | * need to wait again | |
693 | */ | |
694 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
695 | } while (comp_res != 0); |
696 | ||
345b1d3b | 697 | if (comp_res == 0) { |
ce082596 | 698 | /* timeout */ |
2a0a288e | 699 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
5bac3acf | 700 | intr_status, irq_mask); |
ce082596 JR |
701 | |
702 | intr_status = 0; | |
703 | } | |
704 | return intr_status; | |
705 | } | |
706 | ||
43914a2d MY |
707 | /* |
708 | * This helper function setups the registers for ECC and whether or not | |
709 | * the spare area will be transferred. | |
710 | */ | |
5bac3acf | 711 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
712 | bool transfer_spare) |
713 | { | |
5637b69d | 714 | int ecc_en_flag, transfer_spare_flag; |
ce082596 JR |
715 | |
716 | /* set ECC, transfer spare bits if needed */ | |
717 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
718 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
719 | ||
720 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 | 721 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
8125450c | 722 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
723 | } |
724 | ||
43914a2d MY |
725 | /* |
726 | * sends a pipeline command operation to the controller. See the Denali NAND | |
b292c341 | 727 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 728 | */ |
bdca6dae | 729 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
8125450c MY |
730 | bool ecc_en, bool transfer_spare, |
731 | int access_type, int op) | |
ce082596 JR |
732 | { |
733 | int status = PASS; | |
5637b69d MY |
734 | uint32_t page_count = 1; |
735 | uint32_t addr, cmd, irq_status, irq_mask; | |
ce082596 | 736 | |
a99d1796 | 737 | if (op == DENALI_READ) |
9589bf5b | 738 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
739 | else if (op == DENALI_WRITE) |
740 | irq_mask = 0; | |
741 | else | |
742 | BUG(); | |
ce082596 JR |
743 | |
744 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
745 | ||
5bac3acf | 746 | clear_interrupts(denali); |
ce082596 JR |
747 | |
748 | addr = BANK(denali->flash_bank) | denali->page; | |
749 | ||
345b1d3b | 750 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 751 | cmd = MODE_01 | addr; |
24c3fa36 | 752 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 753 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 754 | /* read spare area */ |
5bac3acf | 755 | cmd = MODE_10 | addr; |
3157d1ed | 756 | index_addr(denali, cmd, access_type); |
ce082596 | 757 | |
5bac3acf | 758 | cmd = MODE_01 | addr; |
24c3fa36 | 759 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 760 | } else if (op == DENALI_READ) { |
ce082596 | 761 | /* setup page read request for access type */ |
5bac3acf | 762 | cmd = MODE_10 | addr; |
3157d1ed | 763 | index_addr(denali, cmd, access_type); |
ce082596 | 764 | |
43914a2d MY |
765 | /* |
766 | * page 33 of the NAND controller spec indicates we should not | |
767 | * use the pipeline commands in Spare area only mode. | |
768 | * So we don't. | |
ce082596 | 769 | */ |
345b1d3b | 770 | if (access_type == SPARE_ACCESS) { |
ce082596 | 771 | cmd = MODE_01 | addr; |
24c3fa36 | 772 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 773 | } else { |
3157d1ed | 774 | index_addr(denali, cmd, |
2902330e | 775 | PIPELINE_ACCESS | op | page_count); |
5bac3acf | 776 | |
43914a2d MY |
777 | /* |
778 | * wait for command to be accepted | |
bdca6dae | 779 | * can always use status0 bit as the |
43914a2d MY |
780 | * mask is identical for each bank. |
781 | */ | |
ce082596 JR |
782 | irq_status = wait_for_irq(denali, irq_mask); |
783 | ||
345b1d3b | 784 | if (irq_status == 0) { |
84457949 | 785 | dev_err(denali->dev, |
8125450c MY |
786 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
787 | cmd, denali->page, addr); | |
ce082596 | 788 | status = FAIL; |
345b1d3b | 789 | } else { |
ce082596 | 790 | cmd = MODE_01 | addr; |
24c3fa36 | 791 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
792 | } |
793 | } | |
794 | } | |
795 | return status; | |
796 | } | |
797 | ||
798 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae | 799 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
8125450c | 800 | const uint8_t *buf, int len) |
ce082596 | 801 | { |
93e3c8ad MY |
802 | uint32_t *buf32; |
803 | int i; | |
ce082596 | 804 | |
43914a2d MY |
805 | /* |
806 | * verify that the len is a multiple of 4. | |
807 | * see comment in read_data_from_flash_mem() | |
808 | */ | |
ce082596 JR |
809 | BUG_ON((len % 4) != 0); |
810 | ||
811 | /* write the data to the flash memory */ | |
812 | buf32 = (uint32_t *)buf; | |
813 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 814 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
8125450c | 815 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
816 | } |
817 | ||
818 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae | 819 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
8125450c | 820 | uint8_t *buf, int len) |
ce082596 | 821 | { |
93e3c8ad MY |
822 | uint32_t *buf32; |
823 | int i; | |
ce082596 | 824 | |
43914a2d MY |
825 | /* |
826 | * we assume that len will be a multiple of 4, if not it would be nice | |
827 | * to know about it ASAP rather than have random failures... | |
828 | * This assumption is based on the fact that this function is designed | |
829 | * to be used to read flash pages, which are typically multiples of 4. | |
ce082596 | 830 | */ |
ce082596 JR |
831 | BUG_ON((len % 4) != 0); |
832 | ||
833 | /* transfer the data from the flash */ | |
834 | buf32 = (uint32_t *)buf; | |
835 | for (i = 0; i < len / 4; i++) | |
ce082596 | 836 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
8125450c | 837 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
838 | } |
839 | ||
840 | /* writes OOB data to the device */ | |
841 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
842 | { | |
843 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d | 844 | uint32_t irq_status; |
9589bf5b JI |
845 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
846 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
847 | int status = 0; |
848 | ||
849 | denali->page = page; | |
850 | ||
5bac3acf | 851 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 852 | DENALI_WRITE) == PASS) { |
ce082596 JR |
853 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
854 | ||
ce082596 JR |
855 | /* wait for operation to complete */ |
856 | irq_status = wait_for_irq(denali, irq_mask); | |
857 | ||
345b1d3b | 858 | if (irq_status == 0) { |
84457949 | 859 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
860 | status = -EIO; |
861 | } | |
345b1d3b | 862 | } else { |
84457949 | 863 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 864 | status = -EIO; |
ce082596 JR |
865 | } |
866 | return status; | |
867 | } | |
868 | ||
869 | /* reads OOB data from the device */ | |
870 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
871 | { | |
872 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d MY |
873 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
874 | uint32_t irq_status, addr, cmd; | |
ce082596 JR |
875 | |
876 | denali->page = page; | |
877 | ||
5bac3acf | 878 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 879 | DENALI_READ) == PASS) { |
5bac3acf | 880 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 881 | |
43914a2d MY |
882 | /* |
883 | * wait for command to be accepted | |
884 | * can always use status0 bit as the | |
885 | * mask is identical for each bank. | |
886 | */ | |
ce082596 JR |
887 | irq_status = wait_for_irq(denali, irq_mask); |
888 | ||
889 | if (irq_status == 0) | |
84457949 | 890 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 891 | denali->page); |
ce082596 | 892 | |
43914a2d MY |
893 | /* |
894 | * We set the device back to MAIN_ACCESS here as I observed | |
ce082596 JR |
895 | * instability with the controller if you do a block erase |
896 | * and the last transaction was a SPARE_ACCESS. Block erase | |
897 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 898 | * if you are in MAIN_ACCESS. |
ce082596 JR |
899 | */ |
900 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 901 | cmd = MODE_10 | addr; |
3157d1ed | 902 | index_addr(denali, cmd, MAIN_ACCESS); |
ce082596 JR |
903 | } |
904 | } | |
905 | ||
43914a2d MY |
906 | /* |
907 | * this function examines buffers to see if they contain data that | |
ce082596 JR |
908 | * indicate that the buffer is part of an erased region of flash. |
909 | */ | |
919193ce | 910 | static bool is_erased(uint8_t *buf, int len) |
ce082596 | 911 | { |
5637b69d | 912 | int i; |
8125450c | 913 | |
ce082596 | 914 | for (i = 0; i < len; i++) |
ce082596 | 915 | if (buf[i] != 0xFF) |
ce082596 | 916 | return false; |
ce082596 JR |
917 | return true; |
918 | } | |
919 | #define ECC_SECTOR_SIZE 512 | |
920 | ||
921 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
922 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
923 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
924 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
925 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
926 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
927 | ||
5bac3acf | 928 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
3f91e94f | 929 | uint32_t irq_status, unsigned int *max_bitflips) |
ce082596 JR |
930 | { |
931 | bool check_erased_page = false; | |
3f91e94f | 932 | unsigned int bitflips = 0; |
ce082596 | 933 | |
9589bf5b | 934 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 | 935 | /* read the ECC errors. we'll ignore them for now */ |
5637b69d MY |
936 | uint32_t err_address, err_correction_info, err_byte, |
937 | err_sector, err_device, err_correction_value; | |
8ae61ebd | 938 | denali_set_intr_modes(denali, false); |
ce082596 | 939 | |
345b1d3b | 940 | do { |
5bac3acf | 941 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
942 | ECC_ERROR_ADDRESS); |
943 | err_sector = ECC_SECTOR(err_address); | |
944 | err_byte = ECC_BYTE(err_address); | |
945 | ||
5bac3acf | 946 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 947 | ERR_CORRECTION_INFO); |
5bac3acf | 948 | err_correction_value = |
ce082596 JR |
949 | ECC_CORRECTION_VALUE(err_correction_info); |
950 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
951 | ||
345b1d3b | 952 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
43914a2d MY |
953 | /* |
954 | * If err_byte is larger than ECC_SECTOR_SIZE, | |
25985edc | 955 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
956 | * it. It's no need for us to correct it |
957 | * err_device is represented the NAND error | |
958 | * bits are happened in if there are more | |
959 | * than one NAND connected. | |
43914a2d | 960 | */ |
8ae61ebd | 961 | if (err_byte < ECC_SECTOR_SIZE) { |
442f201b BB |
962 | struct mtd_info *mtd = |
963 | nand_to_mtd(&denali->nand); | |
8ae61ebd | 964 | int offset; |
8125450c | 965 | |
8ae61ebd CD |
966 | offset = (err_sector * |
967 | ECC_SECTOR_SIZE + | |
968 | err_byte) * | |
969 | denali->devnum + | |
970 | err_device; | |
ce082596 JR |
971 | /* correct the ECC error */ |
972 | buf[offset] ^= err_correction_value; | |
442f201b | 973 | mtd->ecc_stats.corrected++; |
3f91e94f | 974 | bitflips++; |
ce082596 | 975 | } |
345b1d3b | 976 | } else { |
43914a2d MY |
977 | /* |
978 | * if the error is not correctable, need to | |
bdca6dae CD |
979 | * look at the page to see if it is an erased |
980 | * page. if so, then it's not a real ECC error | |
43914a2d | 981 | */ |
ce082596 JR |
982 | check_erased_page = true; |
983 | } | |
ce082596 | 984 | } while (!ECC_LAST_ERR(err_correction_info)); |
43914a2d MY |
985 | /* |
986 | * Once handle all ecc errors, controller will triger | |
8ae61ebd CD |
987 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
988 | * for a while for this interrupt | |
43914a2d | 989 | */ |
8ae61ebd | 990 | while (!(read_interrupt_status(denali) & |
9589bf5b | 991 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
992 | cpu_relax(); |
993 | clear_interrupts(denali); | |
994 | denali_set_intr_modes(denali, true); | |
ce082596 | 995 | } |
3f91e94f | 996 | *max_bitflips = bitflips; |
ce082596 JR |
997 | return check_erased_page; |
998 | } | |
999 | ||
1000 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 1001 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 | 1002 | { |
5637b69d | 1003 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
1004 | ioread32(denali->flash_reg + DMA_ENABLE); |
1005 | } | |
1006 | ||
1007 | /* setups the HW to perform the data DMA */ | |
aadff49c | 1008 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 | 1009 | { |
5637b69d | 1010 | uint32_t mode; |
ce082596 | 1011 | const int page_count = 1; |
3157d1ed | 1012 | uint32_t addr = denali->buf.dma_buf; |
ce082596 JR |
1013 | |
1014 | mode = MODE_10 | BANK(denali->flash_bank); | |
1015 | ||
1016 | /* DMA is a four step process */ | |
1017 | ||
1018 | /* 1. setup transfer type and # of pages */ | |
1019 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1020 | ||
1021 | /* 2. set memory high address bits 23:8 */ | |
3157d1ed | 1022 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
ce082596 JR |
1023 | |
1024 | /* 3. set memory low address bits 23:8 */ | |
7c272ac5 | 1025 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
ce082596 | 1026 | |
43914a2d | 1027 | /* 4. interrupt when complete, burst len = 64 bytes */ |
ce082596 JR |
1028 | index_addr(denali, mode | 0x14000, 0x2400); |
1029 | } | |
1030 | ||
43914a2d MY |
1031 | /* |
1032 | * writes a page. user specifies type, and this function handles the | |
1033 | * configuration details. | |
1034 | */ | |
fdbad98d | 1035 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1036 | const uint8_t *buf, bool raw_xfer) |
1037 | { | |
1038 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1039 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1040 | size_t size = mtd->writesize + mtd->oobsize; |
5637b69d | 1041 | uint32_t irq_status; |
9589bf5b JI |
1042 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1043 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 | 1044 | |
43914a2d MY |
1045 | /* |
1046 | * if it is a raw xfer, we want to disable ecc and send the spare area. | |
ce082596 JR |
1047 | * !raw_xfer - enable ecc |
1048 | * raw_xfer - transfer spare | |
1049 | */ | |
1050 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1051 | ||
1052 | /* copy buffer into DMA buffer */ | |
1053 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1054 | ||
345b1d3b | 1055 | if (raw_xfer) { |
ce082596 | 1056 | /* transfer the data to the spare area */ |
5bac3acf C |
1057 | memcpy(denali->buf.buf + mtd->writesize, |
1058 | chip->oob_poi, | |
1059 | mtd->oobsize); | |
ce082596 JR |
1060 | } |
1061 | ||
84457949 | 1062 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1063 | |
1064 | clear_interrupts(denali); | |
5bac3acf | 1065 | denali_enable_dma(denali, true); |
ce082596 | 1066 | |
aadff49c | 1067 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1068 | |
1069 | /* wait for operation to complete */ | |
1070 | irq_status = wait_for_irq(denali, irq_mask); | |
1071 | ||
345b1d3b | 1072 | if (irq_status == 0) { |
8125450c MY |
1073 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
1074 | raw_xfer); | |
c115add9 | 1075 | denali->status = NAND_STATUS_FAIL; |
ce082596 JR |
1076 | } |
1077 | ||
5bac3acf | 1078 | denali_enable_dma(denali, false); |
84457949 | 1079 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
fdbad98d JW |
1080 | |
1081 | return 0; | |
ce082596 JR |
1082 | } |
1083 | ||
1084 | /* NAND core entry points */ | |
1085 | ||
43914a2d MY |
1086 | /* |
1087 | * this is the callback that the NAND core calls to write a page. Since | |
b292c341 CD |
1088 | * writing a page with ECC or without is similar, all the work is done |
1089 | * by write_page above. | |
43914a2d | 1090 | */ |
fdbad98d | 1091 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 1092 | const uint8_t *buf, int oob_required, int page) |
ce082596 | 1093 | { |
43914a2d MY |
1094 | /* |
1095 | * for regular page writes, we let HW handle all the ECC | |
1096 | * data written to the device. | |
1097 | */ | |
fdbad98d | 1098 | return write_page(mtd, chip, buf, false); |
ce082596 JR |
1099 | } |
1100 | ||
43914a2d MY |
1101 | /* |
1102 | * This is the callback that the NAND core calls to write a page without ECC. | |
25985edc | 1103 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1104 | * write_page() function above. |
ce082596 | 1105 | */ |
fdbad98d | 1106 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
1107 | const uint8_t *buf, int oob_required, |
1108 | int page) | |
ce082596 | 1109 | { |
43914a2d MY |
1110 | /* |
1111 | * for raw page writes, we want to disable ECC and simply write | |
1112 | * whatever data is in the buffer. | |
1113 | */ | |
fdbad98d | 1114 | return write_page(mtd, chip, buf, true); |
ce082596 JR |
1115 | } |
1116 | ||
5bac3acf | 1117 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1118 | int page) |
1119 | { | |
5bac3acf | 1120 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1121 | } |
1122 | ||
5bac3acf | 1123 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 1124 | int page) |
ce082596 JR |
1125 | { |
1126 | read_oob_data(mtd, chip->oob_poi, page); | |
1127 | ||
5c2ffb11 | 1128 | return 0; |
ce082596 JR |
1129 | } |
1130 | ||
1131 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1132 | uint8_t *buf, int oob_required, int page) |
ce082596 | 1133 | { |
3f91e94f | 1134 | unsigned int max_bitflips; |
ce082596 | 1135 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
ce082596 JR |
1136 | |
1137 | dma_addr_t addr = denali->buf.dma_buf; | |
442f201b | 1138 | size_t size = mtd->writesize + mtd->oobsize; |
ce082596 | 1139 | |
5637b69d | 1140 | uint32_t irq_status; |
9589bf5b JI |
1141 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1142 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1143 | bool check_erased_page = false; |
1144 | ||
7d8a26fd | 1145 | if (page != denali->page) { |
8125450c MY |
1146 | dev_err(denali->dev, |
1147 | "IN %s: page %d is not equal to denali->page %d", | |
1148 | __func__, page, denali->page); | |
7d8a26fd CD |
1149 | BUG(); |
1150 | } | |
1151 | ||
ce082596 JR |
1152 | setup_ecc_for_xfer(denali, true, false); |
1153 | ||
aadff49c | 1154 | denali_enable_dma(denali, true); |
84457949 | 1155 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1156 | |
1157 | clear_interrupts(denali); | |
aadff49c | 1158 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1159 | |
1160 | /* wait for operation to complete */ | |
1161 | irq_status = wait_for_irq(denali, irq_mask); | |
1162 | ||
84457949 | 1163 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1164 | |
1165 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1166 | |
3f91e94f | 1167 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
aadff49c | 1168 | denali_enable_dma(denali, false); |
ce082596 | 1169 | |
345b1d3b | 1170 | if (check_erased_page) { |
442f201b | 1171 | read_oob_data(mtd, chip->oob_poi, denali->page); |
ce082596 JR |
1172 | |
1173 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1174 | if (check_erased_page) { |
442f201b BB |
1175 | if (!is_erased(buf, mtd->writesize)) |
1176 | mtd->ecc_stats.failed++; | |
1177 | if (!is_erased(buf, mtd->oobsize)) | |
1178 | mtd->ecc_stats.failed++; | |
5bac3acf | 1179 | } |
ce082596 | 1180 | } |
3f91e94f | 1181 | return max_bitflips; |
ce082596 JR |
1182 | } |
1183 | ||
1184 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1185 | uint8_t *buf, int oob_required, int page) |
ce082596 JR |
1186 | { |
1187 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1188 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1189 | size_t size = mtd->writesize + mtd->oobsize; |
9589bf5b | 1190 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1191 | |
7d8a26fd | 1192 | if (page != denali->page) { |
8125450c MY |
1193 | dev_err(denali->dev, |
1194 | "IN %s: page %d is not equal to denali->page %d", | |
1195 | __func__, page, denali->page); | |
7d8a26fd CD |
1196 | BUG(); |
1197 | } | |
1198 | ||
ce082596 | 1199 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1200 | denali_enable_dma(denali, true); |
ce082596 | 1201 | |
84457949 | 1202 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1203 | |
1204 | clear_interrupts(denali); | |
aadff49c | 1205 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1206 | |
1207 | /* wait for operation to complete */ | |
ba5f2bc2 | 1208 | wait_for_irq(denali, irq_mask); |
ce082596 | 1209 | |
84457949 | 1210 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1211 | |
aadff49c | 1212 | denali_enable_dma(denali, false); |
ce082596 JR |
1213 | |
1214 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1215 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1221 | { | |
1222 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1223 | uint8_t result = 0xff; | |
1224 | ||
1225 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1226 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1227 | |
ce082596 JR |
1228 | return result; |
1229 | } | |
1230 | ||
1231 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1232 | { | |
1233 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1234 | |
ce082596 JR |
1235 | spin_lock_irq(&denali->irq_lock); |
1236 | denali->flash_bank = chip; | |
1237 | spin_unlock_irq(&denali->irq_lock); | |
1238 | } | |
1239 | ||
1240 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1241 | { | |
1242 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1243 | int status = denali->status; | |
8125450c | 1244 | |
ce082596 JR |
1245 | denali->status = 0; |
1246 | ||
ce082596 JR |
1247 | return status; |
1248 | } | |
1249 | ||
49c50b97 | 1250 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
1251 | { |
1252 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1253 | ||
5637b69d | 1254 | uint32_t cmd, irq_status; |
ce082596 | 1255 | |
5bac3acf | 1256 | clear_interrupts(denali); |
ce082596 JR |
1257 | |
1258 | /* setup page read request for access type */ | |
1259 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
3157d1ed | 1260 | index_addr(denali, cmd, 0x1); |
ce082596 JR |
1261 | |
1262 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1263 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1264 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1265 | |
7d14ecd0 | 1266 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1267 | } |
1268 | ||
5bac3acf | 1269 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1270 | int page) |
1271 | { | |
1272 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1273 | uint32_t addr, id; |
1274 | int i; | |
ce082596 | 1275 | |
345b1d3b | 1276 | switch (cmd) { |
a99d1796 CD |
1277 | case NAND_CMD_PAGEPROG: |
1278 | break; | |
1279 | case NAND_CMD_STATUS: | |
1280 | read_status(denali); | |
1281 | break; | |
1282 | case NAND_CMD_READID: | |
42af8b58 | 1283 | case NAND_CMD_PARAM: |
a99d1796 | 1284 | reset_buf(denali); |
43914a2d MY |
1285 | /* |
1286 | * sometimes ManufactureId read from register is not right | |
ef41e1bb CD |
1287 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1288 | * So here we send READID cmd to NAND insteand | |
43914a2d | 1289 | */ |
3157d1ed MY |
1290 | addr = MODE_11 | BANK(denali->flash_bank); |
1291 | index_addr(denali, addr | 0, 0x90); | |
9c07d094 | 1292 | index_addr(denali, addr | 1, col); |
d68a5c3d | 1293 | for (i = 0; i < 8; i++) { |
8125450c | 1294 | index_addr_read_data(denali, addr | 2, &id); |
ef41e1bb | 1295 | write_byte_to_buf(denali, id); |
a99d1796 CD |
1296 | } |
1297 | break; | |
1298 | case NAND_CMD_READ0: | |
1299 | case NAND_CMD_SEQIN: | |
1300 | denali->page = page; | |
1301 | break; | |
1302 | case NAND_CMD_RESET: | |
1303 | reset_bank(denali); | |
1304 | break; | |
1305 | case NAND_CMD_READOOB: | |
1306 | /* TODO: Read OOB data */ | |
1307 | break; | |
1308 | default: | |
2a0a288e | 1309 | pr_err(": unsupported command received 0x%x\n", cmd); |
a99d1796 | 1310 | break; |
ce082596 JR |
1311 | } |
1312 | } | |
ce082596 JR |
1313 | /* end NAND core entry points */ |
1314 | ||
1315 | /* Initialization code to bring the device up to a known good state */ | |
1316 | static void denali_hw_init(struct denali_nand_info *denali) | |
1317 | { | |
43914a2d MY |
1318 | /* |
1319 | * tell driver how many bit controller will skip before | |
db9a3210 CD |
1320 | * writing ECC code in OOB, this register may be already |
1321 | * set by firmware. So we read this value out. | |
1322 | * if this value is 0, just let it be. | |
43914a2d | 1323 | */ |
db9a3210 CD |
1324 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
1325 | SPARE_AREA_SKIP_BYTES); | |
bc27ede3 | 1326 | detect_max_banks(denali); |
eda936ef | 1327 | denali_nand_reset(denali); |
24c3fa36 CD |
1328 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1329 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1330 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1331 | |
24c3fa36 | 1332 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1333 | |
1334 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1335 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1336 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1337 | denali_nand_timing_set(denali); |
1338 | denali_irq_init(denali); | |
ce082596 JR |
1339 | } |
1340 | ||
43914a2d MY |
1341 | /* |
1342 | * Althogh controller spec said SLC ECC is forceb to be 4bit, | |
db9a3210 CD |
1343 | * but denali controller in MRST only support 15bit and 8bit ECC |
1344 | * correction | |
43914a2d | 1345 | */ |
db9a3210 | 1346 | #define ECC_8BITS 14 |
db9a3210 | 1347 | #define ECC_15BITS 26 |
14fad62b BB |
1348 | |
1349 | static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1350 | struct mtd_oob_region *oobregion) | |
1351 | { | |
1352 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1353 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1354 | ||
1355 | if (section) | |
1356 | return -ERANGE; | |
1357 | ||
1358 | oobregion->offset = denali->bbtskipbytes; | |
1359 | oobregion->length = chip->ecc.total; | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | static int denali_ooblayout_free(struct mtd_info *mtd, int section, | |
1365 | struct mtd_oob_region *oobregion) | |
1366 | { | |
1367 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1368 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1369 | ||
1370 | if (section) | |
1371 | return -ERANGE; | |
1372 | ||
1373 | oobregion->offset = chip->ecc.total + denali->bbtskipbytes; | |
1374 | oobregion->length = mtd->oobsize - oobregion->offset; | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | static const struct mtd_ooblayout_ops denali_ooblayout_ops = { | |
1380 | .ecc = denali_ooblayout_ecc, | |
1381 | .free = denali_ooblayout_free, | |
ce082596 JR |
1382 | }; |
1383 | ||
1384 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1385 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1386 | ||
1387 | static struct nand_bbt_descr bbt_main_descr = { | |
1388 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1389 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1390 | .offs = 8, | |
1391 | .len = 4, | |
1392 | .veroffs = 12, | |
1393 | .maxblocks = 4, | |
1394 | .pattern = bbt_pattern, | |
1395 | }; | |
1396 | ||
1397 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1398 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1399 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1400 | .offs = 8, | |
1401 | .len = 4, | |
1402 | .veroffs = 12, | |
1403 | .maxblocks = 4, | |
1404 | .pattern = mirror_pattern, | |
1405 | }; | |
1406 | ||
421f91d2 | 1407 | /* initialize driver data structures */ |
8c519436 | 1408 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 | 1409 | { |
43914a2d MY |
1410 | /* |
1411 | * the completion object will be used to notify | |
1412 | * the callee that the interrupt is done | |
1413 | */ | |
ce082596 JR |
1414 | init_completion(&denali->complete); |
1415 | ||
43914a2d MY |
1416 | /* |
1417 | * the spinlock will be used to synchronize the ISR with any | |
1418 | * element that might be access shared data (interrupt status) | |
1419 | */ | |
ce082596 JR |
1420 | spin_lock_init(&denali->irq_lock); |
1421 | ||
1422 | /* indicate that MTD has not selected a valid bank yet */ | |
1423 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1424 | ||
1425 | /* initialize our irq_status variable to indicate no interrupts */ | |
1426 | denali->irq_status = 0; | |
1427 | } | |
1428 | ||
2a0a288e | 1429 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1430 | { |
442f201b | 1431 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
2a0a288e | 1432 | int ret; |
ce082596 | 1433 | |
2a0a288e | 1434 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
1435 | /* |
1436 | * Due to a silicon limitation, we can only support | |
5bac3acf C |
1437 | * ONFI timing mode 1 and below. |
1438 | */ | |
345b1d3b | 1439 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
2a0a288e DN |
1440 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
1441 | return -EINVAL; | |
ce082596 JR |
1442 | } |
1443 | } | |
1444 | ||
e07caa36 HS |
1445 | /* allocate a temporary buffer for nand_scan_ident() */ |
1446 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, | |
1447 | GFP_DMA | GFP_KERNEL); | |
1448 | if (!denali->buf.buf) | |
1449 | return -ENOMEM; | |
ce082596 | 1450 | |
442f201b | 1451 | mtd->dev.parent = denali->dev; |
ce082596 JR |
1452 | denali_hw_init(denali); |
1453 | denali_drv_init(denali); | |
1454 | ||
43914a2d MY |
1455 | /* |
1456 | * denali_isr register is done after all the hardware | |
1457 | * initilization is finished | |
1458 | */ | |
2a0a288e | 1459 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, |
ce082596 | 1460 | DENALI_NAND_NAME, denali)) { |
789ccf17 | 1461 | dev_err(denali->dev, "Unable to request IRQ\n"); |
2a0a288e | 1462 | return -ENODEV; |
ce082596 JR |
1463 | } |
1464 | ||
1465 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1466 | denali_set_intr_modes(denali, true); |
442f201b | 1467 | mtd->name = "denali-nand"; |
ce082596 JR |
1468 | |
1469 | /* register the driver with the NAND core subsystem */ | |
1470 | denali->nand.select_chip = denali_select_chip; | |
1471 | denali->nand.cmdfunc = denali_cmdfunc; | |
1472 | denali->nand.read_byte = denali_read_byte; | |
1473 | denali->nand.waitfunc = denali_waitfunc; | |
1474 | ||
43914a2d MY |
1475 | /* |
1476 | * scan for NAND devices attached to the controller | |
ce082596 | 1477 | * this is the first stage in a two step process to register |
43914a2d MY |
1478 | * with the nand subsystem |
1479 | */ | |
442f201b | 1480 | if (nand_scan_ident(mtd, denali->max_banks, NULL)) { |
ce082596 | 1481 | ret = -ENXIO; |
5c0eb900 | 1482 | goto failed_req_irq; |
ce082596 | 1483 | } |
5bac3acf | 1484 | |
e07caa36 HS |
1485 | /* allocate the right size buffer now */ |
1486 | devm_kfree(denali->dev, denali->buf.buf); | |
1487 | denali->buf.buf = devm_kzalloc(denali->dev, | |
442f201b | 1488 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1489 | GFP_KERNEL); |
1490 | if (!denali->buf.buf) { | |
1491 | ret = -ENOMEM; | |
1492 | goto failed_req_irq; | |
1493 | } | |
1494 | ||
1495 | /* Is 32-bit DMA supported? */ | |
1496 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); | |
1497 | if (ret) { | |
789ccf17 | 1498 | dev_err(denali->dev, "No usable DMA configuration\n"); |
e07caa36 HS |
1499 | goto failed_req_irq; |
1500 | } | |
1501 | ||
1502 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, | |
442f201b | 1503 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1504 | DMA_BIDIRECTIONAL); |
1505 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { | |
789ccf17 | 1506 | dev_err(denali->dev, "Failed to map DMA buffer\n"); |
e07caa36 | 1507 | ret = -EIO; |
5c0eb900 | 1508 | goto failed_req_irq; |
66406524 CD |
1509 | } |
1510 | ||
43914a2d MY |
1511 | /* |
1512 | * support for multi nand | |
1513 | * MTD known nothing about multi nand, so we should tell it | |
1514 | * the real pagesize and anything necessery | |
08b9ab99 CD |
1515 | */ |
1516 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
1517 | denali->nand.chipsize <<= (denali->devnum - 1); | |
1518 | denali->nand.page_shift += (denali->devnum - 1); | |
1519 | denali->nand.pagemask = (denali->nand.chipsize >> | |
1520 | denali->nand.page_shift) - 1; | |
1521 | denali->nand.bbt_erase_shift += (denali->devnum - 1); | |
1522 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; | |
1523 | denali->nand.chip_shift += (denali->devnum - 1); | |
442f201b BB |
1524 | mtd->writesize <<= (denali->devnum - 1); |
1525 | mtd->oobsize <<= (denali->devnum - 1); | |
1526 | mtd->erasesize <<= (denali->devnum - 1); | |
1527 | mtd->size = denali->nand.numchips * denali->nand.chipsize; | |
08b9ab99 CD |
1528 | denali->bbtskipbytes *= denali->devnum; |
1529 | ||
43914a2d MY |
1530 | /* |
1531 | * second stage of the NAND scan | |
5bac3acf | 1532 | * this stage requires information regarding ECC and |
43914a2d MY |
1533 | * bad block management. |
1534 | */ | |
ce082596 JR |
1535 | |
1536 | /* Bad block management */ | |
1537 | denali->nand.bbt_td = &bbt_main_descr; | |
1538 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1539 | ||
1540 | /* skip the scan for now until we have OOB read and write support */ | |
bb9ebd4e | 1541 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 | 1542 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
ce082596 JR |
1543 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1544 | ||
d99d7282 GM |
1545 | /* no subpage writes on denali */ |
1546 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1547 | ||
43914a2d MY |
1548 | /* |
1549 | * Denali Controller only support 15bit and 8bit ECC in MRST, | |
db9a3210 CD |
1550 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
1551 | * SLC if possible. | |
1552 | * */ | |
1d0ed69d | 1553 | if (!nand_is_slc(&denali->nand) && |
442f201b BB |
1554 | (mtd->oobsize > (denali->bbtskipbytes + |
1555 | ECC_15BITS * (mtd->writesize / | |
db9a3210 CD |
1556 | ECC_SECTOR_SIZE)))) { |
1557 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
6a918bad | 1558 | denali->nand.ecc.strength = 15; |
db9a3210 | 1559 | denali->nand.ecc.bytes = ECC_15BITS; |
24c3fa36 | 1560 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
442f201b BB |
1561 | } else if (mtd->oobsize < (denali->bbtskipbytes + |
1562 | ECC_8BITS * (mtd->writesize / | |
db9a3210 | 1563 | ECC_SECTOR_SIZE))) { |
8125450c | 1564 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
5c0eb900 | 1565 | goto failed_req_irq; |
db9a3210 | 1566 | } else { |
6a918bad | 1567 | denali->nand.ecc.strength = 8; |
db9a3210 | 1568 | denali->nand.ecc.bytes = ECC_8BITS; |
24c3fa36 | 1569 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1570 | } |
1571 | ||
14fad62b | 1572 | mtd_set_ooblayout(mtd, &denali_ooblayout_ops); |
08b9ab99 | 1573 | denali->nand.ecc.bytes *= denali->devnum; |
6a918bad | 1574 | denali->nand.ecc.strength *= denali->devnum; |
db9a3210 | 1575 | |
ce082596 | 1576 | /* override the default read operations */ |
08b9ab99 | 1577 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1578 | denali->nand.ecc.read_page = denali_read_page; |
1579 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1580 | denali->nand.ecc.write_page = denali_write_page; | |
1581 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1582 | denali->nand.ecc.read_oob = denali_read_oob; | |
1583 | denali->nand.ecc.write_oob = denali_write_oob; | |
49c50b97 | 1584 | denali->nand.erase = denali_erase; |
ce082596 | 1585 | |
442f201b | 1586 | if (nand_scan_tail(mtd)) { |
ce082596 | 1587 | ret = -ENXIO; |
5c0eb900 | 1588 | goto failed_req_irq; |
ce082596 JR |
1589 | } |
1590 | ||
442f201b | 1591 | ret = mtd_device_register(mtd, NULL, 0); |
ce082596 | 1592 | if (ret) { |
789ccf17 | 1593 | dev_err(denali->dev, "Failed to register MTD: %d\n", ret); |
5c0eb900 | 1594 | goto failed_req_irq; |
ce082596 JR |
1595 | } |
1596 | return 0; | |
1597 | ||
5c0eb900 | 1598 | failed_req_irq: |
2a0a288e DN |
1599 | denali_irq_cleanup(denali->irq, denali); |
1600 | ||
ce082596 JR |
1601 | return ret; |
1602 | } | |
2a0a288e | 1603 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1604 | |
1605 | /* driver exit point */ | |
2a0a288e | 1606 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1607 | { |
442f201b | 1608 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
320092a0 BB |
1609 | /* |
1610 | * Pre-compute DMA buffer size to avoid any problems in case | |
1611 | * nand_release() ever changes in a way that mtd->writesize and | |
1612 | * mtd->oobsize are not reliable after this call. | |
1613 | */ | |
442f201b | 1614 | int bufsize = mtd->writesize + mtd->oobsize; |
320092a0 | 1615 | |
442f201b | 1616 | nand_release(mtd); |
2a0a288e | 1617 | denali_irq_cleanup(denali->irq, denali); |
320092a0 | 1618 | dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize, |
8125450c | 1619 | DMA_BIDIRECTIONAL); |
ce082596 | 1620 | } |
2a0a288e | 1621 | EXPORT_SYMBOL(denali_remove); |