Commit | Line | Data |
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ce082596 JR |
1 | /* |
2 | * NAND Flash Controller Device Driver | |
3 | * Copyright © 2009-2010, Intel Corporation and its suppliers. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
ce082596 JR |
19 | #include <linux/interrupt.h> |
20 | #include <linux/delay.h> | |
84457949 | 21 | #include <linux/dma-mapping.h> |
ce082596 JR |
22 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | |
b8664b37 | 24 | #include <linux/slab.h> |
ce082596 JR |
25 | #include <linux/mtd/mtd.h> |
26 | #include <linux/module.h> | |
27 | ||
28 | #include "denali.h" | |
29 | ||
30 | MODULE_LICENSE("GPL"); | |
31 | ||
43914a2d MY |
32 | /* |
33 | * We define a module parameter that allows the user to override | |
ce082596 JR |
34 | * the hardware and decide what timing mode should be used. |
35 | */ | |
36 | #define NAND_DEFAULT_TIMINGS -1 | |
37 | ||
38 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
39 | module_param(onfi_timing_mode, int, S_IRUGO); | |
8125450c MY |
40 | MODULE_PARM_DESC(onfi_timing_mode, |
41 | "Overrides default ONFI setting. -1 indicates use default timings"); | |
ce082596 JR |
42 | |
43 | #define DENALI_NAND_NAME "denali-nand" | |
44 | ||
43914a2d MY |
45 | /* |
46 | * We define a macro here that combines all interrupts this driver uses into | |
47 | * a single constant value, for convenience. | |
48 | */ | |
9589bf5b JI |
49 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
50 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
51 | INTR_STATUS__ECC_ERR | \ | |
52 | INTR_STATUS__PROGRAM_FAIL | \ | |
53 | INTR_STATUS__LOAD_COMP | \ | |
54 | INTR_STATUS__PROGRAM_COMP | \ | |
55 | INTR_STATUS__TIME_OUT | \ | |
56 | INTR_STATUS__ERASE_FAIL | \ | |
57 | INTR_STATUS__RST_COMP | \ | |
58 | INTR_STATUS__ERASE_COMP) | |
ce082596 | 59 | |
43914a2d MY |
60 | /* |
61 | * indicates whether or not the internal value for the flash bank is | |
62 | * valid or not | |
63 | */ | |
5bac3acf | 64 | #define CHIP_SELECT_INVALID -1 |
ce082596 JR |
65 | |
66 | #define SUPPORT_8BITECC 1 | |
67 | ||
43914a2d MY |
68 | /* |
69 | * This macro divides two integers and rounds fractional values up | |
70 | * to the nearest integer value. | |
71 | */ | |
ce082596 JR |
72 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
73 | ||
43914a2d MY |
74 | /* |
75 | * this macro allows us to convert from an MTD structure to our own | |
ce082596 JR |
76 | * device context (denali) structure. |
77 | */ | |
442f201b BB |
78 | static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) |
79 | { | |
80 | return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); | |
81 | } | |
ce082596 | 82 | |
43914a2d MY |
83 | /* |
84 | * These constants are defined by the driver to enable common driver | |
85 | * configuration options. | |
86 | */ | |
ce082596 JR |
87 | #define SPARE_ACCESS 0x41 |
88 | #define MAIN_ACCESS 0x42 | |
89 | #define MAIN_SPARE_ACCESS 0x43 | |
2902330e | 90 | #define PIPELINE_ACCESS 0x2000 |
ce082596 JR |
91 | |
92 | #define DENALI_READ 0 | |
93 | #define DENALI_WRITE 0x100 | |
94 | ||
95 | /* types of device accesses. We can issue commands and get status */ | |
96 | #define COMMAND_CYCLE 0 | |
97 | #define ADDR_CYCLE 1 | |
98 | #define STATUS_CYCLE 2 | |
99 | ||
43914a2d MY |
100 | /* |
101 | * this is a helper macro that allows us to | |
102 | * format the bank into the proper bits for the controller | |
103 | */ | |
ce082596 JR |
104 | #define BANK(x) ((x) << 24) |
105 | ||
ce082596 JR |
106 | /* forward declarations */ |
107 | static void clear_interrupts(struct denali_nand_info *denali); | |
bdca6dae CD |
108 | static uint32_t wait_for_irq(struct denali_nand_info *denali, |
109 | uint32_t irq_mask); | |
110 | static void denali_irq_enable(struct denali_nand_info *denali, | |
111 | uint32_t int_mask); | |
ce082596 JR |
112 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
113 | ||
43914a2d MY |
114 | /* |
115 | * Certain operations for the denali NAND controller use an indexed mode to | |
116 | * read/write data. The operation is performed by writing the address value | |
117 | * of the command to the device memory followed by the data. This function | |
bdca6dae | 118 | * abstracts this common operation. |
43914a2d | 119 | */ |
bdca6dae CD |
120 | static void index_addr(struct denali_nand_info *denali, |
121 | uint32_t address, uint32_t data) | |
ce082596 | 122 | { |
24c3fa36 CD |
123 | iowrite32(address, denali->flash_mem); |
124 | iowrite32(data, denali->flash_mem + 0x10); | |
ce082596 JR |
125 | } |
126 | ||
127 | /* Perform an indexed read of the device */ | |
128 | static void index_addr_read_data(struct denali_nand_info *denali, | |
129 | uint32_t address, uint32_t *pdata) | |
130 | { | |
24c3fa36 | 131 | iowrite32(address, denali->flash_mem); |
ce082596 JR |
132 | *pdata = ioread32(denali->flash_mem + 0x10); |
133 | } | |
134 | ||
43914a2d MY |
135 | /* |
136 | * We need to buffer some data for some of the NAND core routines. | |
137 | * The operations manage buffering that data. | |
138 | */ | |
ce082596 JR |
139 | static void reset_buf(struct denali_nand_info *denali) |
140 | { | |
141 | denali->buf.head = denali->buf.tail = 0; | |
142 | } | |
143 | ||
144 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
145 | { | |
ce082596 JR |
146 | denali->buf.buf[denali->buf.tail++] = byte; |
147 | } | |
148 | ||
149 | /* reads the status of the device */ | |
150 | static void read_status(struct denali_nand_info *denali) | |
151 | { | |
5637b69d | 152 | uint32_t cmd; |
ce082596 JR |
153 | |
154 | /* initialize the data buffer to store status */ | |
155 | reset_buf(denali); | |
156 | ||
f0bc0c77 CD |
157 | cmd = ioread32(denali->flash_reg + WRITE_PROTECT); |
158 | if (cmd) | |
159 | write_byte_to_buf(denali, NAND_STATUS_WP); | |
160 | else | |
161 | write_byte_to_buf(denali, 0); | |
ce082596 JR |
162 | } |
163 | ||
164 | /* resets a specific device connected to the core */ | |
165 | static void reset_bank(struct denali_nand_info *denali) | |
166 | { | |
5637b69d | 167 | uint32_t irq_status; |
8125450c | 168 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
ce082596 JR |
169 | |
170 | clear_interrupts(denali); | |
171 | ||
9589bf5b | 172 | iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); |
ce082596 JR |
173 | |
174 | irq_status = wait_for_irq(denali, irq_mask); | |
5bac3acf | 175 | |
9589bf5b | 176 | if (irq_status & INTR_STATUS__TIME_OUT) |
84457949 | 177 | dev_err(denali->dev, "reset bank failed.\n"); |
ce082596 JR |
178 | } |
179 | ||
180 | /* Reset the flash controller */ | |
eda936ef | 181 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
ce082596 | 182 | { |
93e3c8ad | 183 | int i; |
ce082596 | 184 | |
84457949 | 185 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 186 | __FILE__, __LINE__, __func__); |
ce082596 | 187 | |
8125450c | 188 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b JI |
189 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
190 | denali->flash_reg + INTR_STATUS(i)); | |
ce082596 | 191 | |
8125450c | 192 | for (i = 0; i < denali->max_banks; i++) { |
9589bf5b | 193 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
8125450c | 194 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
9589bf5b | 195 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
628bfd41 | 196 | cpu_relax(); |
9589bf5b JI |
197 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
198 | INTR_STATUS__TIME_OUT) | |
84457949 | 199 | dev_dbg(denali->dev, |
ce082596 JR |
200 | "NAND Reset operation timed out on bank %d\n", i); |
201 | } | |
202 | ||
c89eeda8 | 203 | for (i = 0; i < denali->max_banks; i++) |
9589bf5b | 204 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
8125450c | 205 | denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
206 | |
207 | return PASS; | |
208 | } | |
209 | ||
43914a2d MY |
210 | /* |
211 | * this routine calculates the ONFI timing values for a given mode and | |
bdca6dae CD |
212 | * programs the clocking register accordingly. The mode is determined by |
213 | * the get_onfi_nand_para routine. | |
ce082596 | 214 | */ |
eda936ef | 215 | static void nand_onfi_timing_set(struct denali_nand_info *denali, |
bdca6dae | 216 | uint16_t mode) |
ce082596 JR |
217 | { |
218 | uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; | |
219 | uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; | |
220 | uint16_t Treh[6] = {30, 15, 15, 10, 10, 7}; | |
221 | uint16_t Trc[6] = {100, 50, 35, 30, 25, 20}; | |
222 | uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
223 | uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5}; | |
224 | uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25}; | |
225 | uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70}; | |
226 | uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100}; | |
227 | uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100}; | |
228 | uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60}; | |
229 | uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15}; | |
230 | ||
ce082596 JR |
231 | uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
232 | uint16_t dv_window = 0; | |
233 | uint16_t en_lo, en_hi; | |
234 | uint16_t acc_clks; | |
235 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
236 | ||
84457949 | 237 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 238 | __FILE__, __LINE__, __func__); |
ce082596 JR |
239 | |
240 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | |
241 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | |
242 | #if ONFI_BLOOM_TIME | |
243 | if ((en_hi * CLK_X) < (Treh[mode] + 2)) | |
244 | en_hi++; | |
245 | #endif | |
246 | ||
247 | if ((en_lo + en_hi) * CLK_X < Trc[mode]) | |
248 | en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X); | |
249 | ||
250 | if ((en_lo + en_hi) < CLK_MULTI) | |
251 | en_lo += CLK_MULTI - en_lo - en_hi; | |
252 | ||
253 | while (dv_window < 8) { | |
254 | data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode]; | |
255 | ||
256 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | |
257 | ||
8125450c MY |
258 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
259 | data_invalid_rhoh : data_invalid_rloh; | |
ce082596 JR |
260 | |
261 | dv_window = data_invalid - Trea[mode]; | |
262 | ||
263 | if (dv_window < 8) | |
264 | en_lo++; | |
265 | } | |
266 | ||
267 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | |
268 | ||
7d14ecd0 | 269 | while (acc_clks * CLK_X - Trea[mode] < 3) |
ce082596 JR |
270 | acc_clks++; |
271 | ||
7d14ecd0 | 272 | if (data_invalid - acc_clks * CLK_X < 2) |
84457949 | 273 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
8125450c | 274 | __FILE__, __LINE__); |
ce082596 JR |
275 | |
276 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | |
277 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | |
278 | re_2_re = CEIL_DIV(Trhz[mode], CLK_X); | |
279 | we_2_re = CEIL_DIV(Twhr[mode], CLK_X); | |
280 | cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X); | |
ce082596 JR |
281 | if (cs_cnt == 0) |
282 | cs_cnt = 1; | |
283 | ||
284 | if (Tcea[mode]) { | |
7d14ecd0 | 285 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
ce082596 JR |
286 | cs_cnt++; |
287 | } | |
288 | ||
289 | #if MODE5_WORKAROUND | |
290 | if (mode == 5) | |
291 | acc_clks = 5; | |
292 | #endif | |
293 | ||
294 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
7d14ecd0 MY |
295 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
296 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) | |
ce082596 JR |
297 | acc_clks = 6; |
298 | ||
24c3fa36 CD |
299 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
300 | iowrite32(re_2_we, denali->flash_reg + RE_2_WE); | |
301 | iowrite32(re_2_re, denali->flash_reg + RE_2_RE); | |
302 | iowrite32(we_2_re, denali->flash_reg + WE_2_RE); | |
303 | iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
304 | iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
305 | iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
306 | iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 JR |
307 | } |
308 | ||
ce082596 JR |
309 | /* queries the NAND device to see what ONFI modes it supports. */ |
310 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |
311 | { | |
312 | int i; | |
43914a2d MY |
313 | |
314 | /* | |
315 | * we needn't to do a reset here because driver has already | |
4c03bbdf | 316 | * reset all the banks before |
43914a2d | 317 | */ |
ce082596 JR |
318 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
319 | ONFI_TIMING_MODE__VALUE)) | |
320 | return FAIL; | |
321 | ||
322 | for (i = 5; i > 0; i--) { | |
bdca6dae CD |
323 | if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
324 | (0x01 << i)) | |
ce082596 JR |
325 | break; |
326 | } | |
327 | ||
eda936ef | 328 | nand_onfi_timing_set(denali, i); |
ce082596 | 329 | |
43914a2d MY |
330 | /* |
331 | * By now, all the ONFI devices we know support the page cache | |
332 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
333 | */ | |
ce082596 JR |
334 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
335 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | |
336 | ||
337 | return PASS; | |
338 | } | |
339 | ||
4c03bbdf CD |
340 | static void get_samsung_nand_para(struct denali_nand_info *denali, |
341 | uint8_t device_id) | |
ce082596 | 342 | { |
4c03bbdf | 343 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ |
ce082596 | 344 | /* Set timing register values according to datasheet */ |
24c3fa36 CD |
345 | iowrite32(5, denali->flash_reg + ACC_CLKS); |
346 | iowrite32(20, denali->flash_reg + RE_2_WE); | |
347 | iowrite32(12, denali->flash_reg + WE_2_RE); | |
348 | iowrite32(14, denali->flash_reg + ADDR_2_DATA); | |
349 | iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
350 | iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
351 | iowrite32(2, denali->flash_reg + CS_SETUP_CNT); | |
ce082596 | 352 | } |
ce082596 JR |
353 | } |
354 | ||
355 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
356 | { | |
ce082596 JR |
357 | uint32_t tmp; |
358 | ||
43914a2d MY |
359 | /* |
360 | * Workaround to fix a controller bug which reports a wrong | |
361 | * spare area size for some kind of Toshiba NAND device | |
362 | */ | |
ce082596 JR |
363 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
364 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
24c3fa36 | 365 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
ce082596 JR |
366 | tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * |
367 | ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
24c3fa36 | 368 | iowrite32(tmp, |
bdca6dae | 369 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
ce082596 | 370 | #if SUPPORT_15BITECC |
24c3fa36 | 371 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 372 | #elif SUPPORT_8BITECC |
24c3fa36 | 373 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
374 | #endif |
375 | } | |
ce082596 JR |
376 | } |
377 | ||
ef41e1bb CD |
378 | static void get_hynix_nand_para(struct denali_nand_info *denali, |
379 | uint8_t device_id) | |
ce082596 | 380 | { |
ce082596 JR |
381 | uint32_t main_size, spare_size; |
382 | ||
ef41e1bb | 383 | switch (device_id) { |
ce082596 JR |
384 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ |
385 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
24c3fa36 CD |
386 | iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK); |
387 | iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
388 | iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
bdca6dae CD |
389 | main_size = 4096 * |
390 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
391 | spare_size = 224 * | |
392 | ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
24c3fa36 | 393 | iowrite32(main_size, |
bdca6dae | 394 | denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); |
24c3fa36 | 395 | iowrite32(spare_size, |
bdca6dae | 396 | denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); |
24c3fa36 | 397 | iowrite32(0, denali->flash_reg + DEVICE_WIDTH); |
ce082596 | 398 | #if SUPPORT_15BITECC |
24c3fa36 | 399 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 400 | #elif SUPPORT_8BITECC |
24c3fa36 | 401 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 | 402 | #endif |
ce082596 JR |
403 | break; |
404 | default: | |
84457949 | 405 | dev_warn(denali->dev, |
8125450c MY |
406 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n" |
407 | "Will use default parameter values instead.\n", | |
408 | device_id); | |
ce082596 JR |
409 | } |
410 | } | |
411 | ||
43914a2d MY |
412 | /* |
413 | * determines how many NAND chips are connected to the controller. Note for | |
b292c341 | 414 | * Intel CE4100 devices we don't support more than one device. |
ce082596 JR |
415 | */ |
416 | static void find_valid_banks(struct denali_nand_info *denali) | |
417 | { | |
c89eeda8 | 418 | uint32_t id[denali->max_banks]; |
ce082596 JR |
419 | int i; |
420 | ||
421 | denali->total_used_banks = 1; | |
c89eeda8 | 422 | for (i = 0; i < denali->max_banks; i++) { |
3157d1ed MY |
423 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
424 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
8125450c | 425 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
ce082596 | 426 | |
84457949 | 427 | dev_dbg(denali->dev, |
ce082596 JR |
428 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
429 | ||
430 | if (i == 0) { | |
431 | if (!(id[i] & 0x0ff)) | |
432 | break; /* WTF? */ | |
433 | } else { | |
434 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
435 | denali->total_used_banks++; | |
436 | else | |
437 | break; | |
438 | } | |
439 | } | |
440 | ||
345b1d3b | 441 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
442 | /* |
443 | * Platform limitations of the CE4100 device limit | |
ce082596 | 444 | * users to a single chip solution for NAND. |
5bac3acf C |
445 | * Multichip support is not enabled. |
446 | */ | |
345b1d3b | 447 | if (denali->total_used_banks != 1) { |
84457949 | 448 | dev_err(denali->dev, |
8125450c | 449 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
ce082596 JR |
450 | BUG(); |
451 | } | |
452 | } | |
84457949 | 453 | dev_dbg(denali->dev, |
ce082596 JR |
454 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
455 | } | |
456 | ||
c89eeda8 JI |
457 | /* |
458 | * Use the configuration feature register to determine the maximum number of | |
459 | * banks that the hardware supports. | |
460 | */ | |
461 | static void detect_max_banks(struct denali_nand_info *denali) | |
462 | { | |
463 | uint32_t features = ioread32(denali->flash_reg + FEATURES); | |
271707b1 GM |
464 | /* |
465 | * Read the revision register, so we can calculate the max_banks | |
466 | * properly: the encoding changed from rev 5.0 to 5.1 | |
467 | */ | |
468 | u32 revision = MAKE_COMPARABLE_REVISION( | |
469 | ioread32(denali->flash_reg + REVISION)); | |
c89eeda8 | 470 | |
271707b1 GM |
471 | if (revision < REVISION_5_1) |
472 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
473 | else | |
474 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); | |
c89eeda8 JI |
475 | } |
476 | ||
ce082596 JR |
477 | static void detect_partition_feature(struct denali_nand_info *denali) |
478 | { | |
43914a2d MY |
479 | /* |
480 | * For MRST platform, denali->fwblks represent the | |
66406524 CD |
481 | * number of blocks firmware is taken, |
482 | * FW is in protect partition and MTD driver has no | |
483 | * permission to access it. So let driver know how many | |
484 | * blocks it can't touch. | |
43914a2d | 485 | */ |
ce082596 | 486 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
9589bf5b JI |
487 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & |
488 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | |
66406524 | 489 | denali->fwblks = |
9589bf5b JI |
490 | ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) & |
491 | MIN_MAX_BANK__MIN_VALUE) * | |
66406524 | 492 | denali->blksperchip) |
ce082596 | 493 | + |
9589bf5b JI |
494 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & |
495 | MIN_BLK_ADDR__VALUE); | |
8125450c | 496 | } else { |
66406524 | 497 | denali->fwblks = SPECTRA_START_BLOCK; |
8125450c MY |
498 | } |
499 | } else { | |
66406524 | 500 | denali->fwblks = SPECTRA_START_BLOCK; |
8125450c | 501 | } |
ce082596 JR |
502 | } |
503 | ||
eda936ef | 504 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
ce082596 JR |
505 | { |
506 | uint16_t status = PASS; | |
d68a5c3d | 507 | uint32_t id_bytes[8], addr; |
93e3c8ad MY |
508 | uint8_t maf_id, device_id; |
509 | int i; | |
ce082596 | 510 | |
8125450c | 511 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
7cfffac0 | 512 | __FILE__, __LINE__, __func__); |
ce082596 | 513 | |
43914a2d MY |
514 | /* |
515 | * Use read id method to get device ID and other params. | |
516 | * For some NAND chips, controller can't report the correct | |
517 | * device ID by reading from DEVICE_ID register | |
518 | */ | |
3157d1ed MY |
519 | addr = MODE_11 | BANK(denali->flash_bank); |
520 | index_addr(denali, addr | 0, 0x90); | |
521 | index_addr(denali, addr | 1, 0); | |
d68a5c3d | 522 | for (i = 0; i < 8; i++) |
ef41e1bb CD |
523 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
524 | maf_id = id_bytes[0]; | |
525 | device_id = id_bytes[1]; | |
ce082596 JR |
526 | |
527 | if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
528 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
529 | if (FAIL == get_onfi_nand_para(denali)) | |
530 | return FAIL; | |
ef41e1bb | 531 | } else if (maf_id == 0xEC) { /* Samsung NAND */ |
4c03bbdf | 532 | get_samsung_nand_para(denali, device_id); |
ef41e1bb | 533 | } else if (maf_id == 0x98) { /* Toshiba NAND */ |
ce082596 | 534 | get_toshiba_nand_para(denali); |
ef41e1bb CD |
535 | } else if (maf_id == 0xAD) { /* Hynix NAND */ |
536 | get_hynix_nand_para(denali, device_id); | |
ce082596 JR |
537 | } |
538 | ||
84457949 | 539 | dev_info(denali->dev, |
8125450c | 540 | "Dump timing register values:\n" |
7cfffac0 CD |
541 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
542 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | |
ce082596 JR |
543 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
544 | ioread32(denali->flash_reg + ACC_CLKS), | |
545 | ioread32(denali->flash_reg + RE_2_WE), | |
7cfffac0 | 546 | ioread32(denali->flash_reg + RE_2_RE), |
ce082596 JR |
547 | ioread32(denali->flash_reg + WE_2_RE), |
548 | ioread32(denali->flash_reg + ADDR_2_DATA), | |
549 | ioread32(denali->flash_reg + RDWR_EN_LO_CNT), | |
550 | ioread32(denali->flash_reg + RDWR_EN_HI_CNT), | |
551 | ioread32(denali->flash_reg + CS_SETUP_CNT)); | |
552 | ||
ce082596 JR |
553 | find_valid_banks(denali); |
554 | ||
555 | detect_partition_feature(denali); | |
556 | ||
43914a2d MY |
557 | /* |
558 | * If the user specified to override the default timings | |
5bac3acf | 559 | * with a specific ONFI mode, we apply those changes here. |
ce082596 JR |
560 | */ |
561 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
eda936ef | 562 | nand_onfi_timing_set(denali, onfi_timing_mode); |
ce082596 JR |
563 | |
564 | return status; | |
565 | } | |
566 | ||
eda936ef | 567 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
ce082596 JR |
568 | uint16_t INT_ENABLE) |
569 | { | |
84457949 | 570 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
8125450c | 571 | __FILE__, __LINE__, __func__); |
ce082596 JR |
572 | |
573 | if (INT_ENABLE) | |
24c3fa36 | 574 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 | 575 | else |
24c3fa36 | 576 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
ce082596 JR |
577 | } |
578 | ||
43914a2d MY |
579 | /* |
580 | * validation function to verify that the controlling software is making | |
b292c341 | 581 | * a valid request |
ce082596 JR |
582 | */ |
583 | static inline bool is_flash_bank_valid(int flash_bank) | |
584 | { | |
7d14ecd0 | 585 | return flash_bank >= 0 && flash_bank < 4; |
ce082596 JR |
586 | } |
587 | ||
588 | static void denali_irq_init(struct denali_nand_info *denali) | |
589 | { | |
5637b69d | 590 | uint32_t int_mask; |
9589bf5b | 591 | int i; |
ce082596 JR |
592 | |
593 | /* Disable global interrupts */ | |
eda936ef | 594 | denali_set_intr_modes(denali, false); |
ce082596 JR |
595 | |
596 | int_mask = DENALI_IRQ_ALL; | |
597 | ||
598 | /* Clear all status bits */ | |
c89eeda8 | 599 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 600 | iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i)); |
ce082596 JR |
601 | |
602 | denali_irq_enable(denali, int_mask); | |
603 | } | |
604 | ||
605 | static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali) | |
606 | { | |
eda936ef | 607 | denali_set_intr_modes(denali, false); |
ce082596 JR |
608 | free_irq(irqnum, denali); |
609 | } | |
610 | ||
bdca6dae CD |
611 | static void denali_irq_enable(struct denali_nand_info *denali, |
612 | uint32_t int_mask) | |
ce082596 | 613 | { |
9589bf5b JI |
614 | int i; |
615 | ||
c89eeda8 | 616 | for (i = 0; i < denali->max_banks; ++i) |
9589bf5b | 617 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
ce082596 JR |
618 | } |
619 | ||
43914a2d MY |
620 | /* |
621 | * This function only returns when an interrupt that this driver cares about | |
5bac3acf | 622 | * occurs. This is to reduce the overhead of servicing interrupts |
ce082596 JR |
623 | */ |
624 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |
625 | { | |
a99d1796 | 626 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
ce082596 JR |
627 | } |
628 | ||
629 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
bdca6dae CD |
630 | static inline void clear_interrupt(struct denali_nand_info *denali, |
631 | uint32_t irq_mask) | |
ce082596 | 632 | { |
5637b69d | 633 | uint32_t intr_status_reg; |
ce082596 | 634 | |
9589bf5b | 635 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 | 636 | |
24c3fa36 | 637 | iowrite32(irq_mask, denali->flash_reg + intr_status_reg); |
ce082596 JR |
638 | } |
639 | ||
640 | static void clear_interrupts(struct denali_nand_info *denali) | |
641 | { | |
5637b69d MY |
642 | uint32_t status; |
643 | ||
ce082596 JR |
644 | spin_lock_irq(&denali->irq_lock); |
645 | ||
646 | status = read_interrupt_status(denali); | |
8ae61ebd | 647 | clear_interrupt(denali, status); |
ce082596 | 648 | |
ce082596 JR |
649 | denali->irq_status = 0x0; |
650 | spin_unlock_irq(&denali->irq_lock); | |
651 | } | |
652 | ||
653 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
654 | { | |
5637b69d | 655 | uint32_t intr_status_reg; |
ce082596 | 656 | |
9589bf5b | 657 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
ce082596 JR |
658 | |
659 | return ioread32(denali->flash_reg + intr_status_reg); | |
660 | } | |
661 | ||
43914a2d MY |
662 | /* |
663 | * This is the interrupt service routine. It handles all interrupts | |
664 | * sent to this device. Note that on CE4100, this is a shared interrupt. | |
ce082596 JR |
665 | */ |
666 | static irqreturn_t denali_isr(int irq, void *dev_id) | |
667 | { | |
668 | struct denali_nand_info *denali = dev_id; | |
5637b69d | 669 | uint32_t irq_status; |
ce082596 JR |
670 | irqreturn_t result = IRQ_NONE; |
671 | ||
672 | spin_lock(&denali->irq_lock); | |
673 | ||
43914a2d | 674 | /* check to see if a valid NAND chip has been selected. */ |
345b1d3b | 675 | if (is_flash_bank_valid(denali->flash_bank)) { |
43914a2d MY |
676 | /* |
677 | * check to see if controller generated the interrupt, | |
678 | * since this is a shared interrupt | |
679 | */ | |
bdca6dae CD |
680 | irq_status = denali_irq_detected(denali); |
681 | if (irq_status != 0) { | |
ce082596 JR |
682 | /* handle interrupt */ |
683 | /* first acknowledge it */ | |
684 | clear_interrupt(denali, irq_status); | |
43914a2d MY |
685 | /* |
686 | * store the status in the device context for someone | |
687 | * to read | |
688 | */ | |
ce082596 JR |
689 | denali->irq_status |= irq_status; |
690 | /* notify anyone who cares that it happened */ | |
691 | complete(&denali->complete); | |
692 | /* tell the OS that we've handled this */ | |
693 | result = IRQ_HANDLED; | |
694 | } | |
695 | } | |
696 | spin_unlock(&denali->irq_lock); | |
697 | return result; | |
698 | } | |
699 | #define BANK(x) ((x) << 24) | |
700 | ||
701 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
702 | { | |
5637b69d MY |
703 | unsigned long comp_res; |
704 | uint32_t intr_status; | |
ce082596 JR |
705 | unsigned long timeout = msecs_to_jiffies(1000); |
706 | ||
345b1d3b | 707 | do { |
bdca6dae CD |
708 | comp_res = |
709 | wait_for_completion_timeout(&denali->complete, timeout); | |
ce082596 JR |
710 | spin_lock_irq(&denali->irq_lock); |
711 | intr_status = denali->irq_status; | |
712 | ||
345b1d3b | 713 | if (intr_status & irq_mask) { |
ce082596 JR |
714 | denali->irq_status &= ~irq_mask; |
715 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
716 | /* our interrupt was detected */ |
717 | break; | |
ce082596 | 718 | } |
8125450c MY |
719 | |
720 | /* | |
721 | * these are not the interrupts you are looking for - | |
722 | * need to wait again | |
723 | */ | |
724 | spin_unlock_irq(&denali->irq_lock); | |
ce082596 JR |
725 | } while (comp_res != 0); |
726 | ||
345b1d3b | 727 | if (comp_res == 0) { |
ce082596 | 728 | /* timeout */ |
2a0a288e | 729 | pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n", |
5bac3acf | 730 | intr_status, irq_mask); |
ce082596 JR |
731 | |
732 | intr_status = 0; | |
733 | } | |
734 | return intr_status; | |
735 | } | |
736 | ||
43914a2d MY |
737 | /* |
738 | * This helper function setups the registers for ECC and whether or not | |
739 | * the spare area will be transferred. | |
740 | */ | |
5bac3acf | 741 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
ce082596 JR |
742 | bool transfer_spare) |
743 | { | |
5637b69d | 744 | int ecc_en_flag, transfer_spare_flag; |
ce082596 JR |
745 | |
746 | /* set ECC, transfer spare bits if needed */ | |
747 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
748 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
749 | ||
750 | /* Enable spare area/ECC per user's request. */ | |
24c3fa36 | 751 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
8125450c | 752 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
ce082596 JR |
753 | } |
754 | ||
43914a2d MY |
755 | /* |
756 | * sends a pipeline command operation to the controller. See the Denali NAND | |
b292c341 | 757 | * controller's user guide for more information (section 4.2.3.6). |
ce082596 | 758 | */ |
bdca6dae | 759 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
8125450c MY |
760 | bool ecc_en, bool transfer_spare, |
761 | int access_type, int op) | |
ce082596 JR |
762 | { |
763 | int status = PASS; | |
5637b69d MY |
764 | uint32_t page_count = 1; |
765 | uint32_t addr, cmd, irq_status, irq_mask; | |
ce082596 | 766 | |
a99d1796 | 767 | if (op == DENALI_READ) |
9589bf5b | 768 | irq_mask = INTR_STATUS__LOAD_COMP; |
a99d1796 CD |
769 | else if (op == DENALI_WRITE) |
770 | irq_mask = 0; | |
771 | else | |
772 | BUG(); | |
ce082596 JR |
773 | |
774 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
775 | ||
5bac3acf | 776 | clear_interrupts(denali); |
ce082596 JR |
777 | |
778 | addr = BANK(denali->flash_bank) | denali->page; | |
779 | ||
345b1d3b | 780 | if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { |
5bac3acf | 781 | cmd = MODE_01 | addr; |
24c3fa36 | 782 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 783 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
ce082596 | 784 | /* read spare area */ |
5bac3acf | 785 | cmd = MODE_10 | addr; |
3157d1ed | 786 | index_addr(denali, cmd, access_type); |
ce082596 | 787 | |
5bac3acf | 788 | cmd = MODE_01 | addr; |
24c3fa36 | 789 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 790 | } else if (op == DENALI_READ) { |
ce082596 | 791 | /* setup page read request for access type */ |
5bac3acf | 792 | cmd = MODE_10 | addr; |
3157d1ed | 793 | index_addr(denali, cmd, access_type); |
ce082596 | 794 | |
43914a2d MY |
795 | /* |
796 | * page 33 of the NAND controller spec indicates we should not | |
797 | * use the pipeline commands in Spare area only mode. | |
798 | * So we don't. | |
ce082596 | 799 | */ |
345b1d3b | 800 | if (access_type == SPARE_ACCESS) { |
ce082596 | 801 | cmd = MODE_01 | addr; |
24c3fa36 | 802 | iowrite32(cmd, denali->flash_mem); |
345b1d3b | 803 | } else { |
3157d1ed | 804 | index_addr(denali, cmd, |
2902330e | 805 | PIPELINE_ACCESS | op | page_count); |
5bac3acf | 806 | |
43914a2d MY |
807 | /* |
808 | * wait for command to be accepted | |
bdca6dae | 809 | * can always use status0 bit as the |
43914a2d MY |
810 | * mask is identical for each bank. |
811 | */ | |
ce082596 JR |
812 | irq_status = wait_for_irq(denali, irq_mask); |
813 | ||
345b1d3b | 814 | if (irq_status == 0) { |
84457949 | 815 | dev_err(denali->dev, |
8125450c MY |
816 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
817 | cmd, denali->page, addr); | |
ce082596 | 818 | status = FAIL; |
345b1d3b | 819 | } else { |
ce082596 | 820 | cmd = MODE_01 | addr; |
24c3fa36 | 821 | iowrite32(cmd, denali->flash_mem); |
ce082596 JR |
822 | } |
823 | } | |
824 | } | |
825 | return status; | |
826 | } | |
827 | ||
828 | /* helper function that simply writes a buffer to the flash */ | |
bdca6dae | 829 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
8125450c | 830 | const uint8_t *buf, int len) |
ce082596 | 831 | { |
93e3c8ad MY |
832 | uint32_t *buf32; |
833 | int i; | |
ce082596 | 834 | |
43914a2d MY |
835 | /* |
836 | * verify that the len is a multiple of 4. | |
837 | * see comment in read_data_from_flash_mem() | |
838 | */ | |
ce082596 JR |
839 | BUG_ON((len % 4) != 0); |
840 | ||
841 | /* write the data to the flash memory */ | |
842 | buf32 = (uint32_t *)buf; | |
843 | for (i = 0; i < len / 4; i++) | |
24c3fa36 | 844 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
8125450c | 845 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
846 | } |
847 | ||
848 | /* helper function that simply reads a buffer from the flash */ | |
bdca6dae | 849 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
8125450c | 850 | uint8_t *buf, int len) |
ce082596 | 851 | { |
93e3c8ad MY |
852 | uint32_t *buf32; |
853 | int i; | |
ce082596 | 854 | |
43914a2d MY |
855 | /* |
856 | * we assume that len will be a multiple of 4, if not it would be nice | |
857 | * to know about it ASAP rather than have random failures... | |
858 | * This assumption is based on the fact that this function is designed | |
859 | * to be used to read flash pages, which are typically multiples of 4. | |
ce082596 | 860 | */ |
ce082596 JR |
861 | BUG_ON((len % 4) != 0); |
862 | ||
863 | /* transfer the data from the flash */ | |
864 | buf32 = (uint32_t *)buf; | |
865 | for (i = 0; i < len / 4; i++) | |
ce082596 | 866 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
8125450c | 867 | return i * 4; /* intent is to return the number of bytes read */ |
ce082596 JR |
868 | } |
869 | ||
870 | /* writes OOB data to the device */ | |
871 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
872 | { | |
873 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d | 874 | uint32_t irq_status; |
9589bf5b JI |
875 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
876 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 JR |
877 | int status = 0; |
878 | ||
879 | denali->page = page; | |
880 | ||
5bac3acf | 881 | if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, |
345b1d3b | 882 | DENALI_WRITE) == PASS) { |
ce082596 JR |
883 | write_data_to_flash_mem(denali, buf, mtd->oobsize); |
884 | ||
ce082596 JR |
885 | /* wait for operation to complete */ |
886 | irq_status = wait_for_irq(denali, irq_mask); | |
887 | ||
345b1d3b | 888 | if (irq_status == 0) { |
84457949 | 889 | dev_err(denali->dev, "OOB write failed\n"); |
ce082596 JR |
890 | status = -EIO; |
891 | } | |
345b1d3b | 892 | } else { |
84457949 | 893 | dev_err(denali->dev, "unable to send pipeline command\n"); |
5bac3acf | 894 | status = -EIO; |
ce082596 JR |
895 | } |
896 | return status; | |
897 | } | |
898 | ||
899 | /* reads OOB data from the device */ | |
900 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
901 | { | |
902 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
5637b69d MY |
903 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
904 | uint32_t irq_status, addr, cmd; | |
ce082596 JR |
905 | |
906 | denali->page = page; | |
907 | ||
5bac3acf | 908 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, |
345b1d3b | 909 | DENALI_READ) == PASS) { |
5bac3acf | 910 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
ce082596 | 911 | |
43914a2d MY |
912 | /* |
913 | * wait for command to be accepted | |
914 | * can always use status0 bit as the | |
915 | * mask is identical for each bank. | |
916 | */ | |
ce082596 JR |
917 | irq_status = wait_for_irq(denali, irq_mask); |
918 | ||
919 | if (irq_status == 0) | |
84457949 | 920 | dev_err(denali->dev, "page on OOB timeout %d\n", |
bdca6dae | 921 | denali->page); |
ce082596 | 922 | |
43914a2d MY |
923 | /* |
924 | * We set the device back to MAIN_ACCESS here as I observed | |
ce082596 JR |
925 | * instability with the controller if you do a block erase |
926 | * and the last transaction was a SPARE_ACCESS. Block erase | |
927 | * is reliable (according to the MTD test infrastructure) | |
5bac3acf | 928 | * if you are in MAIN_ACCESS. |
ce082596 JR |
929 | */ |
930 | addr = BANK(denali->flash_bank) | denali->page; | |
5bac3acf | 931 | cmd = MODE_10 | addr; |
3157d1ed | 932 | index_addr(denali, cmd, MAIN_ACCESS); |
ce082596 JR |
933 | } |
934 | } | |
935 | ||
43914a2d MY |
936 | /* |
937 | * this function examines buffers to see if they contain data that | |
ce082596 JR |
938 | * indicate that the buffer is part of an erased region of flash. |
939 | */ | |
919193ce | 940 | static bool is_erased(uint8_t *buf, int len) |
ce082596 | 941 | { |
5637b69d | 942 | int i; |
8125450c | 943 | |
ce082596 | 944 | for (i = 0; i < len; i++) |
ce082596 | 945 | if (buf[i] != 0xFF) |
ce082596 | 946 | return false; |
ce082596 JR |
947 | return true; |
948 | } | |
949 | #define ECC_SECTOR_SIZE 512 | |
950 | ||
951 | #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12) | |
952 | #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET)) | |
953 | #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK) | |
8ae61ebd CD |
954 | #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE)) |
955 | #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8) | |
ce082596 JR |
956 | #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO) |
957 | ||
5bac3acf | 958 | static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, |
3f91e94f | 959 | uint32_t irq_status, unsigned int *max_bitflips) |
ce082596 JR |
960 | { |
961 | bool check_erased_page = false; | |
3f91e94f | 962 | unsigned int bitflips = 0; |
ce082596 | 963 | |
9589bf5b | 964 | if (irq_status & INTR_STATUS__ECC_ERR) { |
ce082596 | 965 | /* read the ECC errors. we'll ignore them for now */ |
5637b69d MY |
966 | uint32_t err_address, err_correction_info, err_byte, |
967 | err_sector, err_device, err_correction_value; | |
8ae61ebd | 968 | denali_set_intr_modes(denali, false); |
ce082596 | 969 | |
345b1d3b | 970 | do { |
5bac3acf | 971 | err_address = ioread32(denali->flash_reg + |
ce082596 JR |
972 | ECC_ERROR_ADDRESS); |
973 | err_sector = ECC_SECTOR(err_address); | |
974 | err_byte = ECC_BYTE(err_address); | |
975 | ||
5bac3acf | 976 | err_correction_info = ioread32(denali->flash_reg + |
ce082596 | 977 | ERR_CORRECTION_INFO); |
5bac3acf | 978 | err_correction_value = |
ce082596 JR |
979 | ECC_CORRECTION_VALUE(err_correction_info); |
980 | err_device = ECC_ERR_DEVICE(err_correction_info); | |
981 | ||
345b1d3b | 982 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
43914a2d MY |
983 | /* |
984 | * If err_byte is larger than ECC_SECTOR_SIZE, | |
25985edc | 985 | * means error happened in OOB, so we ignore |
8ae61ebd CD |
986 | * it. It's no need for us to correct it |
987 | * err_device is represented the NAND error | |
988 | * bits are happened in if there are more | |
989 | * than one NAND connected. | |
43914a2d | 990 | */ |
8ae61ebd | 991 | if (err_byte < ECC_SECTOR_SIZE) { |
442f201b BB |
992 | struct mtd_info *mtd = |
993 | nand_to_mtd(&denali->nand); | |
8ae61ebd | 994 | int offset; |
8125450c | 995 | |
8ae61ebd CD |
996 | offset = (err_sector * |
997 | ECC_SECTOR_SIZE + | |
998 | err_byte) * | |
999 | denali->devnum + | |
1000 | err_device; | |
ce082596 JR |
1001 | /* correct the ECC error */ |
1002 | buf[offset] ^= err_correction_value; | |
442f201b | 1003 | mtd->ecc_stats.corrected++; |
3f91e94f | 1004 | bitflips++; |
ce082596 | 1005 | } |
345b1d3b | 1006 | } else { |
43914a2d MY |
1007 | /* |
1008 | * if the error is not correctable, need to | |
bdca6dae CD |
1009 | * look at the page to see if it is an erased |
1010 | * page. if so, then it's not a real ECC error | |
43914a2d | 1011 | */ |
ce082596 JR |
1012 | check_erased_page = true; |
1013 | } | |
ce082596 | 1014 | } while (!ECC_LAST_ERR(err_correction_info)); |
43914a2d MY |
1015 | /* |
1016 | * Once handle all ecc errors, controller will triger | |
8ae61ebd CD |
1017 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
1018 | * for a while for this interrupt | |
43914a2d | 1019 | */ |
8ae61ebd | 1020 | while (!(read_interrupt_status(denali) & |
9589bf5b | 1021 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
8ae61ebd CD |
1022 | cpu_relax(); |
1023 | clear_interrupts(denali); | |
1024 | denali_set_intr_modes(denali, true); | |
ce082596 | 1025 | } |
3f91e94f | 1026 | *max_bitflips = bitflips; |
ce082596 JR |
1027 | return check_erased_page; |
1028 | } | |
1029 | ||
1030 | /* programs the controller to either enable/disable DMA transfers */ | |
aadff49c | 1031 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
ce082596 | 1032 | { |
5637b69d | 1033 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
ce082596 JR |
1034 | ioread32(denali->flash_reg + DMA_ENABLE); |
1035 | } | |
1036 | ||
1037 | /* setups the HW to perform the data DMA */ | |
aadff49c | 1038 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
ce082596 | 1039 | { |
5637b69d | 1040 | uint32_t mode; |
ce082596 | 1041 | const int page_count = 1; |
3157d1ed | 1042 | uint32_t addr = denali->buf.dma_buf; |
ce082596 JR |
1043 | |
1044 | mode = MODE_10 | BANK(denali->flash_bank); | |
1045 | ||
1046 | /* DMA is a four step process */ | |
1047 | ||
1048 | /* 1. setup transfer type and # of pages */ | |
1049 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
1050 | ||
1051 | /* 2. set memory high address bits 23:8 */ | |
3157d1ed | 1052 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
ce082596 JR |
1053 | |
1054 | /* 3. set memory low address bits 23:8 */ | |
7c272ac5 | 1055 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
ce082596 | 1056 | |
43914a2d | 1057 | /* 4. interrupt when complete, burst len = 64 bytes */ |
ce082596 JR |
1058 | index_addr(denali, mode | 0x14000, 0x2400); |
1059 | } | |
1060 | ||
43914a2d MY |
1061 | /* |
1062 | * writes a page. user specifies type, and this function handles the | |
1063 | * configuration details. | |
1064 | */ | |
fdbad98d | 1065 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1066 | const uint8_t *buf, bool raw_xfer) |
1067 | { | |
1068 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1069 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1070 | size_t size = mtd->writesize + mtd->oobsize; |
5637b69d | 1071 | uint32_t irq_status; |
9589bf5b JI |
1072 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1073 | INTR_STATUS__PROGRAM_FAIL; | |
ce082596 | 1074 | |
43914a2d MY |
1075 | /* |
1076 | * if it is a raw xfer, we want to disable ecc and send the spare area. | |
ce082596 JR |
1077 | * !raw_xfer - enable ecc |
1078 | * raw_xfer - transfer spare | |
1079 | */ | |
1080 | setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer); | |
1081 | ||
1082 | /* copy buffer into DMA buffer */ | |
1083 | memcpy(denali->buf.buf, buf, mtd->writesize); | |
1084 | ||
345b1d3b | 1085 | if (raw_xfer) { |
ce082596 | 1086 | /* transfer the data to the spare area */ |
5bac3acf C |
1087 | memcpy(denali->buf.buf + mtd->writesize, |
1088 | chip->oob_poi, | |
1089 | mtd->oobsize); | |
ce082596 JR |
1090 | } |
1091 | ||
84457949 | 1092 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
ce082596 JR |
1093 | |
1094 | clear_interrupts(denali); | |
5bac3acf | 1095 | denali_enable_dma(denali, true); |
ce082596 | 1096 | |
aadff49c | 1097 | denali_setup_dma(denali, DENALI_WRITE); |
ce082596 JR |
1098 | |
1099 | /* wait for operation to complete */ | |
1100 | irq_status = wait_for_irq(denali, irq_mask); | |
1101 | ||
345b1d3b | 1102 | if (irq_status == 0) { |
8125450c MY |
1103 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
1104 | raw_xfer); | |
c115add9 | 1105 | denali->status = NAND_STATUS_FAIL; |
ce082596 JR |
1106 | } |
1107 | ||
5bac3acf | 1108 | denali_enable_dma(denali, false); |
84457949 | 1109 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
fdbad98d JW |
1110 | |
1111 | return 0; | |
ce082596 JR |
1112 | } |
1113 | ||
1114 | /* NAND core entry points */ | |
1115 | ||
43914a2d MY |
1116 | /* |
1117 | * this is the callback that the NAND core calls to write a page. Since | |
b292c341 CD |
1118 | * writing a page with ECC or without is similar, all the work is done |
1119 | * by write_page above. | |
43914a2d | 1120 | */ |
fdbad98d | 1121 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 1122 | const uint8_t *buf, int oob_required, int page) |
ce082596 | 1123 | { |
43914a2d MY |
1124 | /* |
1125 | * for regular page writes, we let HW handle all the ECC | |
1126 | * data written to the device. | |
1127 | */ | |
fdbad98d | 1128 | return write_page(mtd, chip, buf, false); |
ce082596 JR |
1129 | } |
1130 | ||
43914a2d MY |
1131 | /* |
1132 | * This is the callback that the NAND core calls to write a page without ECC. | |
25985edc | 1133 | * raw access is similar to ECC page writes, so all the work is done in the |
b292c341 | 1134 | * write_page() function above. |
ce082596 | 1135 | */ |
fdbad98d | 1136 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
1137 | const uint8_t *buf, int oob_required, |
1138 | int page) | |
ce082596 | 1139 | { |
43914a2d MY |
1140 | /* |
1141 | * for raw page writes, we want to disable ECC and simply write | |
1142 | * whatever data is in the buffer. | |
1143 | */ | |
fdbad98d | 1144 | return write_page(mtd, chip, buf, true); |
ce082596 JR |
1145 | } |
1146 | ||
5bac3acf | 1147 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, |
ce082596 JR |
1148 | int page) |
1149 | { | |
5bac3acf | 1150 | return write_oob_data(mtd, chip->oob_poi, page); |
ce082596 JR |
1151 | } |
1152 | ||
5bac3acf | 1153 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, |
5c2ffb11 | 1154 | int page) |
ce082596 JR |
1155 | { |
1156 | read_oob_data(mtd, chip->oob_poi, page); | |
1157 | ||
5c2ffb11 | 1158 | return 0; |
ce082596 JR |
1159 | } |
1160 | ||
1161 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1162 | uint8_t *buf, int oob_required, int page) |
ce082596 | 1163 | { |
3f91e94f | 1164 | unsigned int max_bitflips; |
ce082596 | 1165 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
ce082596 JR |
1166 | |
1167 | dma_addr_t addr = denali->buf.dma_buf; | |
442f201b | 1168 | size_t size = mtd->writesize + mtd->oobsize; |
ce082596 | 1169 | |
5637b69d | 1170 | uint32_t irq_status; |
9589bf5b JI |
1171 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1172 | INTR_STATUS__ECC_ERR; | |
ce082596 JR |
1173 | bool check_erased_page = false; |
1174 | ||
7d8a26fd | 1175 | if (page != denali->page) { |
8125450c MY |
1176 | dev_err(denali->dev, |
1177 | "IN %s: page %d is not equal to denali->page %d", | |
1178 | __func__, page, denali->page); | |
7d8a26fd CD |
1179 | BUG(); |
1180 | } | |
1181 | ||
ce082596 JR |
1182 | setup_ecc_for_xfer(denali, true, false); |
1183 | ||
aadff49c | 1184 | denali_enable_dma(denali, true); |
84457949 | 1185 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1186 | |
1187 | clear_interrupts(denali); | |
aadff49c | 1188 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1189 | |
1190 | /* wait for operation to complete */ | |
1191 | irq_status = wait_for_irq(denali, irq_mask); | |
1192 | ||
84457949 | 1193 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1194 | |
1195 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
5bac3acf | 1196 | |
3f91e94f | 1197 | check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips); |
aadff49c | 1198 | denali_enable_dma(denali, false); |
ce082596 | 1199 | |
345b1d3b | 1200 | if (check_erased_page) { |
442f201b | 1201 | read_oob_data(mtd, chip->oob_poi, denali->page); |
ce082596 JR |
1202 | |
1203 | /* check ECC failures that may have occurred on erased pages */ | |
345b1d3b | 1204 | if (check_erased_page) { |
442f201b BB |
1205 | if (!is_erased(buf, mtd->writesize)) |
1206 | mtd->ecc_stats.failed++; | |
1207 | if (!is_erased(buf, mtd->oobsize)) | |
1208 | mtd->ecc_stats.failed++; | |
5bac3acf | 1209 | } |
ce082596 | 1210 | } |
3f91e94f | 1211 | return max_bitflips; |
ce082596 JR |
1212 | } |
1213 | ||
1214 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1215 | uint8_t *buf, int oob_required, int page) |
ce082596 JR |
1216 | { |
1217 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ce082596 | 1218 | dma_addr_t addr = denali->buf.dma_buf; |
442f201b | 1219 | size_t size = mtd->writesize + mtd->oobsize; |
9589bf5b | 1220 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
5bac3acf | 1221 | |
7d8a26fd | 1222 | if (page != denali->page) { |
8125450c MY |
1223 | dev_err(denali->dev, |
1224 | "IN %s: page %d is not equal to denali->page %d", | |
1225 | __func__, page, denali->page); | |
7d8a26fd CD |
1226 | BUG(); |
1227 | } | |
1228 | ||
ce082596 | 1229 | setup_ecc_for_xfer(denali, false, true); |
aadff49c | 1230 | denali_enable_dma(denali, true); |
ce082596 | 1231 | |
84457949 | 1232 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 JR |
1233 | |
1234 | clear_interrupts(denali); | |
aadff49c | 1235 | denali_setup_dma(denali, DENALI_READ); |
ce082596 JR |
1236 | |
1237 | /* wait for operation to complete */ | |
ba5f2bc2 | 1238 | wait_for_irq(denali, irq_mask); |
ce082596 | 1239 | |
84457949 | 1240 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
ce082596 | 1241 | |
aadff49c | 1242 | denali_enable_dma(denali, false); |
ce082596 JR |
1243 | |
1244 | memcpy(buf, denali->buf.buf, mtd->writesize); | |
1245 | memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1251 | { | |
1252 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1253 | uint8_t result = 0xff; | |
1254 | ||
1255 | if (denali->buf.head < denali->buf.tail) | |
ce082596 | 1256 | result = denali->buf.buf[denali->buf.head++]; |
ce082596 | 1257 | |
ce082596 JR |
1258 | return result; |
1259 | } | |
1260 | ||
1261 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1262 | { | |
1263 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
7cfffac0 | 1264 | |
ce082596 JR |
1265 | spin_lock_irq(&denali->irq_lock); |
1266 | denali->flash_bank = chip; | |
1267 | spin_unlock_irq(&denali->irq_lock); | |
1268 | } | |
1269 | ||
1270 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1271 | { | |
1272 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1273 | int status = denali->status; | |
8125450c | 1274 | |
ce082596 JR |
1275 | denali->status = 0; |
1276 | ||
ce082596 JR |
1277 | return status; |
1278 | } | |
1279 | ||
49c50b97 | 1280 | static int denali_erase(struct mtd_info *mtd, int page) |
ce082596 JR |
1281 | { |
1282 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1283 | ||
5637b69d | 1284 | uint32_t cmd, irq_status; |
ce082596 | 1285 | |
5bac3acf | 1286 | clear_interrupts(denali); |
ce082596 JR |
1287 | |
1288 | /* setup page read request for access type */ | |
1289 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
3157d1ed | 1290 | index_addr(denali, cmd, 0x1); |
ce082596 JR |
1291 | |
1292 | /* wait for erase to complete or failure to occur */ | |
9589bf5b JI |
1293 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1294 | INTR_STATUS__ERASE_FAIL); | |
ce082596 | 1295 | |
7d14ecd0 | 1296 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
ce082596 JR |
1297 | } |
1298 | ||
5bac3acf | 1299 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
ce082596 JR |
1300 | int page) |
1301 | { | |
1302 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
ef41e1bb CD |
1303 | uint32_t addr, id; |
1304 | int i; | |
ce082596 | 1305 | |
345b1d3b | 1306 | switch (cmd) { |
a99d1796 CD |
1307 | case NAND_CMD_PAGEPROG: |
1308 | break; | |
1309 | case NAND_CMD_STATUS: | |
1310 | read_status(denali); | |
1311 | break; | |
1312 | case NAND_CMD_READID: | |
42af8b58 | 1313 | case NAND_CMD_PARAM: |
a99d1796 | 1314 | reset_buf(denali); |
43914a2d MY |
1315 | /* |
1316 | * sometimes ManufactureId read from register is not right | |
ef41e1bb CD |
1317 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1318 | * So here we send READID cmd to NAND insteand | |
43914a2d | 1319 | */ |
3157d1ed MY |
1320 | addr = MODE_11 | BANK(denali->flash_bank); |
1321 | index_addr(denali, addr | 0, 0x90); | |
9c07d094 | 1322 | index_addr(denali, addr | 1, col); |
d68a5c3d | 1323 | for (i = 0; i < 8; i++) { |
8125450c | 1324 | index_addr_read_data(denali, addr | 2, &id); |
ef41e1bb | 1325 | write_byte_to_buf(denali, id); |
a99d1796 CD |
1326 | } |
1327 | break; | |
1328 | case NAND_CMD_READ0: | |
1329 | case NAND_CMD_SEQIN: | |
1330 | denali->page = page; | |
1331 | break; | |
1332 | case NAND_CMD_RESET: | |
1333 | reset_bank(denali); | |
1334 | break; | |
1335 | case NAND_CMD_READOOB: | |
1336 | /* TODO: Read OOB data */ | |
1337 | break; | |
1338 | default: | |
2a0a288e | 1339 | pr_err(": unsupported command received 0x%x\n", cmd); |
a99d1796 | 1340 | break; |
ce082596 JR |
1341 | } |
1342 | } | |
ce082596 JR |
1343 | /* end NAND core entry points */ |
1344 | ||
1345 | /* Initialization code to bring the device up to a known good state */ | |
1346 | static void denali_hw_init(struct denali_nand_info *denali) | |
1347 | { | |
43914a2d MY |
1348 | /* |
1349 | * tell driver how many bit controller will skip before | |
db9a3210 CD |
1350 | * writing ECC code in OOB, this register may be already |
1351 | * set by firmware. So we read this value out. | |
1352 | * if this value is 0, just let it be. | |
43914a2d | 1353 | */ |
db9a3210 CD |
1354 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
1355 | SPARE_AREA_SKIP_BYTES); | |
bc27ede3 | 1356 | detect_max_banks(denali); |
eda936ef | 1357 | denali_nand_reset(denali); |
24c3fa36 CD |
1358 | iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED); |
1359 | iowrite32(CHIP_EN_DONT_CARE__FLAG, | |
bdca6dae | 1360 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); |
ce082596 | 1361 | |
24c3fa36 | 1362 | iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); |
ce082596 JR |
1363 | |
1364 | /* Should set value for these registers when init */ | |
24c3fa36 CD |
1365 | iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); |
1366 | iowrite32(1, denali->flash_reg + ECC_ENABLE); | |
5eab6aaa CD |
1367 | denali_nand_timing_set(denali); |
1368 | denali_irq_init(denali); | |
ce082596 JR |
1369 | } |
1370 | ||
43914a2d MY |
1371 | /* |
1372 | * Althogh controller spec said SLC ECC is forceb to be 4bit, | |
db9a3210 CD |
1373 | * but denali controller in MRST only support 15bit and 8bit ECC |
1374 | * correction | |
43914a2d | 1375 | */ |
db9a3210 | 1376 | #define ECC_8BITS 14 |
db9a3210 | 1377 | #define ECC_15BITS 26 |
14fad62b BB |
1378 | |
1379 | static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1380 | struct mtd_oob_region *oobregion) | |
1381 | { | |
1382 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1383 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1384 | ||
1385 | if (section) | |
1386 | return -ERANGE; | |
1387 | ||
1388 | oobregion->offset = denali->bbtskipbytes; | |
1389 | oobregion->length = chip->ecc.total; | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
1394 | static int denali_ooblayout_free(struct mtd_info *mtd, int section, | |
1395 | struct mtd_oob_region *oobregion) | |
1396 | { | |
1397 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1398 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1399 | ||
1400 | if (section) | |
1401 | return -ERANGE; | |
1402 | ||
1403 | oobregion->offset = chip->ecc.total + denali->bbtskipbytes; | |
1404 | oobregion->length = mtd->oobsize - oobregion->offset; | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static const struct mtd_ooblayout_ops denali_ooblayout_ops = { | |
1410 | .ecc = denali_ooblayout_ecc, | |
1411 | .free = denali_ooblayout_free, | |
ce082596 JR |
1412 | }; |
1413 | ||
1414 | static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; | |
1415 | static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
1416 | ||
1417 | static struct nand_bbt_descr bbt_main_descr = { | |
1418 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1419 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1420 | .offs = 8, | |
1421 | .len = 4, | |
1422 | .veroffs = 12, | |
1423 | .maxblocks = 4, | |
1424 | .pattern = bbt_pattern, | |
1425 | }; | |
1426 | ||
1427 | static struct nand_bbt_descr bbt_mirror_descr = { | |
1428 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
1429 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
1430 | .offs = 8, | |
1431 | .len = 4, | |
1432 | .veroffs = 12, | |
1433 | .maxblocks = 4, | |
1434 | .pattern = mirror_pattern, | |
1435 | }; | |
1436 | ||
421f91d2 | 1437 | /* initialize driver data structures */ |
8c519436 | 1438 | static void denali_drv_init(struct denali_nand_info *denali) |
ce082596 JR |
1439 | { |
1440 | denali->idx = 0; | |
1441 | ||
1442 | /* setup interrupt handler */ | |
43914a2d MY |
1443 | /* |
1444 | * the completion object will be used to notify | |
1445 | * the callee that the interrupt is done | |
1446 | */ | |
ce082596 JR |
1447 | init_completion(&denali->complete); |
1448 | ||
43914a2d MY |
1449 | /* |
1450 | * the spinlock will be used to synchronize the ISR with any | |
1451 | * element that might be access shared data (interrupt status) | |
1452 | */ | |
ce082596 JR |
1453 | spin_lock_init(&denali->irq_lock); |
1454 | ||
1455 | /* indicate that MTD has not selected a valid bank yet */ | |
1456 | denali->flash_bank = CHIP_SELECT_INVALID; | |
1457 | ||
1458 | /* initialize our irq_status variable to indicate no interrupts */ | |
1459 | denali->irq_status = 0; | |
1460 | } | |
1461 | ||
2a0a288e | 1462 | int denali_init(struct denali_nand_info *denali) |
ce082596 | 1463 | { |
442f201b | 1464 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
2a0a288e | 1465 | int ret; |
ce082596 | 1466 | |
2a0a288e | 1467 | if (denali->platform == INTEL_CE4100) { |
43914a2d MY |
1468 | /* |
1469 | * Due to a silicon limitation, we can only support | |
5bac3acf C |
1470 | * ONFI timing mode 1 and below. |
1471 | */ | |
345b1d3b | 1472 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
2a0a288e DN |
1473 | pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); |
1474 | return -EINVAL; | |
ce082596 JR |
1475 | } |
1476 | } | |
1477 | ||
e07caa36 HS |
1478 | /* allocate a temporary buffer for nand_scan_ident() */ |
1479 | denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, | |
1480 | GFP_DMA | GFP_KERNEL); | |
1481 | if (!denali->buf.buf) | |
1482 | return -ENOMEM; | |
ce082596 | 1483 | |
442f201b | 1484 | mtd->dev.parent = denali->dev; |
ce082596 JR |
1485 | denali_hw_init(denali); |
1486 | denali_drv_init(denali); | |
1487 | ||
43914a2d MY |
1488 | /* |
1489 | * denali_isr register is done after all the hardware | |
1490 | * initilization is finished | |
1491 | */ | |
2a0a288e | 1492 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, |
ce082596 | 1493 | DENALI_NAND_NAME, denali)) { |
2a0a288e DN |
1494 | pr_err("Spectra: Unable to allocate IRQ\n"); |
1495 | return -ENODEV; | |
ce082596 JR |
1496 | } |
1497 | ||
1498 | /* now that our ISR is registered, we can enable interrupts */ | |
eda936ef | 1499 | denali_set_intr_modes(denali, true); |
442f201b | 1500 | mtd->name = "denali-nand"; |
ce082596 JR |
1501 | |
1502 | /* register the driver with the NAND core subsystem */ | |
1503 | denali->nand.select_chip = denali_select_chip; | |
1504 | denali->nand.cmdfunc = denali_cmdfunc; | |
1505 | denali->nand.read_byte = denali_read_byte; | |
1506 | denali->nand.waitfunc = denali_waitfunc; | |
1507 | ||
43914a2d MY |
1508 | /* |
1509 | * scan for NAND devices attached to the controller | |
ce082596 | 1510 | * this is the first stage in a two step process to register |
43914a2d MY |
1511 | * with the nand subsystem |
1512 | */ | |
442f201b | 1513 | if (nand_scan_ident(mtd, denali->max_banks, NULL)) { |
ce082596 | 1514 | ret = -ENXIO; |
5c0eb900 | 1515 | goto failed_req_irq; |
ce082596 | 1516 | } |
5bac3acf | 1517 | |
e07caa36 HS |
1518 | /* allocate the right size buffer now */ |
1519 | devm_kfree(denali->dev, denali->buf.buf); | |
1520 | denali->buf.buf = devm_kzalloc(denali->dev, | |
442f201b | 1521 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1522 | GFP_KERNEL); |
1523 | if (!denali->buf.buf) { | |
1524 | ret = -ENOMEM; | |
1525 | goto failed_req_irq; | |
1526 | } | |
1527 | ||
1528 | /* Is 32-bit DMA supported? */ | |
1529 | ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); | |
1530 | if (ret) { | |
1531 | pr_err("Spectra: no usable DMA configuration\n"); | |
1532 | goto failed_req_irq; | |
1533 | } | |
1534 | ||
1535 | denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, | |
442f201b | 1536 | mtd->writesize + mtd->oobsize, |
e07caa36 HS |
1537 | DMA_BIDIRECTIONAL); |
1538 | if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { | |
1539 | dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); | |
1540 | ret = -EIO; | |
5c0eb900 | 1541 | goto failed_req_irq; |
66406524 CD |
1542 | } |
1543 | ||
43914a2d MY |
1544 | /* |
1545 | * support for multi nand | |
1546 | * MTD known nothing about multi nand, so we should tell it | |
1547 | * the real pagesize and anything necessery | |
08b9ab99 CD |
1548 | */ |
1549 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | |
1550 | denali->nand.chipsize <<= (denali->devnum - 1); | |
1551 | denali->nand.page_shift += (denali->devnum - 1); | |
1552 | denali->nand.pagemask = (denali->nand.chipsize >> | |
1553 | denali->nand.page_shift) - 1; | |
1554 | denali->nand.bbt_erase_shift += (denali->devnum - 1); | |
1555 | denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; | |
1556 | denali->nand.chip_shift += (denali->devnum - 1); | |
442f201b BB |
1557 | mtd->writesize <<= (denali->devnum - 1); |
1558 | mtd->oobsize <<= (denali->devnum - 1); | |
1559 | mtd->erasesize <<= (denali->devnum - 1); | |
1560 | mtd->size = denali->nand.numchips * denali->nand.chipsize; | |
08b9ab99 CD |
1561 | denali->bbtskipbytes *= denali->devnum; |
1562 | ||
43914a2d MY |
1563 | /* |
1564 | * second stage of the NAND scan | |
5bac3acf | 1565 | * this stage requires information regarding ECC and |
43914a2d MY |
1566 | * bad block management. |
1567 | */ | |
ce082596 JR |
1568 | |
1569 | /* Bad block management */ | |
1570 | denali->nand.bbt_td = &bbt_main_descr; | |
1571 | denali->nand.bbt_md = &bbt_mirror_descr; | |
1572 | ||
1573 | /* skip the scan for now until we have OOB read and write support */ | |
bb9ebd4e | 1574 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
a40f7341 | 1575 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
ce082596 JR |
1576 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1577 | ||
d99d7282 GM |
1578 | /* no subpage writes on denali */ |
1579 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1580 | ||
43914a2d MY |
1581 | /* |
1582 | * Denali Controller only support 15bit and 8bit ECC in MRST, | |
db9a3210 CD |
1583 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
1584 | * SLC if possible. | |
1585 | * */ | |
1d0ed69d | 1586 | if (!nand_is_slc(&denali->nand) && |
442f201b BB |
1587 | (mtd->oobsize > (denali->bbtskipbytes + |
1588 | ECC_15BITS * (mtd->writesize / | |
db9a3210 CD |
1589 | ECC_SECTOR_SIZE)))) { |
1590 | /* if MLC OOB size is large enough, use 15bit ECC*/ | |
6a918bad | 1591 | denali->nand.ecc.strength = 15; |
db9a3210 | 1592 | denali->nand.ecc.bytes = ECC_15BITS; |
24c3fa36 | 1593 | iowrite32(15, denali->flash_reg + ECC_CORRECTION); |
442f201b BB |
1594 | } else if (mtd->oobsize < (denali->bbtskipbytes + |
1595 | ECC_8BITS * (mtd->writesize / | |
db9a3210 | 1596 | ECC_SECTOR_SIZE))) { |
8125450c | 1597 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
5c0eb900 | 1598 | goto failed_req_irq; |
db9a3210 | 1599 | } else { |
6a918bad | 1600 | denali->nand.ecc.strength = 8; |
db9a3210 | 1601 | denali->nand.ecc.bytes = ECC_8BITS; |
24c3fa36 | 1602 | iowrite32(8, denali->flash_reg + ECC_CORRECTION); |
ce082596 JR |
1603 | } |
1604 | ||
14fad62b | 1605 | mtd_set_ooblayout(mtd, &denali_ooblayout_ops); |
08b9ab99 | 1606 | denali->nand.ecc.bytes *= denali->devnum; |
6a918bad | 1607 | denali->nand.ecc.strength *= denali->devnum; |
db9a3210 | 1608 | |
43914a2d MY |
1609 | /* |
1610 | * Let driver know the total blocks number and how many blocks | |
1611 | * contained by each nand chip. blksperchip will help driver to | |
1612 | * know how many blocks is taken by FW. | |
1613 | */ | |
442f201b | 1614 | denali->totalblks = mtd->size >> denali->nand.phys_erase_shift; |
66406524 CD |
1615 | denali->blksperchip = denali->totalblks / denali->nand.numchips; |
1616 | ||
ce082596 | 1617 | /* override the default read operations */ |
08b9ab99 | 1618 | denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; |
ce082596 JR |
1619 | denali->nand.ecc.read_page = denali_read_page; |
1620 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1621 | denali->nand.ecc.write_page = denali_write_page; | |
1622 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1623 | denali->nand.ecc.read_oob = denali_read_oob; | |
1624 | denali->nand.ecc.write_oob = denali_write_oob; | |
49c50b97 | 1625 | denali->nand.erase = denali_erase; |
ce082596 | 1626 | |
442f201b | 1627 | if (nand_scan_tail(mtd)) { |
ce082596 | 1628 | ret = -ENXIO; |
5c0eb900 | 1629 | goto failed_req_irq; |
ce082596 JR |
1630 | } |
1631 | ||
442f201b | 1632 | ret = mtd_device_register(mtd, NULL, 0); |
ce082596 | 1633 | if (ret) { |
2a0a288e | 1634 | dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n", |
7cfffac0 | 1635 | ret); |
5c0eb900 | 1636 | goto failed_req_irq; |
ce082596 JR |
1637 | } |
1638 | return 0; | |
1639 | ||
5c0eb900 | 1640 | failed_req_irq: |
2a0a288e DN |
1641 | denali_irq_cleanup(denali->irq, denali); |
1642 | ||
ce082596 JR |
1643 | return ret; |
1644 | } | |
2a0a288e | 1645 | EXPORT_SYMBOL(denali_init); |
ce082596 JR |
1646 | |
1647 | /* driver exit point */ | |
2a0a288e | 1648 | void denali_remove(struct denali_nand_info *denali) |
ce082596 | 1649 | { |
442f201b | 1650 | struct mtd_info *mtd = nand_to_mtd(&denali->nand); |
320092a0 BB |
1651 | /* |
1652 | * Pre-compute DMA buffer size to avoid any problems in case | |
1653 | * nand_release() ever changes in a way that mtd->writesize and | |
1654 | * mtd->oobsize are not reliable after this call. | |
1655 | */ | |
442f201b | 1656 | int bufsize = mtd->writesize + mtd->oobsize; |
320092a0 | 1657 | |
442f201b | 1658 | nand_release(mtd); |
2a0a288e | 1659 | denali_irq_cleanup(denali->irq, denali); |
320092a0 | 1660 | dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize, |
8125450c | 1661 | DMA_BIDIRECTIONAL); |
ce082596 | 1662 | } |
2a0a288e | 1663 | EXPORT_SYMBOL(denali_remove); |