Commit | Line | Data |
---|---|---|
266dead2 LHC |
1 | /***************************************************************************** |
2 | * Copyright 2004 - 2009 Broadcom Corporation. All rights reserved. | |
3 | * | |
4 | * Unless you and Broadcom execute a separate written software license | |
5 | * agreement governing use of this software, this software is licensed to you | |
6 | * under the terms of the GNU General Public License version 2, available at | |
7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | |
8 | * | |
9 | * Notwithstanding the above, under no circumstances may you combine this | |
10 | * software in any way with any other Broadcom software provided under a | |
11 | * license other than the GPL, without Broadcom's express prior written | |
12 | * consent. | |
13 | *****************************************************************************/ | |
14 | ||
15 | /* ---- Include Files ---------------------------------------------------- */ | |
266dead2 LHC |
16 | #include <linux/module.h> |
17 | #include <linux/types.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
266dead2 LHC |
21 | #include <linux/string.h> |
22 | #include <linux/ioport.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/mtd/mtd.h> | |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/mtd/nand_ecc.h> | |
31 | #include <linux/mtd/partitions.h> | |
32 | ||
33 | #include <asm/mach-types.h> | |
34 | #include <asm/system.h> | |
35 | ||
36 | #include <mach/reg_nand.h> | |
37 | #include <mach/reg_umi.h> | |
38 | ||
39 | #include "nand_bcm_umi.h" | |
40 | ||
41 | #include <mach/memory_settings.h> | |
42 | ||
43 | #define USE_DMA 1 | |
44 | #include <mach/dma.h> | |
45 | #include <linux/dma-mapping.h> | |
46 | #include <linux/completion.h> | |
47 | ||
48 | /* ---- External Variable Declarations ----------------------------------- */ | |
49 | /* ---- External Function Prototypes ------------------------------------- */ | |
50 | /* ---- Public Variables ------------------------------------------------- */ | |
51 | /* ---- Private Constants and Types -------------------------------------- */ | |
52 | static const __devinitconst char gBanner[] = KERN_INFO \ | |
53 | "BCM UMI MTD NAND Driver: 1.00\n"; | |
54 | ||
55 | #ifdef CONFIG_MTD_PARTITIONS | |
56 | const char *part_probes[] = { "cmdlinepart", NULL }; | |
57 | #endif | |
58 | ||
59 | #if NAND_ECC_BCH | |
60 | static uint8_t scan_ff_pattern[] = { 0xff }; | |
61 | ||
62 | static struct nand_bbt_descr largepage_bbt = { | |
63 | .options = 0, | |
64 | .offs = 0, | |
65 | .len = 1, | |
66 | .pattern = scan_ff_pattern | |
67 | }; | |
68 | #endif | |
69 | ||
70 | /* | |
71 | ** Preallocate a buffer to avoid having to do this every dma operation. | |
72 | ** This is the size of the preallocated coherent DMA buffer. | |
73 | */ | |
74 | #if USE_DMA | |
75 | #define DMA_MIN_BUFLEN 512 | |
76 | #define DMA_MAX_BUFLEN PAGE_SIZE | |
77 | #define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \ | |
78 | ((len) > DMA_MAX_BUFLEN)) | |
79 | ||
80 | /* | |
81 | * The current NAND data space goes from 0x80001900 to 0x80001FFF, | |
82 | * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page | |
83 | * size NAND flash. Need to break the DMA down to multiple 1Ks. | |
84 | * | |
85 | * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000 | |
86 | */ | |
87 | #define DMA_MAX_LEN 1024 | |
88 | ||
89 | #else /* !USE_DMA */ | |
90 | #define DMA_MIN_BUFLEN 0 | |
91 | #define DMA_MAX_BUFLEN 0 | |
92 | #define USE_DIRECT_IO(len) 1 | |
93 | #endif | |
94 | /* ---- Private Function Prototypes -------------------------------------- */ | |
95 | static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len); | |
96 | static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf, | |
97 | int len); | |
98 | ||
99 | /* ---- Private Variables ------------------------------------------------ */ | |
100 | static struct mtd_info *board_mtd; | |
101 | static void __iomem *bcm_umi_io_base; | |
102 | static void *virtPtr; | |
103 | static dma_addr_t physPtr; | |
104 | static struct completion nand_comp; | |
105 | ||
106 | /* ---- Private Functions ------------------------------------------------ */ | |
107 | #if NAND_ECC_BCH | |
108 | #include "bcm_umi_bch.c" | |
109 | #else | |
110 | #include "bcm_umi_hamming.c" | |
111 | #endif | |
112 | ||
113 | #if USE_DMA | |
114 | ||
115 | /* Handler called when the DMA finishes. */ | |
116 | static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData) | |
117 | { | |
118 | complete(&nand_comp); | |
119 | } | |
120 | ||
121 | static int nand_dma_init(void) | |
122 | { | |
123 | int rc; | |
124 | ||
125 | rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM, | |
126 | nand_dma_handler, NULL); | |
127 | if (rc != 0) { | |
128 | printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc); | |
129 | return rc; | |
130 | } | |
131 | ||
132 | virtPtr = | |
133 | dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL); | |
134 | if (virtPtr == NULL) { | |
135 | printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n"); | |
136 | return -ENOMEM; | |
137 | } | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static void nand_dma_term(void) | |
143 | { | |
144 | if (virtPtr != NULL) | |
145 | dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr); | |
146 | } | |
147 | ||
148 | static void nand_dma_read(void *buf, int len) | |
149 | { | |
150 | int offset = 0; | |
151 | int tmp_len = 0; | |
152 | int len_left = len; | |
153 | DMA_Handle_t hndl; | |
154 | ||
155 | if (virtPtr == NULL) | |
156 | panic("nand_dma_read: virtPtr == NULL\n"); | |
157 | ||
158 | if ((void *)physPtr == NULL) | |
159 | panic("nand_dma_read: physPtr == NULL\n"); | |
160 | ||
161 | hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM); | |
162 | if (hndl < 0) { | |
163 | printk(KERN_ERR | |
164 | "nand_dma_read: unable to allocate dma channel: %d\n", | |
165 | (int)hndl); | |
166 | panic("\n"); | |
167 | } | |
168 | ||
169 | while (len_left > 0) { | |
170 | if (len_left > DMA_MAX_LEN) { | |
171 | tmp_len = DMA_MAX_LEN; | |
172 | len_left -= DMA_MAX_LEN; | |
173 | } else { | |
174 | tmp_len = len_left; | |
175 | len_left = 0; | |
176 | } | |
177 | ||
178 | init_completion(&nand_comp); | |
179 | dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR, | |
180 | physPtr + offset, tmp_len); | |
181 | wait_for_completion(&nand_comp); | |
182 | ||
183 | offset += tmp_len; | |
184 | } | |
185 | ||
186 | dma_free_channel(hndl); | |
187 | ||
188 | if (buf != NULL) | |
189 | memcpy(buf, virtPtr, len); | |
190 | } | |
191 | ||
192 | static void nand_dma_write(const void *buf, int len) | |
193 | { | |
194 | int offset = 0; | |
195 | int tmp_len = 0; | |
196 | int len_left = len; | |
197 | DMA_Handle_t hndl; | |
198 | ||
199 | if (buf == NULL) | |
200 | panic("nand_dma_write: buf == NULL\n"); | |
201 | ||
202 | if (virtPtr == NULL) | |
203 | panic("nand_dma_write: virtPtr == NULL\n"); | |
204 | ||
205 | if ((void *)physPtr == NULL) | |
206 | panic("nand_dma_write: physPtr == NULL\n"); | |
207 | ||
208 | memcpy(virtPtr, buf, len); | |
209 | ||
210 | ||
211 | hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM); | |
212 | if (hndl < 0) { | |
213 | printk(KERN_ERR | |
214 | "nand_dma_write: unable to allocate dma channel: %d\n", | |
215 | (int)hndl); | |
216 | panic("\n"); | |
217 | } | |
218 | ||
219 | while (len_left > 0) { | |
220 | if (len_left > DMA_MAX_LEN) { | |
221 | tmp_len = DMA_MAX_LEN; | |
222 | len_left -= DMA_MAX_LEN; | |
223 | } else { | |
224 | tmp_len = len_left; | |
225 | len_left = 0; | |
226 | } | |
227 | ||
228 | init_completion(&nand_comp); | |
229 | dma_transfer_mem_to_mem(hndl, physPtr + offset, | |
230 | REG_NAND_DATA_PADDR, tmp_len); | |
231 | wait_for_completion(&nand_comp); | |
232 | ||
233 | offset += tmp_len; | |
234 | } | |
235 | ||
236 | dma_free_channel(hndl); | |
237 | } | |
238 | ||
239 | #endif | |
240 | ||
241 | static int nand_dev_ready(struct mtd_info *mtd) | |
242 | { | |
243 | return nand_bcm_umi_dev_ready(); | |
244 | } | |
245 | ||
246 | /**************************************************************************** | |
247 | * | |
248 | * bcm_umi_nand_inithw | |
249 | * | |
250 | * This routine does the necessary hardware (board-specific) | |
251 | * initializations. This includes setting up the timings, etc. | |
252 | * | |
253 | ***************************************************************************/ | |
254 | int bcm_umi_nand_inithw(void) | |
255 | { | |
256 | /* Configure nand timing parameters */ | |
257 | REG_UMI_NAND_TCR &= ~0x7ffff; | |
258 | REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; | |
259 | ||
260 | #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) | |
261 | /* enable software control of CS */ | |
262 | REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; | |
263 | #endif | |
264 | ||
265 | /* keep NAND chip select asserted */ | |
266 | REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; | |
267 | ||
268 | REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; | |
269 | /* enable writes to flash */ | |
270 | REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; | |
271 | ||
272 | writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); | |
273 | nand_bcm_umi_wait_till_ready(); | |
274 | ||
275 | #if NAND_ECC_BCH | |
276 | nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES); | |
277 | #endif | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | /* Used to turn latch the proper register for access. */ | |
283 | static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd, | |
284 | unsigned int ctrl) | |
285 | { | |
286 | /* send command to hardware */ | |
287 | struct nand_chip *chip = mtd->priv; | |
288 | if (ctrl & NAND_CTRL_CHANGE) { | |
289 | if (ctrl & NAND_CLE) { | |
290 | chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET; | |
291 | goto CMD; | |
292 | } | |
293 | if (ctrl & NAND_ALE) { | |
294 | chip->IO_ADDR_W = | |
295 | bcm_umi_io_base + REG_NAND_ADDR_OFFSET; | |
296 | goto CMD; | |
297 | } | |
298 | chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET; | |
299 | } | |
300 | ||
301 | CMD: | |
302 | /* Send command to chip directly */ | |
303 | if (cmd != NAND_CMD_NONE) | |
304 | writeb(cmd, chip->IO_ADDR_W); | |
305 | } | |
306 | ||
307 | static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf, | |
308 | int len) | |
309 | { | |
310 | if (USE_DIRECT_IO(len)) { | |
311 | /* Do it the old way if the buffer is small or too large. | |
312 | * Probably quicker than starting and checking dma. */ | |
313 | int i; | |
314 | struct nand_chip *this = mtd->priv; | |
315 | ||
316 | for (i = 0; i < len; i++) | |
317 | writeb(buf[i], this->IO_ADDR_W); | |
318 | } | |
319 | #if USE_DMA | |
320 | else | |
321 | nand_dma_write(buf, len); | |
322 | #endif | |
323 | } | |
324 | ||
325 | static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len) | |
326 | { | |
327 | if (USE_DIRECT_IO(len)) { | |
328 | int i; | |
329 | struct nand_chip *this = mtd->priv; | |
330 | ||
331 | for (i = 0; i < len; i++) | |
332 | buf[i] = readb(this->IO_ADDR_R); | |
333 | } | |
334 | #if USE_DMA | |
335 | else | |
336 | nand_dma_read(buf, len); | |
337 | #endif | |
338 | } | |
339 | ||
340 | static uint8_t readbackbuf[NAND_MAX_PAGESIZE]; | |
341 | static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, | |
342 | int len) | |
343 | { | |
344 | /* | |
345 | * Try to readback page with ECC correction. This is necessary | |
346 | * for MLC parts which may have permanently stuck bits. | |
347 | */ | |
348 | struct nand_chip *chip = mtd->priv; | |
349 | int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0); | |
350 | if (ret < 0) | |
351 | return -EFAULT; | |
352 | else { | |
353 | if (memcmp(readbackbuf, buf, len) == 0) | |
354 | return 0; | |
355 | ||
356 | return -EFAULT; | |
357 | } | |
358 | return 0; | |
359 | } | |
360 | ||
361 | static int __devinit bcm_umi_nand_probe(struct platform_device *pdev) | |
362 | { | |
363 | struct nand_chip *this; | |
364 | struct resource *r; | |
365 | int err = 0; | |
366 | ||
367 | printk(gBanner); | |
368 | ||
369 | /* Allocate memory for MTD device structure and private data */ | |
370 | board_mtd = | |
371 | kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), | |
372 | GFP_KERNEL); | |
373 | if (!board_mtd) { | |
374 | printk(KERN_WARNING | |
375 | "Unable to allocate NAND MTD device structure.\n"); | |
376 | return -ENOMEM; | |
377 | } | |
378 | ||
379 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
380 | ||
381 | if (!r) | |
382 | return -ENXIO; | |
383 | ||
3ad2f3fb | 384 | /* map physical address */ |
266dead2 LHC |
385 | bcm_umi_io_base = ioremap(r->start, r->end - r->start + 1); |
386 | ||
387 | if (!bcm_umi_io_base) { | |
388 | printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n"); | |
389 | kfree(board_mtd); | |
390 | return -EIO; | |
391 | } | |
392 | ||
393 | /* Get pointer to private data */ | |
394 | this = (struct nand_chip *)(&board_mtd[1]); | |
395 | ||
396 | /* Initialize structures */ | |
397 | memset((char *)board_mtd, 0, sizeof(struct mtd_info)); | |
398 | memset((char *)this, 0, sizeof(struct nand_chip)); | |
399 | ||
400 | /* Link the private data with the MTD structure */ | |
401 | board_mtd->priv = this; | |
402 | ||
403 | /* Initialize the NAND hardware. */ | |
404 | if (bcm_umi_nand_inithw() < 0) { | |
405 | printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n"); | |
406 | iounmap(bcm_umi_io_base); | |
407 | kfree(board_mtd); | |
408 | return -EIO; | |
409 | } | |
410 | ||
411 | /* Set address of NAND IO lines */ | |
412 | this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET; | |
413 | this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET; | |
414 | ||
415 | /* Set command delay time, see datasheet for correct value */ | |
416 | this->chip_delay = 0; | |
417 | /* Assign the device ready function, if available */ | |
418 | this->dev_ready = nand_dev_ready; | |
419 | this->options = 0; | |
420 | ||
421 | this->write_buf = bcm_umi_nand_write_buf; | |
422 | this->read_buf = bcm_umi_nand_read_buf; | |
423 | this->verify_buf = bcm_umi_nand_verify_buf; | |
424 | ||
425 | this->cmd_ctrl = bcm_umi_nand_hwcontrol; | |
426 | this->ecc.mode = NAND_ECC_HW; | |
427 | this->ecc.size = 512; | |
428 | this->ecc.bytes = NAND_ECC_NUM_BYTES; | |
429 | #if NAND_ECC_BCH | |
430 | this->ecc.read_page = bcm_umi_bch_read_page_hwecc; | |
431 | this->ecc.write_page = bcm_umi_bch_write_page_hwecc; | |
432 | #else | |
433 | this->ecc.correct = nand_correct_data512; | |
434 | this->ecc.calculate = bcm_umi_hamming_get_hw_ecc; | |
435 | this->ecc.hwctl = bcm_umi_hamming_enable_hwecc; | |
436 | #endif | |
437 | ||
438 | #if USE_DMA | |
439 | err = nand_dma_init(); | |
440 | if (err != 0) | |
441 | return err; | |
442 | #endif | |
443 | ||
444 | /* Figure out the size of the device that we have. | |
445 | * We need to do this to figure out which ECC | |
446 | * layout we'll be using. | |
447 | */ | |
448 | ||
5e81e88a | 449 | err = nand_scan_ident(board_mtd, 1, NULL); |
266dead2 LHC |
450 | if (err) { |
451 | printk(KERN_ERR "nand_scan failed: %d\n", err); | |
452 | iounmap(bcm_umi_io_base); | |
453 | kfree(board_mtd); | |
454 | return err; | |
455 | } | |
456 | ||
457 | /* Now that we know the nand size, we can setup the ECC layout */ | |
458 | ||
459 | switch (board_mtd->writesize) { /* writesize is the pagesize */ | |
460 | case 4096: | |
461 | this->ecc.layout = &nand_hw_eccoob_4096; | |
462 | break; | |
463 | case 2048: | |
464 | this->ecc.layout = &nand_hw_eccoob_2048; | |
465 | break; | |
466 | case 512: | |
467 | this->ecc.layout = &nand_hw_eccoob_512; | |
468 | break; | |
469 | default: | |
470 | { | |
471 | printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n", | |
472 | board_mtd->writesize); | |
473 | return -EINVAL; | |
474 | } | |
475 | } | |
476 | ||
477 | #if NAND_ECC_BCH | |
478 | if (board_mtd->writesize > 512) { | |
479 | if (this->options & NAND_USE_FLASH_BBT) | |
480 | largepage_bbt.options = NAND_BBT_SCAN2NDPAGE; | |
481 | this->badblock_pattern = &largepage_bbt; | |
482 | } | |
483 | #endif | |
484 | ||
485 | /* Now finish off the scan, now that ecc.layout has been initialized. */ | |
486 | ||
487 | err = nand_scan_tail(board_mtd); | |
488 | if (err) { | |
489 | printk(KERN_ERR "nand_scan failed: %d\n", err); | |
490 | iounmap(bcm_umi_io_base); | |
491 | kfree(board_mtd); | |
492 | return err; | |
493 | } | |
494 | ||
495 | /* Register the partitions */ | |
496 | { | |
497 | int nr_partitions; | |
498 | struct mtd_partition *partition_info; | |
499 | ||
500 | board_mtd->name = "bcm_umi-nand"; | |
501 | nr_partitions = | |
502 | parse_mtd_partitions(board_mtd, part_probes, | |
503 | &partition_info, 0); | |
504 | ||
505 | if (nr_partitions <= 0) { | |
506 | printk(KERN_ERR "BCM UMI NAND: Too few partitions - %d\n", | |
507 | nr_partitions); | |
508 | iounmap(bcm_umi_io_base); | |
509 | kfree(board_mtd); | |
510 | return -EIO; | |
511 | } | |
512 | add_mtd_partitions(board_mtd, partition_info, nr_partitions); | |
513 | } | |
514 | ||
515 | /* Return happy */ | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static int bcm_umi_nand_remove(struct platform_device *pdev) | |
520 | { | |
521 | #if USE_DMA | |
522 | nand_dma_term(); | |
523 | #endif | |
524 | ||
525 | /* Release resources, unregister device */ | |
526 | nand_release(board_mtd); | |
527 | ||
3ad2f3fb | 528 | /* unmap physical address */ |
266dead2 LHC |
529 | iounmap(bcm_umi_io_base); |
530 | ||
531 | /* Free the MTD device structure */ | |
532 | kfree(board_mtd); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | #ifdef CONFIG_PM | |
538 | static int bcm_umi_nand_suspend(struct platform_device *pdev, | |
539 | pm_message_t state) | |
540 | { | |
541 | printk(KERN_ERR "MTD NAND suspend is being called\n"); | |
542 | return 0; | |
543 | } | |
544 | ||
545 | static int bcm_umi_nand_resume(struct platform_device *pdev) | |
546 | { | |
547 | printk(KERN_ERR "MTD NAND resume is being called\n"); | |
548 | return 0; | |
549 | } | |
550 | #else | |
551 | #define bcm_umi_nand_suspend NULL | |
552 | #define bcm_umi_nand_resume NULL | |
553 | #endif | |
554 | ||
555 | static struct platform_driver nand_driver = { | |
556 | .driver = { | |
557 | .name = "bcm-nand", | |
558 | .owner = THIS_MODULE, | |
559 | }, | |
560 | .probe = bcm_umi_nand_probe, | |
561 | .remove = bcm_umi_nand_remove, | |
562 | .suspend = bcm_umi_nand_suspend, | |
563 | .resume = bcm_umi_nand_resume, | |
564 | }; | |
565 | ||
566 | static int __init nand_init(void) | |
567 | { | |
568 | return platform_driver_register(&nand_driver); | |
569 | } | |
570 | ||
571 | static void __exit nand_exit(void) | |
572 | { | |
573 | platform_driver_unregister(&nand_driver); | |
574 | } | |
575 | ||
576 | module_init(nand_init); | |
577 | module_exit(nand_exit); | |
578 | ||
579 | MODULE_LICENSE("GPL"); | |
580 | MODULE_AUTHOR("Broadcom"); | |
581 | MODULE_DESCRIPTION("BCM UMI MTD NAND driver"); |