Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/au1550nd.c | |
3 | * | |
4 | * Copyright (C) 2004 Embedded Edge, LLC | |
5 | * | |
1da177e4 LT |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/slab.h> | |
b7f720d6 | 13 | #include <linux/gpio.h> |
1da177e4 | 14 | #include <linux/module.h> |
35af68b5 | 15 | #include <linux/interrupt.h> |
1da177e4 LT |
16 | #include <linux/mtd/mtd.h> |
17 | #include <linux/mtd/nand.h> | |
18 | #include <linux/mtd/partitions.h> | |
b67a1a02 | 19 | #include <linux/platform_device.h> |
1da177e4 | 20 | #include <asm/io.h> |
b67a1a02 ML |
21 | #include <asm/mach-au1x00/au1000.h> |
22 | #include <asm/mach-au1x00/au1550nd.h> | |
1da177e4 | 23 | |
1da177e4 | 24 | |
b67a1a02 ML |
25 | struct au1550nd_ctx { |
26 | struct mtd_info info; | |
27 | struct nand_chip chip; | |
1da177e4 | 28 | |
b67a1a02 ML |
29 | int cs; |
30 | void __iomem *base; | |
31 | void (*write_byte)(struct mtd_info *, u_char); | |
1da177e4 | 32 | }; |
1da177e4 LT |
33 | |
34 | /** | |
35 | * au_read_byte - read one byte from the chip | |
36 | * @mtd: MTD device structure | |
37 | * | |
7854d3f7 | 38 | * read function for 8bit buswidth |
1da177e4 LT |
39 | */ |
40 | static u_char au_read_byte(struct mtd_info *mtd) | |
41 | { | |
42 | struct nand_chip *this = mtd->priv; | |
43 | u_char ret = readb(this->IO_ADDR_R); | |
2f73bfbe | 44 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
45 | return ret; |
46 | } | |
47 | ||
48 | /** | |
49 | * au_write_byte - write one byte to the chip | |
50 | * @mtd: MTD device structure | |
51 | * @byte: pointer to data byte to write | |
52 | * | |
7854d3f7 | 53 | * write function for 8it buswidth |
1da177e4 LT |
54 | */ |
55 | static void au_write_byte(struct mtd_info *mtd, u_char byte) | |
56 | { | |
57 | struct nand_chip *this = mtd->priv; | |
58 | writeb(byte, this->IO_ADDR_W); | |
2f73bfbe | 59 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
60 | } |
61 | ||
62 | /** | |
7854d3f7 | 63 | * au_read_byte16 - read one byte endianness aware from the chip |
1da177e4 LT |
64 | * @mtd: MTD device structure |
65 | * | |
7854d3f7 | 66 | * read function for 16bit buswidth with endianness conversion |
1da177e4 LT |
67 | */ |
68 | static u_char au_read_byte16(struct mtd_info *mtd) | |
69 | { | |
70 | struct nand_chip *this = mtd->priv; | |
71 | u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); | |
2f73bfbe | 72 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
73 | return ret; |
74 | } | |
75 | ||
76 | /** | |
7854d3f7 | 77 | * au_write_byte16 - write one byte endianness aware to the chip |
1da177e4 LT |
78 | * @mtd: MTD device structure |
79 | * @byte: pointer to data byte to write | |
80 | * | |
7854d3f7 | 81 | * write function for 16bit buswidth with endianness conversion |
1da177e4 LT |
82 | */ |
83 | static void au_write_byte16(struct mtd_info *mtd, u_char byte) | |
84 | { | |
85 | struct nand_chip *this = mtd->priv; | |
86 | writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); | |
2f73bfbe | 87 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
88 | } |
89 | ||
90 | /** | |
91 | * au_read_word - read one word from the chip | |
92 | * @mtd: MTD device structure | |
93 | * | |
7854d3f7 | 94 | * read function for 16bit buswidth without endianness conversion |
1da177e4 LT |
95 | */ |
96 | static u16 au_read_word(struct mtd_info *mtd) | |
97 | { | |
98 | struct nand_chip *this = mtd->priv; | |
99 | u16 ret = readw(this->IO_ADDR_R); | |
2f73bfbe | 100 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
101 | return ret; |
102 | } | |
103 | ||
1da177e4 LT |
104 | /** |
105 | * au_write_buf - write buffer to chip | |
106 | * @mtd: MTD device structure | |
107 | * @buf: data buffer | |
108 | * @len: number of bytes to write | |
109 | * | |
7854d3f7 | 110 | * write function for 8bit buswidth |
1da177e4 LT |
111 | */ |
112 | static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
113 | { | |
114 | int i; | |
115 | struct nand_chip *this = mtd->priv; | |
116 | ||
e0c7d767 | 117 | for (i = 0; i < len; i++) { |
1da177e4 | 118 | writeb(buf[i], this->IO_ADDR_W); |
2f73bfbe | 119 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
120 | } |
121 | } | |
122 | ||
123 | /** | |
61b03bd7 | 124 | * au_read_buf - read chip data into buffer |
1da177e4 LT |
125 | * @mtd: MTD device structure |
126 | * @buf: buffer to store date | |
127 | * @len: number of bytes to read | |
128 | * | |
7854d3f7 | 129 | * read function for 8bit buswidth |
1da177e4 LT |
130 | */ |
131 | static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
132 | { | |
133 | int i; | |
134 | struct nand_chip *this = mtd->priv; | |
135 | ||
e0c7d767 | 136 | for (i = 0; i < len; i++) { |
1da177e4 | 137 | buf[i] = readb(this->IO_ADDR_R); |
2f73bfbe | 138 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
139 | } |
140 | } | |
141 | ||
1da177e4 LT |
142 | /** |
143 | * au_write_buf16 - write buffer to chip | |
144 | * @mtd: MTD device structure | |
145 | * @buf: data buffer | |
146 | * @len: number of bytes to write | |
147 | * | |
7854d3f7 | 148 | * write function for 16bit buswidth |
1da177e4 LT |
149 | */ |
150 | static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) | |
151 | { | |
152 | int i; | |
153 | struct nand_chip *this = mtd->priv; | |
154 | u16 *p = (u16 *) buf; | |
155 | len >>= 1; | |
61b03bd7 | 156 | |
e0c7d767 | 157 | for (i = 0; i < len; i++) { |
1da177e4 | 158 | writew(p[i], this->IO_ADDR_W); |
2f73bfbe | 159 | wmb(); /* drain writebuffer */ |
1da177e4 | 160 | } |
61b03bd7 | 161 | |
1da177e4 LT |
162 | } |
163 | ||
164 | /** | |
61b03bd7 | 165 | * au_read_buf16 - read chip data into buffer |
1da177e4 LT |
166 | * @mtd: MTD device structure |
167 | * @buf: buffer to store date | |
168 | * @len: number of bytes to read | |
169 | * | |
7854d3f7 | 170 | * read function for 16bit buswidth |
1da177e4 LT |
171 | */ |
172 | static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
173 | { | |
174 | int i; | |
175 | struct nand_chip *this = mtd->priv; | |
176 | u16 *p = (u16 *) buf; | |
177 | len >>= 1; | |
178 | ||
e0c7d767 | 179 | for (i = 0; i < len; i++) { |
1da177e4 | 180 | p[i] = readw(this->IO_ADDR_R); |
2f73bfbe | 181 | wmb(); /* drain writebuffer */ |
1da177e4 LT |
182 | } |
183 | } | |
184 | ||
7abd3ef9 TG |
185 | /* Select the chip by setting nCE to low */ |
186 | #define NAND_CTL_SETNCE 1 | |
187 | /* Deselect the chip by setting nCE to high */ | |
188 | #define NAND_CTL_CLRNCE 2 | |
189 | /* Select the command latch by setting CLE to high */ | |
190 | #define NAND_CTL_SETCLE 3 | |
191 | /* Deselect the command latch by setting CLE to low */ | |
192 | #define NAND_CTL_CLRCLE 4 | |
193 | /* Select the address latch by setting ALE to high */ | |
194 | #define NAND_CTL_SETALE 5 | |
195 | /* Deselect the address latch by setting ALE to low */ | |
196 | #define NAND_CTL_CLRALE 6 | |
1da177e4 LT |
197 | |
198 | static void au1550_hwcontrol(struct mtd_info *mtd, int cmd) | |
199 | { | |
b67a1a02 ML |
200 | struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info); |
201 | struct nand_chip *this = mtd->priv; | |
1da177e4 | 202 | |
e0c7d767 DW |
203 | switch (cmd) { |
204 | ||
205 | case NAND_CTL_SETCLE: | |
b67a1a02 | 206 | this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD; |
e0c7d767 DW |
207 | break; |
208 | ||
209 | case NAND_CTL_CLRCLE: | |
b67a1a02 | 210 | this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; |
e0c7d767 | 211 | break; |
1da177e4 | 212 | |
e0c7d767 | 213 | case NAND_CTL_SETALE: |
b67a1a02 | 214 | this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR; |
e0c7d767 | 215 | break; |
1da177e4 | 216 | |
61b03bd7 | 217 | case NAND_CTL_CLRALE: |
b67a1a02 | 218 | this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA; |
e0c7d767 | 219 | /* FIXME: Nobody knows why this is necessary, |
1da177e4 | 220 | * but it works only that way */ |
61b03bd7 | 221 | udelay(1); |
1da177e4 LT |
222 | break; |
223 | ||
61b03bd7 | 224 | case NAND_CTL_SETNCE: |
1da177e4 | 225 | /* assert (force assert) chip enable */ |
9cf12167 | 226 | alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL); |
1da177e4 LT |
227 | break; |
228 | ||
61b03bd7 | 229 | case NAND_CTL_CLRNCE: |
e0c7d767 | 230 | /* deassert chip enable */ |
9cf12167 | 231 | alchemy_wrsmem(0, AU1000_MEM_STNDCTL); |
1da177e4 LT |
232 | break; |
233 | } | |
234 | ||
235 | this->IO_ADDR_R = this->IO_ADDR_W; | |
61b03bd7 | 236 | |
2f73bfbe | 237 | wmb(); /* Drain the writebuffer */ |
1da177e4 LT |
238 | } |
239 | ||
240 | int au1550_device_ready(struct mtd_info *mtd) | |
241 | { | |
9cf12167 | 242 | return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0; |
1da177e4 LT |
243 | } |
244 | ||
35af68b5 SS |
245 | /** |
246 | * au1550_select_chip - control -CE line | |
247 | * Forbid driving -CE manually permitting the NAND controller to do this. | |
248 | * Keeping -CE asserted during the whole sector reads interferes with the | |
249 | * NOR flash and PCMCIA drivers as it causes contention on the static bus. | |
250 | * We only have to hold -CE low for the NAND read commands since the flash | |
251 | * chip needs it to be asserted during chip not ready time but the NAND | |
252 | * controller keeps it released. | |
253 | * | |
254 | * @mtd: MTD device structure | |
255 | * @chip: chipnumber to select, -1 for deselect | |
256 | */ | |
257 | static void au1550_select_chip(struct mtd_info *mtd, int chip) | |
258 | { | |
259 | } | |
260 | ||
261 | /** | |
262 | * au1550_command - Send command to NAND device | |
263 | * @mtd: MTD device structure | |
264 | * @command: the command to be sent | |
265 | * @column: the column address for this command, -1 if none | |
266 | * @page_addr: the page address for this command, -1 if none | |
267 | */ | |
268 | static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr) | |
269 | { | |
b67a1a02 ML |
270 | struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info); |
271 | struct nand_chip *this = mtd->priv; | |
35af68b5 | 272 | int ce_override = 0, i; |
b67a1a02 | 273 | unsigned long flags = 0; |
35af68b5 SS |
274 | |
275 | /* Begin command latch cycle */ | |
7abd3ef9 | 276 | au1550_hwcontrol(mtd, NAND_CTL_SETCLE); |
35af68b5 SS |
277 | /* |
278 | * Write out the command to the device. | |
279 | */ | |
280 | if (command == NAND_CMD_SEQIN) { | |
281 | int readcmd; | |
282 | ||
28318776 | 283 | if (column >= mtd->writesize) { |
35af68b5 | 284 | /* OOB area */ |
28318776 | 285 | column -= mtd->writesize; |
35af68b5 SS |
286 | readcmd = NAND_CMD_READOOB; |
287 | } else if (column < 256) { | |
288 | /* First 256 bytes --> READ0 */ | |
289 | readcmd = NAND_CMD_READ0; | |
290 | } else { | |
291 | column -= 256; | |
292 | readcmd = NAND_CMD_READ1; | |
293 | } | |
b67a1a02 | 294 | ctx->write_byte(mtd, readcmd); |
35af68b5 | 295 | } |
b67a1a02 | 296 | ctx->write_byte(mtd, command); |
35af68b5 SS |
297 | |
298 | /* Set ALE and clear CLE to start address cycle */ | |
7abd3ef9 | 299 | au1550_hwcontrol(mtd, NAND_CTL_CLRCLE); |
35af68b5 SS |
300 | |
301 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 302 | au1550_hwcontrol(mtd, NAND_CTL_SETALE); |
35af68b5 SS |
303 | |
304 | /* Serially input address */ | |
305 | if (column != -1) { | |
306 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
307 | if (this->options & NAND_BUSWIDTH_16 && |
308 | !nand_opcode_8bits(command)) | |
35af68b5 | 309 | column >>= 1; |
b67a1a02 | 310 | ctx->write_byte(mtd, column); |
35af68b5 SS |
311 | } |
312 | if (page_addr != -1) { | |
b67a1a02 | 313 | ctx->write_byte(mtd, (u8)(page_addr & 0xff)); |
35af68b5 SS |
314 | |
315 | if (command == NAND_CMD_READ0 || | |
316 | command == NAND_CMD_READ1 || | |
317 | command == NAND_CMD_READOOB) { | |
318 | /* | |
319 | * NAND controller will release -CE after | |
320 | * the last address byte is written, so we'll | |
321 | * have to forcibly assert it. No interrupts | |
322 | * are allowed while we do this as we don't | |
323 | * want the NOR flash or PCMCIA drivers to | |
324 | * steal our precious bytes of data... | |
325 | */ | |
326 | ce_override = 1; | |
327 | local_irq_save(flags); | |
7abd3ef9 | 328 | au1550_hwcontrol(mtd, NAND_CTL_SETNCE); |
35af68b5 SS |
329 | } |
330 | ||
b67a1a02 | 331 | ctx->write_byte(mtd, (u8)(page_addr >> 8)); |
35af68b5 SS |
332 | |
333 | /* One more address cycle for devices > 32MiB */ | |
334 | if (this->chipsize > (32 << 20)) | |
b67a1a02 ML |
335 | ctx->write_byte(mtd, |
336 | ((page_addr >> 16) & 0x0f)); | |
35af68b5 SS |
337 | } |
338 | /* Latch in address */ | |
7abd3ef9 | 339 | au1550_hwcontrol(mtd, NAND_CTL_CLRALE); |
35af68b5 SS |
340 | } |
341 | ||
342 | /* | |
343 | * Program and erase have their own busy handlers. | |
344 | * Status and sequential in need no delay. | |
345 | */ | |
346 | switch (command) { | |
347 | ||
348 | case NAND_CMD_PAGEPROG: | |
349 | case NAND_CMD_ERASE1: | |
350 | case NAND_CMD_ERASE2: | |
351 | case NAND_CMD_SEQIN: | |
352 | case NAND_CMD_STATUS: | |
353 | return; | |
354 | ||
355 | case NAND_CMD_RESET: | |
356 | break; | |
357 | ||
358 | case NAND_CMD_READ0: | |
359 | case NAND_CMD_READ1: | |
360 | case NAND_CMD_READOOB: | |
361 | /* Check if we're really driving -CE low (just in case) */ | |
362 | if (unlikely(!ce_override)) | |
363 | break; | |
364 | ||
365 | /* Apply a short delay always to ensure that we do wait tWB. */ | |
366 | ndelay(100); | |
367 | /* Wait for a chip to become ready... */ | |
368 | for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i) | |
369 | udelay(1); | |
370 | ||
371 | /* Release -CE and re-enable interrupts. */ | |
7abd3ef9 | 372 | au1550_hwcontrol(mtd, NAND_CTL_CLRNCE); |
35af68b5 SS |
373 | local_irq_restore(flags); |
374 | return; | |
375 | } | |
376 | /* Apply this short delay always to ensure that we do wait tWB. */ | |
377 | ndelay(100); | |
378 | ||
379 | while(!this->dev_ready(mtd)); | |
380 | } | |
381 | ||
06f25510 | 382 | static int find_nand_cs(unsigned long nand_base) |
1da177e4 | 383 | { |
b67a1a02 ML |
384 | void __iomem *base = |
385 | (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR); | |
386 | unsigned long addr, staddr, start, mask, end; | |
387 | int i; | |
61b03bd7 | 388 | |
b67a1a02 ML |
389 | for (i = 0; i < 4; i++) { |
390 | addr = 0x1000 + (i * 0x10); /* CSx */ | |
391 | staddr = __raw_readl(base + addr + 0x08); /* STADDRx */ | |
392 | /* figure out the decoded range of this CS */ | |
393 | start = (staddr << 4) & 0xfffc0000; | |
394 | mask = (staddr << 18) & 0xfffc0000; | |
395 | end = (start | (start - 1)) & ~(start ^ mask); | |
396 | if ((nand_base >= start) && (nand_base < end)) | |
397 | return i; | |
398 | } | |
1da177e4 | 399 | |
b67a1a02 ML |
400 | return -ENODEV; |
401 | } | |
1da177e4 | 402 | |
06f25510 | 403 | static int au1550nd_probe(struct platform_device *pdev) |
b67a1a02 ML |
404 | { |
405 | struct au1550nd_platdata *pd; | |
406 | struct au1550nd_ctx *ctx; | |
407 | struct nand_chip *this; | |
408 | struct resource *r; | |
409 | int ret, cs; | |
9bdcf336 | 410 | |
453810b7 | 411 | pd = dev_get_platdata(&pdev->dev); |
b67a1a02 ML |
412 | if (!pd) { |
413 | dev_err(&pdev->dev, "missing platform data\n"); | |
414 | return -ENODEV; | |
1da177e4 | 415 | } |
b67a1a02 ML |
416 | |
417 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
ce3737f0 | 418 | if (!ctx) |
b67a1a02 | 419 | return -ENOMEM; |
b67a1a02 ML |
420 | |
421 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
422 | if (!r) { | |
423 | dev_err(&pdev->dev, "no NAND memory resource\n"); | |
424 | ret = -ENODEV; | |
425 | goto out1; | |
ef6f0d1f | 426 | } |
b67a1a02 ML |
427 | if (request_mem_region(r->start, resource_size(r), "au1550-nand")) { |
428 | dev_err(&pdev->dev, "cannot claim NAND memory area\n"); | |
429 | ret = -ENOMEM; | |
430 | goto out1; | |
ef6f0d1f | 431 | } |
b67a1a02 ML |
432 | |
433 | ctx->base = ioremap_nocache(r->start, 0x1000); | |
434 | if (!ctx->base) { | |
435 | dev_err(&pdev->dev, "cannot remap NAND memory area\n"); | |
436 | ret = -ENODEV; | |
437 | goto out2; | |
ef6f0d1f | 438 | } |
1da177e4 | 439 | |
b67a1a02 ML |
440 | this = &ctx->chip; |
441 | ctx->info.priv = this; | |
442 | ctx->info.owner = THIS_MODULE; | |
ef6f0d1f | 443 | |
b67a1a02 ML |
444 | /* figure out which CS# r->start belongs to */ |
445 | cs = find_nand_cs(r->start); | |
446 | if (cs < 0) { | |
447 | dev_err(&pdev->dev, "cannot detect NAND chipselect\n"); | |
448 | ret = -ENODEV; | |
449 | goto out3; | |
450 | } | |
451 | ctx->cs = cs; | |
1da177e4 | 452 | |
1da177e4 | 453 | this->dev_ready = au1550_device_ready; |
35af68b5 SS |
454 | this->select_chip = au1550_select_chip; |
455 | this->cmdfunc = au1550_command; | |
456 | ||
1da177e4 | 457 | /* 30 us command delay time */ |
61b03bd7 | 458 | this->chip_delay = 30; |
6dfc6d25 | 459 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 | 460 | |
b67a1a02 | 461 | if (pd->devwidth) |
1da177e4 LT |
462 | this->options |= NAND_BUSWIDTH_16; |
463 | ||
b67a1a02 ML |
464 | this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte; |
465 | ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte; | |
1da177e4 | 466 | this->read_word = au_read_word; |
b67a1a02 ML |
467 | this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf; |
468 | this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf; | |
b67a1a02 ML |
469 | |
470 | ret = nand_scan(&ctx->info, 1); | |
471 | if (ret) { | |
472 | dev_err(&pdev->dev, "NAND scan failed with %d\n", ret); | |
473 | goto out3; | |
1da177e4 LT |
474 | } |
475 | ||
b67a1a02 | 476 | mtd_device_register(&ctx->info, pd->parts, pd->num_parts); |
1da177e4 | 477 | |
a1d7994e WY |
478 | platform_set_drvdata(pdev, ctx); |
479 | ||
1da177e4 LT |
480 | return 0; |
481 | ||
b67a1a02 ML |
482 | out3: |
483 | iounmap(ctx->base); | |
484 | out2: | |
485 | release_mem_region(r->start, resource_size(r)); | |
486 | out1: | |
487 | kfree(ctx); | |
488 | return ret; | |
1da177e4 LT |
489 | } |
490 | ||
810b7e06 | 491 | static int au1550nd_remove(struct platform_device *pdev) |
1da177e4 | 492 | { |
b67a1a02 ML |
493 | struct au1550nd_ctx *ctx = platform_get_drvdata(pdev); |
494 | struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1da177e4 | 495 | |
b67a1a02 ML |
496 | nand_release(&ctx->info); |
497 | iounmap(ctx->base); | |
498 | release_mem_region(r->start, 0x1000); | |
499 | kfree(ctx); | |
500 | return 0; | |
1da177e4 | 501 | } |
e0c7d767 | 502 | |
b67a1a02 ML |
503 | static struct platform_driver au1550nd_driver = { |
504 | .driver = { | |
505 | .name = "au1550-nand", | |
b67a1a02 ML |
506 | }, |
507 | .probe = au1550nd_probe, | |
5153b88c | 508 | .remove = au1550nd_remove, |
b67a1a02 ML |
509 | }; |
510 | ||
511 | module_platform_driver(au1550nd_driver); | |
1da177e4 LT |
512 | |
513 | MODULE_LICENSE("GPL"); | |
514 | MODULE_AUTHOR("Embedded Edge, LLC"); | |
515 | MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board"); |