[linux-2.6-block.git] / drivers / mtd / maps / intel_vr_nor.c

/*
 * drivers/mtd/maps/intel_vr_nor.c
 *
 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
 * Vermilion Range chipset.
 *
 * The Vermilion Range Expansion Bus supports four chip selects, each of which
 * has 64MiB of address space.  The 2nd BAR of the Expansion Bus PCI Device
 * is a 256MiB memory region containing the address spaces for all four of the
 * chip selects, with start addresses hardcoded on 64MiB boundaries.
 *
 * This map driver only supports NOR flash on chip select 0.  The buswidth
 * (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
 * and Control Register for Chip Select 0 (EXP_TIMING_CS0).  This driver does
 * not modify the value in the EXP_TIMING_CS0 register except to enable writing
 * and disable boot acceleration.  The timing parameters in the register are
 * assumed to have been properly initialized by the BIOS.  The reset default
 * timing parameters are maximally conservative (slow), so access to the flash
 * will be slower than it should be if the BIOS has not initialized the timing
 * parameters.
 *
 * Author: Andy Lowe <alowe@mvista.com>
 *
 * 2006 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/flashchip.h>

#define DRV_NAME "vr_nor"

struct vr_nor_mtd {
	void __iomem *csr_base;
	struct map_info map;
	struct mtd_info *info;
	struct pci_dev *dev;
};

/* Expansion Bus Configuration and Status Registers are in BAR 0 */
#define EXP_CSR_MBAR 0
/* Expansion Bus Memory Window is BAR 1 */
#define EXP_WIN_MBAR 1
/* Maximum address space for Chip Select 0 is 64MiB */
#define CS0_SIZE 0x04000000
/* Chip Select 0 is at offset 0 in the Memory Window */
#define CS0_START 0x0
/* Chip Select 0 Timing Register is at offset 0 in CSR */
#define EXP_TIMING_CS0 0x00
#define TIMING_CS_EN		(1 << 31)	/* Chip Select Enable */
#define TIMING_BOOT_ACCEL_DIS	(1 <<  8)	/* Boot Acceleration Disable */
#define TIMING_WR_EN		(1 <<  1)	/* Write Enable */
#define TIMING_BYTE_EN		(1 <<  0)	/* 8-bit vs 16-bit bus */
#define TIMING_MASK		0x3FFF0000

static void vr_nor_destroy_partitions(struct vr_nor_mtd *p)
{
	mtd_device_unregister(p->info);
}

static int vr_nor_init_partitions(struct vr_nor_mtd *p)
{
	/* register the flash bank */
	/* partition the flash bank */
	return mtd_device_parse_register(p->info, NULL, NULL, NULL, 0);
}

static void vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
{
	map_destroy(p->info);
}

static int vr_nor_mtd_setup(struct vr_nor_mtd *p)
{
	static const char * const probe_types[] =
	    { "cfi_probe", "jedec_probe", NULL };
	const char * const *type;

	for (type = probe_types; !p->info && *type; type++)
		p->info = do_map_probe(*type, &p->map);
	if (!p->info)
		return -ENODEV;

	p->info->owner = THIS_MODULE;

	return 0;
}

static void vr_nor_destroy_maps(struct vr_nor_mtd *p)
{
	unsigned int exp_timing_cs0;

	/* write-protect the flash bank */
	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	exp_timing_cs0 &= ~TIMING_WR_EN;
	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);

	/* unmap the flash window */
	iounmap(p->map.virt);

	/* unmap the csr window */
	iounmap(p->csr_base);
}

/*
 * Initialize the map_info structure and map the flash.
 * Returns 0 on success, nonzero otherwise.
 */
static int vr_nor_init_maps(struct vr_nor_mtd *p)
{
	unsigned long csr_phys, csr_len;
	unsigned long win_phys, win_len;
	unsigned int exp_timing_cs0;
	int err;

	csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
	csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
	win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
	win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);

	if (!csr_phys || !csr_len || !win_phys || !win_len)
		return -ENODEV;

	if (win_len < (CS0_START + CS0_SIZE))
		return -ENXIO;

	p->csr_base = ioremap_nocache(csr_phys, csr_len);
	if (!p->csr_base)
		return -ENOMEM;

	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	if (!(exp_timing_cs0 & TIMING_CS_EN)) {
		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
		       "is disabled.\n");
		err = -ENODEV;
		goto release;
	}
	if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
		       "is configured for maximally slow access times.\n");
	}
	p->map.name = DRV_NAME;
	p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
	p->map.phys = win_phys + CS0_START;
	p->map.size = CS0_SIZE;
	p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
	if (!p->map.virt) {
		err = -ENOMEM;
		goto release;
	}
	simple_map_init(&p->map);

	/* Enable writes to flash bank */
	exp_timing_cs0 |= TIMING_BOOT_ACCEL_DIS | TIMING_WR_EN;
	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);

	return 0;

      release:
	iounmap(p->csr_base);
	return err;
}

static struct pci_device_id vr_nor_pci_ids[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
	{0,}
};

static void vr_nor_pci_remove(struct pci_dev *dev)
{
	struct vr_nor_mtd *p = pci_get_drvdata(dev);

	pci_set_drvdata(dev, NULL);
	vr_nor_destroy_partitions(p);
	vr_nor_destroy_mtd_setup(p);
	vr_nor_destroy_maps(p);
	kfree(p);
	pci_release_regions(dev);
	pci_disable_device(dev);
}

static int vr_nor_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct vr_nor_mtd *p = NULL;
	unsigned int exp_timing_cs0;
	int err;

	err = pci_enable_device(dev);
	if (err)
		goto out;

	err = pci_request_regions(dev, DRV_NAME);
	if (err)
		goto disable_dev;

	p = kzalloc(sizeof(*p), GFP_KERNEL);
	err = -ENOMEM;
	if (!p)
		goto release;

	p->dev = dev;

	err = vr_nor_init_maps(p);
	if (err)
		goto release;

	err = vr_nor_mtd_setup(p);
	if (err)
		goto destroy_maps;

	err = vr_nor_init_partitions(p);
	if (err)
		goto destroy_mtd_setup;

	pci_set_drvdata(dev, p);

	return 0;

      destroy_mtd_setup:
	map_destroy(p->info);

      destroy_maps:
	/* write-protect the flash bank */
	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	exp_timing_cs0 &= ~TIMING_WR_EN;
	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);

	/* unmap the flash window */
	iounmap(p->map.virt);

	/* unmap the csr window */
	iounmap(p->csr_base);

      release:
	kfree(p);
	pci_release_regions(dev);

      disable_dev:
	pci_disable_device(dev);

      out:
	return err;
}

static struct pci_driver vr_nor_pci_driver = {
	.name = DRV_NAME,
	.probe = vr_nor_pci_probe,
	.remove = vr_nor_pci_remove,
	.id_table = vr_nor_pci_ids,
};

module_pci_driver(vr_nor_pci_driver);

MODULE_AUTHOR("Andy Lowe");
MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);
Commit	Line	Data
0bac5111 DW	1	/*
	2	* drivers/mtd/maps/intel_vr_nor.c
	3	*
	4	* An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
	5	* Vermilion Range chipset.
	6	*
	7	* The Vermilion Range Expansion Bus supports four chip selects, each of which
	8	* has 64MiB of address space. The 2nd BAR of the Expansion Bus PCI Device
	9	* is a 256MiB memory region containing the address spaces for all four of the
	10	* chip selects, with start addresses hardcoded on 64MiB boundaries.
	11	*
	12	* This map driver only supports NOR flash on chip select 0. The buswidth
	13	* (either 8 bits or 16 bits) is determined by reading the Expansion Bus Timing
	14	* and Control Register for Chip Select 0 (EXP_TIMING_CS0). This driver does
	15	* not modify the value in the EXP_TIMING_CS0 register except to enable writing
	16	* and disable boot acceleration. The timing parameters in the register are
	17	* assumed to have been properly initialized by the BIOS. The reset default
	18	* timing parameters are maximally conservative (slow), so access to the flash
	19	* will be slower than it should be if the BIOS has not initialized the timing
	20	* parameters.
	21	*
	22	* Author: Andy Lowe <alowe@mvista.com>
	23	*
	24	* 2006 (c) MontaVista Software, Inc. This file is licensed under
	25	* the terms of the GNU General Public License version 2. This program
	26	* is licensed "as is" without any warranty of any kind, whether express
	27	* or implied.
	28	*/
	29
	30	#include <linux/module.h>
	31	#include <linux/kernel.h>
5a0e3ad6	32	#include <linux/slab.h>
0bac5111 DW	33	#include <linux/pci.h>
	34	#include <linux/init.h>
	35	#include <linux/mtd/mtd.h>
	36	#include <linux/mtd/map.h>
	37	#include <linux/mtd/partitions.h>
	38	#include <linux/mtd/cfi.h>
	39	#include <linux/mtd/flashchip.h>
	40
	41	#define DRV_NAME "vr_nor"
	42
	43	struct vr_nor_mtd {
	44	void __iomem *csr_base;
	45	struct map_info map;
	46	struct mtd_info *info;
0bac5111 DW	47	struct pci_dev *dev;
	48	};
	49
	50	/* Expansion Bus Configuration and Status Registers are in BAR 0 */
	51	#define EXP_CSR_MBAR 0
	52	/* Expansion Bus Memory Window is BAR 1 */
	53	#define EXP_WIN_MBAR 1
	54	/* Maximum address space for Chip Select 0 is 64MiB */
	55	#define CS0_SIZE 0x04000000
	56	/* Chip Select 0 is at offset 0 in the Memory Window */
	57	#define CS0_START 0x0
	58	/* Chip Select 0 Timing Register is at offset 0 in CSR */
	59	#define EXP_TIMING_CS0 0x00
	60	#define TIMING_CS_EN (1 << 31) /* Chip Select Enable */
	61	#define TIMING_BOOT_ACCEL_DIS (1 << 8) /* Boot Acceleration Disable */
	62	#define TIMING_WR_EN (1 << 1) /* Write Enable */
	63	#define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */
	64	#define TIMING_MASK 0x3FFF0000
	65
810b7e06	66	static void vr_nor_destroy_partitions(struct vr_nor_mtd *p)
0bac5111	67	{
95bf224f	68	mtd_device_unregister(p->info);
0bac5111 DW	69	}
0bac5111 DW	70
06f25510	71	static int vr_nor_init_partitions(struct vr_nor_mtd *p)
0bac5111	72	{
0bac5111	73	/* register the flash bank */
0bac5111	74	/* partition the flash bank */
42d7fbe2	75	return mtd_device_parse_register(p->info, NULL, NULL, NULL, 0);
0bac5111 DW	76	}
0bac5111 DW	77
810b7e06	78	static void vr_nor_destroy_mtd_setup(struct vr_nor_mtd *p)
0bac5111 DW	79	{
	80	map_destroy(p->info);
	81	}
	82
06f25510	83	static int vr_nor_mtd_setup(struct vr_nor_mtd *p)
0bac5111	84	{
0984c891	85	static const char * const probe_types[] =
0bac5111	86	{ "cfi_probe", "jedec_probe", NULL };
0984c891	87	const char * const *type;
0bac5111 DW	88
	89	for (type = probe_types; !p->info && *type; type++)
	90	p->info = do_map_probe(*type, &p->map);
	91	if (!p->info)
	92	return -ENODEV;
	93
	94	p->info->owner = THIS_MODULE;
	95
	96	return 0;
	97	}
	98
810b7e06	99	static void vr_nor_destroy_maps(struct vr_nor_mtd *p)
0bac5111 DW	100	{
	101	unsigned int exp_timing_cs0;
	102
	103	/* write-protect the flash bank */
	104	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	105	exp_timing_cs0 &= ~TIMING_WR_EN;
	106	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
	107
	108	/* unmap the flash window */
	109	iounmap(p->map.virt);
	110
	111	/* unmap the csr window */
	112	iounmap(p->csr_base);
	113	}
	114
	115	/*
	116	* Initialize the map_info structure and map the flash.
	117	* Returns 0 on success, nonzero otherwise.
	118	*/
06f25510	119	static int vr_nor_init_maps(struct vr_nor_mtd *p)
0bac5111 DW	120	{
	121	unsigned long csr_phys, csr_len;
	122	unsigned long win_phys, win_len;
	123	unsigned int exp_timing_cs0;
	124	int err;
	125
	126	csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);
	127	csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);
	128	win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);
	129	win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);
	130
	131	if (!csr_phys \|\| !csr_len \|\| !win_phys \|\| !win_len)
	132	return -ENODEV;
	133
	134	if (win_len < (CS0_START + CS0_SIZE))
	135	return -ENXIO;
	136
	137	p->csr_base = ioremap_nocache(csr_phys, csr_len);
	138	if (!p->csr_base)
	139	return -ENOMEM;
	140
	141	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	142	if (!(exp_timing_cs0 & TIMING_CS_EN)) {
	143	dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
	144	"is disabled.\n");
	145	err = -ENODEV;
	146	goto release;
	147	}
	148	if ((exp_timing_cs0 & TIMING_MASK) == TIMING_MASK) {
	149	dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "
	150	"is configured for maximally slow access times.\n");
	151	}
	152	p->map.name = DRV_NAME;
	153	p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;
	154	p->map.phys = win_phys + CS0_START;
	155	p->map.size = CS0_SIZE;
	156	p->map.virt = ioremap_nocache(p->map.phys, p->map.size);
	157	if (!p->map.virt) {
	158	err = -ENOMEM;
	159	goto release;
	160	}
	161	simple_map_init(&p->map);
	162
	163	/* Enable writes to flash bank */
	164	exp_timing_cs0 \|= TIMING_BOOT_ACCEL_DIS \| TIMING_WR_EN;
	165	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
	166
	167	return 0;
	168
	169	release:
	170	iounmap(p->csr_base);
	171	return err;
	172	}
	173
	174	static struct pci_device_id vr_nor_pci_ids[] = {
	175	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x500D)},
	176	{0,}
	177	};
	178
810b7e06	179	static void vr_nor_pci_remove(struct pci_dev *dev)
0bac5111 DW	180	{
	181	struct vr_nor_mtd *p = pci_get_drvdata(dev);
	182
	183	pci_set_drvdata(dev, NULL);
	184	vr_nor_destroy_partitions(p);
	185	vr_nor_destroy_mtd_setup(p);
	186	vr_nor_destroy_maps(p);
	187	kfree(p);
	188	pci_release_regions(dev);
	189	pci_disable_device(dev);
	190	}
	191
d8929942	192	static int vr_nor_pci_probe(struct pci_dev dev, const struct pci_device_id id)
0bac5111 DW	193	{
	194	struct vr_nor_mtd *p = NULL;
	195	unsigned int exp_timing_cs0;
	196	int err;
	197
	198	err = pci_enable_device(dev);
	199	if (err)
	200	goto out;
	201
	202	err = pci_request_regions(dev, DRV_NAME);
	203	if (err)
	204	goto disable_dev;
	205
	206	p = kzalloc(sizeof(*p), GFP_KERNEL);
	207	err = -ENOMEM;
	208	if (!p)
	209	goto release;
	210
	211	p->dev = dev;
	212
	213	err = vr_nor_init_maps(p);
	214	if (err)
	215	goto release;
	216
	217	err = vr_nor_mtd_setup(p);
	218	if (err)
	219	goto destroy_maps;
	220
	221	err = vr_nor_init_partitions(p);
	222	if (err)
	223	goto destroy_mtd_setup;
	224
	225	pci_set_drvdata(dev, p);
	226
	227	return 0;
	228
	229	destroy_mtd_setup:
	230	map_destroy(p->info);
	231
	232	destroy_maps:
	233	/* write-protect the flash bank */
	234	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);
	235	exp_timing_cs0 &= ~TIMING_WR_EN;
	236	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);
	237
	238	/* unmap the flash window */
	239	iounmap(p->map.virt);
	240
	241	/* unmap the csr window */
	242	iounmap(p->csr_base);
	243
	244	release:
	245	kfree(p);
	246	pci_release_regions(dev);
	247
	248	disable_dev:
	249	pci_disable_device(dev);
	250
	251	out:
	252	return err;
	253	}
	254
	255	static struct pci_driver vr_nor_pci_driver = {
	256	.name = DRV_NAME,
257	.probe = vr_nor_pci_probe,
5153b88c	258	.remove = vr_nor_pci_remove,
0bac5111 DW	259	.id_table = vr_nor_pci_ids,
	260	};
	261
4d16cd65	262	module_pci_driver(vr_nor_pci_driver);
0bac5111 DW	263
	264	MODULE_AUTHOR("Andy Lowe");
	265	MODULE_DESCRIPTION("MTD map driver for NOR flash on Intel Vermilion Range");
	266	MODULE_LICENSE("GPL");
	267	MODULE_DEVICE_TABLE(pci, vr_nor_pci_ids);