[linux-block.git] / drivers / mtd / maps / ichxrom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ichxrom.c
 *
 * Normal mappings of chips in physical memory
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/flashchip.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/list.h>

#define xstr(s) str(s)
#define str(s) #s
#define MOD_NAME xstr(KBUILD_BASENAME)

#define ADDRESS_NAME_LEN 18

#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */

#define BIOS_CNTL	0x4e
#define FWH_DEC_EN1	0xE3
#define FWH_DEC_EN2	0xF0
#define FWH_SEL1	0xE8
#define FWH_SEL2	0xEE

struct ichxrom_window {
	void __iomem* virt;
	unsigned long phys;
	unsigned long size;
	struct list_head maps;
	struct resource rsrc;
	struct pci_dev *pdev;
};

struct ichxrom_map_info {
	struct list_head list;
	struct map_info map;
	struct mtd_info *mtd;
	struct resource rsrc;
	char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
};

static struct ichxrom_window ichxrom_window = {
	.maps = LIST_HEAD_INIT(ichxrom_window.maps),
};

static void ichxrom_cleanup(struct ichxrom_window *window)
{
	struct ichxrom_map_info *map, *scratch;
	u16 word;
	int ret;

	/* Disable writes through the rom window */
	ret = pci_read_config_word(window->pdev, BIOS_CNTL, &word);
	if (!ret)
		pci_write_config_word(window->pdev, BIOS_CNTL, word & ~1);
	pci_dev_put(window->pdev);

	/* Free all of the mtd devices */
	list_for_each_entry_safe(map, scratch, &window->maps, list) {
		if (map->rsrc.parent)
			release_resource(&map->rsrc);
		mtd_device_unregister(map->mtd);
		map_destroy(map->mtd);
		list_del(&map->list);
		kfree(map);
	}
	if (window->rsrc.parent)
		release_resource(&window->rsrc);
	if (window->virt) {
		iounmap(window->virt);
		window->virt = NULL;
		window->phys = 0;
		window->size = 0;
		window->pdev = NULL;
	}
}


static int __init ichxrom_init_one(struct pci_dev *pdev,
				   const struct pci_device_id *ent)
{
	static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
	struct ichxrom_window *window = &ichxrom_window;
	struct ichxrom_map_info *map = NULL;
	unsigned long map_top;
	u8 byte;
	u16 word;

	/* For now I just handle the ichx and I assume there
	 * are not a lot of resources up at the top of the address
	 * space.  It is possible to handle other devices in the
	 * top 16MB but it is very painful.  Also since
	 * you can only really attach a FWH to an ICHX there
	 * a number of simplifications you can make.
	 *
	 * Also you can page firmware hubs if an 8MB window isn't enough
	 * but don't currently handle that case either.
	 */
	window->pdev = pdev;

	/* Find a region continuous to the end of the ROM window  */
	window->phys = 0;
	pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
	if (byte == 0xff) {
		window->phys = 0xffc00000;
		pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
		if ((byte & 0x0f) == 0x0f) {
			window->phys = 0xff400000;
		}
		else if ((byte & 0x0e) == 0x0e) {
			window->phys = 0xff500000;
		}
		else if ((byte & 0x0c) == 0x0c) {
			window->phys = 0xff600000;
		}
		else if ((byte & 0x08) == 0x08) {
			window->phys = 0xff700000;
		}
	}
	else if ((byte & 0xfe) == 0xfe) {
		window->phys = 0xffc80000;
	}
	else if ((byte & 0xfc) == 0xfc) {
		window->phys = 0xffd00000;
	}
	else if ((byte & 0xf8) == 0xf8) {
		window->phys = 0xffd80000;
	}
	else if ((byte & 0xf0) == 0xf0) {
		window->phys = 0xffe00000;
	}
	else if ((byte & 0xe0) == 0xe0) {
		window->phys = 0xffe80000;
	}
	else if ((byte & 0xc0) == 0xc0) {
		window->phys = 0xfff00000;
	}
	else if ((byte & 0x80) == 0x80) {
		window->phys = 0xfff80000;
	}

	if (window->phys == 0) {
		printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
		goto out;
	}
	window->phys -= 0x400000UL;
	window->size = (0xffffffffUL - window->phys) + 1UL;

	/* Enable writes through the rom window */
	pci_read_config_word(pdev, BIOS_CNTL, &word);
	if (!(word & 1)  && (word & (1<<1))) {
		/* The BIOS will generate an error if I enable
		 * this device, so don't even try.
		 */
		printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
		goto out;
	}
	pci_write_config_word(pdev, BIOS_CNTL, word | 1);

	/*
	 * Try to reserve the window mem region.  If this fails then
	 * it is likely due to the window being "reserved" by the BIOS.
	 */
	window->rsrc.name = MOD_NAME;
	window->rsrc.start = window->phys;
	window->rsrc.end   = window->phys + window->size - 1;
	window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
	if (request_resource(&iomem_resource, &window->rsrc)) {
		window->rsrc.parent = NULL;
		printk(KERN_DEBUG MOD_NAME ": "
		       "%s(): Unable to register resource %pR - kernel bug?\n",
		       __func__, &window->rsrc);
	}

	/* Map the firmware hub into my address space. */
	window->virt = ioremap_nocache(window->phys, window->size);
	if (!window->virt) {
		printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
			window->phys, window->size);
		goto out;
	}

	/* Get the first address to look for an rom chip at */
	map_top = window->phys;
	if ((window->phys & 0x3fffff) != 0) {
		map_top = window->phys + 0x400000;
	}
#if 1
	/* The probe sequence run over the firmware hub lock
	 * registers sets them to 0x7 (no access).
	 * Probe at most the last 4M of the address space.
	 */
	if (map_top < 0xffc00000) {
		map_top = 0xffc00000;
	}
#endif
	/* Loop through and look for rom chips */
	while((map_top - 1) < 0xffffffffUL) {
		struct cfi_private *cfi;
		unsigned long offset;
		int i;

		if (!map) {
			map = kmalloc(sizeof(*map), GFP_KERNEL);
		}
		if (!map) {
			printk(KERN_ERR MOD_NAME ": kmalloc failed");
			goto out;
		}
		memset(map, 0, sizeof(*map));
		INIT_LIST_HEAD(&map->list);
		map->map.name = map->map_name;
		map->map.phys = map_top;
		offset = map_top - window->phys;
		map->map.virt = (void __iomem *)
			(((unsigned long)(window->virt)) + offset);
		map->map.size = 0xffffffffUL - map_top + 1UL;
		/* Set the name of the map to the address I am trying */
		sprintf(map->map_name, "%s @%08Lx",
			MOD_NAME, (unsigned long long)map->map.phys);

		/* Firmware hubs only use vpp when being programmed
		 * in a factory setting.  So in-place programming
		 * needs to use a different method.
		 */
		for(map->map.bankwidth = 32; map->map.bankwidth;
			map->map.bankwidth >>= 1)
		{
			char **probe_type;
			/* Skip bankwidths that are not supported */
			if (!map_bankwidth_supported(map->map.bankwidth))
				continue;

			/* Setup the map methods */
			simple_map_init(&map->map);

			/* Try all of the probe methods */
			probe_type = rom_probe_types;
			for(; *probe_type; probe_type++) {
				map->mtd = do_map_probe(*probe_type, &map->map);
				if (map->mtd)
					goto found;
			}
		}
		map_top += ROM_PROBE_STEP_SIZE;
		continue;
	found:
		/* Trim the size if we are larger than the map */
		if (map->mtd->size > map->map.size) {
			printk(KERN_WARNING MOD_NAME
				" rom(%llu) larger than window(%lu). fixing...\n",
				(unsigned long long)map->mtd->size, map->map.size);
			map->mtd->size = map->map.size;
		}
		if (window->rsrc.parent) {
			/*
			 * Registering the MTD device in iomem may not be possible
			 * if there is a BIOS "reserved" and BUSY range.  If this
			 * fails then continue anyway.
			 */
			map->rsrc.name  = map->map_name;
			map->rsrc.start = map->map.phys;
			map->rsrc.end   = map->map.phys + map->mtd->size - 1;
			map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
			if (request_resource(&window->rsrc, &map->rsrc)) {
				printk(KERN_ERR MOD_NAME
					": cannot reserve MTD resource\n");
				map->rsrc.parent = NULL;
			}
		}

		/* Make the whole region visible in the map */
		map->map.virt = window->virt;
		map->map.phys = window->phys;
		cfi = map->map.fldrv_priv;
		for(i = 0; i < cfi->numchips; i++) {
			cfi->chips[i].start += offset;
		}

		/* Now that the mtd devices is complete claim and export it */
		map->mtd->owner = THIS_MODULE;
		if (mtd_device_register(map->mtd, NULL, 0)) {
			map_destroy(map->mtd);
			map->mtd = NULL;
			goto out;
		}


		/* Calculate the new value of map_top */
		map_top += map->mtd->size;

		/* File away the map structure */
		list_add(&map->list, &window->maps);
		map = NULL;
	}

 out:
	/* Free any left over map structures */
	kfree(map);

	/* See if I have any map structures */
	if (list_empty(&window->maps)) {
		ichxrom_cleanup(window);
		return -ENODEV;
	}
	return 0;
}


static void ichxrom_remove_one(struct pci_dev *pdev)
{
	struct ichxrom_window *window = &ichxrom_window;
	ichxrom_cleanup(window);
}

static const struct pci_device_id ichxrom_pci_tbl[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
	  PCI_ANY_ID, PCI_ANY_ID, },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
	  PCI_ANY_ID, PCI_ANY_ID, },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
	  PCI_ANY_ID, PCI_ANY_ID, },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
	  PCI_ANY_ID, PCI_ANY_ID, },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
	  PCI_ANY_ID, PCI_ANY_ID, },
	{ 0, },
};

#if 0
MODULE_DEVICE_TABLE(pci, ichxrom_pci_tbl);

static struct pci_driver ichxrom_driver = {
	.name =		MOD_NAME,
	.id_table =	ichxrom_pci_tbl,
	.probe =	ichxrom_init_one,
	.remove =	ichxrom_remove_one,
};
#endif

static int __init init_ichxrom(void)
{
	struct pci_dev *pdev;
	const struct pci_device_id *id;

	pdev = NULL;
	for (id = ichxrom_pci_tbl; id->vendor; id++) {
		pdev = pci_get_device(id->vendor, id->device, NULL);
		if (pdev) {
			break;
		}
	}
	if (pdev) {
		return ichxrom_init_one(pdev, &ichxrom_pci_tbl[0]);
	}
	return -ENXIO;
#if 0
	return pci_register_driver(&ichxrom_driver);
#endif
}

static void __exit cleanup_ichxrom(void)
{
	ichxrom_remove_one(ichxrom_window.pdev);
}

module_init(init_ichxrom);
module_exit(cleanup_ichxrom);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");
MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ICHX southbridge");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	/*
	3	* ichxrom.c
	4	*
	5	* Normal mappings of chips in physical memory
1da177e4 LT	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/types.h>
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
5a0e3ad6	12	#include <linux/slab.h>
1da177e4 LT	13	#include <asm/io.h>
	14	#include <linux/mtd/mtd.h>
	15	#include <linux/mtd/map.h>
	16	#include <linux/mtd/cfi.h>
	17	#include <linux/mtd/flashchip.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/pci_ids.h>
	20	#include <linux/list.h>
	21
	22	#define xstr(s) str(s)
	23	#define str(s) #s
	24	#define MOD_NAME xstr(KBUILD_BASENAME)
	25
	26	#define ADDRESS_NAME_LEN 18
	27
	28	#define ROM_PROBE_STEP_SIZE (641024) / 64KiB */
	29
	30	#define BIOS_CNTL 0x4e
	31	#define FWH_DEC_EN1 0xE3
	32	#define FWH_DEC_EN2 0xF0
	33	#define FWH_SEL1 0xE8
	34	#define FWH_SEL2 0xEE
	35
	36	struct ichxrom_window {
	37	void __iomem* virt;
	38	unsigned long phys;
	39	unsigned long size;
	40	struct list_head maps;
	41	struct resource rsrc;
	42	struct pci_dev *pdev;
	43	};
	44
	45	struct ichxrom_map_info {
	46	struct list_head list;
	47	struct map_info map;
	48	struct mtd_info *mtd;
	49	struct resource rsrc;
	50	char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
	51	};
	52
	53	static struct ichxrom_window ichxrom_window = {
	54	.maps = LIST_HEAD_INIT(ichxrom_window.maps),
	55	};
	56
	57	static void ichxrom_cleanup(struct ichxrom_window *window)
	58	{
	59	struct ichxrom_map_info map, scratch;
	60	u16 word;
e70dda08	61	int ret;
1da177e4 LT	62
1da177e4 LT	63	/* Disable writes through the rom window */
e70dda08 AB	64	ret = pci_read_config_word(window->pdev, BIOS_CNTL, &word);
	65	if (!ret)
	66	pci_write_config_word(window->pdev, BIOS_CNTL, word & ~1);
dd8e9ed6	67	pci_dev_put(window->pdev);
1da177e4 LT	68
	69	/* Free all of the mtd devices */
	70	list_for_each_entry_safe(map, scratch, &window->maps, list) {
	71	if (map->rsrc.parent)
	72	release_resource(&map->rsrc);
ee0e87b1	73	mtd_device_unregister(map->mtd);
1da177e4 LT	74	map_destroy(map->mtd);
	75	list_del(&map->list);
	76	kfree(map);
	77	}
	78	if (window->rsrc.parent)
	79	release_resource(&window->rsrc);
	80	if (window->virt) {
	81	iounmap(window->virt);
	82	window->virt = NULL;
	83	window->phys = 0;
	84	window->size = 0;
	85	window->pdev = NULL;
	86	}
	87	}
	88
	89
e4106a7c JL	90	static int __init ichxrom_init_one(struct pci_dev *pdev,
e4106a7c JL	91	const struct pci_device_id *ent)
1da177e4 LT	92	{
	93	static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
	94	struct ichxrom_window *window = &ichxrom_window;
	95	struct ichxrom_map_info *map = NULL;
	96	unsigned long map_top;
	97	u8 byte;
	98	u16 word;
	99
	100	/* For now I just handle the ichx and I assume there
	101	* are not a lot of resources up at the top of the address
	102	* space. It is possible to handle other devices in the
	103	* top 16MB but it is very painful. Also since
	104	* you can only really attach a FWH to an ICHX there
	105	* a number of simplifications you can make.
	106	*
69f34c98	107	* Also you can page firmware hubs if an 8MB window isn't enough
1da177e4 LT	108	* but don't currently handle that case either.
	109	*/
	110	window->pdev = pdev;
	111
	112	/* Find a region continuous to the end of the ROM window */
	113	window->phys = 0;
	114	pci_read_config_byte(pdev, FWH_DEC_EN1, &byte);
	115	if (byte == 0xff) {
	116	window->phys = 0xffc00000;
	117	pci_read_config_byte(pdev, FWH_DEC_EN2, &byte);
	118	if ((byte & 0x0f) == 0x0f) {
	119	window->phys = 0xff400000;
	120	}
	121	else if ((byte & 0x0e) == 0x0e) {
	122	window->phys = 0xff500000;
	123	}
	124	else if ((byte & 0x0c) == 0x0c) {
	125	window->phys = 0xff600000;
	126	}
	127	else if ((byte & 0x08) == 0x08) {
	128	window->phys = 0xff700000;
	129	}
	130	}
	131	else if ((byte & 0xfe) == 0xfe) {
	132	window->phys = 0xffc80000;
	133	}
	134	else if ((byte & 0xfc) == 0xfc) {
	135	window->phys = 0xffd00000;
	136	}
	137	else if ((byte & 0xf8) == 0xf8) {
	138	window->phys = 0xffd80000;
	139	}
	140	else if ((byte & 0xf0) == 0xf0) {
	141	window->phys = 0xffe00000;
	142	}
	143	else if ((byte & 0xe0) == 0xe0) {
	144	window->phys = 0xffe80000;
	145	}
	146	else if ((byte & 0xc0) == 0xc0) {
	147	window->phys = 0xfff00000;
	148	}
	149	else if ((byte & 0x80) == 0x80) {
69f34c98	150	window->phys = 0xfff80000;
1da177e4 LT	151	}
	152
	153	if (window->phys == 0) {
	154	printk(KERN_ERR MOD_NAME ": Rom window is closed\n");
	155	goto out;
	156	}
	157	window->phys -= 0x400000UL;
	158	window->size = (0xffffffffUL - window->phys) + 1UL;
	159
	160	/* Enable writes through the rom window */
	161	pci_read_config_word(pdev, BIOS_CNTL, &word);
	162	if (!(word & 1) && (word & (1<<1))) {
	163	/* The BIOS will generate an error if I enable
	164	* this device, so don't even try.
	165	*/
	166	printk(KERN_ERR MOD_NAME ": firmware access control, I can't enable writes\n");
	167	goto out;
	168	}
	169	pci_write_config_word(pdev, BIOS_CNTL, word \| 1);
	170
	171	/*
	172	* Try to reserve the window mem region. If this fails then
01d0afdd	173	* it is likely due to the window being "reserved" by the BIOS.
1da177e4 LT	174	*/
	175	window->rsrc.name = MOD_NAME;
	176	window->rsrc.start = window->phys;
	177	window->rsrc.end = window->phys + window->size - 1;
	178	window->rsrc.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	179	if (request_resource(&iomem_resource, &window->rsrc)) {
	180	window->rsrc.parent = NULL;
f9a5279c JP	181	printk(KERN_DEBUG MOD_NAME ": "
	182	"%s(): Unable to register resource %pR - kernel bug?\n",
	183	__func__, &window->rsrc);
1da177e4 LT	184	}
	185
	186	/* Map the firmware hub into my address space. */
	187	window->virt = ioremap_nocache(window->phys, window->size);
	188	if (!window->virt) {
	189	printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
	190	window->phys, window->size);
	191	goto out;
	192	}
	193
	194	/* Get the first address to look for an rom chip at */
	195	map_top = window->phys;
	196	if ((window->phys & 0x3fffff) != 0) {
	197	map_top = window->phys + 0x400000;
	198	}
	199	#if 1
	200	/* The probe sequence run over the firmware hub lock
	201	* registers sets them to 0x7 (no access).
	202	* Probe at most the last 4M of the address space.
	203	*/
	204	if (map_top < 0xffc00000) {
	205	map_top = 0xffc00000;
	206	}
	207	#endif
	208	/* Loop through and look for rom chips */
	209	while((map_top - 1) < 0xffffffffUL) {
	210	struct cfi_private *cfi;
	211	unsigned long offset;
	212	int i;
	213
	214	if (!map) {
	215	map = kmalloc(sizeof(*map), GFP_KERNEL);
	216	}
	217	if (!map) {
	218	printk(KERN_ERR MOD_NAME ": kmalloc failed");
	219	goto out;
	220	}
	221	memset(map, 0, sizeof(*map));
	222	INIT_LIST_HEAD(&map->list);
	223	map->map.name = map->map_name;
	224	map->map.phys = map_top;
	225	offset = map_top - window->phys;
	226	map->map.virt = (void __iomem *)
	227	(((unsigned long)(window->virt)) + offset);
	228	map->map.size = 0xffffffffUL - map_top + 1UL;
	229	/* Set the name of the map to the address I am trying */
3a38d3af AM	230	sprintf(map->map_name, "%s @%08Lx",
3a38d3af AM	231	MOD_NAME, (unsigned long long)map->map.phys);
1da177e4 LT	232
	233	/* Firmware hubs only use vpp when being programmed
	234	* in a factory setting. So in-place programming
	235	* needs to use a different method.
	236	*/
69f34c98	237	for(map->map.bankwidth = 32; map->map.bankwidth;
1da177e4 LT	238	map->map.bankwidth >>= 1)
	239	{
	240	char **probe_type;
	241	/* Skip bankwidths that are not supported */
	242	if (!map_bankwidth_supported(map->map.bankwidth))
	243	continue;
	244
	245	/* Setup the map methods */
	246	simple_map_init(&map->map);
	247
	248	/* Try all of the probe methods */
	249	probe_type = rom_probe_types;
	250	for(; *probe_type; probe_type++) {
	251	map->mtd = do_map_probe(*probe_type, &map->map);
	252	if (map->mtd)
	253	goto found;
	254	}
	255	}
	256	map_top += ROM_PROBE_STEP_SIZE;
	257	continue;
	258	found:
	259	/* Trim the size if we are larger than the map */
	260	if (map->mtd->size > map->map.size) {
	261	printk(KERN_WARNING MOD_NAME
69423d99 AH	262	" rom(%llu) larger than window(%lu). fixing...\n",
69423d99 AH	263	(unsigned long long)map->mtd->size, map->map.size);
1da177e4 LT	264	map->mtd->size = map->map.size;
	265	}
	266	if (window->rsrc.parent) {
	267	/*
	268	* Registering the MTD device in iomem may not be possible
	269	* if there is a BIOS "reserved" and BUSY range. If this
	270	* fails then continue anyway.
	271	*/
	272	map->rsrc.name = map->map_name;
	273	map->rsrc.start = map->map.phys;
	274	map->rsrc.end = map->map.phys + map->mtd->size - 1;
	275	map->rsrc.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	276	if (request_resource(&window->rsrc, &map->rsrc)) {
	277	printk(KERN_ERR MOD_NAME
	278	": cannot reserve MTD resource\n");
	279	map->rsrc.parent = NULL;
	280	}
	281	}
	282
	283	/* Make the whole region visible in the map */
	284	map->map.virt = window->virt;
	285	map->map.phys = window->phys;
	286	cfi = map->map.fldrv_priv;
	287	for(i = 0; i < cfi->numchips; i++) {
	288	cfi->chips[i].start += offset;
	289	}
69f34c98	290
1da177e4 LT	291	/* Now that the mtd devices is complete claim and export it */
1da177e4 LT	292	map->mtd->owner = THIS_MODULE;
ee0e87b1	293	if (mtd_device_register(map->mtd, NULL, 0)) {
1da177e4 LT	294	map_destroy(map->mtd);
	295	map->mtd = NULL;
	296	goto out;
	297	}
	298
	299
	300	/* Calculate the new value of map_top */
	301	map_top += map->mtd->size;
	302
	303	/* File away the map structure */
	304	list_add(&map->list, &window->maps);
	305	map = NULL;
	306	}
	307
	308	out:
	309	/* Free any left over map structures */
fa671646 JJ	310	kfree(map);
fa671646 JJ	311
1da177e4 LT	312	/* See if I have any map structures */
	313	if (list_empty(&window->maps)) {
	314	ichxrom_cleanup(window);
	315	return -ENODEV;
	316	}
	317	return 0;
	318	}
	319
	320
7bf350b7	321	static void ichxrom_remove_one(struct pci_dev *pdev)
1da177e4 LT	322	{
	323	struct ichxrom_window *window = &ichxrom_window;
	324	ichxrom_cleanup(window);
	325	}
	326
68002593	327	static const struct pci_device_id ichxrom_pci_tbl[] = {
69f34c98	328	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
1da177e4	329	PCI_ANY_ID, PCI_ANY_ID, },
69f34c98	330	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
1da177e4	331	PCI_ANY_ID, PCI_ANY_ID, },
69f34c98	332	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
1da177e4 LT	333	PCI_ANY_ID, PCI_ANY_ID, },
	334	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
	335	PCI_ANY_ID, PCI_ANY_ID, },
	336	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
	337	PCI_ANY_ID, PCI_ANY_ID, },
	338	{ 0, },
	339	};
	340
b9c86d59	341	#if 0
1da177e4 LT	342	MODULE_DEVICE_TABLE(pci, ichxrom_pci_tbl);
1da177e4 LT	343
1da177e4 LT	344	static struct pci_driver ichxrom_driver = {
	345	.name = MOD_NAME,
	346	.id_table = ichxrom_pci_tbl,
	347	.probe = ichxrom_init_one,
	348	.remove = ichxrom_remove_one,
	349	};
	350	#endif
	351
	352	static int __init init_ichxrom(void)
	353	{
	354	struct pci_dev *pdev;
68002593	355	const struct pci_device_id *id;
1da177e4 LT	356
	357	pdev = NULL;
	358	for (id = ichxrom_pci_tbl; id->vendor; id++) {
dd8e9ed6	359	pdev = pci_get_device(id->vendor, id->device, NULL);
1da177e4 LT	360	if (pdev) {
	361	break;
	362	}
	363	}
	364	if (pdev) {
	365	return ichxrom_init_one(pdev, &ichxrom_pci_tbl[0]);
	366	}
	367	return -ENXIO;
	368	#if 0
ff3bc4eb	369	return pci_register_driver(&ichxrom_driver);
1da177e4 LT	370	#endif
	371	}
	372
	373	static void __exit cleanup_ichxrom(void)
	374	{
	375	ichxrom_remove_one(ichxrom_window.pdev);
	376	}
	377
	378	module_init(init_ichxrom);
	379	module_exit(cleanup_ichxrom);
	380
	381	MODULE_LICENSE("GPL");
	382	MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");
	383	MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ICHX southbridge");