[linux-2.6-block.git] / drivers / mtd / maps / ck804xrom.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ck804xrom.c
 *
 * Normal mappings of chips in physical memory
 *
 * Dave Olsen <dolsen@lnxi.com>
 * Ryan Jackson <rjackson@lnxi.com>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/flashchip.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/list.h>


#define MOD_NAME KBUILD_BASENAME

#define ADDRESS_NAME_LEN 18

#define ROM_PROBE_STEP_SIZE (64*1024)

#define DEV_CK804 1
#define DEV_MCP55 2

struct ck804xrom_window {
	void __iomem *virt;
	unsigned long phys;
	unsigned long size;
	struct list_head maps;
	struct resource rsrc;
	struct pci_dev *pdev;
};

struct ck804xrom_map_info {
	struct list_head list;
	struct map_info map;
	struct mtd_info *mtd;
	struct resource rsrc;
	char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
};

/*
 * The following applies to ck804 only:
 * The 2 bits controlling the window size are often set to allow reading
 * the BIOS, but too small to allow writing, since the lock registers are
 * 4MiB lower in the address space than the data.
 *
 * This is intended to prevent flashing the bios, perhaps accidentally.
 *
 * This parameter allows the normal driver to override the BIOS settings.
 *
 * The bits are 6 and 7.  If both bits are set, it is a 5MiB window.
 * If only the 7 Bit is set, it is a 4MiB window.  Otherwise, a
 * 64KiB window.
 *
 * The following applies to mcp55 only:
 * The 15 bits controlling the window size are distributed as follows: 
 * byte @0x88: bit 0..7
 * byte @0x8c: bit 8..15
 * word @0x90: bit 16..30
 * If all bits are enabled, we have a 16? MiB window
 * Please set win_size_bits to 0x7fffffff if you actually want to do something
 */
static uint win_size_bits = 0;
module_param(win_size_bits, uint, 0);
MODULE_PARM_DESC(win_size_bits, "ROM window size bits override, normally set by BIOS.");

static struct ck804xrom_window ck804xrom_window = {
	.maps = LIST_HEAD_INIT(ck804xrom_window.maps),
};

static void ck804xrom_cleanup(struct ck804xrom_window *window)
{
	struct ck804xrom_map_info *map, *scratch;
	u8 byte;

	if (window->pdev) {
		/* Disable writes through the rom window */
		pci_read_config_byte(window->pdev, 0x6d, &byte);
		pci_write_config_byte(window->pdev, 0x6d, byte & ~1);
	}

	/* Free all of the mtd devices */
	list_for_each_entry_safe(map, scratch, &window->maps, list) {
		if (map->rsrc.parent)
			release_resource(&map->rsrc);

		mtd_device_unregister(map->mtd);
		map_destroy(map->mtd);
		list_del(&map->list);
		kfree(map);
	}
	if (window->rsrc.parent)
		release_resource(&window->rsrc);

	if (window->virt) {
		iounmap(window->virt);
		window->virt = NULL;
		window->phys = 0;
		window->size = 0;
	}
	pci_dev_put(window->pdev);
}


static int __init ck804xrom_init_one(struct pci_dev *pdev,
				     const struct pci_device_id *ent)
{
	static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
	u8 byte;
	u16 word;
	struct ck804xrom_window *window = &ck804xrom_window;
	struct ck804xrom_map_info *map = NULL;
	unsigned long map_top;

	/* Remember the pci dev I find the window in */
	window->pdev = pci_dev_get(pdev);

	switch (ent->driver_data) {
	case DEV_CK804:
		/* Enable the selected rom window.  This is often incorrectly
		 * set up by the BIOS, and the 4MiB offset for the lock registers
		 * requires the full 5MiB of window space.
		 *
		 * This 'write, then read' approach leaves the bits for
		 * other uses of the hardware info.
		 */
		pci_read_config_byte(pdev, 0x88, &byte);
		pci_write_config_byte(pdev, 0x88, byte | win_size_bits );

		/* Assume the rom window is properly setup, and find it's size */
		pci_read_config_byte(pdev, 0x88, &byte);

		if ((byte & ((1<<7)|(1<<6))) == ((1<<7)|(1<<6)))
			window->phys = 0xffb00000; /* 5MiB */
		else if ((byte & (1<<7)) == (1<<7))
			window->phys = 0xffc00000; /* 4MiB */
		else
			window->phys = 0xffff0000; /* 64KiB */
		break;

	case DEV_MCP55:
		pci_read_config_byte(pdev, 0x88, &byte);
		pci_write_config_byte(pdev, 0x88, byte | (win_size_bits & 0xff));

		pci_read_config_byte(pdev, 0x8c, &byte);
		pci_write_config_byte(pdev, 0x8c, byte | ((win_size_bits & 0xff00) >> 8));

		pci_read_config_word(pdev, 0x90, &word);
		pci_write_config_word(pdev, 0x90, word | ((win_size_bits & 0x7fff0000) >> 16));

		window->phys = 0xff000000; /* 16MiB, hardcoded for now */
		break;
	}

	window->size = 0xffffffffUL - window->phys + 1UL;

	/*
	 * Try to reserve the window mem region.  If this fails then
	 * it is likely due to a fragment of the window being
	 * "reserved" by the BIOS.  In the case that the
	 * request_mem_region() fails then once the rom size is
	 * discovered we will try to reserve the unreserved fragment.
	 */
	window->rsrc.name = MOD_NAME;
	window->rsrc.start = window->phys;
	window->rsrc.end   = window->phys + window->size - 1;
	window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
	if (request_resource(&iomem_resource, &window->rsrc)) {
		window->rsrc.parent = NULL;
		printk(KERN_ERR MOD_NAME
		       " %s(): Unable to register resource %pR - kernel bug?\n",
			__func__, &window->rsrc);
	}


	/* Enable writes through the rom window */
	pci_read_config_byte(pdev, 0x6d, &byte);
	pci_write_config_byte(pdev, 0x6d, byte | 1);

	/* FIXME handle registers 0x80 - 0x8C the bios region locks */

	/* For write accesses caches are useless */
	window->virt = ioremap_nocache(window->phys, window->size);
	if (!window->virt) {
		printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
			window->phys, window->size);
		goto out;
	}

	/* Get the first address to look for a rom chip at */
	map_top = window->phys;
#if 1
	/* The probe sequence run over the firmware hub lock
	 * registers sets them to 0x7 (no access).
	 * Probe at most the last 4MiB of the address space.
	 */
	if (map_top < 0xffc00000)
		map_top = 0xffc00000;
#endif
	/* Loop  through and look for rom chips.  Since we don't know the
	 * starting address for each chip, probe every ROM_PROBE_STEP_SIZE
	 * bytes from the starting address of the window.
	 */
	while((map_top - 1) < 0xffffffffUL) {
		struct cfi_private *cfi;
		unsigned long offset;
		int i;

		if (!map)
			map = kmalloc(sizeof(*map), GFP_KERNEL);

		if (!map) {
			printk(KERN_ERR MOD_NAME ": kmalloc failed");
			goto out;
		}
		memset(map, 0, sizeof(*map));
		INIT_LIST_HEAD(&map->list);
		map->map.name = map->map_name;
		map->map.phys = map_top;
		offset = map_top - window->phys;
		map->map.virt = (void __iomem *)
			(((unsigned long)(window->virt)) + offset);
		map->map.size = 0xffffffffUL - map_top + 1UL;
		/* Set the name of the map to the address I am trying */
		sprintf(map->map_name, "%s @%08Lx",
			MOD_NAME, (unsigned long long)map->map.phys);

		/* There is no generic VPP support */
		for(map->map.bankwidth = 32; map->map.bankwidth;
			map->map.bankwidth >>= 1)
		{
			char **probe_type;
			/* Skip bankwidths that are not supported */
			if (!map_bankwidth_supported(map->map.bankwidth))
				continue;

			/* Setup the map methods */
			simple_map_init(&map->map);

			/* Try all of the probe methods */
			probe_type = rom_probe_types;
			for(; *probe_type; probe_type++) {
				map->mtd = do_map_probe(*probe_type, &map->map);
				if (map->mtd)
					goto found;
			}
		}
		map_top += ROM_PROBE_STEP_SIZE;
		continue;
	found:
		/* Trim the size if we are larger than the map */
		if (map->mtd->size > map->map.size) {
			printk(KERN_WARNING MOD_NAME
				" rom(%llu) larger than window(%lu). fixing...\n",
				(unsigned long long)map->mtd->size, map->map.size);
			map->mtd->size = map->map.size;
		}
		if (window->rsrc.parent) {
			/*
			 * Registering the MTD device in iomem may not be possible
			 * if there is a BIOS "reserved" and BUSY range.  If this
			 * fails then continue anyway.
			 */
			map->rsrc.name  = map->map_name;
			map->rsrc.start = map->map.phys;
			map->rsrc.end   = map->map.phys + map->mtd->size - 1;
			map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
			if (request_resource(&window->rsrc, &map->rsrc)) {
				printk(KERN_ERR MOD_NAME
					": cannot reserve MTD resource\n");
				map->rsrc.parent = NULL;
			}
		}

		/* Make the whole region visible in the map */
		map->map.virt = window->virt;
		map->map.phys = window->phys;
		cfi = map->map.fldrv_priv;
		for(i = 0; i < cfi->numchips; i++)
			cfi->chips[i].start += offset;

		/* Now that the mtd devices is complete claim and export it */
		map->mtd->owner = THIS_MODULE;
		if (mtd_device_register(map->mtd, NULL, 0)) {
			map_destroy(map->mtd);
			map->mtd = NULL;
			goto out;
		}


		/* Calculate the new value of map_top */
		map_top += map->mtd->size;

		/* File away the map structure */
		list_add(&map->list, &window->maps);
		map = NULL;
	}

 out:
	/* Free any left over map structures */
	kfree(map);

	/* See if I have any map structures */
	if (list_empty(&window->maps)) {
		ck804xrom_cleanup(window);
		return -ENODEV;
	}
	return 0;
}


static void ck804xrom_remove_one(struct pci_dev *pdev)
{
	struct ck804xrom_window *window = &ck804xrom_window;

	ck804xrom_cleanup(window);
}

static const struct pci_device_id ck804xrom_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0051), .driver_data = DEV_CK804 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0360), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0361), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0362), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0363), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0364), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0365), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0366), .driver_data = DEV_MCP55 },
	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0367), .driver_data = DEV_MCP55 },
	{ 0, }
};

#if 0
MODULE_DEVICE_TABLE(pci, ck804xrom_pci_tbl);

static struct pci_driver ck804xrom_driver = {
	.name =		MOD_NAME,
	.id_table =	ck804xrom_pci_tbl,
	.probe =	ck804xrom_init_one,
	.remove =	ck804xrom_remove_one,
};
#endif

static int __init init_ck804xrom(void)
{
	struct pci_dev *pdev;
	const struct pci_device_id *id;
	int retVal;
	pdev = NULL;

	for(id = ck804xrom_pci_tbl; id->vendor; id++) {
		pdev = pci_get_device(id->vendor, id->device, NULL);
		if (pdev)
			break;
	}
	if (pdev) {
		retVal = ck804xrom_init_one(pdev, id);
		pci_dev_put(pdev);
		return retVal;
	}
	return -ENXIO;
#if 0
	return pci_register_driver(&ck804xrom_driver);
#endif
}

static void __exit cleanup_ck804xrom(void)
{
	ck804xrom_remove_one(ck804xrom_window.pdev);
}

module_init(init_ck804xrom);
module_exit(cleanup_ck804xrom);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>, Dave Olsen <dolsen@lnxi.com>");
MODULE_DESCRIPTION("MTD map driver for BIOS chips on the Nvidia ck804 southbridge");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
90afffc8 DO	2	/*
	3	* ck804xrom.c
	4	*
	5	* Normal mappings of chips in physical memory
	6	*
	7	* Dave Olsen <dolsen@lnxi.com>
	8	* Ryan Jackson <rjackson@lnxi.com>
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/types.h>
90afffc8 DO	13	#include <linux/kernel.h>
90afffc8 DO	14	#include <linux/init.h>
5a0e3ad6	15	#include <linux/slab.h>
90afffc8 DO	16	#include <asm/io.h>
	17	#include <linux/mtd/mtd.h>
	18	#include <linux/mtd/map.h>
	19	#include <linux/mtd/cfi.h>
	20	#include <linux/mtd/flashchip.h>
	21	#include <linux/pci.h>
	22	#include <linux/pci_ids.h>
	23	#include <linux/list.h>
	24
	25
	26	#define MOD_NAME KBUILD_BASENAME
	27
	28	#define ADDRESS_NAME_LEN 18
	29
c9ac5977	30	#define ROM_PROBE_STEP_SIZE (64*1024)
90afffc8	31
c3f08b35 CDH	32	#define DEV_CK804 1
	33	#define DEV_MCP55 2
	34
90afffc8 DO	35	struct ck804xrom_window {
	36	void __iomem *virt;
	37	unsigned long phys;
	38	unsigned long size;
	39	struct list_head maps;
	40	struct resource rsrc;
	41	struct pci_dev *pdev;
	42	};
	43
	44	struct ck804xrom_map_info {
	45	struct list_head list;
	46	struct map_info map;
	47	struct mtd_info *mtd;
	48	struct resource rsrc;
	49	char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];
	50	};
	51
c3f08b35 CDH	52	/*
	53	* The following applies to ck804 only:
	54	* The 2 bits controlling the window size are often set to allow reading
90afffc8 DO	55	* the BIOS, but too small to allow writing, since the lock registers are
	56	* 4MiB lower in the address space than the data.
	57	*
	58	* This is intended to prevent flashing the bios, perhaps accidentally.
	59	*
	60	* This parameter allows the normal driver to override the BIOS settings.
	61	*
	62	* The bits are 6 and 7. If both bits are set, it is a 5MiB window.
	63	* If only the 7 Bit is set, it is a 4MiB window. Otherwise, a
	64	* 64KiB window.
	65	*
c3f08b35 CDH	66	* The following applies to mcp55 only:
	67	* The 15 bits controlling the window size are distributed as follows:
	68	* byte @0x88: bit 0..7
	69	* byte @0x8c: bit 8..15
	70	* word @0x90: bit 16..30
	71	* If all bits are enabled, we have a 16? MiB window
	72	* Please set win_size_bits to 0x7fffffff if you actually want to do something
90afffc8 DO	73	*/
	74	static uint win_size_bits = 0;
	75	module_param(win_size_bits, uint, 0);
c3f08b35	76	MODULE_PARM_DESC(win_size_bits, "ROM window size bits override, normally set by BIOS.");
90afffc8 DO	77
	78	static struct ck804xrom_window ck804xrom_window = {
	79	.maps = LIST_HEAD_INIT(ck804xrom_window.maps),
	80	};
	81
	82	static void ck804xrom_cleanup(struct ck804xrom_window *window)
	83	{
	84	struct ck804xrom_map_info map, scratch;
	85	u8 byte;
	86
	87	if (window->pdev) {
	88	/* Disable writes through the rom window */
	89	pci_read_config_byte(window->pdev, 0x6d, &byte);
	90	pci_write_config_byte(window->pdev, 0x6d, byte & ~1);
	91	}
	92
	93	/* Free all of the mtd devices */
	94	list_for_each_entry_safe(map, scratch, &window->maps, list) {
	95	if (map->rsrc.parent)
	96	release_resource(&map->rsrc);
	97
ee0e87b1	98	mtd_device_unregister(map->mtd);
90afffc8 DO	99	map_destroy(map->mtd);
	100	list_del(&map->list);
	101	kfree(map);
	102	}
	103	if (window->rsrc.parent)
	104	release_resource(&window->rsrc);
	105
	106	if (window->virt) {
	107	iounmap(window->virt);
	108	window->virt = NULL;
	109	window->phys = 0;
	110	window->size = 0;
	111	}
	112	pci_dev_put(window->pdev);
	113	}
	114
	115
e4106a7c JL	116	static int __init ck804xrom_init_one(struct pci_dev *pdev,
e4106a7c JL	117	const struct pci_device_id *ent)
90afffc8 DO	118	{
	119	static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };
	120	u8 byte;
c3f08b35	121	u16 word;
90afffc8 DO	122	struct ck804xrom_window *window = &ck804xrom_window;
	123	struct ck804xrom_map_info *map = NULL;
	124	unsigned long map_top;
	125
	126	/* Remember the pci dev I find the window in */
	127	window->pdev = pci_dev_get(pdev);
	128
c3f08b35 CDH	129	switch (ent->driver_data) {
	130	case DEV_CK804:
	131	/* Enable the selected rom window. This is often incorrectly
	132	* set up by the BIOS, and the 4MiB offset for the lock registers
	133	* requires the full 5MiB of window space.
	134	*
	135	* This 'write, then read' approach leaves the bits for
	136	* other uses of the hardware info.
	137	*/
	138	pci_read_config_byte(pdev, 0x88, &byte);
	139	pci_write_config_byte(pdev, 0x88, byte \| win_size_bits );
	140
	141	/* Assume the rom window is properly setup, and find it's size */
	142	pci_read_config_byte(pdev, 0x88, &byte);
	143
	144	if ((byte & ((1<<7)\|(1<<6))) == ((1<<7)\|(1<<6)))
	145	window->phys = 0xffb00000; /* 5MiB */
	146	else if ((byte & (1<<7)) == (1<<7))
	147	window->phys = 0xffc00000; /* 4MiB */
	148	else
	149	window->phys = 0xffff0000; /* 64KiB */
	150	break;
	151
	152	case DEV_MCP55:
	153	pci_read_config_byte(pdev, 0x88, &byte);
	154	pci_write_config_byte(pdev, 0x88, byte \| (win_size_bits & 0xff));
	155
	156	pci_read_config_byte(pdev, 0x8c, &byte);
	157	pci_write_config_byte(pdev, 0x8c, byte \| ((win_size_bits & 0xff00) >> 8));
	158
	159	pci_read_config_word(pdev, 0x90, &word);
	160	pci_write_config_word(pdev, 0x90, word \| ((win_size_bits & 0x7fff0000) >> 16));
	161
	162	window->phys = 0xff000000; /* 16MiB, hardcoded for now */
	163	break;
	164	}
90afffc8 DO	165
	166	window->size = 0xffffffffUL - window->phys + 1UL;
	167
	168	/*
	169	* Try to reserve the window mem region. If this fails then
	170	* it is likely due to a fragment of the window being
	171	* "reserved" by the BIOS. In the case that the
	172	* request_mem_region() fails then once the rom size is
	173	* discovered we will try to reserve the unreserved fragment.
	174	*/
	175	window->rsrc.name = MOD_NAME;
	176	window->rsrc.start = window->phys;
	177	window->rsrc.end = window->phys + window->size - 1;
	178	window->rsrc.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	179	if (request_resource(&iomem_resource, &window->rsrc)) {
	180	window->rsrc.parent = NULL;
	181	printk(KERN_ERR MOD_NAME
f9a5279c JP	182	" %s(): Unable to register resource %pR - kernel bug?\n",
f9a5279c JP	183	__func__, &window->rsrc);
90afffc8 DO	184	}
	185
	186
	187	/* Enable writes through the rom window */
	188	pci_read_config_byte(pdev, 0x6d, &byte);
	189	pci_write_config_byte(pdev, 0x6d, byte \| 1);
	190
	191	/* FIXME handle registers 0x80 - 0x8C the bios region locks */
	192
	193	/* For write accesses caches are useless */
	194	window->virt = ioremap_nocache(window->phys, window->size);
	195	if (!window->virt) {
	196	printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",
	197	window->phys, window->size);
	198	goto out;
	199	}
	200
	201	/* Get the first address to look for a rom chip at */
	202	map_top = window->phys;
	203	#if 1
	204	/* The probe sequence run over the firmware hub lock
	205	* registers sets them to 0x7 (no access).
	206	* Probe at most the last 4MiB of the address space.
	207	*/
	208	if (map_top < 0xffc00000)
	209	map_top = 0xffc00000;
	210	#endif
	211	/* Loop through and look for rom chips. Since we don't know the
	212	* starting address for each chip, probe every ROM_PROBE_STEP_SIZE
	213	* bytes from the starting address of the window.
	214	*/
	215	while((map_top - 1) < 0xffffffffUL) {
	216	struct cfi_private *cfi;
	217	unsigned long offset;
	218	int i;
	219
	220	if (!map)
	221	map = kmalloc(sizeof(*map), GFP_KERNEL);
	222
	223	if (!map) {
	224	printk(KERN_ERR MOD_NAME ": kmalloc failed");
	225	goto out;
	226	}
	227	memset(map, 0, sizeof(*map));
	228	INIT_LIST_HEAD(&map->list);
	229	map->map.name = map->map_name;
	230	map->map.phys = map_top;
	231	offset = map_top - window->phys;
	232	map->map.virt = (void __iomem *)
	233	(((unsigned long)(window->virt)) + offset);
	234	map->map.size = 0xffffffffUL - map_top + 1UL;
	235	/* Set the name of the map to the address I am trying */
65af0714 AM	236	sprintf(map->map_name, "%s @%08Lx",
65af0714 AM	237	MOD_NAME, (unsigned long long)map->map.phys);
90afffc8 DO	238
	239	/* There is no generic VPP support */
	240	for(map->map.bankwidth = 32; map->map.bankwidth;
	241	map->map.bankwidth >>= 1)
	242	{
	243	char **probe_type;
	244	/* Skip bankwidths that are not supported */
	245	if (!map_bankwidth_supported(map->map.bankwidth))
	246	continue;
	247
	248	/* Setup the map methods */
	249	simple_map_init(&map->map);
	250
	251	/* Try all of the probe methods */
	252	probe_type = rom_probe_types;
	253	for(; *probe_type; probe_type++) {
	254	map->mtd = do_map_probe(*probe_type, &map->map);
	255	if (map->mtd)
	256	goto found;
	257	}
	258	}
	259	map_top += ROM_PROBE_STEP_SIZE;
	260	continue;
	261	found:
	262	/* Trim the size if we are larger than the map */
	263	if (map->mtd->size > map->map.size) {
	264	printk(KERN_WARNING MOD_NAME
69423d99 AH	265	" rom(%llu) larger than window(%lu). fixing...\n",
69423d99 AH	266	(unsigned long long)map->mtd->size, map->map.size);
90afffc8 DO	267	map->mtd->size = map->map.size;
	268	}
	269	if (window->rsrc.parent) {
	270	/*
	271	* Registering the MTD device in iomem may not be possible
	272	* if there is a BIOS "reserved" and BUSY range. If this
	273	* fails then continue anyway.
	274	*/
	275	map->rsrc.name = map->map_name;
	276	map->rsrc.start = map->map.phys;
	277	map->rsrc.end = map->map.phys + map->mtd->size - 1;
	278	map->rsrc.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	279	if (request_resource(&window->rsrc, &map->rsrc)) {
	280	printk(KERN_ERR MOD_NAME
	281	": cannot reserve MTD resource\n");
	282	map->rsrc.parent = NULL;
	283	}
	284	}
	285
	286	/* Make the whole region visible in the map */
	287	map->map.virt = window->virt;
	288	map->map.phys = window->phys;
	289	cfi = map->map.fldrv_priv;
	290	for(i = 0; i < cfi->numchips; i++)
	291	cfi->chips[i].start += offset;
	292
	293	/* Now that the mtd devices is complete claim and export it */
	294	map->mtd->owner = THIS_MODULE;
ee0e87b1	295	if (mtd_device_register(map->mtd, NULL, 0)) {
90afffc8 DO	296	map_destroy(map->mtd);
	297	map->mtd = NULL;
	298	goto out;
	299	}
	300
	301
	302	/* Calculate the new value of map_top */
	303	map_top += map->mtd->size;
	304
	305	/* File away the map structure */
	306	list_add(&map->list, &window->maps);
	307	map = NULL;
	308	}
	309
	310	out:
	311	/* Free any left over map structures */
8be84e03	312	kfree(map);
90afffc8 DO	313
	314	/* See if I have any map structures */
	315	if (list_empty(&window->maps)) {
	316	ck804xrom_cleanup(window);
	317	return -ENODEV;
	318	}
	319	return 0;
	320	}
	321
	322
7bf350b7	323	static void ck804xrom_remove_one(struct pci_dev *pdev)
90afffc8 DO	324	{
	325	struct ck804xrom_window *window = &ck804xrom_window;
	326
	327	ck804xrom_cleanup(window);
	328	}
	329
13727344	330	static const struct pci_device_id ck804xrom_pci_tbl[] = {
edb2301f DW	331	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0051), .driver_data = DEV_CK804 },
	332	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0360), .driver_data = DEV_MCP55 },
	333	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0361), .driver_data = DEV_MCP55 },
	334	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0362), .driver_data = DEV_MCP55 },
	335	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0363), .driver_data = DEV_MCP55 },
	336	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0364), .driver_data = DEV_MCP55 },
	337	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0365), .driver_data = DEV_MCP55 },
	338	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0366), .driver_data = DEV_MCP55 },
	339	{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x0367), .driver_data = DEV_MCP55 },
90afffc8 DO	340	{ 0, }
	341	};
	342
b50be33e	343	#if 0
90afffc8 DO	344	MODULE_DEVICE_TABLE(pci, ck804xrom_pci_tbl);
90afffc8 DO	345
90afffc8 DO	346	static struct pci_driver ck804xrom_driver = {
	347	.name = MOD_NAME,
	348	.id_table = ck804xrom_pci_tbl,
	349	.probe = ck804xrom_init_one,
	350	.remove = ck804xrom_remove_one,
	351	};
	352	#endif
	353
	354	static int __init init_ck804xrom(void)
	355	{
	356	struct pci_dev *pdev;
13727344	357	const struct pci_device_id *id;
90afffc8 DO	358	int retVal;
	359	pdev = NULL;
	360
	361	for(id = ck804xrom_pci_tbl; id->vendor; id++) {
c033a7e3	362	pdev = pci_get_device(id->vendor, id->device, NULL);
90afffc8 DO	363	if (pdev)
	364	break;
	365	}
	366	if (pdev) {
c3f08b35	367	retVal = ck804xrom_init_one(pdev, id);
90afffc8 DO	368	pci_dev_put(pdev);
	369	return retVal;
	370	}
	371	return -ENXIO;
	372	#if 0
28b57cdd	373	return pci_register_driver(&ck804xrom_driver);
90afffc8 DO	374	#endif
	375	}
	376
	377	static void __exit cleanup_ck804xrom(void)
	378	{
	379	ck804xrom_remove_one(ck804xrom_window.pdev);
	380	}
	381
	382	module_init(init_ck804xrom);
	383	module_exit(cleanup_ck804xrom);
	384
	385	MODULE_LICENSE("GPL");
	386	MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>, Dave Olsen <dolsen@lnxi.com>");
	387	MODULE_DESCRIPTION("MTD map driver for BIOS chips on the Nvidia ck804 southbridge");
	388