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mtd: spear_smi: clear status register on init
[linux-2.6-block.git] / drivers / mtd / devices / spear_smi.c
CommitLineData
f18dbbb1
SH		 1/*
2 * SMI (Serial Memory Controller) device driver for Serial NOR Flash on
3 * SPEAr platform
4 * The serial nor interface is largely based on drivers/mtd/m25p80.c,
5 * however the SPI interface has been replaced by SMI.
6 *
7 * Copyright © 2010 STMicroelectronics.
8 * Ashish Priyadarshi
9 * Shiraz Hashim <shiraz.hashim@st.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/err.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/jiffies.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/param.h>
28#include <linux/platform_device.h>
770daa43 29#include <linux/pm.h>
f18dbbb1
SH		 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/spear_smi.h>
33#include <linux/mutex.h>
34#include <linux/sched.h>
35#include <linux/slab.h>
36#include <linux/wait.h>
6551ab5d
SR		 37#include <linux/of.h>
38#include <linux/of_address.h>
f18dbbb1
SH		 39
40/* SMI clock rate */
41#define SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */
42
43/* MAX time out to safely come out of a erase or write busy conditions */
44#define SMI_PROBE_TIMEOUT (HZ / 10)
45#define SMI_MAX_TIME_OUT (3 * HZ)
46
47/* timeout for command completion */
48#define SMI_CMD_TIMEOUT (HZ / 10)
49
50/* registers of smi */
51#define SMI_CR1 0x0 /* SMI control register 1 */
52#define SMI_CR2 0x4 /* SMI control register 2 */
53#define SMI_SR 0x8 /* SMI status register */
54#define SMI_TR 0xC /* SMI transmit register */
55#define SMI_RR 0x10 /* SMI receive register */
56
57/* defines for control_reg 1 */
58#define BANK_EN (0xF << 0) /* enables all banks */
59#define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */
60#define SW_MODE (0x1 << 28) /* enables SW Mode */
61#define WB_MODE (0x1 << 29) /* Write Burst Mode */
62#define FAST_MODE (0x1 << 15) /* Fast Mode */
63#define HOLD1 (0x1 << 16) /* Clock Hold period selection */
64
65/* defines for control_reg 2 */
66#define SEND (0x1 << 7) /* Send data */
67#define TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */
68#define WCIE (0x1 << 9) /* Write Complete Interrupt Enable */
69#define RD_STATUS_REG (0x1 << 10) /* reads status reg */
70#define WE (0x1 << 11) /* Write Enable */
71
72#define TX_LEN_SHIFT 0
73#define RX_LEN_SHIFT 4
74#define BANK_SHIFT 12
75
76/* defines for status register */
77#define SR_WIP 0x1 /* Write in progress */
78#define SR_WEL 0x2 /* Write enable latch */
79#define SR_BP0 0x4 /* Block protect 0 */
80#define SR_BP1 0x8 /* Block protect 1 */
81#define SR_BP2 0x10 /* Block protect 2 */
82#define SR_SRWD 0x80 /* SR write protect */
83#define TFF 0x100 /* Transfer Finished Flag */
84#define WCF 0x200 /* Transfer Finished Flag */
85#define ERF1 0x400 /* Forbidden Write Request */
86#define ERF2 0x800 /* Forbidden Access */
87
88#define WM_SHIFT 12
89
90/* flash opcodes */
91#define OPCODE_RDID 0x9f /* Read JEDEC ID */
92
93/* Flash Device Ids maintenance section */
94
95/* data structure to maintain flash ids from different vendors */
96struct flash_device {
97 char *name;
98 u8 erase_cmd;
99 u32 device_id;
100 u32 pagesize;
101 unsigned long sectorsize;
102 unsigned long size_in_bytes;
103};
104
105#define FLASH_ID(n, es, id, psize, ssize, size) \
106{ \
107 .name = n, \
108 .erase_cmd = es, \
109 .device_id = id, \
110 .pagesize = psize, \
111 .sectorsize = ssize, \
112 .size_in_bytes = size \
113}
114
115static struct flash_device flash_devices[] = {
116 FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
117 FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
118 FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
119 FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
120 FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000),
121 FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000),
122 FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
123 FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
124 FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
125 FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
126 FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
127 FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
128 FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
129 FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
130 FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
131 FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
132 FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
133 FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
134 FLASH_ID("atmel 25f512" , 0x52, 0x0065001F, 0x80 , 0x8000 , 0x10000),
135 FLASH_ID("atmel 25f1024" , 0x52, 0x0060001F, 0x100, 0x8000 , 0x20000),
136 FLASH_ID("atmel 25f2048" , 0x52, 0x0063001F, 0x100, 0x10000, 0x40000),
137 FLASH_ID("atmel 25f4096" , 0x52, 0x0064001F, 0x100, 0x10000, 0x80000),
138 FLASH_ID("atmel 25fs040" , 0xd7, 0x0004661F, 0x100, 0x10000, 0x80000),
139 FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000),
140 FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000),
141 FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000),
142 FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
143 FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000),
144 FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000),
145 FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000),
146 FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000),
147 FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
148 FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000),
149 FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000),
150};
151
f18dbbb1
SH		 152/* Define spear specific structures */
153
154struct spear_snor_flash;
155
156/**
157 * struct spear_smi - Structure for SMI Device
158 *
159 * @clk: functional clock
160 * @status: current status register of SMI.
161 * @clk_rate: functional clock rate of SMI (default: SMI_MAX_CLOCK_FREQ)
162 * @lock: lock to prevent parallel access of SMI.
163 * @io_base: base address for registers of SMI.
164 * @pdev: platform device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
166 * @num_flashes: number of flashes actually present on board.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
168 */
169struct spear_smi {
170 struct clk *clk;
171 u32 status;
172 unsigned long clk_rate;
173 struct mutex lock;
174 void __iomem *io_base;
175 struct platform_device *pdev;
176 wait_queue_head_t cmd_complete;
177 u32 num_flashes;
178 struct spear_snor_flash *flash[MAX_NUM_FLASH_CHIP];
179};
180
181/**
182 * struct spear_snor_flash - Structure for Serial NOR Flash
183 *
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
186 * @lock: lock to manage flash read, write and erase operations
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
190 * @page_size: Page size of NOR-flash.
191 * @base_addr: Base address of NOR-flash.
192 * @erase_cmd: erase command may vary on different flash types
193 * @fast_mode: flash supports read in fast mode
194 */
195struct spear_snor_flash {
196 u32 bank;
197 u32 dev_id;
198 struct mutex lock;
199 struct mtd_info mtd;
200 u32 num_parts;
201 struct mtd_partition *parts;
202 u32 page_size;
203 void __iomem *base_addr;
204 u8 erase_cmd;
205 u8 fast_mode;
206};
207
208static inline struct spear_snor_flash *get_flash_data(struct mtd_info *mtd)
209{
210 return container_of(mtd, struct spear_snor_flash, mtd);
211}
212
213/**
214 * spear_smi_read_sr - Read status register of flash through SMI
215 * @dev: structure of SMI information.
216 * @bank: bank to which flash is connected
217 *
218 * This routine will return the status register of the flash chip present at the
219 * given bank.
220 */
221static int spear_smi_read_sr(struct spear_smi *dev, u32 bank)
222{
223 int ret;
224 u32 ctrlreg1;
225
226 mutex_lock(&dev->lock);
227 dev->status = 0; /* Will be set in interrupt handler */
228
229 ctrlreg1 = readl(dev->io_base + SMI_CR1);
230 /* program smi in hw mode */
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);
232
233 /* performing a rsr instruction in hw mode */
234 writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,
235 dev->io_base + SMI_CR2);
236
237 /* wait for tff */
238 ret = wait_event_interruptible_timeout(dev->cmd_complete,
239 dev->status & TFF, SMI_CMD_TIMEOUT);
240
241 /* copy dev->status (lower 16 bits) in order to release lock */
242 if (ret > 0)
243 ret = dev->status & 0xffff;
244 else
245 ret = -EIO;
246
247 /* restore the ctrl regs state */
248 writel(ctrlreg1, dev->io_base + SMI_CR1);
249 writel(0, dev->io_base + SMI_CR2);
250 mutex_unlock(&dev->lock);
251
252 return ret;
253}
254
255/**
256 * spear_smi_wait_till_ready - wait till flash is ready
257 * @dev: structure of SMI information.
258 * @bank: flash corresponding to this bank
259 * @timeout: timeout for busy wait condition
260 *
261 * This routine checks for WIP (write in progress) bit in Status register
262 * If successful the routine returns 0 else -EBUSY
263 */
264static int spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank,
265 unsigned long timeout)
266{
267 unsigned long finish;
268 int status;
269
270 finish = jiffies + timeout;
271 do {
272 status = spear_smi_read_sr(dev, bank);
273 if (status < 0)
274 continue; /* try till timeout */
275 else if (!(status & SR_WIP))
276 return 0;
277
278 cond_resched();
279 } while (!time_after_eq(jiffies, finish));
280
281 dev_err(&dev->pdev->dev, "smi controller is busy, timeout\n");
282 return status;
283}
284
285/**
286 * spear_smi_int_handler - SMI Interrupt Handler.
287 * @irq: irq number
288 * @dev_id: structure of SMI device, embedded in dev_id.
289 *
290 * The handler clears all interrupt conditions and records the status in
291 * dev->status which is used by the driver later.
292 */
293static irqreturn_t spear_smi_int_handler(int irq, void *dev_id)
294{
295 u32 status = 0;
296 struct spear_smi *dev = dev_id;
297
298 status = readl(dev->io_base + SMI_SR);
299
300 if (unlikely(!status))
301 return IRQ_NONE;
302
303 /* clear all interrupt conditions */
304 writel(0, dev->io_base + SMI_SR);
305
306 /* copy the status register in dev->status */
307 dev->status |= status;
308
309 /* send the completion */
310 wake_up_interruptible(&dev->cmd_complete);
311
312 return IRQ_HANDLED;
313}
314
315/**
316 * spear_smi_hw_init - initializes the smi controller.
317 * @dev: structure of smi device
318 *
319 * this routine initializes the smi controller wit the default values
320 */
321static void spear_smi_hw_init(struct spear_smi *dev)
322{
323 unsigned long rate = 0;
324 u32 prescale = 0;
325 u32 val;
326
327 rate = clk_get_rate(dev->clk);
328
329 /* functional clock of smi */
330 prescale = DIV_ROUND_UP(rate, dev->clk_rate);
331
332 /*
333 * setting the standard values, fast mode, prescaler for
334 * SMI_MAX_CLOCK_FREQ (50MHz) operation and bank enable
335 */
336 val = HOLD1 | BANK_EN | DSEL_TIME | (prescale << 8);
337
338 mutex_lock(&dev->lock);
4dc48c37
SH		 339 /* clear all interrupt conditions */
340 writel(0, dev->io_base + SMI_SR);
341
f18dbbb1
SH		 342 writel(val, dev->io_base + SMI_CR1);
343 mutex_unlock(&dev->lock);
344}
345
346/**
347 * get_flash_index - match chip id from a flash list.
348 * @flash_id: a valid nor flash chip id obtained from board.
349 *
350 * try to validate the chip id by matching from a list, if not found then simply
351 * returns negative. In case of success returns index in to the flash devices
352 * array.
353 */
354static int get_flash_index(u32 flash_id)
355{
356 int index;
357
358 /* Matches chip-id to entire list of 'serial-nor flash' ids */
359 for (index = 0; index < ARRAY_SIZE(flash_devices); index++) {
360 if (flash_devices[index].device_id == flash_id)
361 return index;
362 }
363
364 /* Memory chip is not listed and not supported */
365 return -ENODEV;
366}
367
368/**
369 * spear_smi_write_enable - Enable the flash to do write operation
370 * @dev: structure of SMI device
371 * @bank: enable write for flash connected to this bank
372 *
373 * Set write enable latch with Write Enable command.
374 * Returns 0 on success.
375 */
376static int spear_smi_write_enable(struct spear_smi *dev, u32 bank)
377{
378 int ret;
379 u32 ctrlreg1;
380
381 mutex_lock(&dev->lock);
382 dev->status = 0; /* Will be set in interrupt handler */
383
384 ctrlreg1 = readl(dev->io_base + SMI_CR1);
385 /* program smi in h/w mode */
386 writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);
387
388 /* give the flash, write enable command */
389 writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);
390
391 ret = wait_event_interruptible_timeout(dev->cmd_complete,
392 dev->status & TFF, SMI_CMD_TIMEOUT);
393
394 /* restore the ctrl regs state */
395 writel(ctrlreg1, dev->io_base + SMI_CR1);
396 writel(0, dev->io_base + SMI_CR2);
397
398 if (ret <= 0) {
399 ret = -EIO;
400 dev_err(&dev->pdev->dev,
401 "smi controller failed on write enable\n");
402 } else {
403 /* check whether write mode status is set for required bank */
404 if (dev->status & (1 << (bank + WM_SHIFT)))
405 ret = 0;
406 else {
407 dev_err(&dev->pdev->dev, "couldn't enable write\n");
408 ret = -EIO;
409 }
410 }
411
412 mutex_unlock(&dev->lock);
413 return ret;
414}
415
416static inline u32
417get_sector_erase_cmd(struct spear_snor_flash *flash, u32 offset)
418{
419 u32 cmd;
420 u8 *x = (u8 *)&cmd;
421
422 x[0] = flash->erase_cmd;
423 x[1] = offset >> 16;
424 x[2] = offset >> 8;
425 x[3] = offset;
426
427 return cmd;
428}
429
430/**
431 * spear_smi_erase_sector - erase one sector of flash
432 * @dev: structure of SMI information
433 * @command: erase command to be send
434 * @bank: bank to which this command needs to be send
435 * @bytes: size of command
436 *
437 * Erase one sector of flash memory at offset ``offset'' which is any
438 * address within the sector which should be erased.
439 * Returns 0 if successful, non-zero otherwise.
440 */
441static int spear_smi_erase_sector(struct spear_smi *dev,
442 u32 bank, u32 command, u32 bytes)
443{
444 u32 ctrlreg1 = 0;
445 int ret;
446
447 ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
448 if (ret)
449 return ret;
450
451 ret = spear_smi_write_enable(dev, bank);
452 if (ret)
453 return ret;
454
455 mutex_lock(&dev->lock);
456
457 ctrlreg1 = readl(dev->io_base + SMI_CR1);
458 writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);
459
460 /* send command in sw mode */
461 writel(command, dev->io_base + SMI_TR);
462
463 writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),
464 dev->io_base + SMI_CR2);
465
466 ret = wait_event_interruptible_timeout(dev->cmd_complete,
467 dev->status & TFF, SMI_CMD_TIMEOUT);
468
469 if (ret <= 0) {
470 ret = -EIO;
471 dev_err(&dev->pdev->dev, "sector erase failed\n");
472 } else
473 ret = 0; /* success */
474
475 /* restore ctrl regs */
476 writel(ctrlreg1, dev->io_base + SMI_CR1);
477 writel(0, dev->io_base + SMI_CR2);
478
479 mutex_unlock(&dev->lock);
480 return ret;
481}
482
483/**
484 * spear_mtd_erase - perform flash erase operation as requested by user
485 * @mtd: Provides the memory characteristics
486 * @e_info: Provides the erase information
487 *
488 * Erase an address range on the flash chip. The address range may extend
489 * one or more erase sectors. Return an error is there is a problem erasing.
490 */
491static int spear_mtd_erase(struct mtd_info *mtd, struct erase_info *e_info)
492{
493 struct spear_snor_flash *flash = get_flash_data(mtd);
494 struct spear_smi *dev = mtd->priv;
495 u32 addr, command, bank;
496 int len, ret;
497
498 if (!flash || !dev)
499 return -ENODEV;
500
f18dbbb1
SH		 501 bank = flash->bank;
502 if (bank > dev->num_flashes - 1) {
503 dev_err(&dev->pdev->dev, "Invalid Bank Num");
504 return -EINVAL;
505 }
506
507 addr = e_info->addr;
508 len = e_info->len;
509
510 mutex_lock(&flash->lock);
511
512 /* now erase sectors in loop */
513 while (len) {
514 command = get_sector_erase_cmd(flash, addr);
515 /* preparing the command for flash */
516 ret = spear_smi_erase_sector(dev, bank, command, 4);
517 if (ret) {
518 e_info->state = MTD_ERASE_FAILED;
519 mutex_unlock(&flash->lock);
520 return ret;
521 }
522 addr += mtd->erasesize;
523 len -= mtd->erasesize;
524 }
525
526 mutex_unlock(&flash->lock);
527 e_info->state = MTD_ERASE_DONE;
528 mtd_erase_callback(e_info);
529
530 return 0;
531}
532
533/**
534 * spear_mtd_read - performs flash read operation as requested by the user
535 * @mtd: MTD information of the memory bank
536 * @from: Address from which to start read
537 * @len: Number of bytes to be read
538 * @retlen: Fills the Number of bytes actually read
539 * @buf: Fills this after reading
540 *
541 * Read an address range from the flash chip. The address range
542 * may be any size provided it is within the physical boundaries.
543 * Returns 0 on success, non zero otherwise
544 */
545static int spear_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
546 size_t *retlen, u8 *buf)
547{
548 struct spear_snor_flash *flash = get_flash_data(mtd);
549 struct spear_smi *dev = mtd->priv;
550 void *src;
551 u32 ctrlreg1, val;
552 int ret;
553
f18dbbb1
SH		 554 if (!flash || !dev)
555 return -ENODEV;
556
f18dbbb1
SH		 557 if (flash->bank > dev->num_flashes - 1) {
558 dev_err(&dev->pdev->dev, "Invalid Bank Num");
559 return -EINVAL;
560 }
561
f18dbbb1
SH		 562 /* select address as per bank number */
563 src = flash->base_addr + from;
564
565 mutex_lock(&flash->lock);
566
567 /* wait till previous write/erase is done. */
568 ret = spear_smi_wait_till_ready(dev, flash->bank, SMI_MAX_TIME_OUT);
569 if (ret) {
570 mutex_unlock(&flash->lock);
571 return ret;
572 }
573
574 mutex_lock(&dev->lock);
575 /* put smi in hw mode not wbt mode */
576 ctrlreg1 = val = readl(dev->io_base + SMI_CR1);
577 val &= ~(SW_MODE | WB_MODE);
578 if (flash->fast_mode)
579 val |= FAST_MODE;
580
581 writel(val, dev->io_base + SMI_CR1);
582
583 memcpy_fromio(buf, (u8 *)src, len);
584
585 /* restore ctrl reg1 */
586 writel(ctrlreg1, dev->io_base + SMI_CR1);
587 mutex_unlock(&dev->lock);
588
589 *retlen = len;
590 mutex_unlock(&flash->lock);
591
592 return 0;
593}
594
595static inline int spear_smi_cpy_toio(struct spear_smi *dev, u32 bank,
596 void *dest, const void *src, size_t len)
597{
598 int ret;
599 u32 ctrlreg1;
600
601 /* wait until finished previous write command. */
602 ret = spear_smi_wait_till_ready(dev, bank, SMI_MAX_TIME_OUT);
603 if (ret)
604 return ret;
605
606 /* put smi in write enable */
607 ret = spear_smi_write_enable(dev, bank);
608 if (ret)
609 return ret;
610
611 /* put smi in hw, write burst mode */
612 mutex_lock(&dev->lock);
613
614 ctrlreg1 = readl(dev->io_base + SMI_CR1);
615 writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
616
617 memcpy_toio(dest, src, len);
618
619 writel(ctrlreg1, dev->io_base + SMI_CR1);
620
621 mutex_unlock(&dev->lock);
622 return 0;
623}
624
625/**
626 * spear_mtd_write - performs write operation as requested by the user.
627 * @mtd: MTD information of the memory bank.
628 * @to: Address to write.
629 * @len: Number of bytes to be written.
630 * @retlen: Number of bytes actually wrote.
631 * @buf: Buffer from which the data to be taken.
632 *
633 * Write an address range to the flash chip. Data must be written in
634 * flash_page_size chunks. The address range may be any size provided
635 * it is within the physical boundaries.
636 * Returns 0 on success, non zero otherwise
637 */
638static int spear_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
639 size_t *retlen, const u8 *buf)
640{
641 struct spear_snor_flash *flash = get_flash_data(mtd);
642 struct spear_smi *dev = mtd->priv;
643 void *dest;
644 u32 page_offset, page_size;
645 int ret;
646
647 if (!flash || !dev)
648 return -ENODEV;
649
f18dbbb1
SH		 650 if (flash->bank > dev->num_flashes - 1) {
651 dev_err(&dev->pdev->dev, "Invalid Bank Num");
652 return -EINVAL;
653 }
654
f18dbbb1
SH		 655 /* select address as per bank number */
656 dest = flash->base_addr + to;
657 mutex_lock(&flash->lock);
658
659 page_offset = (u32)to % flash->page_size;
660
661 /* do if all the bytes fit onto one page */
662 if (page_offset + len <= flash->page_size) {
663 ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf, len);
664 if (!ret)
665 *retlen += len;
666 } else {
667 u32 i;
668
669 /* the size of data remaining on the first page */
670 page_size = flash->page_size - page_offset;
671
672 ret = spear_smi_cpy_toio(dev, flash->bank, dest, buf,
673 page_size);
674 if (ret)
675 goto err_write;
676 else
677 *retlen += page_size;
678
679 /* write everything in pagesize chunks */
680 for (i = page_size; i < len; i += page_size) {
681 page_size = len - i;
682 if (page_size > flash->page_size)
683 page_size = flash->page_size;
684
685 ret = spear_smi_cpy_toio(dev, flash->bank, dest + i,
686 buf + i, page_size);
687 if (ret)
688 break;
689 else
690 *retlen += page_size;
691 }
692 }
693
694err_write:
695 mutex_unlock(&flash->lock);
696
697 return ret;
698}
699
700/**
701 * spear_smi_probe_flash - Detects the NOR Flash chip.
702 * @dev: structure of SMI information.
703 * @bank: bank on which flash must be probed
704 *
705 * This routine will check whether there exists a flash chip on a given memory
706 * bank ID.
707 * Return index of the probed flash in flash devices structure
708 */
709static int spear_smi_probe_flash(struct spear_smi *dev, u32 bank)
710{
711 int ret;
712 u32 val = 0;
713
714 ret = spear_smi_wait_till_ready(dev, bank, SMI_PROBE_TIMEOUT);
715 if (ret)
716 return ret;
717
718 mutex_lock(&dev->lock);
719
720 dev->status = 0; /* Will be set in interrupt handler */
721 /* put smi in sw mode */
722 val = readl(dev->io_base + SMI_CR1);
723 writel(val | SW_MODE, dev->io_base + SMI_CR1);
724
725 /* send readid command in sw mode */
726 writel(OPCODE_RDID, dev->io_base + SMI_TR);
727
728 val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) |
729 (3 << RX_LEN_SHIFT) | TFIE;
730 writel(val, dev->io_base + SMI_CR2);
731
732 /* wait for TFF */
733 ret = wait_event_interruptible_timeout(dev->cmd_complete,
734 dev->status & TFF, SMI_CMD_TIMEOUT);
735 if (ret <= 0) {
736 ret = -ENODEV;
737 goto err_probe;
738 }
739
740 /* get memory chip id */
741 val = readl(dev->io_base + SMI_RR);
742 val &= 0x00ffffff;
743 ret = get_flash_index(val);
744
745err_probe:
746 /* clear sw mode */
747 val = readl(dev->io_base + SMI_CR1);
748 writel(val & ~SW_MODE, dev->io_base + SMI_CR1);
749
750 mutex_unlock(&dev->lock);
751 return ret;
752}
753
6551ab5d
SR		 754
755#ifdef CONFIG_OF
756static int __devinit spear_smi_probe_config_dt(struct platform_device *pdev,
757 struct device_node *np)
758{
759 struct spear_smi_plat_data *pdata = dev_get_platdata(&pdev->dev);
760 struct device_node *pp = NULL;
761 const __be32 *addr;
762 u32 val;
763 int len;
764 int i = 0;
765
766 if (!np)
767 return -ENODEV;
768
769 of_property_read_u32(np, "clock-rate", &val);
770 pdata->clk_rate = val;
771
772 pdata->board_flash_info = devm_kzalloc(&pdev->dev,
773 sizeof(*pdata->board_flash_info),
774 GFP_KERNEL);
775
776 /* Fill structs for each subnode (flash device) */
777 while ((pp = of_get_next_child(np, pp))) {
778 struct spear_smi_flash_info *flash_info;
779
780 flash_info = &pdata->board_flash_info[i];
781 pdata->np[i] = pp;
782
783 /* Read base-addr and size from DT */
784 addr = of_get_property(pp, "reg", &len);
785 pdata->board_flash_info->mem_base = be32_to_cpup(&addr[0]);
786 pdata->board_flash_info->size = be32_to_cpup(&addr[1]);
787
788 if (of_get_property(pp, "st,smi-fast-mode", NULL))
789 pdata->board_flash_info->fast_mode = 1;
790
791 i++;
792 }
793
794 pdata->num_flashes = i;
795
796 return 0;
797}
798#else
799static int __devinit spear_smi_probe_config_dt(struct platform_device *pdev,
800 struct device_node *np)
801{
802 return -ENOSYS;
803}
804#endif
805
806static int spear_smi_setup_banks(struct platform_device *pdev,
807 u32 bank, struct device_node *np)
f18dbbb1
SH		 808{
809 struct spear_smi *dev = platform_get_drvdata(pdev);
6551ab5d 810 struct mtd_part_parser_data ppdata = {};
f18dbbb1
SH		 811 struct spear_smi_flash_info *flash_info;
812 struct spear_smi_plat_data *pdata;
813 struct spear_snor_flash *flash;
f7e3dd8f
SR		 814 struct mtd_partition *parts = NULL;
815 int count = 0;
f18dbbb1
SH		 816 int flash_index;
817 int ret = 0;
818
819 pdata = dev_get_platdata(&pdev->dev);
820 if (bank > pdata->num_flashes - 1)
821 return -EINVAL;
822
823 flash_info = &pdata->board_flash_info[bank];
824 if (!flash_info)
825 return -ENODEV;
826
827 flash = kzalloc(sizeof(*flash), GFP_ATOMIC);
828 if (!flash)
829 return -ENOMEM;
830 flash->bank = bank;
831 flash->fast_mode = flash_info->fast_mode ? 1 : 0;
832 mutex_init(&flash->lock);
833
834 /* verify whether nor flash is really present on board */
835 flash_index = spear_smi_probe_flash(dev, bank);
836 if (flash_index < 0) {
837 dev_info(&dev->pdev->dev, "smi-nor%d not found\n", bank);
838 ret = flash_index;
839 goto err_probe;
840 }
841 /* map the memory for nor flash chip */
842 flash->base_addr = ioremap(flash_info->mem_base, flash_info->size);
843 if (!flash->base_addr) {
844 ret = -EIO;
845 goto err_probe;
846 }
847
848 dev->flash[bank] = flash;
849 flash->mtd.priv = dev;
850
851 if (flash_info->name)
852 flash->mtd.name = flash_info->name;
853 else
854 flash->mtd.name = flash_devices[flash_index].name;
855
856 flash->mtd.type = MTD_NORFLASH;
857 flash->mtd.writesize = 1;
858 flash->mtd.flags = MTD_CAP_NORFLASH;
859 flash->mtd.size = flash_info->size;
860 flash->mtd.erasesize = flash_devices[flash_index].sectorsize;
861 flash->page_size = flash_devices[flash_index].pagesize;
81fefdf2 862 flash->mtd.writebufsize = flash->page_size;
f18dbbb1 863 flash->erase_cmd = flash_devices[flash_index].erase_cmd;
3c3c10bb
AB		 864 flash->mtd._erase = spear_mtd_erase;
865 flash->mtd._read = spear_mtd_read;
866 flash->mtd._write = spear_mtd_write;
f18dbbb1
SH		 867 flash->dev_id = flash_devices[flash_index].device_id;
868
869 dev_info(&dev->pdev->dev, "mtd .name=%s .size=%llx(%lluM)\n",
870 flash->mtd.name, flash->mtd.size,
871 flash->mtd.size / (1024 * 1024));
872
873 dev_info(&dev->pdev->dev, ".erasesize = 0x%x(%uK)\n",
874 flash->mtd.erasesize, flash->mtd.erasesize / 1024);
875
6551ab5d 876#ifndef CONFIG_OF
f18dbbb1
SH		 877 if (flash_info->partitions) {
878 parts = flash_info->partitions;
879 count = flash_info->nr_partitions;
f18dbbb1 880 }
6551ab5d
SR		 881#endif
882 ppdata.of_node = np;
883
884 ret = mtd_device_parse_register(&flash->mtd, NULL, &ppdata, parts,
885 count);
f7e3dd8f 886 if (ret) {
f18dbbb1 887 dev_err(&dev->pdev->dev, "Err MTD partition=%d\n", ret);
f7e3dd8f
SR		 888 goto err_map;
889 }
f18dbbb1 890
f7e3dd8f 891 return 0;
f18dbbb1
SH		 892
893err_map:
894 iounmap(flash->base_addr);
895
896err_probe:
897 kfree(flash);
898 return ret;
899}
900
901/**
902 * spear_smi_probe - Entry routine
903 * @pdev: platform device structure
904 *
905 * This is the first routine which gets invoked during booting and does all
906 * initialization/allocation work. The routine looks for available memory banks,
907 * and do proper init for any found one.
908 * Returns 0 on success, non zero otherwise
909 */
910static int __devinit spear_smi_probe(struct platform_device *pdev)
911{
6551ab5d
SR		 912 struct device_node *np = pdev->dev.of_node;
913 struct spear_smi_plat_data *pdata = NULL;
f18dbbb1
SH		 914 struct spear_smi *dev;
915 struct resource *smi_base;
916 int irq, ret = 0;
917 int i;
918
6551ab5d
SR		 919 if (np) {
920 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
921 if (!pdata) {
922 pr_err("%s: ERROR: no memory", __func__);
923 ret = -ENOMEM;
924 goto err;
925 }
926 pdev->dev.platform_data = pdata;
927 ret = spear_smi_probe_config_dt(pdev, np);
928 if (ret) {
929 ret = -ENODEV;
930 dev_err(&pdev->dev, "no platform data\n");
931 goto err;
932 }
933 } else {
934 pdata = dev_get_platdata(&pdev->dev);
935 if (pdata < 0) {
936 ret = -ENODEV;
937 dev_err(&pdev->dev, "no platform data\n");
938 goto err;
939 }
f18dbbb1
SH		 940 }
941
942 smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
943 if (!smi_base) {
944 ret = -ENODEV;
945 dev_err(&pdev->dev, "invalid smi base address\n");
946 goto err;
947 }
948
949 irq = platform_get_irq(pdev, 0);
950 if (irq < 0) {
951 ret = -ENODEV;
952 dev_err(&pdev->dev, "invalid smi irq\n");
953 goto err;
954 }
955
956 dev = kzalloc(sizeof(*dev), GFP_ATOMIC);
957 if (!dev) {
958 ret = -ENOMEM;
959 dev_err(&pdev->dev, "mem alloc fail\n");
960 goto err;
961 }
962
963 smi_base = request_mem_region(smi_base->start, resource_size(smi_base),
964 pdev->name);
965 if (!smi_base) {
966 ret = -EBUSY;
967 dev_err(&pdev->dev, "request mem region fail\n");
968 goto err_mem;
969 }
970
971 dev->io_base = ioremap(smi_base->start, resource_size(smi_base));
972 if (!dev->io_base) {
973 ret = -EIO;
974 dev_err(&pdev->dev, "ioremap fail\n");
975 goto err_ioremap;
976 }
977
978 dev->pdev = pdev;
979 dev->clk_rate = pdata->clk_rate;
980
981 if (dev->clk_rate < 0 || dev->clk_rate > SMI_MAX_CLOCK_FREQ)
982 dev->clk_rate = SMI_MAX_CLOCK_FREQ;
983
984 dev->num_flashes = pdata->num_flashes;
985
986 if (dev->num_flashes > MAX_NUM_FLASH_CHIP) {
987 dev_err(&pdev->dev, "exceeding max number of flashes\n");
988 dev->num_flashes = MAX_NUM_FLASH_CHIP;
989 }
990
991 dev->clk = clk_get(&pdev->dev, NULL);
992 if (IS_ERR(dev->clk)) {
993 ret = PTR_ERR(dev->clk);
994 goto err_clk;
995 }
996
c0010eb5 997 ret = clk_prepare_enable(dev->clk);
f18dbbb1 998 if (ret)
c0010eb5 999 goto err_clk_prepare_enable;
f18dbbb1
SH		 1000
1001 ret = request_irq(irq, spear_smi_int_handler, 0, pdev->name, dev);
1002 if (ret) {
1003 dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n");
1004 goto err_irq;
1005 }
1006
1007 mutex_init(&dev->lock);
1008 init_waitqueue_head(&dev->cmd_complete);
1009 spear_smi_hw_init(dev);
1010 platform_set_drvdata(pdev, dev);
1011
1012 /* loop for each serial nor-flash which is connected to smi */
1013 for (i = 0; i < dev->num_flashes; i++) {
6551ab5d 1014 ret = spear_smi_setup_banks(pdev, i, pdata->np[i]);
f18dbbb1
SH		 1015 if (ret) {
1016 dev_err(&dev->pdev->dev, "bank setup failed\n");
1017 goto err_bank_setup;
1018 }
1019 }
1020
1021 return 0;
1022
1023err_bank_setup:
1024 free_irq(irq, dev);
1025 platform_set_drvdata(pdev, NULL);
1026err_irq:
c0010eb5
VK		 1027 clk_disable_unprepare(dev->clk);
1028err_clk_prepare_enable:
f18dbbb1
SH		 1029 clk_put(dev->clk);
1030err_clk:
1031 iounmap(dev->io_base);
1032err_ioremap:
1033 release_mem_region(smi_base->start, resource_size(smi_base));
1034err_mem:
1035 kfree(dev);
1036err:
1037 return ret;
1038}
1039
1040/**
1041 * spear_smi_remove - Exit routine
1042 * @pdev: platform device structure
1043 *
1044 * free all allocations and delete the partitions.
1045 */
1046static int __devexit spear_smi_remove(struct platform_device *pdev)
1047{
1048 struct spear_smi *dev;
6551ab5d 1049 struct spear_smi_plat_data *pdata;
f18dbbb1 1050 struct spear_snor_flash *flash;
495c47d7 1051 struct resource *smi_base;
f18dbbb1
SH		 1052 int ret;
1053 int i, irq;
1054
1055 dev = platform_get_drvdata(pdev);
1056 if (!dev) {
1057 dev_err(&pdev->dev, "dev is null\n");
1058 return -ENODEV;
1059 }
1060
6551ab5d
SR		 1061 pdata = dev_get_platdata(&pdev->dev);
1062
f18dbbb1
SH		 1063 /* clean up for all nor flash */
1064 for (i = 0; i < dev->num_flashes; i++) {
1065 flash = dev->flash[i];
1066 if (!flash)
1067 continue;
1068
1069 /* clean up mtd stuff */
1070 ret = mtd_device_unregister(&flash->mtd);
1071 if (ret)
1072 dev_err(&pdev->dev, "error removing mtd\n");
1073
1074 iounmap(flash->base_addr);
1075 kfree(flash);
1076 }
1077
1078 irq = platform_get_irq(pdev, 0);
1079 free_irq(irq, dev);
1080
c0010eb5 1081 clk_disable_unprepare(dev->clk);
f18dbbb1
SH		 1082 clk_put(dev->clk);
1083 iounmap(dev->io_base);
1084 kfree(dev);
495c47d7
SH		 1085
1086 smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1087 release_mem_region(smi_base->start, resource_size(smi_base));
f18dbbb1
SH		 1088 platform_set_drvdata(pdev, NULL);
1089
1090 return 0;
1091}
1092
770daa43
VK		 1093#ifdef CONFIG_PM
1094static int spear_smi_suspend(struct device *dev)
f18dbbb1 1095{
770daa43 1096 struct spear_smi *sdev = dev_get_drvdata(dev);
f18dbbb1 1097
770daa43
VK		 1098 if (sdev && sdev->clk)
1099 clk_disable_unprepare(sdev->clk);
f18dbbb1
SH		 1100
1101 return 0;
1102}
1103
770daa43 1104static int spear_smi_resume(struct device *dev)
f18dbbb1 1105{
770daa43 1106 struct spear_smi *sdev = dev_get_drvdata(dev);
f18dbbb1
SH		 1107 int ret = -EPERM;
1108
770daa43
VK		 1109 if (sdev && sdev->clk)
1110 ret = clk_prepare_enable(sdev->clk);
f18dbbb1
SH		 1111
1112 if (!ret)
770daa43 1113 spear_smi_hw_init(sdev);
f18dbbb1
SH		 1114 return ret;
1115}
1116
770daa43
VK		 1117static SIMPLE_DEV_PM_OPS(spear_smi_pm_ops, spear_smi_suspend, spear_smi_resume);
1118#endif
1119
6551ab5d
SR		 1120#ifdef CONFIG_OF
1121static const struct of_device_id spear_smi_id_table[] = {
1122 { .compatible = "st,spear600-smi" },
1123 {}
1124};
1125MODULE_DEVICE_TABLE(of, spear_smi_id_table);
1126#endif
1127
f18dbbb1
SH		 1128static struct platform_driver spear_smi_driver = {
1129 .driver = {
1130 .name = "smi",
1131 .bus = &platform_bus_type,
1132 .owner = THIS_MODULE,
6551ab5d 1133 .of_match_table = of_match_ptr(spear_smi_id_table),
770daa43
VK		 1134#ifdef CONFIG_PM
1135 .pm = &spear_smi_pm_ops,
1136#endif
f18dbbb1
SH		 1137 },
1138 .probe = spear_smi_probe,
1139 .remove = __devexit_p(spear_smi_remove),
f18dbbb1
SH		 1140};
1141
1142static int spear_smi_init(void)
1143{
1144 return platform_driver_register(&spear_smi_driver);
1145}
1146module_init(spear_smi_init);
1147
1148static void spear_smi_exit(void)
1149{
1150 platform_driver_unregister(&spear_smi_driver);
1151}
1152module_exit(spear_smi_exit);
1153
1154MODULE_LICENSE("GPL");
1155MODULE_AUTHOR("Ashish Priyadarshi, Shiraz Hashim <shiraz.hashim@st.com>");
1156MODULE_DESCRIPTION("MTD SMI driver for serial nor flash chips");
Linux 6.x block layer and io_uring tree(s)