Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | #ifndef FWH_LOCK_H |
3 | #define FWH_LOCK_H | |
4 | ||
5 | ||
6 | enum fwh_lock_state { | |
7 | FWH_UNLOCKED = 0, | |
8 | FWH_DENY_WRITE = 1, | |
9 | FWH_IMMUTABLE = 2, | |
10 | FWH_DENY_READ = 4, | |
11 | }; | |
12 | ||
13 | struct fwh_xxlock_thunk { | |
14 | enum fwh_lock_state val; | |
15 | flstate_t state; | |
16 | }; | |
17 | ||
18 | ||
19 | #define FWH_XXLOCK_ONEBLOCK_LOCK ((struct fwh_xxlock_thunk){ FWH_DENY_WRITE, FL_LOCKING}) | |
20 | #define FWH_XXLOCK_ONEBLOCK_UNLOCK ((struct fwh_xxlock_thunk){ FWH_UNLOCKED, FL_UNLOCKING}) | |
21 | ||
22 | /* | |
23 | * This locking/unlock is specific to firmware hub parts. Only one | |
24 | * is known that supports the Intel command set. Firmware | |
25 | * hub parts cannot be interleaved as they are on the LPC bus | |
26 | * so this code has not been tested with interleaved chips, | |
27 | * and will likely fail in that context. | |
28 | */ | |
1f948b43 | 29 | static int fwh_xxlock_oneblock(struct map_info *map, struct flchip *chip, |
1da177e4 LT |
30 | unsigned long adr, int len, void *thunk) |
31 | { | |
32 | struct cfi_private *cfi = map->fldrv_priv; | |
33 | struct fwh_xxlock_thunk *xxlt = (struct fwh_xxlock_thunk *)thunk; | |
34 | int ret; | |
35 | ||
36 | /* Refuse the operation if the we cannot look behind the chip */ | |
37 | if (chip->start < 0x400000) { | |
289c0522 | 38 | pr_debug( "MTD %s(): chip->start: %lx wanted >= 0x400000\n", |
1da177e4 LT |
39 | __func__, chip->start ); |
40 | return -EIO; | |
41 | } | |
42 | /* | |
43 | * lock block registers: | |
44 | * - on 64k boundariesand | |
45 | * - bit 1 set high | |
46 | * - block lock registers are 4MiB lower - overflow subtract (danger) | |
1f948b43 | 47 | * |
1da177e4 LT |
48 | * The address manipulation is first done on the logical address |
49 | * which is 0 at the start of the chip, and then the offset of | |
50 | * the individual chip is addted to it. Any other order a weird | |
51 | * map offset could cause problems. | |
52 | */ | |
53 | adr = (adr & ~0xffffUL) | 0x2; | |
54 | adr += chip->start - 0x400000; | |
55 | ||
56 | /* | |
57 | * This is easy because these are writes to registers and not writes | |
58 | * to flash memory - that means that we don't have to check status | |
59 | * and timeout. | |
60 | */ | |
c4e77376 | 61 | mutex_lock(&chip->mutex); |
1da177e4 LT |
62 | ret = get_chip(map, chip, adr, FL_LOCKING); |
63 | if (ret) { | |
c4e77376 | 64 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
65 | return ret; |
66 | } | |
67 | ||
e6be133b | 68 | chip->oldstate = chip->state; |
1da177e4 LT |
69 | chip->state = xxlt->state; |
70 | map_write(map, CMD(xxlt->val), adr); | |
71 | ||
72 | /* Done and happy. */ | |
e6be133b | 73 | chip->state = chip->oldstate; |
1da177e4 | 74 | put_chip(map, chip, adr); |
c4e77376 | 75 | mutex_unlock(&chip->mutex); |
1da177e4 LT |
76 | return 0; |
77 | } | |
78 | ||
79 | ||
69423d99 | 80 | static int fwh_lock_varsize(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
1da177e4 LT |
81 | { |
82 | int ret; | |
83 | ||
84 | ret = cfi_varsize_frob(mtd, fwh_xxlock_oneblock, ofs, len, | |
85 | (void *)&FWH_XXLOCK_ONEBLOCK_LOCK); | |
86 | ||
87 | return ret; | |
88 | } | |
89 | ||
90 | ||
69423d99 | 91 | static int fwh_unlock_varsize(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
1da177e4 LT |
92 | { |
93 | int ret; | |
94 | ||
95 | ret = cfi_varsize_frob(mtd, fwh_xxlock_oneblock, ofs, len, | |
96 | (void *)&FWH_XXLOCK_ONEBLOCK_UNLOCK); | |
1f948b43 | 97 | |
1da177e4 LT |
98 | return ret; |
99 | } | |
100 | ||
cc318222 | 101 | static void fixup_use_fwh_lock(struct mtd_info *mtd) |
1da177e4 LT |
102 | { |
103 | printk(KERN_NOTICE "using fwh lock/unlock method\n"); | |
104 | /* Setup for the chips with the fwh lock method */ | |
3c3c10bb AB |
105 | mtd->_lock = fwh_lock_varsize; |
106 | mtd->_unlock = fwh_unlock_varsize; | |
1da177e4 LT |
107 | } |
108 | #endif /* FWH_LOCK_H */ |