[linux-2.6-block.git] / drivers / mtd / chips / Kconfig

# SPDX-License-Identifier: GPL-2.0-only
menu "RAM/ROM/Flash chip drivers"
	depends on MTD!=n

config MTD_CFI
	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface specification was developed by Intel,
	  AMD and other flash manufactures that provides a universal method
	  for probing the capabilities of flash devices. If you wish to
	  support any device that is CFI-compliant, you need to enable this
	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	  for more information on CFI.

config MTD_JEDECPROBE
	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  This option enables JEDEC-style probing of flash chips which are not
	  compatible with the Common Flash Interface, but will use the common
	  CFI-targeted flash drivers for any chips which are identified which
	  are in fact compatible in all but the probe method. This actually
	  covers most AMD/Fujitsu-compatible chips and also non-CFI
	  Intel chips.

config MTD_GEN_PROBE
	tristate

config MTD_CFI_ADV_OPTIONS
	bool "Flash chip driver advanced configuration options"
	depends on MTD_GEN_PROBE
	help
	  If you need to specify a specific endianness for access to flash
	  chips, or if you wish to reduce the size of the kernel by including
	  support for only specific arrangements of flash chips, say 'Y'. This
	  option does not directly affect the code, but will enable other
	  configuration options which allow you to do so.

	  If unsure, say 'N'.

choice
	prompt "Flash cmd/query data swapping"
	depends on MTD_CFI_ADV_OPTIONS
	default MTD_CFI_NOSWAP
	help
	  This option defines the way in which the CPU attempts to arrange
	  data bits when writing the 'magic' commands to the chips. Saying
	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	  enabled, means that the CPU will not do any swapping; the chips
	  are expected to be wired to the CPU in 'host-endian' form.
	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.

config MTD_CFI_NOSWAP
	bool "NO"

config MTD_CFI_BE_BYTE_SWAP
	bool "BIG_ENDIAN_BYTE"

config MTD_CFI_LE_BYTE_SWAP
	bool "LITTLE_ENDIAN_BYTE"

endchoice

config MTD_CFI_GEOMETRY
	bool "Specific CFI Flash geometry selection"
	depends on MTD_CFI_ADV_OPTIONS
	select MTD_MAP_BANK_WIDTH_1 if  !(MTD_MAP_BANK_WIDTH_2 || \
		 MTD_MAP_BANK_WIDTH_4  || MTD_MAP_BANK_WIDTH_8 || \
		 MTD_MAP_BANK_WIDTH_16 || MTD_MAP_BANK_WIDTH_32)
	select MTD_CFI_I1 if !(MTD_CFI_I2 || MTD_CFI_I4 || MTD_CFI_I8)
	help
	  This option does not affect the code directly, but will enable
	  some other configuration options which would allow you to reduce
	  the size of the kernel by including support for only certain
	  arrangements of CFI chips. If unsure, say 'N' and all options
	  which are supported by the current code will be enabled.

config MTD_MAP_BANK_WIDTH_1
	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  8 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_2
	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  16 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_4
	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  32 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_8
	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  64 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_16
	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  128 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_32
	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	select MTD_COMPLEX_MAPPINGS if HAS_IOMEM
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  256 bits wide, say 'Y'.

config MTD_CFI_I1
	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are not interleaved - i.e. you only have one
	  flash chip addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I2
	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are interleaved in pairs - i.e. you have two
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I4
	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in fours - i.e. you have four
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I8
	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in eights - i.e. you have eight
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_OTP
	bool "Protection Registers aka one-time programmable (OTP) bits"
	depends on MTD_CFI_ADV_OPTIONS
	default n
	help
	  This enables support for reading, writing and locking so called
	  "Protection Registers" present on some flash chips.
	  A subset of them are pre-programmed at the factory with a
	  unique set of values. The rest is user-programmable.

	  The user-programmable Protection Registers contain one-time
	  programmable (OTP) bits; when programmed, register bits cannot be
	  erased. Each Protection Register can be accessed multiple times to
	  program individual bits, as long as the register remains unlocked.

	  Each Protection Register has an associated Lock Register bit. When a
	  Lock Register bit is programmed, the associated Protection Register
	  can only be read; it can no longer be programmed. Additionally,
	  because the Lock Register bits themselves are OTP, when programmed,
	  Lock Register bits cannot be erased. Therefore, when a Protection
	  Register is locked, it cannot be unlocked.

	  This feature should therefore be used with extreme care. Any mistake
	  in the programming of OTP bits will waste them.

config MTD_CFI_INTELEXT
	tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for command set 0001, used on Intel StrataFlash
	  and other parts.

config MTD_CFI_AMDSTD
	tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for command set 0002, used on chips including
	  the AMD Am29LV320.

config MTD_CFI_STAA
	tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for command set 0020.

config MTD_CFI_UTIL
	tristate

config MTD_RAM
	tristate "Support for RAM chips in bus mapping"
	help
	  This option enables basic support for RAM chips accessed through
	  a bus mapping driver.

config MTD_ROM
	tristate "Support for ROM chips in bus mapping"
	help
	  This option enables basic support for ROM chips accessed through
	  a bus mapping driver.

config MTD_ABSENT
	tristate "Support for absent chips in bus mapping"
	help
	  This option enables support for a dummy probing driver used to
	  allocated placeholder MTD devices on systems that have socketed
	  or removable media.  Use of this driver as a fallback chip probe
	  preserves the expected registration order of MTD device nodes on
	  the system regardless of media presence.  Device nodes created
	  with this driver will return -ENODEV upon access.

config MTD_XIP
	bool "XIP aware MTD support"
	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
	default y if XIP_KERNEL
	help
	  This allows MTD support to work with flash memory which is also
	  used for XIP purposes.  If you're not sure what this is all about
	  then say N.

endmenu
Commit	Line	Data
ec8f24b7	1	# SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	menu "RAM/ROM/Flash chip drivers"
	3	depends on MTD!=n
	4
	5	config MTD_CFI
	6	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
1da177e4	7	select MTD_GEN_PROBE
5e706469	8	select MTD_CFI_UTIL
1da177e4 LT	9	help
	10	The Common Flash Interface specification was developed by Intel,
	11	AMD and other flash manufactures that provides a universal method
	12	for probing the capabilities of flash devices. If you wish to
	13	support any device that is CFI-compliant, you need to enable this
	14	option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	15	for more information on CFI.
	16
	17	config MTD_JEDECPROBE
	18	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
1da177e4	19	select MTD_GEN_PROBE
bde90062	20	select MTD_CFI_UTIL
1da177e4 LT	21	help
	22	This option enables JEDEC-style probing of flash chips which are not
	23	compatible with the Common Flash Interface, but will use the common
25985edc	24	CFI-targeted flash drivers for any chips which are identified which
1da177e4	25	are in fact compatible in all but the probe method. This actually
8917f6f7 AB	26	covers most AMD/Fujitsu-compatible chips and also non-CFI
8917f6f7 AB	27	Intel chips.
1da177e4 LT	28
	29	config MTD_GEN_PROBE
	30	tristate
	31
	32	config MTD_CFI_ADV_OPTIONS
	33	bool "Flash chip driver advanced configuration options"
	34	depends on MTD_GEN_PROBE
	35	help
	36	If you need to specify a specific endianness for access to flash
	37	chips, or if you wish to reduce the size of the kernel by including
	38	support for only specific arrangements of flash chips, say 'Y'. This
1f948b43	39	option does not directly affect the code, but will enable other
1da177e4 LT	40	configuration options which allow you to do so.
	41
	42	If unsure, say 'N'.
	43
	44	choice
	45	prompt "Flash cmd/query data swapping"
	46	depends on MTD_CFI_ADV_OPTIONS
	47	default MTD_CFI_NOSWAP
a8222a84	48	help
1da177e4 LT	49	This option defines the way in which the CPU attempts to arrange
	50	data bits when writing the 'magic' commands to the chips. Saying
	51	'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	52	enabled, means that the CPU will not do any swapping; the chips
1f948b43	53	are expected to be wired to the CPU in 'host-endian' form.
1da177e4 LT	54	Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	55	LITTLE_ENDIAN_BYTE, if the bytes are reversed.
	56
2e61c3a5 PB	57	config MTD_CFI_NOSWAP
2e61c3a5 PB	58	bool "NO"
1da177e4 LT	59
	60	config MTD_CFI_BE_BYTE_SWAP
	61	bool "BIG_ENDIAN_BYTE"
	62
	63	config MTD_CFI_LE_BYTE_SWAP
	64	bool "LITTLE_ENDIAN_BYTE"
	65
	66	endchoice
	67
	68	config MTD_CFI_GEOMETRY
	69	bool "Specific CFI Flash geometry selection"
	70	depends on MTD_CFI_ADV_OPTIONS
f5f92b36 AB	71	select MTD_MAP_BANK_WIDTH_1 if !(MTD_MAP_BANK_WIDTH_2 \|\| \
	72	MTD_MAP_BANK_WIDTH_4 \|\| MTD_MAP_BANK_WIDTH_8 \|\| \
	73	MTD_MAP_BANK_WIDTH_16 \|\| MTD_MAP_BANK_WIDTH_32)
	74	select MTD_CFI_I1 if !(MTD_CFI_I2 \|\| MTD_CFI_I4 \|\| MTD_CFI_I8)
1da177e4	75	help
1f948b43	76	This option does not affect the code directly, but will enable
1da177e4	77	some other configuration options which would allow you to reduce
1f948b43 TG	78	the size of the kernel by including support for only certain
1f948b43 TG	79	arrangements of CFI chips. If unsure, say 'N' and all options
1da177e4 LT	80	which are supported by the current code will be enabled.
	81
	82	config MTD_MAP_BANK_WIDTH_1
	83	bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
	84	default y
	85	help
	86	If you wish to support CFI devices on a physical bus which is
	87	8 bits wide, say 'Y'.
	88
	89	config MTD_MAP_BANK_WIDTH_2
	90	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	91	default y
	92	help
	93	If you wish to support CFI devices on a physical bus which is
	94	16 bits wide, say 'Y'.
	95
	96	config MTD_MAP_BANK_WIDTH_4
	97	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	98	default y
	99	help
	100	If you wish to support CFI devices on a physical bus which is
	101	32 bits wide, say 'Y'.
	102
	103	config MTD_MAP_BANK_WIDTH_8
	104	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	105	default n
	106	help
	107	If you wish to support CFI devices on a physical bus which is
	108	64 bits wide, say 'Y'.
	109
	110	config MTD_MAP_BANK_WIDTH_16
	111	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	112	default n
	113	help
	114	If you wish to support CFI devices on a physical bus which is
	115	128 bits wide, say 'Y'.
	116
	117	config MTD_MAP_BANK_WIDTH_32
	118	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
fddcca51	119	select MTD_COMPLEX_MAPPINGS if HAS_IOMEM
1da177e4 LT	120	default n
	121	help
	122	If you wish to support CFI devices on a physical bus which is
	123	256 bits wide, say 'Y'.
	124
	125	config MTD_CFI_I1
	126	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	127	default y
	128	help
	129	If your flash chips are not interleaved - i.e. you only have one
	130	flash chip addressed by each bus cycle, then say 'Y'.
	131
	132	config MTD_CFI_I2
	133	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	134	default y
	135	help
	136	If your flash chips are interleaved in pairs - i.e. you have two
	137	flash chips addressed by each bus cycle, then say 'Y'.
	138
	139	config MTD_CFI_I4
	140	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	141	default n
	142	help
	143	If your flash chips are interleaved in fours - i.e. you have four
	144	flash chips addressed by each bus cycle, then say 'Y'.
	145
	146	config MTD_CFI_I8
	147	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	148	default n
	149	help
	150	If your flash chips are interleaved in eights - i.e. you have eight
	151	flash chips addressed by each bus cycle, then say 'Y'.
	152
f77814dd NP	153	config MTD_OTP
	154	bool "Protection Registers aka one-time programmable (OTP) bits"
	155	depends on MTD_CFI_ADV_OPTIONS
	156	default n
	157	help
	158	This enables support for reading, writing and locking so called
	159	"Protection Registers" present on some flash chips.
	160	A subset of them are pre-programmed at the factory with a
	161	unique set of values. The rest is user-programmable.
	162
	163	The user-programmable Protection Registers contain one-time
	164	programmable (OTP) bits; when programmed, register bits cannot be
	165	erased. Each Protection Register can be accessed multiple times to
	166	program individual bits, as long as the register remains unlocked.
	167
	168	Each Protection Register has an associated Lock Register bit. When a
	169	Lock Register bit is programmed, the associated Protection Register
	170	can only be read; it can no longer be programmed. Additionally,
	171	because the Lock Register bits themselves are OTP, when programmed,
	172	Lock Register bits cannot be erased. Therefore, when a Protection
	173	Register is locked, it cannot be unlocked.
	174
	175	This feature should therefore be used with extreme care. Any mistake
	176	in the programming of OTP bits will waste them.
	177
1da177e4	178	config MTD_CFI_INTELEXT
5a4c4c5e	179	tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
1da177e4 LT	180	depends on MTD_GEN_PROBE
	181	select MTD_CFI_UTIL
	182	help
	183	The Common Flash Interface defines a number of different command
	184	sets which a CFI-compliant chip may claim to implement. This code
5a4c4c5e PDM	185	provides support for command set 0001, used on Intel StrataFlash
5a4c4c5e PDM	186	and other parts.
1da177e4 LT	187
1da177e4 LT	188	config MTD_CFI_AMDSTD
5a4c4c5e	189	tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
1da177e4 LT	190	depends on MTD_GEN_PROBE
	191	select MTD_CFI_UTIL
	192	help
	193	The Common Flash Interface defines a number of different command
	194	sets which a CFI-compliant chip may claim to implement. This code
5a4c4c5e PDM	195	provides support for command set 0002, used on chips including
5a4c4c5e PDM	196	the AMD Am29LV320.
1da177e4	197
1da177e4	198	config MTD_CFI_STAA
5a4c4c5e	199	tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
1da177e4 LT	200	depends on MTD_GEN_PROBE
	201	select MTD_CFI_UTIL
	202	help
	203	The Common Flash Interface defines a number of different command
	204	sets which a CFI-compliant chip may claim to implement. This code
5a4c4c5e	205	provides support for command set 0020.
1da177e4 LT	206
	207	config MTD_CFI_UTIL
	208	tristate
	209
	210	config MTD_RAM
	211	tristate "Support for RAM chips in bus mapping"
1da177e4	212	help
1f948b43	213	This option enables basic support for RAM chips accessed through
1da177e4 LT	214	a bus mapping driver.
	215
	216	config MTD_ROM
	217	tristate "Support for ROM chips in bus mapping"
1da177e4	218	help
1f948b43	219	This option enables basic support for ROM chips accessed through
1da177e4 LT	220	a bus mapping driver.
	221
	222	config MTD_ABSENT
	223	tristate "Support for absent chips in bus mapping"
1da177e4 LT	224	help
	225	This option enables support for a dummy probing driver used to
	226	allocated placeholder MTD devices on systems that have socketed
	227	or removable media. Use of this driver as a fallback chip probe
	228	preserves the expected registration order of MTD device nodes on
	229	the system regardless of media presence. Device nodes created
	230	with this driver will return -ENODEV upon access.
	231
1da177e4 LT	232	config MTD_XIP
1da177e4 LT	233	bool "XIP aware MTD support"
7b4dd55b	234	depends on !SMP && (MTD_CFI_INTELEXT \|\| MTD_CFI_AMDSTD) && ARCH_MTD_XIP
1da177e4 LT	235	default y if XIP_KERNEL
	236	help
	237	This allows MTD support to work with flash memory which is also
	238	used for XIP purposes. If you're not sure what this is all about
	239	then say N.
	240
	241	endmenu