[linux-2.6-block.git] / drivers / mtd / chips / Kconfig

menu "RAM/ROM/Flash chip drivers"
	depends on MTD!=n

config MTD_CFI
	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface specification was developed by Intel,
	  AMD and other flash manufactures that provides a universal method
	  for probing the capabilities of flash devices. If you wish to
	  support any device that is CFI-compliant, you need to enable this
	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	  for more information on CFI.

config MTD_JEDECPROBE
	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
	select MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  This option enables JEDEC-style probing of flash chips which are not
	  compatible with the Common Flash Interface, but will use the common
	  CFI-targeted flash drivers for any chips which are identified which
	  are in fact compatible in all but the probe method. This actually
	  covers most AMD/Fujitsu-compatible chips and also non-CFI
	  Intel chips.

config MTD_GEN_PROBE
	tristate

config MTD_CFI_ADV_OPTIONS
	bool "Flash chip driver advanced configuration options"
	depends on MTD_GEN_PROBE
	help
	  If you need to specify a specific endianness for access to flash
	  chips, or if you wish to reduce the size of the kernel by including
	  support for only specific arrangements of flash chips, say 'Y'. This
	  option does not directly affect the code, but will enable other
	  configuration options which allow you to do so.

	  If unsure, say 'N'.

choice
	prompt "Flash cmd/query data swapping"
	depends on MTD_CFI_ADV_OPTIONS
	default MTD_CFI_NOSWAP
	---help---
	  This option defines the way in which the CPU attempts to arrange
	  data bits when writing the 'magic' commands to the chips. Saying
	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	  enabled, means that the CPU will not do any swapping; the chips
	  are expected to be wired to the CPU in 'host-endian' form.
	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.

config MTD_CFI_NOSWAP
	bool "NO"

config MTD_CFI_BE_BYTE_SWAP
	bool "BIG_ENDIAN_BYTE"

config MTD_CFI_LE_BYTE_SWAP
	bool "LITTLE_ENDIAN_BYTE"

endchoice

config MTD_CFI_GEOMETRY
	bool "Specific CFI Flash geometry selection"
	depends on MTD_CFI_ADV_OPTIONS
	select MTD_MAP_BANK_WIDTH_1 if  !(MTD_MAP_BANK_WIDTH_2 || \
		 MTD_MAP_BANK_WIDTH_4  || MTD_MAP_BANK_WIDTH_8 || \
		 MTD_MAP_BANK_WIDTH_16 || MTD_MAP_BANK_WIDTH_32)
	select MTD_CFI_I1 if !(MTD_CFI_I2 || MTD_CFI_I4 || MTD_CFI_I8)
	help
	  This option does not affect the code directly, but will enable
	  some other configuration options which would allow you to reduce
	  the size of the kernel by including support for only certain
	  arrangements of CFI chips. If unsure, say 'N' and all options
	  which are supported by the current code will be enabled.

config MTD_MAP_BANK_WIDTH_1
	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  8 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_2
	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  16 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_4
	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	default y
	help
	  If you wish to support CFI devices on a physical bus which is
	  32 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_8
	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  64 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_16
	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  128 bits wide, say 'Y'.

config MTD_MAP_BANK_WIDTH_32
	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	default n
	help
	  If you wish to support CFI devices on a physical bus which is
	  256 bits wide, say 'Y'.

config MTD_CFI_I1
	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are not interleaved - i.e. you only have one
	  flash chip addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I2
	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	default y
	help
	  If your flash chips are interleaved in pairs - i.e. you have two
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I4
	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in fours - i.e. you have four
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_CFI_I8
	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
	default n
	help
	  If your flash chips are interleaved in eights - i.e. you have eight
	  flash chips addressed by each bus cycle, then say 'Y'.

config MTD_OTP
	bool "Protection Registers aka one-time programmable (OTP) bits"
	depends on MTD_CFI_ADV_OPTIONS
	default n
	help
	  This enables support for reading, writing and locking so called
	  "Protection Registers" present on some flash chips.
	  A subset of them are pre-programmed at the factory with a
	  unique set of values. The rest is user-programmable.

	  The user-programmable Protection Registers contain one-time
	  programmable (OTP) bits; when programmed, register bits cannot be
	  erased. Each Protection Register can be accessed multiple times to
	  program individual bits, as long as the register remains unlocked.

	  Each Protection Register has an associated Lock Register bit. When a
	  Lock Register bit is programmed, the associated Protection Register
	  can only be read; it can no longer be programmed. Additionally,
	  because the Lock Register bits themselves are OTP, when programmed,
	  Lock Register bits cannot be erased. Therefore, when a Protection
	  Register is locked, it cannot be unlocked.

	  This feature should therefore be used with extreme care. Any mistake
	  in the programming of OTP bits will waste them.

config MTD_CFI_INTELEXT
	tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for command set 0001, used on Intel StrataFlash
	  and other parts.

config MTD_CFI_AMDSTD
	tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for command set 0002, used on chips including
	  the AMD Am29LV320.

config MTD_CFI_STAA
	tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
	depends on MTD_GEN_PROBE
	select MTD_CFI_UTIL
	help
	  The Common Flash Interface defines a number of different command
	  sets which a CFI-compliant chip may claim to implement. This code
	  provides support for command set 0020.

config MTD_CFI_UTIL
	tristate

config MTD_RAM
	tristate "Support for RAM chips in bus mapping"
	help
	  This option enables basic support for RAM chips accessed through
	  a bus mapping driver.

config MTD_ROM
	tristate "Support for ROM chips in bus mapping"
	help
	  This option enables basic support for ROM chips accessed through
	  a bus mapping driver.

config MTD_ABSENT
	tristate "Support for absent chips in bus mapping"
	help
	  This option enables support for a dummy probing driver used to
	  allocated placeholder MTD devices on systems that have socketed
	  or removable media.  Use of this driver as a fallback chip probe
	  preserves the expected registration order of MTD device nodes on
	  the system regardless of media presence.  Device nodes created
	  with this driver will return -ENODEV upon access.

config MTD_XIP
	bool "XIP aware MTD support"
	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
	default y if XIP_KERNEL
	help
	  This allows MTD support to work with flash memory which is also
	  used for XIP purposes.  If you're not sure what this is all about
	  then say N.

endmenu
Commit	Line	Data
1da177e4 LT	1	menu "RAM/ROM/Flash chip drivers"
	2	depends on MTD!=n
	3
	4	config MTD_CFI
	5	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
1da177e4	6	select MTD_GEN_PROBE
5e706469	7	select MTD_CFI_UTIL
1da177e4 LT	8	help
	9	The Common Flash Interface specification was developed by Intel,
	10	AMD and other flash manufactures that provides a universal method
	11	for probing the capabilities of flash devices. If you wish to
	12	support any device that is CFI-compliant, you need to enable this
	13	option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
	14	for more information on CFI.
	15
	16	config MTD_JEDECPROBE
	17	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
1da177e4	18	select MTD_GEN_PROBE
bde90062	19	select MTD_CFI_UTIL
1da177e4 LT	20	help
	21	This option enables JEDEC-style probing of flash chips which are not
	22	compatible with the Common Flash Interface, but will use the common
25985edc	23	CFI-targeted flash drivers for any chips which are identified which
1da177e4	24	are in fact compatible in all but the probe method. This actually
8917f6f7 AB	25	covers most AMD/Fujitsu-compatible chips and also non-CFI
8917f6f7 AB	26	Intel chips.
1da177e4 LT	27
	28	config MTD_GEN_PROBE
	29	tristate
	30
	31	config MTD_CFI_ADV_OPTIONS
	32	bool "Flash chip driver advanced configuration options"
	33	depends on MTD_GEN_PROBE
	34	help
	35	If you need to specify a specific endianness for access to flash
	36	chips, or if you wish to reduce the size of the kernel by including
	37	support for only specific arrangements of flash chips, say 'Y'. This
1f948b43	38	option does not directly affect the code, but will enable other
1da177e4 LT	39	configuration options which allow you to do so.
	40
	41	If unsure, say 'N'.
	42
	43	choice
	44	prompt "Flash cmd/query data swapping"
	45	depends on MTD_CFI_ADV_OPTIONS
	46	default MTD_CFI_NOSWAP
1da177e4 LT	47	---help---
	48	This option defines the way in which the CPU attempts to arrange
	49	data bits when writing the 'magic' commands to the chips. Saying
	50	'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
	51	enabled, means that the CPU will not do any swapping; the chips
1f948b43	52	are expected to be wired to the CPU in 'host-endian' form.
1da177e4 LT	53	Specific arrangements are possible with the BIG_ENDIAN_BYTE and
	54	LITTLE_ENDIAN_BYTE, if the bytes are reversed.
	55
2e61c3a5 PB	56	config MTD_CFI_NOSWAP
2e61c3a5 PB	57	bool "NO"
1da177e4 LT	58
	59	config MTD_CFI_BE_BYTE_SWAP
	60	bool "BIG_ENDIAN_BYTE"
	61
	62	config MTD_CFI_LE_BYTE_SWAP
	63	bool "LITTLE_ENDIAN_BYTE"
	64
	65	endchoice
	66
	67	config MTD_CFI_GEOMETRY
	68	bool "Specific CFI Flash geometry selection"
	69	depends on MTD_CFI_ADV_OPTIONS
f5f92b36 AB	70	select MTD_MAP_BANK_WIDTH_1 if !(MTD_MAP_BANK_WIDTH_2 \|\| \
	71	MTD_MAP_BANK_WIDTH_4 \|\| MTD_MAP_BANK_WIDTH_8 \|\| \
	72	MTD_MAP_BANK_WIDTH_16 \|\| MTD_MAP_BANK_WIDTH_32)
	73	select MTD_CFI_I1 if !(MTD_CFI_I2 \|\| MTD_CFI_I4 \|\| MTD_CFI_I8)
1da177e4	74	help
1f948b43	75	This option does not affect the code directly, but will enable
1da177e4	76	some other configuration options which would allow you to reduce
1f948b43 TG	77	the size of the kernel by including support for only certain
1f948b43 TG	78	arrangements of CFI chips. If unsure, say 'N' and all options
1da177e4 LT	79	which are supported by the current code will be enabled.
	80
	81	config MTD_MAP_BANK_WIDTH_1
	82	bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
	83	default y
	84	help
	85	If you wish to support CFI devices on a physical bus which is
	86	8 bits wide, say 'Y'.
	87
	88	config MTD_MAP_BANK_WIDTH_2
	89	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
	90	default y
	91	help
	92	If you wish to support CFI devices on a physical bus which is
	93	16 bits wide, say 'Y'.
	94
	95	config MTD_MAP_BANK_WIDTH_4
	96	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
	97	default y
	98	help
	99	If you wish to support CFI devices on a physical bus which is
	100	32 bits wide, say 'Y'.
	101
	102	config MTD_MAP_BANK_WIDTH_8
	103	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
	104	default n
	105	help
	106	If you wish to support CFI devices on a physical bus which is
	107	64 bits wide, say 'Y'.
	108
	109	config MTD_MAP_BANK_WIDTH_16
	110	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
	111	default n
	112	help
	113	If you wish to support CFI devices on a physical bus which is
	114	128 bits wide, say 'Y'.
	115
	116	config MTD_MAP_BANK_WIDTH_32
	117	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
	118	default n
	119	help
	120	If you wish to support CFI devices on a physical bus which is
	121	256 bits wide, say 'Y'.
	122
	123	config MTD_CFI_I1
	124	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
	125	default y
	126	help
	127	If your flash chips are not interleaved - i.e. you only have one
	128	flash chip addressed by each bus cycle, then say 'Y'.
	129
	130	config MTD_CFI_I2
	131	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
	132	default y
	133	help
	134	If your flash chips are interleaved in pairs - i.e. you have two
	135	flash chips addressed by each bus cycle, then say 'Y'.
	136
	137	config MTD_CFI_I4
	138	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
	139	default n
	140	help
	141	If your flash chips are interleaved in fours - i.e. you have four
	142	flash chips addressed by each bus cycle, then say 'Y'.
143
144	config MTD_CFI_I8
145	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
146	default n
147	help
148	If your flash chips are interleaved in eights - i.e. you have eight
149	flash chips addressed by each bus cycle, then say 'Y'.
150
f77814dd NP	151	config MTD_OTP
	152	bool "Protection Registers aka one-time programmable (OTP) bits"
	153	depends on MTD_CFI_ADV_OPTIONS
	154	default n
	155	help
	156	This enables support for reading, writing and locking so called
	157	"Protection Registers" present on some flash chips.
	158	A subset of them are pre-programmed at the factory with a
	159	unique set of values. The rest is user-programmable.
	160
	161	The user-programmable Protection Registers contain one-time
	162	programmable (OTP) bits; when programmed, register bits cannot be
	163	erased. Each Protection Register can be accessed multiple times to
	164	program individual bits, as long as the register remains unlocked.
	165
	166	Each Protection Register has an associated Lock Register bit. When a
	167	Lock Register bit is programmed, the associated Protection Register
	168	can only be read; it can no longer be programmed. Additionally,
	169	because the Lock Register bits themselves are OTP, when programmed,
	170	Lock Register bits cannot be erased. Therefore, when a Protection
	171	Register is locked, it cannot be unlocked.
	172
	173	This feature should therefore be used with extreme care. Any mistake
	174	in the programming of OTP bits will waste them.
	175
1da177e4	176	config MTD_CFI_INTELEXT
5a4c4c5e	177	tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
1da177e4 LT	178	depends on MTD_GEN_PROBE
	179	select MTD_CFI_UTIL
	180	help
	181	The Common Flash Interface defines a number of different command
	182	sets which a CFI-compliant chip may claim to implement. This code
5a4c4c5e PDM	183	provides support for command set 0001, used on Intel StrataFlash
5a4c4c5e PDM	184	and other parts.
1da177e4 LT	185
1da177e4 LT	186	config MTD_CFI_AMDSTD
5a4c4c5e	187	tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
1da177e4 LT	188	depends on MTD_GEN_PROBE
	189	select MTD_CFI_UTIL
	190	help
	191	The Common Flash Interface defines a number of different command
	192	sets which a CFI-compliant chip may claim to implement. This code
5a4c4c5e PDM	193	provides support for command set 0002, used on chips including
5a4c4c5e PDM	194	the AMD Am29LV320.
1da177e4	195
1da177e4	196	config MTD_CFI_STAA
5a4c4c5e	197	tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
1da177e4 LT	198	depends on MTD_GEN_PROBE
	199	select MTD_CFI_UTIL
	200	help
	201	The Common Flash Interface defines a number of different command
	202	sets which a CFI-compliant chip may claim to implement. This code
5a4c4c5e	203	provides support for command set 0020.
1da177e4 LT	204
	205	config MTD_CFI_UTIL
	206	tristate
	207
	208	config MTD_RAM
	209	tristate "Support for RAM chips in bus mapping"
1da177e4	210	help
1f948b43	211	This option enables basic support for RAM chips accessed through
1da177e4 LT	212	a bus mapping driver.
	213
	214	config MTD_ROM
	215	tristate "Support for ROM chips in bus mapping"
1da177e4	216	help
1f948b43	217	This option enables basic support for ROM chips accessed through
1da177e4 LT	218	a bus mapping driver.
	219
	220	config MTD_ABSENT
	221	tristate "Support for absent chips in bus mapping"
1da177e4 LT	222	help
	223	This option enables support for a dummy probing driver used to
	224	allocated placeholder MTD devices on systems that have socketed
	225	or removable media. Use of this driver as a fallback chip probe
	226	preserves the expected registration order of MTD device nodes on
	227	the system regardless of media presence. Device nodes created
	228	with this driver will return -ENODEV upon access.
	229
1da177e4 LT	230	config MTD_XIP
1da177e4 LT	231	bool "XIP aware MTD support"
7b4dd55b	232	depends on !SMP && (MTD_CFI_INTELEXT \|\| MTD_CFI_AMDSTD) && ARCH_MTD_XIP
1da177e4 LT	233	default y if XIP_KERNEL
	234	help
	235	This allows MTD support to work with flash memory which is also
	236	used for XIP purposes. If you're not sure what this is all about
	237	then say N.
	238
	239	endmenu