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1 | /* |
2 | * linux/drivers/mmc/sdhci.h - Secure Digital Host Controller Interface driver | |
3 | * | |
4 | * Copyright (C) 2005 Pierre Ossman, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * PCI registers | |
13 | */ | |
14 | ||
15 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
16 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
17 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
18 | ||
19 | /* | |
20 | * Controller registers | |
21 | */ | |
22 | ||
23 | #define SDHCI_DMA_ADDRESS 0x00 | |
24 | ||
25 | #define SDHCI_BLOCK_SIZE 0x04 | |
26 | ||
27 | #define SDHCI_BLOCK_COUNT 0x06 | |
28 | ||
29 | #define SDHCI_ARGUMENT 0x08 | |
30 | ||
31 | #define SDHCI_TRANSFER_MODE 0x0C | |
32 | #define SDHCI_TRNS_DMA 0x01 | |
33 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 | |
34 | #define SDHCI_TRNS_ACMD12 0x04 | |
35 | #define SDHCI_TRNS_READ 0x10 | |
36 | #define SDHCI_TRNS_MULTI 0x20 | |
37 | ||
38 | #define SDHCI_COMMAND 0x0E | |
39 | #define SDHCI_CMD_RESP_MASK 0x03 | |
40 | #define SDHCI_CMD_CRC 0x08 | |
41 | #define SDHCI_CMD_INDEX 0x10 | |
42 | #define SDHCI_CMD_DATA 0x20 | |
43 | ||
44 | #define SDHCI_CMD_RESP_NONE 0x00 | |
45 | #define SDHCI_CMD_RESP_LONG 0x01 | |
46 | #define SDHCI_CMD_RESP_SHORT 0x02 | |
47 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 | |
48 | ||
49 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) | |
50 | ||
51 | #define SDHCI_RESPONSE 0x10 | |
52 | ||
53 | #define SDHCI_BUFFER 0x20 | |
54 | ||
55 | #define SDHCI_PRESENT_STATE 0x24 | |
56 | #define SDHCI_CMD_INHIBIT 0x00000001 | |
57 | #define SDHCI_DATA_INHIBIT 0x00000002 | |
58 | #define SDHCI_DOING_WRITE 0x00000100 | |
59 | #define SDHCI_DOING_READ 0x00000200 | |
60 | #define SDHCI_SPACE_AVAILABLE 0x00000400 | |
61 | #define SDHCI_DATA_AVAILABLE 0x00000800 | |
62 | #define SDHCI_CARD_PRESENT 0x00010000 | |
63 | #define SDHCI_WRITE_PROTECT 0x00080000 | |
64 | ||
65 | #define SDHCI_HOST_CONTROL 0x28 | |
66 | #define SDHCI_CTRL_LED 0x01 | |
67 | #define SDHCI_CTRL_4BITBUS 0x02 | |
68 | ||
69 | #define SDHCI_POWER_CONTROL 0x29 | |
146ad66e PO |
70 | #define SDHCI_POWER_ON 0x01 |
71 | #define SDHCI_POWER_180 0x0A | |
72 | #define SDHCI_POWER_300 0x0C | |
73 | #define SDHCI_POWER_330 0x0E | |
d129bceb PO |
74 | |
75 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A | |
76 | ||
77 | #define SDHCI_WALK_UP_CONTROL 0x2B | |
78 | ||
79 | #define SDHCI_CLOCK_CONTROL 0x2C | |
80 | #define SDHCI_DIVIDER_SHIFT 8 | |
81 | #define SDHCI_CLOCK_CARD_EN 0x0004 | |
82 | #define SDHCI_CLOCK_INT_STABLE 0x0002 | |
83 | #define SDHCI_CLOCK_INT_EN 0x0001 | |
84 | ||
85 | #define SDHCI_TIMEOUT_CONTROL 0x2E | |
86 | ||
87 | #define SDHCI_SOFTWARE_RESET 0x2F | |
88 | #define SDHCI_RESET_ALL 0x01 | |
89 | #define SDHCI_RESET_CMD 0x02 | |
90 | #define SDHCI_RESET_DATA 0x04 | |
91 | ||
92 | #define SDHCI_INT_STATUS 0x30 | |
93 | #define SDHCI_INT_ENABLE 0x34 | |
94 | #define SDHCI_SIGNAL_ENABLE 0x38 | |
95 | #define SDHCI_INT_RESPONSE 0x00000001 | |
96 | #define SDHCI_INT_DATA_END 0x00000002 | |
97 | #define SDHCI_INT_DMA_END 0x00000008 | |
98 | #define SDHCI_INT_BUF_EMPTY 0x00000010 | |
99 | #define SDHCI_INT_BUF_FULL 0x00000020 | |
100 | #define SDHCI_INT_CARD_INSERT 0x00000040 | |
101 | #define SDHCI_INT_CARD_REMOVE 0x00000080 | |
102 | #define SDHCI_INT_CARD_INT 0x00000100 | |
103 | #define SDHCI_INT_TIMEOUT 0x00010000 | |
104 | #define SDHCI_INT_CRC 0x00020000 | |
105 | #define SDHCI_INT_END_BIT 0x00040000 | |
106 | #define SDHCI_INT_INDEX 0x00080000 | |
107 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 | |
108 | #define SDHCI_INT_DATA_CRC 0x00200000 | |
109 | #define SDHCI_INT_DATA_END_BIT 0x00400000 | |
110 | #define SDHCI_INT_BUS_POWER 0x00800000 | |
111 | #define SDHCI_INT_ACMD12ERR 0x01000000 | |
112 | ||
113 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF | |
114 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 | |
115 | ||
116 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ | |
117 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) | |
118 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ | |
119 | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL | \ | |
120 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ | |
121 | SDHCI_INT_DATA_END_BIT) | |
122 | ||
123 | #define SDHCI_ACMD12_ERR 0x3C | |
124 | ||
125 | /* 3E-3F reserved */ | |
126 | ||
127 | #define SDHCI_CAPABILITIES 0x40 | |
d129bceb PO |
128 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
129 | #define SDHCI_CLOCK_BASE_SHIFT 8 | |
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130 | #define SDHCI_CAN_DO_DMA 0x00400000 |
131 | #define SDHCI_CAN_VDD_330 0x01000000 | |
132 | #define SDHCI_CAN_VDD_300 0x02000000 | |
133 | #define SDHCI_CAN_VDD_180 0x04000000 | |
d129bceb PO |
134 | |
135 | /* 44-47 reserved for more caps */ | |
136 | ||
137 | #define SDHCI_MAX_CURRENT 0x48 | |
138 | ||
139 | /* 4C-4F reserved for more max current */ | |
140 | ||
141 | /* 50-FB reserved */ | |
142 | ||
143 | #define SDHCI_SLOT_INT_STATUS 0xFC | |
144 | ||
145 | #define SDHCI_HOST_VERSION 0xFE | |
146 | ||
147 | struct sdhci_chip; | |
148 | ||
149 | struct sdhci_host { | |
150 | struct sdhci_chip *chip; | |
151 | struct mmc_host *mmc; /* MMC structure */ | |
152 | ||
153 | spinlock_t lock; /* Mutex */ | |
154 | ||
155 | int flags; /* Host attributes */ | |
156 | #define SDHCI_USE_DMA (1<<0) | |
157 | ||
158 | unsigned int max_clk; /* Max possible freq (MHz) */ | |
159 | ||
160 | unsigned int clock; /* Current clock (MHz) */ | |
146ad66e | 161 | unsigned short power; /* Current voltage */ |
d129bceb PO |
162 | |
163 | struct mmc_request *mrq; /* Current request */ | |
164 | struct mmc_command *cmd; /* Current command */ | |
165 | struct mmc_data *data; /* Current data request */ | |
166 | ||
167 | struct scatterlist *cur_sg; /* We're working on this */ | |
168 | char *mapped_sg; /* This is where it's mapped */ | |
169 | int num_sg; /* Entries left */ | |
170 | int offset; /* Offset into current sg */ | |
171 | int remain; /* Bytes left in current */ | |
172 | ||
173 | int size; /* Remaining bytes in transfer */ | |
174 | ||
175 | char slot_descr[20]; /* Name for reservations */ | |
176 | ||
177 | int irq; /* Device IRQ */ | |
178 | int bar; /* PCI BAR index */ | |
179 | unsigned long addr; /* Bus address */ | |
180 | void __iomem * ioaddr; /* Mapped address */ | |
181 | ||
182 | struct tasklet_struct card_tasklet; /* Tasklet structures */ | |
183 | struct tasklet_struct finish_tasklet; | |
184 | ||
185 | struct timer_list timer; /* Timer for timeouts */ | |
186 | }; | |
187 | ||
188 | struct sdhci_chip { | |
189 | struct pci_dev *pdev; | |
190 | ||
191 | int num_slots; /* Slots on controller */ | |
192 | struct sdhci_host *hosts[0]; /* Pointers to hosts */ | |
193 | }; |